M48T35-70PC6E [STMICROELECTRONICS]
5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM; 5V ， 256千位（ 32 KB ×8 ） TIMEKEEPER SRAM
| 型号： | M48T35-70PC6E |
| 厂家： | 
ST |
| 描述： | 5V, 256 Kbit (32 Kb x 8) TIMEKEEPER SRAM |
| 文件： | 总29页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T35
M48T35Y
5V, 256 Kbit (32 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated, ultra low power SRAM, real time
clock, power-fail control circuit and battery
■ BYTEWIDE™ RAM-like clock access
■ BCD coded year, month, day, date, hours,
minutes, and seconds
28
■ Frequency test output for real time clock
1
■ Automatic power-fail chip deselect and WRITE
protection
■ WRITE protect voltages
PCDIP28 (PC)
Battery/Crystal
CAPHAT
(V
= Power-fail Deselect Voltage):
PFD
– M48T35: V = 4.75 to 5.5V
CC
– 4.5V ≤ V
≤ 4.75V
PFD
– M48T35Y: V = 4.5 to 5.5V
CC
SNAPHAT (SH)
Battery/Crystal
– 4.2V ≤ V
≤ 4.5V
PFD
■ Self-contained battery and crystal in the
CAPHAT™ DIP package
■ SOIC package provides direct connection for a
®
SNAPHAT housing containing the battery and
crystal
®
■ SNAPHAT housing (battery and crystal) is
replaceable
28
1
■ Pin and function compatible with JEDEC
standard 32 Kb x 8 SRAMs
SOH28 (MH)
■ RoHS compliant
– Lead-free second level interconnect
August 2007
Rev 7
1/29
www.st.com
1
Contents
M48T35 M48T35Y
Contents
1
2
Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.1
3.2
3.3
3.4
3.5
3.6
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Century bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 15
4
5
6
7
8
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/29
M48T35 M48T35Y
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data . . . . . . . . . . . 21
SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT, package mechanical data . . . 22
SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package mechanical data . . 23
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package mechanical data . 24
PMDIP28 – 28-pin plastic DIP, hybrid, package mechanical data . . . . . . . . . . . . . . . . . . . 25
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SNAPHAT battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3/29
List of figures
M48T35 M48T35Y
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SOIC connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Read mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write enable controlled, write AC waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip enable controlled, write AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline. . . . . . . . . . . . . . . . . . . 21
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 22
Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline . . . . . . . . . . 23
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package outline . . . . . . . . . 24
Figure 17. PMDIP28 – 28-pin plastic DIP, hybrid, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4/29
M48T35 M48T35Y
Summary description
1
Summary description
®
The M48T35/Y TIMEKEEPER RAM is a 32Kb x 8 non-volatile static RAM and real time
clock. The monolithic chip is available in two special packages to provide a highly integrated
battery backed-up memory and real time clock solution.
The M48T35/Y is a non-volatile pin and function equivalent to any JEDEC standard 32Kb x
8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the
non-volatility of PROMs without any requirement for special WRITE timing or limitations on
the number of WRITEs that can be performed.
The 28-pin, 600mil DIP CAPHAT houses the M48T35/Y silicon with a quartz crystal and a
long life lithium button cell in a single package.
The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct
®
connection to a separate SNAPHAT housing containing the battery and crystal. The
unique design allows the SNAPHAT battery package to be mounted on top of the SOIC
package after the completion of the surface mount process. Insertion of the SNAPHAT
housing after reflow prevents potential battery and crystal damage due to the high
temperatures required for device surface-mounting. The SNAPHAT housing is keyed to
prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in
plastic anti-static tubes or in Tape & Reel form.
For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4T28-
BR12SH” (see Table 18 on page 27).
Figure 1.
Logic diagram
V
CC
15
8
A0-A14
DQ0-DQ7
W
E
M48T35
M48T35Y
G
V
SS
AI01620B
5/29
Summary description
M48T35 M48T35Y
Table 1.
Signal names
A0-A14
Address inputs
Data inputs / outputs
Chip enable
DQ0-DQ7
E
G
Output enable
WRITE Enable
Supply voltage
Ground
W
VCC
VSS
Figure 2.
DIP connections
A14
A12
A7
1
2
3
4
5
6
7
8
9
28
27
V
CC
W
26 A13
25 A8
24 A9
23 A11
A6
A5
A4
A3
22
G
M48T35
M48T35Y
A2
21 A10
A1
20
E
A0 10
DQ0 11
DQ1 12
DQ2 13
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
V
14
SS
AI01621B
Figure 3.
SOIC connections
A14
1
28
V
CC
A12
A7
2
27
26
25
24
23
22
21
20
19
18
17
16
15
W
3
A13
A8
A6
4
A5
5
A9
A4
6
A11
G
A3
7
M48T35Y
A2
8
A10
E
A1
9
A0
10
11
12
13
14
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
DQ1
DQ2
V
SS
AI01622B
6/29
M48T35 M48T35Y
Figure 4. Block diagram
Summary description
OSCILLATOR AND
CLOCK CHAIN
8 x 8 BiPORT
SRAM ARRAY
32,768 Hz
CRYSTAL
A0-A14
POWER
DQ0-DQ7
32,760 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
V
CC
SS
AI01623
7/29
Operation modes
M48T35 M48T35Y
2
Operation modes
As Figure 4 on page 7 shows, the static memory array and the quartz controlled clock
oscillator of the M48T35/Y are integrated on one silicon chip. The two circuits are
interconnected at the upper eight memory locations to provide user accessible BYTEWIDE
clock information in the bytes with addresses 7FF8h-7FFFh.
The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour
BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day months are
made automatically. Byte 7FF8h is the clock control register. This byte controls user access
to the clock information and also stores the clock calibration setting.
The eight clock bytes are not the actual clock counters themselves; they are memory
locations consisting of BiPORT™ READ/WRITE memory cells. The M48T35/Y includes a
clock control circuit which updates the clock bytes with current information once per second.
The information can be accessed by the user in the same manner as any other location in
the static memory array.
The M48T35/Y also has its own Power-fail Detect circuit. The control circuitry constantly
monitors the single 5V supply for an out of tolerance condition. When V is out of
CC
tolerance, the circuit write protects the SRAM, providing a high degree of data security in the
midst of unpredictable system operation brought on by low V . As V falls below the
CC
CC
Battery Back-up Switchover Voltage (V ), the control circuitry connects the battery which
SO
maintains data and clock operation until valid power returns.
Table 2.
Mode
Operating modes
VCC
E
G
W
DQ0-DQ7
Power
Deselect
WRITE
READ
VIH
VIL
VIL
VIL
X
X
X
X
High Z
DIN
Standby
Active
4.75 to 5.5V
or
VIL
VIH
VIH
X
VIL
VIH
X
DOUT
High Z
High Z
Active
4.5 to 5.5V
READ
Active
Deselect
VSO to VPFD (min)(1)
CMOS Standby
Battery Back-up
Mode
(1)
Deselect
≤ VSO
X
X
X
High Z
1. See Table 11 on page 20 for details.
Note:
X = V or V ; V = Battery Back-up Switchover Voltage.
IH IL SO
2.1
Read mode
The M48T35/Y is in the READ Mode whenever W (WRITE Enable) is high and E (Chip
Enable) is low. The unique address specified by the 15 Address Inputs defines which one of
the 32,768 bytes of data is to be accessed. Valid data will be available at the Data I/O pins
within Address Access time (t
) after the last address input signal is stable, providing
AVQV
that the E and G access times are also satisfied.
If the E and G access times are not met, valid data will be available after the latter of the
Chip Enable Access time (t
) or Output Enable Access time (t
).
ELQV
GLQV
The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are
activated before t , the data lines will be driven to an indeterminate state until t
.
AVQV
AVQV
8/29
M48T35 M48T35Y
Operation modes
If the Address Inputs are changed while E and G remain active, output data will remain valid
for Output Data Hold time (t
) but will go indeterminate until the next Address Access.
AXQX
Figure 5.
Read mode AC waveforms
tAVAV
VALID
A0-A14
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI00925
Note:
WRITE Enable (W) = High.
Table 3.
Read mode AC characteristics
Parameter(1)
M48T35/Y
Symbol
Unit
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
READ Cycle Time
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to Output Valid
70
70
35
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
(2)
tELQX
5
5
(2)
tGLQX
(2)
tEHQZ
25
25
(2)
tGHQZ
tAXQX
10
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. CL = 5pF.
2.2
Write mode
The M48T35/Y is in the WRITE Mode whenever W and E are low. The start of a WRITE is
referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
from Chip Enable or t
from WRITE Enable
EHAX
WHAX
prior to the initiation of another READ or WRITE Cycle. Data-in must be valid t
prior to
DVWH
the end of WRITE and remain valid for t
afterward. G should be kept high during
WHDX
9/29
Operation modes
M48T35 M48T35Y
WRITE Cycles to avoid bus contention; although, if the output bus has been activated by a
low on E and G, a low on W will disable the outputs t
after W falls.
WLQZ
Figure 6.
Write enable controlled, write AC waveform
tAVAV
A0-A14
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI00926
Figure 7.
Chip enable controlled, write AC waveforms
tAVAV
A0-A14
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI00927
Table 4.
Symbol
Write mode AC characteristics
Parameter(1)
M48T35/Y
Unit
Min
Max
tAVAV
tAVWL
tAVEL
WRITE Cycle Time
70
0
ns
ns
ns
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
0
10/29
M48T35 M48T35Y
Operation modes
Table 4.
Symbol
Write mode AC characteristics (continued)
M48T35/Y
Parameter(1)
Unit
Min
Max
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
WRITE Enable Pulse Width
50
55
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable Low to Chip Enable High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
0
30
30
5
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
5
(2)(3)
tWLQZ
25
tAVWH
tAVEH
60
60
5
(2)(3)
tWHQX
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. CL = 5pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid V applied, the M48T35/Y operates as a conventional BYTEWIDE static RAM.
CC
Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V falls within the V
(max), V
(min) window. All outputs
CC
PFD
PFD
become high impedance, and all inputs are treated as “Don't care” (see Figure 12 on
page 19, Table 10, and Table 11 on page 20).
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the
PFD
user can be assured the memory will be in a write protected state, provided the V fall time
CC
is not less than tF. The M48T35/Y may respond to transient noise spikes on V that reach
CC
into the deselect window during the time the device is sampling V . Therefore, decoupling
CC
of the power supply lines is recommended.
When V drops below V , the control circuit switches power to the internal battery which
CC
SO
preserves data and powers the clock. The internal button cell will maintain data in the
M48T35/Y for an accumulated period of at least 7 years when V is less than V . As
CC
SO
system power returns and V rises above V , the battery is disconnected, and the power
CC
SO
supply is switched to external V . Write protection continues until V reaches V (min)
CC
CC
PFD
plus t (min). E should be kept high as V rises past V (min) to prevent inadvertent
rec
CC
PFD
WRITE Cycles prior to processor stabilization. Normal RAM operation can resume t after
rec
V
exceeds V
(max).
CC
PFD
For more information on Battery Storage Life refer to the Application Note AN1012.
11/29
Clock operations
M48T35 M48T35Y
3
Clock operations
3.1
Reading the clock
®
Updates to the TIMEKEEPER registers (see Table 5) should be halted before clock data is
read to prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM
array are only data registers and not the actual clock counters, so updating the registers can
be halted without disturbing the clock itself.
Updating is halted when a '1' is written to the READ Bit, D6 in the Control Register 7FF8h.
As long as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the count; that is, the day, date, and the time that
were current at the moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
Bit D7 of the Control Register 7FF8h is the WRITE Bit. Setting the WRITE Bit to a '1,' like
®
the READ Bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24 hour BCD format (see Table 5). Resetting the
WRITE Bit to a '0' then transfers the values of all time registers 7FF9h-7FFFh to the actual
TIMEKEEPER counters and allows normal operation to resume. The FT Bit and the bits
marked as '0' in Table 5 must be written to '0' to allow for normal TIMEKEEPER and RAM
operation. After the WRITE Bit is reset, the next clock update will occur within one second.
®
st
See the Application Note AN923, “TIMEKEEPER Rolling Into the 21 Century” for
information on Century Rollover.
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP Bit is the MSB of the seconds register. Setting it to a '1' stops the
oscillator. The M48T35/Y is shipped from STMicroelectronics with the STOP Bit set to a '1.'
When reset to a '0,' the M48T35/Y oscillator starts within 1 second.
12/29
M48T35 M48T35Y
Table 5.
Clock operations
Register map
Data
D4
Function/Range
BCD Format
Address
D7
D6
D5
D3
D2
D1
Year
D0
7FFFh
7FFEh
7FFDh
10 Years
Year
00-99
01-12
01-31
0
0
0
0
0
10 M.
CB
Month
Date
Month
Date
10 Date
Century/ 00-01/01-
7FFCh
7FFBh
0
0
FT
0
CEB
0
Day
Day
07
10 Hours
Hours
Hours
00-23
7FFAh
7FF9h
7FF8h
0
ST
W
10 Minutes
10 Seconds
S
Minutes
Minutes
Seconds
Control
00-59
Seconds
00-59
R
Calibration
Keys:
S = SIGN Bit
FT = FREQUENCY TEST Bit (Must be set to '0' upon power for normal operation)
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
CEB = Century Enable Bit
CB = Century Bit
Note:
When CEB is set to '1,' CB will toggle from '0' to '1' or from '1' to '0' at the turn of the century
(dependent upon the initial value set).
When CEB is set to '0,' CB will not toggle. The WRITE Bit does not need to be set to write to
CEB.
3.4
Calibrating the clock
The M48T35/Y is driven by a quartz-controlled oscillator with a nominal frequency of 32,768
Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency
error at 25°C, which equates to about 1.53 minutes per month. With the calibration bits
properly set, the accuracy of each M48T35/Y improves to better than +1/–2 ppm at 25°C.
The oscillation rate of any crystal changes with temperature (see Figure 8 on page 15).
Most clock chips compensate for crystal frequency and temperature shift error with
cumbersome “trim” capacitors. The M48T35/Y design, however, employs periodic counter
correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit
at the divide by 256 stage, as shown in Figure 9 on page 15. The number of times pulses
are blanked (subtracted, negative calibration) or split (added, positive calibration) depends
upon the value loaded into the five calibration bits found in the Control Register. Adding
counts speeds the clock up, subtracting counts slows the clock down.
The Calibration Byte occupies the five lower order bits (D4-D0) in the Control Register
7FF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is the Sign Bit; '1' indicates positive calibration, '0' indicates negative calibration.
Calibration occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per
13/29
Clock operations
M48T35 M48T35Y
minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If
a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be
modified; if a binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is in
fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration Byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Two methods are available for ascertaining how much calibration a given M48T35/Y may
require. The first involves simply setting the clock, letting it run for a month and comparing it
to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows
the designer to give the end user the ability to calibrate his clock as his environment may
require, even after the final product is packaged in a non-user serviceable enclosure. All the
designer has to do is provide a simple utility that accesses the Calibration Byte.
The second approach is better suited to a manufacturing environment, and involves the use
of some test equipment. When the Frequency Test (FT) Bit, the seventh-most significant bit
in the Day Register is set to a '1,' and D7 of the Seconds Register is a '0' (Oscillator
Running), DQ0 will toggle at 512 Hz during a READ of the Seconds Register. Any deviation
from 512 Hz indicates the degree and direction of oscillator frequency shift at the test
temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator
frequency error, requiring a –10 (WR001010) to be loaded into the Calibration Byte for
correction.
Note:
Setting or changing the Calibration Byte does not affect the Frequency Test output
frequency.
The FT Bit MUST be reset to '0' for normal clock operations to resume. The FT Bit is
automatically Reset on power-down.
®
For more information on calibration, see Application Note AN934, “TIMEKEEPER
Calibration.”
3.5
Century bit
Bit D5 and D4 of Clock Register 1FFCh contain the CENTURY ENABLE Bit (CEB) and the
CENTURY Bit (CB). Setting CEB to a '1' will cause CB to toggle, either from a '0' to '1' or
from '1' to '0' at the turn of the century (depending upon its initial state). If CEB is set to a '0,'
CB will not toggle.
Note:
The WRITE Bit must be set in order to write to the CENTURY Bit.
14/29
M48T35 M48T35Y
Figure 8.
Clock operations
Crystal accuracy across temperature
ppm
20
0
-20
-40
-60
-80
-100
2
ΔF
F
ppm
C2
= -0.038
(T - T0) 10%
T0 = 25 °C
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 9.
Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
3.6
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A bypass capacitor value of 0.1µF (as shown in Figure 10
on page 16) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
schottky diode from V to V (cathode connected to V , anode to V ). Schottky diode
CC
SS
CC
SS
15/29
Clock operations
M48T35 M48T35Y
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 10. Supply voltage protection
V
CC
V
CC
0.1μF
DEVICE
V
SS
AI02169
16/29
M48T35 M48T35Y
Maximum rating
4
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
Grade 1
Grade 6
0 to 70
–40 to 85
–40 to 85
260
°C
°C
°C
°C
V
TA
Ambient Operating Temperature
TSTG
Storage Temperature (VCC Off, Oscillator Off)
Lead Solder Temperature for 10 seconds
(1)(2)(3)
TSLD
M48T35
–0.3 to 7
–0.3 to 7
–0.3 to 7
–0.3 to 7
20
VIO
Input or Output Voltages
Supply Voltage
M48T35Y
M48T35
V
V
VCC
M48T35Y
V
IO
Output Current
mA
W
PD
Power Dissipation
1
1. For DIP package: Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to
exceed 150°C for longer than 30 seconds).
2. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds).
3. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
Caution:
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
17/29
DC and AC parameters
M48T35 M48T35Y
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter
Supply Voltage (VCC
M48T35
M48T35Y
Unit
)
4.75 to 5.5
0 to 70
100
4.5 to 5.5
–40 to 85
100
V
°C
pF
ns
V
Ambient Operating Temperature (TA)
Load Capacitance (CL)
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
1.5
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 11. AC measurement load circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
C
= 100pF or 5pF
L
C
includes JIG capacitance
L
AI01030
Table 8.
Symbol
Capacitance
Parameter(1)(2)
Min
Max
Unit
CIN
Input Capacitance
Output Capacitance
10
10
pF
pF
(3)
COUT
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
18/29
M48T35 M48T35Y
DC and AC parameters
Table 9.
Symbol
ILI
DC characteristics
M48T35
Max
M48T35Y
Unit
Parameter
Test condition(1)
Min
Min
Max
Input Leakage Current
Output Leakage Current
Supply Current
0V ≤ VIN ≤ VCC
0V ≤ VOUT ≤ VCC
Outputs open
1
1
1
1
µA
µA
(2)(2)
ILO
ICC
50
30
mA
Supply Current (Standby)
TTL
ICC1
E = VIH
3
2
3
2
mA
mA
Supply Current (Standby)
CMOS
ICC2
E = VCC – 0.2V
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
VCC + 0.3
0.4
–0.3
2.2
0.8
VCC + 0.3
0.4
V
V
V
V
VOL
VOH
IOL = 2.1mA
IOH = –1mA
2.4
2.4
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. Outputs deselected.
Figure 12. Power down/up mode AC waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
tPD
tDR
trec
RECOGNIZED
RECOGNIZED
INPUTS
DON'T CARE
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI01168C
19/29
DC and AC parameters
M48T35 M48T35Y
Table 10. Power down/up AC characteristics
Symbol
Parameter(1)
Min
Max
Unit
tPD
E or W at VIH before Power Down
0
300
10
10
10
1
µs
µs
µs
µs
µs
µs
ms
(2)
tF
VPFD (max) to VPFD (min) VCC Fall Time
VPFD (min) to VSS VCC Fall Time
M48T35
(3)
tFB
M48T35Y
tR
VPFD (min) to VPFD (max) VCC Rise Time
VSS to VPFD (min) VCC Rise Time
VPFD (max) to Inputs Recognized
tRB
(4)(4)
trec
40
200
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
V
CC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4. trec (min) = 20ms for industrial temperature Grade 6 device.
Table 11. Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max
Unit
M48T35
M48T35Y
M48T35
M48T35Y
Grade 1
Grade 6
4.5
4.2
4.6
4.35
3.0
4.75
4.5
V
VPFD
Power-fail Deselect Voltage
V
V
VSO
Battery Back-up Switchover Voltage
Expected Data Retention Time
3.0
V
10(4)
10(5)
YEARS
YEARS
(3)(5)
tDR
1. Valid for Ambient Operating Temperature: TA = 0 to 70 or –40 to 85°C; VCC = 4.75 to 5.5V or 4.5 to 5.5V (except where
noted).
2. All voltages referenced to VSS
.
3. CAPHAT and M4T32-BR12SH1 SNAPHAT only, M4T28-BR12SH1 SNAPHAT top tDR = 7 years (typ).
4. Using larger M4T32-BR12SH6 SNAPHAT top (recommended for Industrial Temperature Range - Grade 6 device).
5. At 25°C, VCC = 0V.
20/29
M48T35 M48T35Y
Package mechanical information
6
Package mechanical information
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 13. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package outline
A2
A
L
A1
e1
C
B1
B
eA
e3
D
N
1
E
PCDIP
Note:
Drawing is not to scale.
Table 12. PCDIP28 – 28-pin plastic DIP, battery CAPHAT, package mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
8.89
0.38
8.38
0.38
1.14
0.20
39.37
17.83
2.29
29.72
15.24
3.05
28
9.65
0.76
0.350
0.015
0.330
0.015
0.045
0.008
1.550
0.702
0.090
1.170
0.600
0.120
28
0.380
0.030
0.350
0.021
0.070
0.012
1.570
0.722
0.110
1.430
0.630
0.150
8.89
0.53
B1
C
1.78
0.31
D
39.88
18.34
2.79
E
e1
e3
eA
L
36.32
16.00
3.81
N
21/29
Package mechanical information
M48T35 M48T35Y
Figure 14. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT,
package outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 13. SOH28 – 28-lead plastic SO, 4-socket battery SNAPHAT, package
mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
B
3.05
0.36
2.69
0.51
0.32
18.49
8.89
–
0.120
0.014
0.106
0.020
0.012
0.728
0.350
–
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
1.27
0.050
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
a
N
28
28
CP
0.10
0.004
22/29
M48T35 M48T35Y
Package mechanical information
Figure 15. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK
Note:
Drawing is not to scale.
Table 14. SH – 4-pin SNAPHAT housing for 48mAh battery & crystal, package
mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
A3
B
9.78
7.24
6.99
0.38
0.56
21.84
14.99
3.61
2.29
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
3.20
0.018
0.835
0.560
0.126
0.080
D
E
eB
L
2.03
23/29
Package mechanical information
M48T35 M48T35Y
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
outline
A2
A3
A1
A
eA
D
B
L
eB
E
SHTK
Note:
Drawing is not to scale.
Table 15. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, package
mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
A2
A3
B
10.54
8.51
8.00
0.38
0.56
21.84
18.03
3.61
2.29
0.415
0.335
0.315
0.015
0.022
0.860
0.710
0.142
0.090
8.00
7.24
0.315
0.285
0.46
21.21
17.27
3.20
0.018
0.835
0.680
0.126
0.080
D
E
eB
L
2.03
24/29
M48T35 M48T35Y
Package mechanical information
Figure 17. PMDIP28 – 28-pin plastic DIP, hybrid, package outline
A
L
A1
e1
C
eA
S
B
e3
D
N
1
E
PMDIP
Note:
Drawing is not to scale.
Table 16. PMDIP28 – 28-pin plastic DIP, hybrid, package mechanical data
mm
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
A1
B
9.27
0.38
9.53
0.365
0.015
0.017
0.008
1.470
0.710
0.090
0.375
0.43
0.58
0.33
0.023
0.013
1.490
0.740
0.110
C
0.20
D
37.34
18.03
2.29
37.85
18.80
2.79
E
e1
e3
eA
L
33.02
1.300
14.99
3.05
1.91
28
16.00
3.81
2.67
0.590
0.120
0.075
28
0.630
0.150
0.105
S
N
25/29
Part numbering
M48T35 M48T35Y
7
Part numbering
Table 17. Ordering information scheme
Example:
M48T
35
–70
PC
1
E
Device type
M48T
Supply voltage and write protect voltage
35(1) = VCC = 4.75 to 5.5V; VPFD = 4.5 to 4.75V
35Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Speed
–70 = 70ns
Package
PC = PCDIP28
MH(2) = SOH28
PM = PMDIP28 (NND)(3)
Temperature range
1 = 0 to 70°C
6 = –40 to 85°C(4)
Shipping method
For SOH28:
blank = Tubes (Not for New Design - Use E)
E = ECOPACK package, tubes
F = ECOPACK package, tape & reel
TR = Tape & Reel (Not for New Design - Use F)
For PCDIP28:
blank = ECOPACK package, tubes
1. The M48T35 part is offered with the PCDIP28 (e.g., CAPHAT) package only.
2. The SOIC package (SOH28) requires the SNAPHAT® battery package which is ordered
separately under the part number “M4TXX-BR12SH” in plastic tube or “M4TXX-BR12SHTR” in
Tape & Reel form (see Table 18 on page 27).
3. This package is not to be used for New Design.
4. Available in SOIC package only.
Caution:
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
26/29
M48T35 M48T35Y
Table 18. SNAPHAT battery table
Part numbering
Package
Part number
Description
M4T28-BR12SH
M4T32-BR12SH
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
SH
SH
27/29
Revision history
M48T35 M48T35Y
8
Revision history
Table 19. Document revision history
Date
Revision
Changes
Nov- 1999
1.0
1.1
First Issue
tDR Description changed (Table 9)
07-Feb-2000
Reformatted; temp/voltage info. added to tables (Table 8, 9, 3, 4, 10,
11); add Century Bit text
04-Jun-2001
31-Jul-2001
06-Mar-2002
2.0
2.1
2.2
Formatting changes based on latest document reviews
Add PMDIP Packaging option, which is “Not for New Design” (NND)
(Table 17, 16, and Figure 17)
20-May-2002
26-Jun-2002
31-Mar-2003
10-Dec-2003
31-Mar-2004
05-Dec20-05
2.3
2.4
3.0
4.0
5.0
6.0
Modify reflow time and temperature footnotes (Table 6)
Add footnote to table (Table 11)
v2.2 template applied; data retention condition updated (Table 11)
Reformatted; update DC Characteristics (Table 9)
Reformatted; update Pb-free package information (Table 6, 17)
Updated template, Lead-free text, and remove footnote (Table 9, 17)
Reformatted; added lead-free second level interconnect information to
cover page and Section 6: Package mechanical information.
01-Aug-2007
7.0
28/29
M48T35 M48T35Y
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