M48T212Y-85MH1E [STMICROELECTRONICS]
5V/3.3V TIMEKEEPER CONTROLLER Supervisor; 5V / 3.3V TIMEKEEPER控制器监事
| 型号： | M48T212Y-85MH1E |
| 厂家： | 
ST |
| 描述： | 5V/3.3V TIMEKEEPER CONTROLLER Supervisor |
| 文件： | 总32页 (文件大小：619K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T212Y
M48T212V
®
5.0V or 3.3V TIMEKEEPER Supervisor
FEATURES SUMMARY
■
INTEGRATED REAL TIME CLOCK, POWER-
Figure 1. 44-pin SOIC Package
FAIL CONTROL CIRCUIT, BATTERY AND
CRYSTAL
■
CONVERTS LOW POWER SRAM INTO
NVRAMs
SNAPHAT (SH)
Crystal/Battery
■
■
■
■
YEAR 2000 COMPLIANT (4-Digit Year)
BATTERY LOW FLAG
MICROPROCESSOR POWER-ON RESET
PROGRAMMABLE ALARM OUTPUT
ACTIVE IN THE BATTERY BACKED-UP
MODE
■
■
WATCHDOG TIMER
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
■
CHOICE OF WRITE PROTECT VOLTAGES
44
(V
–
= Power-fail Deselect Voltage):
PFD
1
M48T212Y: V = 4.5 to 5.5V
CC
4.2V ≤ V
≤ 4.5V
PFD
SOH44 (MH)
–
M48T212V: V = 3.0 to 3.6V
CC
2.7V ≤ V
≤ 3.0V
PFD
■
PACKAGING INCLUDES A 44-LEAD SOIC
AND SNAPHAT TOP (to be ordered
®
separately)
April 2004
1/32
M48T212Y, M48T212V
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 44-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. SOIC Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Address Decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Truth Table for SRAM Bank Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 5. Chip Enable Control and Bank Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Chip Enable Control and Bank Select Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. READ Cycle Timing: RTC Control Signal Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
TIMEKEEPER® Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 8. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Alarm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
V
CC
Switch Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10.(RSTIN1 & RSTIN2) Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Initial Power-on Defaults. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10. Default Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2/32
M48T212Y, M48T212V
Figure 12.Calibration Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 13.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 15. Power Down/Up Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline . . . . . . . . . . . . . . 27
Table 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . . 27
Figure 17.SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline . . . . . . 28
Table 17. SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mech. Data . . . 28
Figure 18.SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline . . . . . . 29
Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data. . . 29
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 19. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 20. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
M48T212Y, M48T212V
DESCRIPTION
The M48T212Y/V are self-contained devices that
include a real time clock (RTC), programmable
alarms, a watchdog timer, and two external chip
enable outputs which provide control of up to four
(two in parallel) external low-power static RAMs.
mounted on top of the SOIC package after the
completion of the surface mount process.
Insertion of the SNAPHAT housing after reflow
prevents potential battery and crystal damage due
to the high temperatures required for device sur-
face-mounting. The SNAPHAT housing is keyed
to prevent reverse insertion.
The SOIC and battery/crystal packages are
shipped separately in plastic anti-static tubes or in
Tape & Reel form. For the-44 lead SOIC, the bat-
tery/crystal package (e.g., SNAPHAT) part num-
®
Access to all TIMEKEEPER functions and the
external RAM is the same as conventional byte-
wide SRAM. The 16 TIMEKEEPER Registers offer
Century, Year, Month, Date, Day, Hour, Minute,
Second, Calibration, Alarm, Watchdog, and Flags.
Externally attached static RAMs are controlled by
the M48T212Y/V via the E1
nals (see Table 3., page 8).
and E2
sig-
CON
CON
ber
is
“M4TXX-BR12SH”
(see
Table
20., page 30).
The 44-pin, 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing con-
taining the battery and crystal. The unique design
allows the SNAPHAT battery package to be
Caution: Do not place the SNAPHAT battery/crys-
tal top in conductive foam, as this will drain the lith-
ium button-cell battery.
®
4/32
M48T212Y, M48T212V
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A3
DQ0-DQ7
RSTIN1
RSTIN2
RST
WDI
A
Address Inputs
Data Inputs/Outputs
Reset 1 Input
V
V
CCSW
CC
Reset 2 Input
Reset Output (Open Drain)
Watchdog Input
4
8
A0-A3
DQ0-DQ7
Bank Select Input
A
E
E
Chip Enable Input
IRQ/FT
RST
EX
External Chip Enable Input
Output Enable Input
WRITE Enable Input
RAM Chip Enable 1 Output
RAM Chip Enable 2 Output
Int/Freq Test Output (Open Drain)
EX
M48T212Y
M48T212V
G
W
E1
CON
CON
W
G
E2
E1
CON
WDI
RSTIN1
RSTIN2
E2
V
CON
OUT
IRQ/FT
Vccsw
V
CC
Switch Output
V
Supply Voltage Output
Supply Voltage
OUT
V
SS
AI03019
V
CC
V
SS
Ground
NC
Not Connected internally
5/32
M48T212Y, M48T212V
Figure 3. SOIC Connections
RSTIN1
RSTIN2
RST
NC
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
V
V
V
CC
2
OUT
3
CCSW
4
IRQ/FT
EX
NC
NC
NC
NC
NC
G
NC
5
NC
6
NC
7
NC
8
A
9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
M48T212Y
M48T212V
NC
NC
W
A3
NC
NC
E
A2
A1
A0
E1
CON
WDI
DQ7
DQ6
DQ5
DQ4
DQ3
NC
E2
CON
DQ0
DQ1
DQ2
V
SS
AI03020
6/32
M48T212Y, M48T212V
Figure 4. Hardware Hookup
A0-A18
MOTOROLA
MTD20P06HDL
5V/3.3V
A0-A3
V
CCSW
V
CC
A0-Axx
(1)
1N5817
0.1µF
V
V
OUT
CC
A
E
0.1µF
(3)
E2
CMOS
SRAM
E
EX
W
E1
CON
Note 2
G
E2
CON
WDI
RSTIN1
RSTIN2
A0-Axx
RST
V
CC
DQ0-DQ7
IRQ/FT
(3)
E2
CMOS
SRAM
V
E
SS
M48T212Y/V
AI03046
Note: 1. See description in Power Supply Decoupling and Undershoot Protection.
2. Traces connecting E1 and E2 to external SRAM should be as short as possible.
CON
CON
3. If the second chip enable pin (E2) is unused, it should be tied to V
.
OUT
7/32
M48T212Y, M48T212V
OPERATION
Automatic backup and write protection for an ex-
ternal SRAM is provided through V
timer can generate either a reset or an interrupt,
depending on the state of the Watchdog Steering
Bit (WDS). Bytes 6h-2h include bits that, when
programmed, provide for clock alarm functionality.
Alarms are activated when the register content
matches the month, date, hours, minutes, and
seconds of the clock registers. Byte 1h contains
century information. Byte 0h contains additional
flag information pertaining to the watchdog timer,
alarm and battery status.
, E1
OUT
CON
and E2
pins. (Users are urged to insure that
CON
voltage specifications, for both the SUPERVISOR
chip and external SRAM chosen, are similar). The
®
SNAPHAT containing the lithium energy source
used to permanently power the real time clock is
also used to retain RAM data in the absence of
V
power through the V
pin.
CC
OUT
The chip enable outputs to RAM (E1
and
CON
E2
) are controlled during power transients to
CON
The M48T212Y/V also has its own Power-Fail De-
tect circuit. This control circuitry constantly moni-
tors the supply voltage for an out of tolerance
prevent data corruption. The date is automatically
adjusted for months with less than 31 days and
corrects for leap years (valid until 2100). The inter-
nal watchdog timer provides programmable alarm
windows.
condition. When V is out of tolerance, the circuit
CC
®
write protects the TIMEKEEPER register data
and external SRAM, providing data security in the
The nine clock bytes (Fh-9h and 1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT READ/WRITE memory
midst of unpredictable system operation. As V
CC
falls below V , the control circuitry automatically
SO
™
switches to the battery, maintaining data and clock
operation until valid power is restored.
Address Decoding
The M48T212Y/V accommodates 4 address lines
(A3-A0) which allow access to the sixteen bytes of
the TIMEKEEPER clock registers. All TIMEKEEP-
ER registers reside in the SUPERVISOR chip it-
self. All TIMEKEEPER registers are accessed by
enabling E (Chip Enable).
cells within the static RAM array. Clock circuitry
updates the clock bytes with current information
once per second. The information can be access-
ed by the user in the same manner as any other lo-
cation in the static memory array.
Byte 8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting. Byte 7h con-
tains the watchdog timer setting. The watchdog
Table 2. Operating Modes
V
Mode
Deselect
WRITE
READ
E
G
X
X
W
DQ7-DQ0
Power
Standby
Active
CC
V
IH
X
High-Z
4.5V to 5.5V
or
3.0V to 3.6V
V
IL
V
IL
V
IL
V
D
IL
IH
IH
IN
V
V
V
D
Active
IL
OUT
V
IH
READ
High-Z
High-Z
High-Z
Active
(1)
Deselect
X
X
X
CMOS Standby
V
SO
to V
(min)
PFD
(1)
Deselect
X
X
X
Battery Back-Up
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage
IH
IL
SO
1. See Table 14., page 25 for details.
Table 3. Truth Table for SRAM Bank Select
V
E1
E2
Mode
EX
Low
Low
High
A
Low
High
X
Power
Active
CC
CON
CON
Low
High
Low
High
4.5V to 5.5V
or
3.0V to 3.6V
Select
High
High
Active
Deselect
Deselect
Standby
(1)
X
X
X
X
High
High
High
High
CMOS Standby
Battery Back-Up
V
SO
to V
(min)
PFD
(1)
Deselect
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage
IH
IL
SO
1. See Table 14., page 25 for details.
8/32
M48T212Y, M48T212V
Figure 5. Chip Enable Control and Bank Select Timing
EX
tEXPD
tAPD
A
tEXPD
E1
CON
E2
CON
AI02639
Table 4. Chip Enable Control and Bank Select Characteristics
M48T212Y
–70
M48T212V
Symbol
Parameter
–85
Unit
Min
Max
Min
Max
15
t
EX to E1
A to E1
or E2
(Low or High)
CON
10
10
ns
ns
EXPD
CON
t
or E2
(Low or High)
CON
15
APD
CON
9/32
M48T212Y, M48T212V
READ Mode
The M48T212Y/V executes a READ cycle when-
ever W (WRITE Enable) is high and E (Chip En-
able) is low. The unique address specified by the
address inputs (A3-A0) defines which one of the
are also satisfied.If they are not, then data access
must be measured from the latter occurring signal
(E or G) and the limiting parameter is either t
ELQV
for E or t
time.
for G rather than the address access
GLQV
®
on-chip TIMEKEEPER registers is to be access-
ed. When the address presented to the
M48T212Y/V is in the range of 0h-Fh, one of the
on-board TIMEKEEPER registers is accessed and
valid data will be available to the eight data output
When EX input is low, an external SRAM location
will be selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
drivers within t
after the address input signal
AVQV
is stable, providing that the E and G access times
Figure 6. READ Cycle Timing: RTC Control Signal Waveforms
READ
tAVAV
READ
tAVAV
WRITE
tAVAV
ADDRESS
tELQV
tAVQV
tAVWL
tWHAX
E
tELQX
tGLQV
G
tWLWH
W
tGLQX
tAXQX
tGHQZ
DATA OUT
VALID
DATA OUT
VALID
DATA IN
VALID
DQ7-DQ0
AI02640
Note: EX is assumed High.
Table 5. READ Mode AC Characteristics
M48T212Y
–70
M48T212V
–85
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
Read Cycle Time
70
85
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
25
85
85
35
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
ELQV
t
GLQV
(2)
5
0
5
0
t
ELQX
GLQX
EHQZ
(2)
(2)
(2)
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
ns
ns
ns
ns
t
t
20
20
25
25
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
GHQZ
t
5
5
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
10/32
M48T212Y, M48T212V
WRITE Mode
The M48T212Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are in a
low state after the address inputs are stable. The
start of a WRITE is referenced from the latter oc-
curring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The
addresses must be held valid throughout the cy-
G should be kept high during WRITE cycles to
avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on
W will disable the outputs t
after W falls.
WLQZ
When E is low during the WRITE, one of the on-
®
board TIMEKEEPER registers will be selected
and data will be written into the device. When EX
is low (and E is high) an external SRAM location is
selected.
Note: Care should be taken to avoid taking both E
and EX low simultaneously to avoid bus conten-
tion.
cle. E or W must return high for a minimum of t
E-
from Chip Enable or t
from WRITE
HAX
WHAX
Enable prior to the initiation of another READ or
WRITE cycle. Data-in must be valid t prior to
DVWH
the end of WRITE and remain valid for t
terward.
af-
WHDX
Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms
WRITE
tAVAV
WRITE
tAVAV
READ
tAVAV
ADDRESS
tAVEH
tELEH
tAVWH
tEHAX tWHAX
tAVEL
tAVQV
E
tGLQV
G
tEHDX
tAVWL
tWLWH
tWHQX
tWLQZ
W
tEHQZ
tDVEH tDVWH
tWHDX
DATA OUT
VALID
DATA IN
VALID
DATA IN
VALID
DATA OUT
VALID
DQ0-DQ7
AI02641
Note: EX is assumed High.
11/32
M48T212Y, M48T212V
Table 6. WRITE Mode AC Characteristics
M48T212Y
–70
M48T212V
–85
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
Write Cycle Time
70
0
85
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
45
50
0
55
60
0
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
0
0
EHAX
t
25
25
0
30
30
0
DVWH
t
DVEH
t
Write Enable High to Input Transition
Chip Enable High to Input Transition
WHDX
t
0
0
EHDX
(2,3)
Write Enable Low to Output High-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
20
25
ns
ns
ns
ns
t
WLQZ
t
55
55
5
65
65
5
AVWH
t
AVEH
(2,3)
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF
L
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
12/32
M48T212Y, M48T212V
Data Retention Mode
With valid V applied, the M48T212Y/V can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M48T212Y/V will automatically deselect, write
protecting itself (and any external SRAM) when
some criteria which should be used in making the
final choice of an SRAM to use. The SRAM must
be designed in a way where the chip enable input
disables all other inputs to the SRAM. This allows
inputs to the M48T212Y/V and SRAMs to be
CC
V
falls between V
(max) and V
(min).
“Don't care” once V falls below V
SRAM should also guarantee data retention down
(min). The
CC
PFD
PFD
CC
PFD
This is accomplished by internally inhibiting ac-
cess to the clock registers via the E signal. At this
time, the Reset pin (RST) is driven active and will
to V = 2.0V. The chip enable access time must
CC
be sufficient to meet the system needs with the
chip enable output propagation delays included.
remain active until V returns to nominal levels.
CC
External RAM access is inhibited in a similar man-
If the SRAM includes a second chip enable pin
ner by forcing E1
and E2
to a high level.
(E2), this pin should be tied to V
.
CON
CON
OUT
This level is within 0.2 volts of the V
. E1
BAT
CON
CC
If data retention lifetime is a critical parameter for
the system, it is important to review the data reten-
tion current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a
data retention current at 3.0V. Manufacturers gen-
erally specify a typical condition for room temper-
ature along with a worst case condition (generally
at elevated temperatures). The system level re-
quirements will determine the choice of which val-
ue to use.
and E2
will remain at this level as long as V
CON
remains at an out-of-tolerance condition.
When V falls below battery back-up switchover
CC
voltage (V ), power input is switched from the
SO
®
V
pin to the SNAPHAT battery and the clock
CC
registers and external SRAM are maintained from
the attached battery supply. All outputs become
high impedance. The V
pin is capable of sup-
OUT
plying 100µA of current to the attached memory
with less than 0.3V drop under this condition. On
The data retention current value of the SRAMs can
power up, when V
returns to a nominal value,
CC
then be added to the I
value of the M48T212Y/
BAT
write protection continues for 200ms (max) by in-
hibiting E1 or E2
V to determine the total current requirements for
data retention. The available battery capacity for
.
CON
CON
®
The RST signal also remains active during this
time (see Figure 15., page 26).
Note: Most low power SRAMs on the market to-
the SNAPHAT of your choice can then be divided
by this current to determine the amount of data re-
tention available (see Table 20., page 30).
day can be used with the M48T212Y/V TIME-
KEEPER SUPERVISOR. There are, however
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
®
13/32
M48T212Y, M48T212V
CLOCK OPERATION
®
TIMEKEEPER Registers
Setting the Clock
The M48T212Y/V offers 16 internal registers
which contain TIMEKEEPER , Alarm, Watchdog,
Bit D7 of the Control Register (8h) is the WRITE
Bit. Setting the WRITE Bit to a '1,' like the READ
Bit, halts updates to the TIMEKEEPER registers.
The user can then load them with the correct day,
date, and time data in 24 hour BCD format (see
Table 7., page 15).
®
Flag, and Control data. These registers are mem-
ory locations which contain external (user accessi-
ble) and internal copies of the data (usually
™
referred to as BiPORT TIMEKEEPER cells).
The external copies are independent of internal
functions except that they are updated periodically
by the simultaneous transfer of the incremented
internal copy. TIMEKEEPER and Alarm Registers
store data in BCD. Control, Watchdog and Flags
Registers store data in Binary Format.
Resetting the WRITE Bit to a '0' then transfers the
values of all time registers (Fh-9h, 1h) to the actual
TIMEKEEPER counters and allows normal opera-
tion to resume. After the WRITE Bit is reset, the
next clock update will occur one second later.
Note: Upon power-up following a power failure,
the READ Bit will automatically be set to a '1.' This
will prevent the clock from updating the TIME-
KEEPER registers, and will allow the user to read
the exact time of the power-down event.
Reading the Clock
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. The BiPORT TIMEKEEPER
cells in the RAM array are only data registers and
not the actual clock counters, so updating the reg-
isters can be halted without disturbing the clock it-
self.
Resetting the READ Bit to a '0' will allow the clock
to update these registers with the current time.
The WRITE Bit will be reset to a '0' upon power-up.
Stopping and Starting the Oscillator
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (8h). As long
as a '1' remains in that position, updating is halted.
After a halt is issued, the registers reflect the
count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued.
All of the TIMEKEEPER registers are updated si-
multaneously. A halt will not interrupt an update in
progress. Updating occurs 1 second after the
READ Bit is reset to a '0.'
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within the Seconds Register
(9h). Setting it to a '1' stops the oscillator. When re-
set to a '0,' the M48T212Y/V oscillator starts within
one second.
Note: It is not necessary to set the WRITE Bit
when setting or resetting the FREQUENCY TEST
Bit (FT) or the STOP Bit (ST).
14/32
M48T212Y, M48T212V
®
Table 7. TIMEKEEPER Register Map
Function/Range
BCD Format
Address
D7
D6
D5
D4
10M
0
D3
D2
D1
D0
Fh
Eh
Dh
Ch
Bh
Ah
9h
8h
7h
6h
5h
4h
3h
2h
1h
0h
10 Years
Year
Year
Month
Date
00-99
01-12
01-31
01-7
0
0
0
0
0
Month
10 Date
Date: Day of Month
Day of Week
0
FT
0
0
0
Day
0
10 Hours
Hours (24 Hour Format)
Minutes
Hours
Min
00-23
00-59
00-59
0
10 Minutes
10 Seconds
S
ST
Seconds
Sec
W
R
BMB4
0
Calibration
Control
Watchdog
A Month
A Date
A Hour
A Min
A Sec
Century
Flag
WDS
AFE
RPT4
RPT3
RPT2
RPT1
BMB3
BMB2
BMB1
BMB0
RB1
RB0
ABE
Al 10M
Alarm Month
Alarm Date
01-12
01-31
00-23
00-59
00-59
00-99
RPT5
0
AI 10 Date
AI 10 Hour
Alarm Hour
Alarm Minutes
Alarm Seconds
100 Year
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
WDF
AF
Y
BL
Y
Y
Y
Y
Keys: S = Sign Bit
FT = Frequency Test Bit
AFE = Alarm Flag Enable Flag
RB0-RB1 = Watchdog Resolution Bits
WDS = Watchdog Steering Bit
R = READ Bit
W = WRITE Bit
ST = Stop Bit
0 = Must be set to '0'
BL = Battery Low Flag (Read only)
ABE = Alarm in Battery Back-Up Mode Enable Bit
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag (Read only)
AF = Alarm Flag (Read only)
BMB0-BMB4 = Watchdog Multiplier Bits
Y = '1' or '0'
15/32
M48T212Y, M48T212V
Setting the Alarm Clock
Address locations 6h-2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every year, month,
day, hour, minute, or second. It can also be pro-
grammed to go off while the M48T212Y/V is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 put the alarm in the repeat mode
of operation. Table 8 shows the possible configu-
rations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
If AFE (Alarm Flag Enable) is also set, the alarm
condition activates the IRQ/FT pin. To disable
alarm, write '0' to the Alarm Date registers and
RPT1-5. The IRQ/FT output is cleared by a READ
to the Flags Register as shown in Figure 8. A sub-
sequent READ of the Flags Register is necessary
to see that the value of the Alarm Flag has been
reset to '0.'
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE Bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T212Y/V was in the deselect mode
during power-up. Figure 9., page 17 illustrates the
back-up mode alarm timing.
Note: User must transition address (or toggle chip
enable) to see Flag Bit change.
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set.
Figure 8. Alarm Interrupt Reset Waveforms
A0-A3
1h
ADDRESS 0h
Fh
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI03021
Table 8. Alarm Repeat Modes
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
Once per Second
Once per Minute
Once per Hour
Once per Day
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Once per Month
Once per Year
16/32
M48T212Y, M48T212V
Figure 9. Back-up Mode Alarm Waveforms
tREC
V
CC
V
V
(max)
(min)
PFD
PFD
AFE Bit/ABE Bit
AF Bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI03622
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 7h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower-order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five-bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds).
Watchdog time-out when the WDS Bit is set to a
'1.'
The watchdog timer can be reset by two methods:
1. a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or
2. the microprocessor can perform a WRITE of
the Watchdog Register.
The time-out period then starts over. The WDI pin
should be tied to V if not used. The watchdog
SS
will be reset on each transition (edge) seen by the
WDI pin. In the order to perform a software reset
of the watchdog timer, the original time-out period
can be written into the Watchdog Register, effec-
tively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
Bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A READ of the Flags Register
will reset the Watchdog Flag (Bit D7; Register 0h).
The watchdog function is automatically disabled
upon power-down and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT pin and the frequency test function is
activated, the watchdog or alarm function prevails
and the frequency test function is denied.
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T212Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 0h).
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a '0.' the watchdog will activate the IRQ/FT pin
when timed-out. When WDS is set to a '1,' the
watchdog will output a negative pulse on the RST
pin for 40 to 200 ms. The Watchdog register, AFE,
ABE, and FT Bits will reset to a '0' at the end of a
17/32
M48T212Y, M48T212V
V
Switch Output
CC
Vccsw output goes low when V
switches to
priate pull-up resistor to V
control rise time.
should be chosen to
CC
OUT
V
turning on a customer supplied P-Channel
CC
MOSFET (see Figure 4., page 7). The Motorola
MTD20P06HDL is recommended. This MOSFET
Note: If the RST output is fed back into either of
the RSTIN inputs (for a microprocessor with a bi-
directional reset) then a 1kΩ (max) pull-up resistor
is recommended.
in turn connects V
the current requirement is greater than I
to a separate supply when
OUT
(see
OUT1
Table 14., page 25). This output may also be used
simply to indicate the status of the internal battery
switchover comparator, which controls the source
Reset Inputs (RSTIN1 & RSTIN2)
The M48T212Y/V provides two independent in-
puts which can generate an output reset. The du-
ration and function of these resets is identical to a
reset generated by a power cycle. Table 9 and Fig-
ure 10 illustrate the AC reset characteristics of this
(V or battery) of the V
output.
CC
OUT
Power-on Reset
The M48T212Y/V continuously monitors V
.
CC
When V
falls to the power fail detect trip point,
CC
function. During the time RST is enabled (t
R1HRH
the RST pulls low (open drain) and remains low on
power-up for t after V passes V (max).
& t
), the Reset Inputs are ignored.
R2HRH
rec
CC
PFD
Note: RSTIN1 and RSTIN2 are each internally
The RST pin is an open drain output and an appro-
pulled up to V through a 100KΩ resistor.
CC
Figure 10. (RSTIN1 & RSTIN2) Timing Waveforms
RSTIN1
tR1
RSTIN2
tR2
RST
tR1HRH
tR2HRH
AI02642
Table 9. Reset AC Characteristics
(1)
Symbol
Min
200
100
40
Max
Unit
ns
Parameter
RSTIN1 Low to RSTIN1 High
(2)
t
t
R1
(3)
RSTIN2 Low to RSTIN2 High
RSTIN1 High to RST High
RSTIN2 High to RST High
ms
ms
ms
R2
(4)
(4)
200
200
t
t
R1HRH
40
R2HRH
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. Pulse width less than 50ns will result in no RESET (for noise immunity).
3. Pulse width less than 20ms will result in no RESET (for noise immunity).
4. C = 5pF (see Figure 14., page 24).
L
18/32
M48T212Y, M48T212V
Calibrating the Clock
The M48T212Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768 Hz.
The devices are tested not to exceed ±35 ppm
(parts per million) oscillator frequency error at
25°C, which equates to about ±1.53 minutes per
month (see Figure 11., page 21). When the Cali-
bration circuit is properly employed, accuracy im-
proves to better than +1/–2 ppm at 25°C.
The oscillation rate of crystals changes with tem-
perature. The M48T212Y/V design employs peri-
odic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 256 stage, as shown in Fig-
ure 12., page 21. The number of times pulses
which are blanked (subtracted, negative calibra-
tion) or split (added, positive calibration) depends
upon the value loaded into the five Calibration bits
found in the Control Register. Adding counts
speeds the clock up, subtracting counts slows the
clock down.
The Calibration bits occupy the five lower-order
bits (D4-D0) in the Control Register 8h. These bits
can be set to represent any value between 0 and
31 in binary form. Bit D5 is a Sign Bit; '1' indicates
positive calibration, ‘0' indicates negative calibra-
tion. Calibration occurs within a 64 minute cycle.
The first 62 minutes in the cycle may, once per
minute, have one second either shortened by 128
or lengthened by 256 oscillator cycles.
If a binary ‘1' is loaded into the register, only the
first 2 minutes in the 64 minute cycle will be modi-
fied; if a binary 6 is loaded, the first 12 will be af-
fected, and so on.
which corresponds to a total range of +5.5 or –2.75
minutes per month.
Two methods are available for ascertaining how
much calibration a given M48T212Y/V may re-
quire. The first involves setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference and recording deviation over a fixed
period of time. Calibration values, including the
number of seconds lost or gained in a given peri-
od, can be found in Application Note, “AN934,
®
TIMEKEEPER Calibration.”
This allows the designer to give the end user the
ability to calibrate the clock as the environment re-
quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop Bit (ST, D7 of 9h) is '0,' the Frequency Test
Bit (FT, D6 of Ch) is '1,' the Alarm Flag Enable Bit
(AFE, D7 of 6h) is '0,' and the Watchdog Steering
Bit (WDS, D7 of 7h) is '1' or the Watchdog Register
(7h=0) is reset.
Any deviation from 512 Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124 Hz would indicate a +20 ppm oscilla-
tor frequency error, requiring a –10 (WR001010)
to be loaded into the Calibration Byte for correc-
tion. Note that setting or changing the Calibration
Byte does not affect the Frequency test output fre-
quency.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768 Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
The IRQ/FT pin is an open drain output which re-
quires a pull-up resistor to V
for proper opera-
CC
tion. A 500-10kΩ resistor is recommended in order
to control the rise time. The FT Bit is cleared on
power-up.
19/32
M48T212Y, M48T212V
Battery Low Warning
The M48T212Y/V automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) Bit, Bit D4 of Flags
Register 0h, will be asserted if the battery voltage
is found to be less than approximately 2.5V. The
BL Bit will remain asserted until completion of bat-
tery replacement and subsequent battery low
monitoring tests, either during the next power-up
sequence or the next scheduled 24-hour interval.
If a battery low is generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct. A
fresh battery should be installed.
subsequent periods of battery back-up mode, the
battery should be replaced. The SNAPHAT bat-
®
tery/crystal top should be replaced with V
ering the device to avoid data loss.
pow-
CC
Note: this will cause the clock to lose time during
the time interval the battery crystal is removed.
The M48T212Y/V only monitors the battery when
a nominal V is applied to the device. Thus appli-
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial.
Additionally, if a battery low is indicated, data in-
tegrity should be verified upon power-up via a
checksum or other technique.
Initial Power-on Defaults
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
Upon application of power to the device, the fol-
lowing register bits are set to a ’0' state: WDS,
BMB0-BMB4, RB0-RB1, AFE, ABE, W, and FT
(see Tabel 10).
promised due to the fact that a nominal V
is
CC
supplied. In order to insure data integrity during
Table 10. Default Values
WATCHDOG
Condition
W
R
FT
AFE
ABE
(1)
Register
Initial Power-up
0
0
0
0
0
0
(2)
(Battery Attach for SNAPHAT)
(3)
0
0
0
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
RESET
(4)
Power-down
Subsequent Power-up
Note: 1. WDS, BMB0-BMB4, RB0, RB1.
2. State of other control bits undefined.
3. State of other control bits remains unchanged.
4. Assuming these bits set to '1' prior to power-down.
20/32
M48T212Y, M48T212V
Figure 11. Crystal Accuracy Across Temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
–100
–120
–140
–160
T0 = 25 °C
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999
Figure 12. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
21/32
M48T212Y, M48T212V
V
Noise And Negative Going Transients
Figure 13. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
13) is recommended in order to provide the need-
ed filtering.
V
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
CC
V
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, STMicroelectronics recom-
AI02169
mends connecting a schottky diode from V
to
CC
V
(cathode connected to V , anode to V ).
SS
CC SS
Schottky diode 1N5817 is recommended for
through hole and MBRS120T3 is recommended
for surface mount.
22/32
M48T212Y, M48T212V
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 11. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Value
0 to 70
Unit
°C
T
A
®
–40 to 85
–55 to 125
260
°C
SNAPHAT
SOIC
T
Storage Temperature
STG
°C
(1,2)
Lead Solder Temperature for 10 seconds
Input or Output Voltage
°C
T
SLD
–0.3 to V
+ 0.3
V
V
V
IO
CC
–0.3 to 7.0
–0.3 to 4.6
20
M48T212Y
M48T212V
V
Supply Voltage
CC
V
I
Output Current
mA
W
O
P
D
Power Dissipation
1
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget not to exceed 180°C for
between 90 to 150 seconds).
2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal budget not to exceed 245°C
for greater than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
23/32
M48T212Y, M48T212V
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 12. DC and AC Measurement Conditions
Parameter
M48T212Y
4.5 to 5.5V
0 to 70°C
–40 to 85°C
100pF
M48T212V
3.0 to 3.6V
0 to 70°C
–40 to 85°C
50pF
V
Supply Voltage
CC
Grade 1
Grade 6
Ambient Operating Temperature
Load Capacitance (C )
L
Input Rise and Fall Times
Input Pulse Voltages
≤ 5ns
≤ 5ns
0 to 3V
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
1.5V
Note: Output High Z is defined as the point where data is no longer driven.
Figure 14. AC Testing Load Circuit
645Ω
DEVICE
UNDER
TEST
C
C
= 100pF or 5pF (1)
= 30 pF (2)
1.75V
L
L
C
includes JIG capacitance
L
AI03239
Note: Excluding open-drain output pins; 50pF for M48T212V.
1. DQ0-DQ7
2. E1
and E2
CON
CON
Table 13. Capacitance
Symbol
(1,2)
Min
Max
10
Unit
pF
Parameter
C
Input Capacitance
Input/Output Capacitance
IN
(3)
10
pF
C
OUT
Note: 1. Effective capacitance measured with power supply at 5V (M48T212Y) or 3.3V (M48T212V); sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
24/32
M48T212Y, M48T212V
Table 14. DC Characteristics
M48T212Y
–70
M48T212V
(1)
Sym
Parameter
–85
Typ
Unit
Test Condition
Min
Typ
Max
Min
Max
(2)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±1
±1
µA
µA
I
IN
CC
LI
(3)
0V ≤ V
≤ V
CC
±1
15
±1
10
I
OUT
LO
I
Outputs open
8
4
mA
CC
Supply Current (Standby)
TTL
I
E = V
5
3
mA
CC1
CC2
IH
Supply Current (Standby)
CMOS
I
E = V –0.2
3
2
mA
nA
nA
CC
Battery Current OSC ON
575
950
800
1250
575
950
800
1250
Battery Current OSC
(4)
I
V
CC
= 0V
BAT
ON
Battery Current OSC
OFF
100
0.8
100
0.8
nA
V
V
V
Input Low Voltage
Input High Voltage
–0.3
2.2
–0.3
2.0
IL
V
CC
+
V
CC
+
V
IH
0.3
0.3
I
= 2.1mA
= 10mA
Output Low Voltage
Output Low Voltage
0.4
0.4
0.4
0.4
V
OL
V
V
OL
I
V
OL
(5)
(open drain)
I
= –1.0mA
= –1.0µA
Output High Voltage
2.4
2.0
2.4
2.0
V
V
OH
OH
(6)
V
V
V
Battery Back-up
Current (Active)
I
OUT2
3.6
3.6
70
V
I
OH
OHB
(7)
V
> V –0.3
CC
100
mA
OUT
OUT1
OUT1
Current (Battery
OUT
I
V
> V
–0.3
100
4.5
100
3.0
µA
V
OUT2
OUT2
BAT
Back-up)
Power-fail Deselect
Voltage
V
PFD
4.2
4.35
2.7
2.9
V
–
Battery Back-up
Switchover Voltage
PFD
V
3.0
3.0
V
V
SO
100mV
V
BAT
Battery Voltage
3.0
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. RSTIN1 and RSTIN2 internally pulled-up to V through 100KΩ resistor. WDI internally pulled-down to V through 100KΩ resistor.
CC
SS
3. Outputs deselected.
4. I (OSC ON) = Industrial Temperature Range - Grade 6 device.
BAT
5. For IRQ/FT & RST pins (Open Drain).
6. Conditioned outputs (E1 - E2
rents will reduce battery life.
) can only sustain CMOS leakage currents in the battery back-up mode. Higher leakage cur-
®
CON
CON
7. External SRAM must match TIMEKEEPER SUPERVISOR chip V specification.
CC
25/32
M48T212Y, M48T212V
Figure 15. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
trec
INPUTS
VALID
DON'T CARE
VALID
HIGH-Z
OUTPUTS
VALID
VALID
RST
V
CCSW
AI02638
Table 15. Power Down/Up Mode AC Characteristics
(1)
Symbol
Min
Max
Unit
Parameter
t
V
V
(max) to V
(min) V Fall Time
300
10
150
10
1
µs
µs
µs
µs
µs
ms
F
PFD
PFD
PFD
PFD
CC
M48T212Y
M48T212V
t
(min) to V
(min) to V
V
Fall Time
FB
SS CC
t
R
V
V
V
(max) V Rise Time
PFD CC
t
to V
(min) V Rise Time
PFD CC
RB
SS
t
(max) to RST High
40
200
rec
PFD
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C or –40 to 85°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
26/32
M48T212Y, M48T212V
PACKAGE MECHANICAL INFORMATION
Figure 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note: Drawing is not to scale.
Table 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
0.81
0.032
eB
H
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
27/32
M48T212Y, M48T212V
Figure 17. SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 17. SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
28/32
M48T212Y, M48T212V
Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Note: Drawing is not to scale.
Table 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Mech. Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
29/32
M48T212Y, M48T212V
PART NUMBERING
Table 19. Ordering Information Example
Example:
M48T
212Y
–70
MH
1
TR
Device Type
M48T
Supply and Write Protect Voltage
212Y = V = 4.5 to 5.5V; 4.2V ≤ V
≤ 4.5V
≤ 3.0V
CC
PFD
212V = V = 3.0 to 3.6V; 2.7V ≤ V
CC
PFD
Speed
–70 = 70ns (for M48T212Y)
–85 = 85ns (for M48T212V)
Package
(1)
MH = SOH44
Temperature Range
1 = 0 to 70°C
6 = –40 to 85°C
Shipping Method
blank = Tubes (Not for New Design - Use E)
®
E = Lead-free Package (ECO PACK ), Tubes
®
F = Lead-free Package (ECO PACK ), Tape & Reel
TR = Tape & Reel (Not for New Design - Use F)
®
Note: 1. The SOIC package (SOH44) requires the SNAPHAT battery package which is ordered separately under the part number
“M4Txx-BR12SH” in plastic tube or “M4Txx-BR12SHTR” in Tape & Reel form (see Table 20).
Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithium button-cell bat-
tery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
®
Table 20. SNAPHAT Battery Table
Part Number
M4T28-BR12SH
M4T32-BR12SH
Description
Lithium Battery (48mAh) SNAPHAT
Lithium Battery (120mAh) SNAPHAT
Package
SH
SH
30/32
M48T212Y, M48T212V
REVISION HISTORY
Table 21. Document Revision History
Date
Rev. #
1.0
Revision Details
October 1999
01-Mar-00
21-Apr-00
10-Nov-00
30-May-01
First Issue
2.0
Document Layout changed; Default Values table added (Table 10)
From Preliminary Data to Data Sheet
3.0
3.1
Table 16 changed
3.2
Changed “Controller” references to “SUPERVISOR”
Reformatted; added temp./voltage info. to tables (Table 14, 5, 6, 15, 9); added E2 to
Hookup (Figure 4); Improve text in “Setting the Alarm Clock” section
10-Sep-01
4.0
13-May-02
16-Jul-02
27-Mar-03
31-Mar-04
4.1
4.1
5.0
6.0
Modify reflow time and temperature footnote (Table 11)
Updated DC Characteristics, footnotes (Table 14)
v2.2 template applied; updated test condition (Table 14)
Reformatted; updated with Pb-free information (Table 11, 19)
31/32
M48T212Y, M48T212V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners.
© 2004 STMicroelectronics - All rights reserved
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32/32
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