M48T248V_技术文档

M48T248Y

M48T248V

®

5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM

FEATURES SUMMARY

■ 5.0V OR 3.3V OPERATING VOLTAGE

Figure 1. 32-pin, DIP Package

■ REAL TIME CLOCK KEEPS TRACK OF

TENTHS/HUNDREDTHS OF SECONDS,

SECONDS, MINUTES, HOURS, DAYS, DATE

OF THE MONTH, MONTHS, and YEARS

■ AUTOMATIC LEAP YEAR CORRECTION

VALID UP TO THE YEAR 2100

■ AUTOMATIC SWITCH-OVER and DESELECT

CIRCUITRY

32

■ CHOICE OF POWER-FAIL DESELECT

1

VOLTAGES:

(V

= Power-fail Deselect Voltage):

PFD

PMDIP32 (PM)

– M48T248Y: 4.25V ≤ V_PFD≤ 4.50V

– M48T248V: 2.80V ≤ V_PFD≤ 2.97V

■ FULL 10% V

OPERATING RANGE

CC

■ OVER 10 YEARS’ DATA RETENTION IN THE

ABSENCE OF POWER

■ WATCH FUNCTION IS TRANSPARENT TO

RAM OPERATION

■ 128K x 8 NV SRAM DIRECTLY REPLACES

VOLATILE STATIC RAM OR EEPROM

March 2003

1/24

Rev. 2.0

M48T248Y, M48T248V

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . 7

Table 3. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 4. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Table 5. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Memory READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Memory WRITE Cycle 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 8. Memory WRITE Cycle 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 7. Memory AC Characteristics, M48T248Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 8. Memory AC Characteristics, M48T248V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 9. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

PHANTOM CLOCK OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. Comparison Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clock Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2/24

M48T248Y, M48T248V

Zero Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Phantom Clock Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 11. Phantom Clock READ Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 12. Phantom Clock WRITE Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. Phantom Clock Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Phantom Clock AC Characteristics (M48T248Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 12. Phantom Clock AC Characteristics (M48T248V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

3/24

M48T248Y, M48T248V

SUMMARY DESCRIPTION

®

The M48T248Y/V TIMEKEEPER RAM is a

128Kbit x 8 non-volatile static RAM and real time

clock organized as 131,072 words by 8 bits. The

special DIP package provides a fully integrated

battery back-up memory and real time clock solu-

tion. In the event of power instability or absence, a

self-contained battery maintains the timekeeping

operation and provides power for a CMOS static

and year information. The last day of the month is

automatically adjusted for months with less than

31 days, including leap year correction.

The clock operates in one of two formats:

– a 12-hour mode with an AM/PM indicator; or

– a 24-hour mode

The M48T248Y/V is a 32-pin (PM) DIP module

that integrates the RTC, the battery, and SRAM in

one package.

The modules are shipped in plastic, anti-static

tubes (see Table 14, page 22).

RAM. Control circuitry monitors V

and invokes

CC

write protection to prevent data corruption in the

memory and RTC.

The clock keeps track of tenths/hundredths of sec-

onds, seconds, minutes, hours, day, date, month,

Figure 2. Logic Diagram

Table 1. Signal Names

A0–A16

RST

Address Input

V

CC

Reset Input

CE

Chip Enable

OE

Output Enable Input

WRITE Enable Input

Data Inputs/Outputs

Supply Voltage Input

Ground

A0-A16

WE

DQ0-D7

WE

DQ0–DQ7

M48T248Y

M48T248V

CE

V

CC

V

SS

OE

RST

Figure 3. DIP Connections

V

32

31

30

29

28

27

26

25

24

23

22

21

RST

1

2

CC

V

SS

A15

NC

A16

A14

AI04661

3

WE

4

A13

5

A7

A6

A8

6

A5

7

A9

M48T248Y

M48T248V

A4

8

A11

OE

A3

9

10

11

12

13

14

15

16

A2

A10

CE

A1

A0

DQ7

DQ6

DQ5

DQ4

DQ3

DQ0

20

19

18

17

DQ1

DQ2

V

SS

AI04662

4/24

M48T248Y, M48T248V

Figure 4. Block Diagram

XO

XI

CLOCK/CALENDAR

LOGIC

32.768 Hz

CRYSTAL

UPDATE

READ

TIMEKEEPER

REGISTER

CE

OE

WRITE

CONTROL

LOGIC

POWER

FAIL

WE

RST

A0–A16

SRAM

DQ0–DQ7

ACCESS

ENABLE

SEQUENCE

DETECTOR

COMPARISON

REGISTER

I/O

DATA

DQ0

BUFFERS

INTERNAL V

CC

POWER-FAIL

DETECT

V

CC

LOGIC

V

BAT

AI04238

5/24

M48T248Y, M48T248V

MAXIMUM RATING

Stressing the device above the rating listed in the

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Exposure to Absolute Maximum Rat-

ing conditions for extended periods may affect de-

vice

reliability.

Refer

also

to

the

STMicroelectronics SURE Program and other rel-

evant quality documents.

Table 2. Absolute Maximum Ratings

Symbol

Parameter

Operating Temperature

Value

0 to 70

Unit

°C

T

A

T

Storage Temperature (V , Oscillator Off)

–40 to 85

°C

STG

CC

(1)

Lead Solder Temperature for 10 seconds

260

°C

T

SLD

M48T248Y

–0.3 to +7.0

–0.3 to +4.6

V

Supply Voltage (on any pin

relative to Ground)

V

CC

M48T248V

V

–0.3 to V + 0.3

Input or Output Voltages

Output Current

V

IO

CC

I

O

20

1

mA

W

P

Power Dissipation

D

Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).

CAUTION! Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up Mode.

6/24

M48T248Y, M48T248V

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Characteristic tables are

derived from tests performed under the Measure-

ment Conditions listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 3. DC and AC Measurement Conditions

Parameter

M48T248Y

4.5 to 5.5V

0 to 70°C

100pF

M48T248V

3.0 to 3.6V

0 to 70°C

50pF

V

Supply Voltage

CC

Ambient Operating Temperature

Load Capacitance (C )

L

Input Rise and Fall Times

≤ 5ns

Input Pulse Voltages

0 to 3V

1.5V

Input and Output Timing Ref. Voltages

1.5V

Note: Output High Z is defined as the point where data is no longer driven (see Table 3, page 7).

Figure 5. AC Testing Load Circuit

V

CCI

1.1 KΩ

DEVICE

UNDER

TEST

680 Ω

C = 50 pF

L

AI04240

Note: 50pF for M48T248V.

Table 4. Capacitance

Symbol

(1,2)

Min

Max

10

Unit

pF

Parameter

C

Input Capacitance

Input / Output Capacitance

IN

(3)

10

pF

C

IO

Note: 1. Effective capacitance measured with power supply at 5V. Sampled only; not 100% tested.

2. At 25°C, f = 1MHz.

3. Outputs were deselected.

7/24

M48T248Y, M48T248V

Table 5. DC Characteristics

M48T248Y

–70

M48T248V

–85

Test

Sym

Parameter

Unit

(1)

Condition

Min

Typ

Max

±1

Min

Typ

Max

±1

(2)

0V ≤ V ≤ V

Input Leakage Current

Output Leakage Current

Supply Current

µA

I

IN

CC

LI

I

0V ≤ V

≤ V

OUT CC

±1

LO

I

85

50

mA

CC1

Supply Current (TTL

Standby)

I

CE = V

IH

5

3

10

5

2

7

mA

CC2

V

Power Supply

CC

I

CE = V

– 0.2

5

3

mA

V

CC3

CCI

Current

(3)

Input Low Voltage

–0.3

2.2

0.8

–0.3

2.2

0.6

V

IL

(3)

IH

V

+ 0.3

V

CC

+ 0.3

Input High Voltage

Output Low Voltage

Output High Voltage

Power Fail Deselect

V

CC

V

I

= 2.0 mA

0.4

OL

V

I

= –1.0 mA

2.4

OH

(3)

4.25

4.37

4.50

2.80

2.86

2.5

2.97

V

PFD

Battery Back-up

Switchover

(3)

V

SO

BAT

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. RST (Pin 1) has an internal pull-up resistor.

3. All voltages are referenced to Ground.

8/24

M48T248Y, M48T248V

OPERATION MODES

Table 6. Operating Modes

V

Mode

Deselect

WRITE

READ

CE

OE

X

WE

DQ7-DQ0

Power

Standby

Active

CC

V

X

High-Z

IH

4.5V to 5.5V

or

3.0V to 3.6V

V

IL

V

D

X

IL

IN

V

IL

V

D

Active

IL

IH

OUT

V

READ

High-Z

Active

IL

IH

(1)

Deselect

X

CMOS Standby

V

SO

to V

(min)

PFD

(1)

Deselect

Battery Back-Up

≤ V

SO

Note: X = V or V ; V = Battery Back-up Switchover Voltage

IH

IL

SO

1. See Table 9, page 14 for details.

READ

WRITE

A READ cycle executes whenever WRITE Enable

(WE) is high and Chip Enable (CE) is low (see Fig-

ure 6). The distinct address defined by the 19 ad-

dress inputs (A0-A18) specifies which of the 512K

bytes of data is to be accessed. Valid data will be

accessed by the eight data output drivers within

WRITE Mode (see Figure 7, page 10 and Figure 8,

page 11) occurs whenever CE and WE signals are

low (after address inputs are stable). The most re-

cent falling edge of CE and WE will determine

when the WRITE cycle begins (the earlier, rising

edge of CE or WE determines cycle termination).

All address inputs must be kept stable throughout

the WRITE cycle. WE must be high (inactive) for a

the specified Access Time (t

) after the last ad-

ACC

dress input signal is stable, the CE and OE access

times, and their respective parameters are satis-

minimum recovery time (t ) before a subsequent

WR

fied. When CE t

and OE t

are not satisfied,

ACC

cycle is initiated. The OE control signal should be

kept high (inactive) during the WRITE cycles to

avoid bus contention. If CE and OE are low (ac-

tive), WE will disable the outputs for Output Data

ACC

then data access times must be measured from

the more recent CE and OE signals, with the limit-

ing parameter being t (for CE) or t (for OE) in-

CO

OE

stead of address access.

WRITE Time (t

) from its falling edge.

ODW

Figure 6. Memory READ Cycle

tRC

ADDRESSES

tACC

tCO

tOH

CE

OE

tOD

tOE

tODO

tCOE

DATA OUTPUT

VALID

DQ0 - DQ7

AI04230

Note: WE is high for a READ cycle.

9/24

M48T248Y, M48T248V

Figure 7. Memory WRITE Cycle 1

tWC

ADDRESSES

tAW

CE

tWR

tWP

WE

tOEW

tODW

HIGH IMPEDANCE

tDS

tDH

DQ0–DQ7

DATA IN

STABLE

AI04231

Note: 1. OE = V or V . If OE = V during a WRITE cycle, the output buffers remain in a high impedance state.

IH

IL

IH

2. If the CE low transition occurs simultaneously with or later than the WE low transition in WRITE Cycle 1, the output buffers remain

in a high impedance state during this period.

3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state

during this period.

10/24

M48T248Y, M48T248V

Figure 8. Memory WRITE Cycle 2

tWC

ADDRESSES

tAW

tWP

tWR

CE

tOEW

WE

tODW

tCOE

tDS

tDH

DQ0–DQ7

DATA IN

STABLE

AI04232

Note: 1. OE = V or V . If OE = V during a WRITE cycle, the output buffers remain in a high impedance state.

IH

IL

IH

2. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers remain in a high

impedance state during this period.

11/24

M48T248Y, M48T248V

Table 7. Memory AC Characteristics, M48T248Y

M48T248Y–70

(1)

Symbol

Unit

Parameter

Min

Max

t

RC

READ Cycle Time

Access Time

70

ns

AVAV

t

ACC

70

35

AVQV

ELQV

t

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

CO

GLQV

OE

t

ELQX

Chip Enable or Output Enable Low to Output Transition

Output Hold from Address Change

5

ns

t

COE

t

GLQX

tOH

AXQX

EHQZ

GHQZ

(2)

Chip Enable or Output Enable High to Output Hi-Z

25

t

OD

t

(2)

t

Output Hi-Z from WE

WRITE Cycle Time

ns

WLQZ

t

ODW

t

70

50

AVAV

WC

t

WLWH

(3)

WP

WE, CE Pulse Width

Address Setup Time

ns

t

ELEH

t

AVEL

t

0

AW

t

AVWL

t

WRITE Recovery Time

15

0

ns

EHAX

WR1

t

Address Hold Time from WE

WHAX

WR2

Output Active from WE

Data Setup Time

5

ns

WHQX

OEW

t

DVEH

(4)

30

t

DS

t

DVWH

(4)

t

Data Hold Time from WE

Data Hold Time from CE

0

ns

t

WHDX

DH1

(4)

t

10

t

EHDX

DH2

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. These parameters are sampled with a 5 pF load are not 100% tested.

3. t is specified as the logical AND of CE and WE. t is measured from the latter of CE or WE going low to the earlier of CE or

WP

WE going high.

4. t and t are measured from the earlier of CE or WE going high.

DH

DS

12/24

M48T248Y, M48T248V

Table 8. Memory AC Characteristics, M48T248V

M48T248V–85

Unit

(1)

Symbol

Parameter

Min

Max

t

RC

READ Cycle Time

Access Time

85

ns

AVAV

t

ACC

85

45

AVQV

ELQV

t

Chip Enable Low to Output Valid

Output Enable Low to Output Valid

CO

GLQV

OE

t

ELQX

Chip Enable or Output Enable Low to Output Transition

Output Hold from Address Change

5

ns

t

COE

t

GLQX

t

AXQX

OH

EHQZ

GHQZ

(2)

Chip Enable or Output Enable High to Output Hi-Z

35

30

t

OD

t

(2)

t

Output Hi-Z from WE

WRITE Cycle Time

ns

WLQZ

t

ODW

t

85

65

75

AVAV

WC

(3)

t

WRITE Enable Pulse Width

Chip Enable Pulse Width

t

WLWH

WP1

t

ELEH

WP2

t

AVEL

t

Address Setup Time

0

ns

AW

t

AVWL

(4)

t

WRITE Recovery Time

Address Hold Time from WE

Output Active from WE

15

5

ns

EHAX

t

WR1

t

WHAX

WR2

5

WHQX

t

OEW

t

DVEH

(5)

DS

Data Setup Time

35

ns

t

DVWH

(5)

t

Data Hold Time from WE

Data Hold Time from CE

0

ns

t

WHDX

DH1

t

15

t

EHDX

DH2

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. These parameters are sampled with a 5 pF load are not 100% tested.

3. t is specified as the logical AND of CE and WE. t is measured from the latter of CE or WE going low to the earlier of CE or

WP

WE going high.

4. t is a function of the latter occurring edge of WE or CE.

WR

5. t and t are measured from the earlier of CE or WE going high.

DH

DS

13/24

M48T248Y, M48T248V

Data Retention Mode

Data can be read or written only when V

is

data retention when V

is absent or unstable.

CC

greater than V

. When V

is below V (the

The capability of this source is sufficient to power

the device continuously for the life of the equip-

ment into which it has been installed. For specifi-

cation purposes, life expectancy is ten (10) years

at 25°C with the internal oscillator running without

PFD

CC

PFD

point at which write protection occurs), the clock

registers and the SRAM are blocked from any ac-

cess. When V

falls below the Battery Switch

CC

Over threshold (V ), the device is switched from

SO

V

to battery backup (V

). RTC operation and

V

. Each unit is shipped with its energy source

CC

BAT

CC

SRAM data are maintained via battery backup un-

til power is stable. All control, data, and address

disconnected, guaranteeing full energy capacity.

When V is first applied at a level greater than

CC

signals must be powered down when V is pow-

ered down.

The lithium power source is designed to provide

power for RTC activity as well as RTC and RAM

V

, the energy source is enabled for battery

CC

PFD

backup operation. The actual life expectancy will

be much longer if no battery energy is used (e.g.,

when V is present).

CC

Figure 9. Power Down/Up Mode AC Waveforms

V

CC

tF

tR

V

(max)

(min)

PFD

V

PFD

V

SO

tFB

tREC

tPD

CE

tDR

AI04236

Table 9. Power Down/Up Trip Points DC Characteristics

(1)

Symbol

Min

1.5

300

10

0

Max

Unit

ms

µs

Parameter

(max) to CE low

t

V

PFD

V

PFD

V

PFD

V

PFD

2.5

REC

t

(max) to V

(min) to V

(min) V

Fall Time

F

PFD

CC

V

Fall Time

t

FB

µs

SO CC

PFD

t

(min) to V

(max) V

Rise Time

CC

µs

R

t

CE High to Power-Fail

Expected Data Retention Time

0

µs

PD

(2)

10

Years

t

DR

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. At 25°C, V = 0V; the expected t is defined as cumulative time in the absence of V with the clock oscillator running.

CC

DR

CC

14/24

M48T248Y, M48T248V

PHANTOM CLOCK OPERATION

Communication with the Phantom Clock is estab-

lished by pattern recognition of a serial bit-stream

of 64 bits which must be matched by executing 64

consecutive WRITE cycles containing the proper

data on DQ0.

All accesses which occur prior to recognition of the

64-bit pattern are directed to memory.

aside just one address location in RAM as a Phan-

tom Clock scratch pad.

When the first WRITE cycle is executed, it is com-

pared to Bit 1 of the 64-bit comparison register. If

a match is found, the pointer increments to the

next location of the comparison register and

awaits the next WRITE cycle.

After recognition is established, the next 64 READ

or WRITE cycles either extract or update data in

the clock while disabling the memory.

If a match is not found, the pointer does not ad-

vance and all subsequent WRITE cycles are ig-

nored. If a READ cycle occurs at any time during

pattern recognition, the present sequence is abort-

ed and the comparison register pointer is reset.

Pattern recognition continues for a total of 64

WRITE cycles as described above until all of the

bits in the comparison register have been

matched. With a correct match for 64-bits, the

Phantom Clock is enabled and data transfer to or

from the timekeeping registers can proceed. The

next 64 cycles will cause the Phantom Clock to ei-

ther receive or transmit data on DQ0, depending

on the level of the OE pin or the WE pin. Cycles to

other locations outside the memory block can be

interleaved with CE cycles without interrupting the

pattern recognition sequence or data transfer se-

quence to the Phantom Clock.

Data transfer to and from the timekeeping function

is accomplished with a serial bit-stream under con-

trol of Chip Enable (CE), Output Enable (OE), and

WRITE Enable (WE). Initially, a READ cycle using

the CE and OE control of the clock starts the pat-

tern recognition sequence by moving the pointer to

the first bit of the 64-bit comparison register (see

Figure 10, page 16).

Next, 64 consecutive WRITE cycles are executed

using the CE and WE control of the device. These

64 WRITE cycles are used only to gain access to

the clock. Therefore, any address to the memory

is acceptable. However, the WRITE cycles gener-

ated to gain access to the Phantom Clock are also

writing data to a location in the mated RAM. The

preferred way to manage this requirement is to set

15/24

M48T248Y, M48T248V

Figure 10. Comparison Register Definition

Hex

Value

6

1

5

0

4

0

3

0

2

1

0

1

7

1

0

C5

3A

BYTE 0

BYTE 1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BYTE 2

BYTE 3

BYTE 4

BYTE 5

BYTE 6

A3

5C

C5

3A

A3

5C

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

BYTE 7

0

1

0

1

AI04262

19

Note: The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 10 . This pattern is

sent to the clock LSB to MSB.

16/24

M48T248Y, M48T248V

Clock Register Information

AM-PM/12/24 Mode

Clock information is contained in eight registers of

8 bits, each of which is sequentially accessed one

(1) bit at a time after the 64-bit pattern recognition

sequence has been completed. When updating

the clock registers, each must be handled in

groups of 8 bits. Writing and reading individual bits

within a register could produce erroneous results.

These READ/WRITE registers are defined in the

clock register map (see Table 10).

Bit 7 of the hours register is defined as the 12-hour

or 24-hour mode select bit. When it is high, the 12-

hour mode is selected. In the 12-hour mode, Bit 5

is the AM/PM bit with the logic high being “PM.” In

the 24-hour mode, Bit 5 is the second 10-hour bit

(20-23 hours).

Oscillator and Reset Bits

Bits 4 and 5 of the day register are used to control

the reset and oscillator functions. Bit 4 controls the

reset pin input. When the reset bit is set to logic '1,'

the Reset Input pin is ignored. When the reset bit

logic is set to '0,' a low input on the reset pin will

cause the device to abort data transfer without

changing data in the timekeeping registers. Reset

operates independently of all other inputs. Bit 5

controls the oscillator. When set to logic '0,' the os-

cillator turns on and the RTC/calendar begins to

increment.

Data contained in the clock registers is in Binary

Coded Decimal format (BCD). Reading and writing

the registers is always accomplished by stepping

through all eight registers, starting with Bit 0 of

Register 0 and ending with Bit 7 of Register 7.

Clock Accuracy

The RTC is guaranteed to keep time accuracy to

with ±1 minute per month at 25°C. The clock is fac-

tory-tuned with special calibration elements, and

does not require additional calibration. Moderate

temperature deviation will have a negligible effect

in most applications.

Zero Bits

Registers 1, 2, 3, 4, 5, and 6 contain one (1) or

more bits that will always read logic '0.' When writ-

ing to these locations, either a logic '1' or '0' is ac-

ceptable.

Table 10. Phantom Clock Register Map

Function/Range

BCD Format

Register

D7

D6

0.1 Seconds

10 Seconds

D5

D4

D3

D2

D1

D0

0

1

2

0.01 Seconds

Seconds

Minutes

00-99

00-59

0

10 Minutes

Minutes

10 /

A/P

01-12/

00-23

3

12/24

0

Hrs

Hours (24 Hour Format)

Hours

4

5

6

7

0

OSC

RST

0

Day of the Week

Date: Day of the Month

Month

Day

Date

Month

Year

01-7

01-31

01-12

00-99

10 date

0

10M

10 Years

Year

Keys: A/P = AM/PM Bit

RST = Reset Bit

12/24 = 12 or 24-hour mode Bit

OSC = Oscillator Bit

0 = Must be set to '0'

17/24

M48T248Y, M48T248V

Figure 11. Phantom Clock READ Cycle

WE

tRC

tCW

tRR

tCO

CE

OE

tOW

tOD

tODO

tOE

tOEE

tCOE

DATA OUTPUT VALID

Q

AI04259

Figure 12. Phantom Clock WRITE Cycle

OE

tWC

tWP

tWR

WE

tWR

tCW

CE

t

DH

tDH

tDS

D

DATA INPUT STABLE

AI04261

Figure 13. Phantom Clock Reset

tRST

RST

AI04235

18/24

M48T248Y, M48T248V

Table 11. Phantom Clock AC Characteristics (M48T248Y)

(1)

Symbol

Min

Typ

Max

Unit

ns

Parameter

READ Cycle Time

t

65

AVAV

RC

t

CE Access Time

55

ns

ELQV

CO

t

OE Access Time

CE to Output Low Z

OE to Output Low Z

ns

GLQV

OE

t

COE

5

ns

ELQX

t

ns

GLQX

OEE

(2)

CE to Output High Z

25

ns

t

EHQZ

OD

(2)

OE to Output High Z

READ Recovery

ns

t

GHQZ

ODO

t

10

65

RR

t

WC

WRITE Cycle Time

AVAV

(3)

t

WRITE Pulse Width

WRITE Recovery

55

10

30

0

ns

WLWH

t

WP

(4)

t

EHAX

DVEH

WHDX

WR

(5)

DS

t

Data Setup Time

t

(5)

t

Data Hold Time from WE

t

DH1

(5)

t

Data Hold Time from CE

CE Pulse Width

0

ns

t

EHDX

DH2

t

55

65

ELEH

CW

t

RST Pulse Width

RST

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. These parameters are sampled with a 5 pF load and are not 100% tested.

3. t is specified as the logical AND of CE and WE. t is measured from the latter of CE or WE going low to the earlier of CE or

WP

WE going high.

4. t is a function of the latter occurring edge of WE or CE.

WR

5. t and t are measured from the earlier of CE or WE going high.

DH

DS

19/24

M48T248Y, M48T248V

Table 12. Phantom Clock AC Characteristics (M48T248V)

(1)

Symbol

Min

Typ

Max

Unit

ns

Parameter

READ Cycle Time

t

85

AVAV

RC

t

CE Access Time

85

ns

ELQV

CO

t

OE Access Time

CE to Output Low Z

OE to Output Low Z

ns

GLQV

OE

t

COE

5

ns

ELQX

t

ns

GLQX

OEE

(2)

CE to Output High Z

30

ns

t

EHQZ

OD

(2)

OE to Output High Z

READ Recovery

ns

t

GHQZ

ODO

t

20

85

RR

t

WC

WRITE Cycle Time

AVAV

(3)

t

WRITE Pulse Width

WRITE Recovery

60

20

35

0

ns

WLWH

t

WP

(4)

t

EHAX

DVEH

WHDX

WR

(5)

DS

t

Data Setup Time

t

(5)

t

Data Hold Time from WE

t

DH1

(5)

t

Data Hold Time from CE

CE Pulse Width

0

ns

t

EHDX

DH2

t

65

85

ELEH

CW

t

RST Pulse Width

RST

Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).

A

CC

2. These parameters are sampled with a 5 pF load and are not 100% tested.

3. t is specified as the logical AND of CE and WE. t is measured from the latter of CE or WE going low to the earlier of CE or

WP

WE going high.

4. t is a function of the latter occurring edge of WE or CE.

WR

5. t and t are measured from the earlier of CE or WE going high.

DH

DS

20/24

M48T248Y, M48T248V

PACKAGE MECHANICAL INFORMATION

Figure 14. PMDIP32 – 32-pin Plastic Module DIP, Package Outline

A

A1

e1

L

C

eA

S

B

e3

D

N

1

E

PMDIP

Note: Drawing is not to scale.

Table 13. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data

mm

inches

Min

Symb

Typ

Min

9.27

0.38

0.43

0.20

42.42

18.03

2.29

34.29

14.99

3.05

1.91

32

Max

9.52

–

Typ

Max

0.375

–

A

A1

B

0.365

0.015

0.017

0.008

1.670

0.710

0.090

1.350

0.590

0.120

0.075

32

0.59

0.33

43.18

18.80

2.79

41.91

16.00

3.81

2.79

0.023

0.013

1.700

0.740

0.110

1.650

0.630

0.150

0.110

C

D

E

e1

e3

eA

L

S

N

21/24

M48T248Y, M48T248V

PART NUMBERING

Table 14. Ordering Information Example

Example:

M48T

248Y

–70

PM

1

TR

Device Type

M48T

Supply Voltage and Write Protect Voltage

248Y = V

248V = V

= 4.5 to 5.5V; V

= 4.25 to 4.50V

= 2.80 to 2.97V

CC

PFD

= 3.0 to 3.6V; V

Speed

–70 = 70ns (M48T248Y)

–85 = 85ns (M48T248V)

Package

PM = PMDIP32

Temperature Range

1 = 0 to 70°C

Shipping Method for SOIC

blank = Tubes

TR = Tape & Reel

For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,

please contact the ST Sales Office nearest to you.

22/24

M48T248Y, M48T248V

REVISION HISTORY

Table 15. Document Revision History

Date

Rev. #

1.0

Revision Details

June 2001

28-Mar-03

First Issue

v2.2 template applied; test condition updated (Table 9)

2.0

23/24

M48T248Y, M48T248V

M48T248, M48T248Y, M48T248V, 48T248, 48T248Y, 48T248V,

T248, T248Y, T248V, TIMEKEEPER, TIMEKEEPER, TIMEKEEP-

ER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEP-

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Power-fail, Power-fail,

Power-fail, Power-fail, Power-fail, Power-fail, Power-fail, Power-

fail, Power-fail, Power-fail, Comparator, Comparator, Comparator,

Comparator, Comparator, Comparator, Comparator, Comparator,

Comparator, Comparator, Crystal, Crystal, Crystal, Crystal, Crys-

tal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crys-

tal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal,

Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal, Crystal,

Crystal, Crystal, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Battery, Battery, Battery, Battery, Battery,

Battery, Battery, Battery, Battery, Battery, Battery, Switchover,

Switchover, Switchover, Switchover, Switchover, Switchover,

Switchover, Switchover, Switchover, Switchover, Backup, Backup,

Backup, Backup, Backup, Backup, Backup, Backup, Backup, Back-

up, Backup, Backup, Backup, Backup, Backup, Backup, Backup,

Backup, Backup, Backup,5V,5V,5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,

5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V,

5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 5V, 3.3V, 3.3V,

3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V, 3.3V

ER,

TIMEKEEPER,

TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, TIMEKEEPER,

TIMEKEEPER, TIMEKEEPER, TIMEKEEPER, NVRAM, NVRAM,

NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM,

NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, SRAM,

SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM, SRAM,

SRAM, SRAM, SRAM, SRAM, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC, RTC,

RTC, RTC, RTC, RTC, Transparent, Transparent, Transparent,

Transparent, Transparent, Transparent, Transparent, Transparent,

Transparent, Transparent, Clock, Clock, Clock, Clock, Clock,

Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock, Clock,

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is registered trademark of STMicroelectronics

All other names are the property of their respective owners.

STMicroelectronics GROUP OF COMPANIES

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Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.

www.st.com

24/24


型号：	M48T248V
厂家：	ST
描述：	5.0 or 3.3V, 1024K TIMEKEEPER SRAM with PHANTOM 5.0或3.3V ， 1024K TIMEKEEPER SRAM ，带幻像静态存储器
文件：	总24页 (文件大小：289K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M48T248V [STMICROELECTRONICS]

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