M48T128Y-80PM1 [STMICROELECTRONICS]
5.0 or 3.3 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM; 5.0或3.3 V ， 1兆位（ 128 KB ×8 ） TIMEKEEPER® SRAM
| 型号： | M48T128Y-80PM1 |
| 厂家： | 
ST |
| 描述： | 5.0 or 3.3 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM |
| 文件： | 总23页 (文件大小：364K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T128Y
M48T128V
5.0 or 3.3 V, 1 Mbit (128 Kb x 8) TIMEKEEPER® SRAM
Features
■ Integrated, ultra low power SRAM, real-time
clock, power-fail control circuit, battery, and
crystal
■ BCD coded year, month, day, date, hours,
minutes, and seconds
■ Automatic power-fail chip deselect and WRITE
32
protection
1
■ WRITE protect voltages
(V
= power-fail deselect voltage):
PMDIP32 module (PM)
PFD
– M48T128Y: V = 4.5 to 5.5 V
CC
4.1 V ≤ V
≤ 4.5 V
PFD
– M48T128V: V = 3.0 to 3.6 V
CC
2.7 V ≤ V
≤ 3.0 V
PFD
(contact the ST sales office for availability)
■ Conventional SRAM operation; unlimited
WRITE cycles
■ Software-controlled clock calibration for high
accuracy applications
■ 10 years of data retention and clock operation
in the absence of power
■ Self-contained battery and crystal in the DIP
package
■ Pin and function compatible with JEDEC
standard 128 K x 8 SRAMs
■ RoHS compliant
– Lead-free second level interconnect
June 2010
Doc ID 5746 Rev 6
1/23
www.st.com
1
Contents
M48T128Y, M48T128V
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1
2.2
2.3
READ mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Clock operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.1
3.2
3.3
3.4
3.5
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 14
4
5
6
7
8
9
Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Environmental information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
READ mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE mode AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Operating and AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power down/up trip points DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PMDIP32 – 32-pin plastic module DIP, package mechanical data. . . . . . . . . . . . . . . . . . . 19
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Doc ID 5746 Rev 6
3/23
List of figures
M48T128Y, M48T128V
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
DIP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WRITE enable controlled, WRITE AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chip enable controlled, WRITE AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11. Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Recycling symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Description
1
Description
®
The M48T128Y/V TIMEKEEPER RAM is a 128 Kb x 8 non-volatile static RAM and real-
time clock. The special DIP package provides a fully integrated battery-backed memory and
real-time clock solution. The M48T128Y/V directly replaces industry standard 128 Kb x 8
SRAM.
It also provides the non-volatility of Flash without any requirement for special WRITE timing
or limitations on the number of WRITEs that can be performed. The 32-pin, 600 mil DIP
hybrid houses a controller chip, SRAM, quartz crystal, and a long-life lithium button cell in a
single package.
Figure 1.
Logic diagram
V
CC
17
8
A0-A16
DQ0-DQ7
W
E
M48T128Y
M48T128V
G
V
SS
AI02244
Table 1.
Signal names
A0-A16
Address inputs
Data inputs / outputs
Chip enable
DQ0-DQ7
E
G
Output enable
WRITE enable
Supply voltage
Ground
W
VCC
VSS
NC
Not connected internally
Doc ID 5746 Rev 6
5/23
Description
M48T128Y, M48T128V
Figure 2.
DIP connections
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A15
30 NC
29
W
28 A13
27 A8
A6
A5
26 A9
A4
M48T128Y 25 A11
M48T128V
A3
24
23 A10
22
G
A2 10
A1 11
E
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
V
16
SS
AI02245
Figure 3.
Block diagram
8 x 8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
A0-A16
POWER
DQ0-DQ7
131,064 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
W
G
V
PFD
V
V
CC
SS
AI01804
6/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Operation modes
2
Operation modes
Figure 3 on page 6 illustrates the static memory array and the quartz controlled clock
oscillator. The clock locations contain the year, month, date, day, hour, minute, and second
in 24 hour BCD format. Corrections for 28, 29 (leap year - valid until 2100), 30, and 31 day
months are made automatically. Byte 1FFF8h is the clock control register. This byte controls
user access to the clock information and also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1FFF8h) are not the actual clock counters, they are memory locations
consisting of BiPORT™ READ/WRITE memory cells within the static RAM array. The
M48T128Y/V includes a clock control circuit which updates the clock bytes with current
information once per second. The information can be accessed by the user in the same
manner as any other location in the static memory array. The M48T128Y/V also has its own
power-fail detect circuit. This control circuitry constantly monitors the supply voltage for an
out of tolerance condition. When V is out of tolerance, the circuit write protects the
CC
®
TIMEKEEPER register data and external SRAM, providing data security in the midst of
unpredictable system operation. As V falls below the battery backup switchover voltage
CC
(V ), the control circuitry automatically switches to the battery, maintaining data and clock
SO
operation until valid power is restored.
Table 2.
Mode
Operating modes
VCC
E
G
W
DQ0-DQ7
Power
Deselect
WRITE
READ
VIH
VIL
VIL
VIL
X
X
X
X
VIL
VIH
VIH
X
High Z
DIN
Standby
Active
4.5 to 5.5 V
or
VIL
VIH
X
DOUT
High Z
High Z
High Z
Active
3.0 to 3.6 V
READ
Active
Deselect VSO to VPFD (min)(1)
CMOS standby
Battery backup mode
(1)
Deselect
≤ VSO
X
X
X
1. See Table 11 on page 18 for details.
Note:
X = V or V ; V = battery backup switchover voltage.
IH IL SO
Doc ID 5746 Rev 6
7/23
Operation modes
M48T128Y, M48T128V
2.1
READ mode
The M48T128Y/V is in the READ mode whenever W (WRITE enable) is high and E (chip
enable) is low. The unique address specified by the 17 address inputs defines which one of
the 131,072 bytes of data is to be accessed.
Valid data will be available at the data I/O pins within t
(address access time) after the
AVQV
last address input signal is stable, providing the E and G access times are also satisfied. If
the E and G access times are not met, valid data will be available after the latter of the chip
enable access times (t
) or output enable access time (t
). The state of the eight
ELQV
GLQV
three-state data I/O signals is controlled by E and G. If the outputs are activated before
, the data lines will be driven to an indeterminate state until t . If the address inputs
t
AVQV
AVQV
are changed while E and G remain active, output data will remain valid for t
data hold time) but will go indeterminate until the next address access.
(output
AXQX
Figure 4.
READ mode AC waveforms
tAVAV
A0-A16
VALID
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Note:
WE = High.
Table 3.
READ mode AC characteristics
Parameter(1)
M48T128Y
–70
M48T128V
–85
Symbol
Unit
Min
Max
Min
Max
tAVAV
tAVQV
tELQV
tGLQV
READ cycle time
70
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to output valid
Chip enable low to output valid
Output enable low to output valid
Chip enable low to output transition
70
70
40
85
85
55
(2)
tELQX
5
5
5
5
(2)
tGLQX
Output enable low to output transition
Chip enable high to output Hi-Z
(2)
tEHQZ
25
25
30
30
(2)
tGHQZ
Output enable high to output Hi-Z
Address transition to output transition
tAXQX
10
5
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. CL = 5 pF.
8/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Operation modes
2.2
WRITE mode
The M48T128Y/V is in the WRITE mode whenever W (WRITE enable) and E (chip enable)
are low state after the address inputs are stable.
The start of a WRITE is referenced from the latter occurring falling edge of W or E. A WRITE
is terminated by the earlier rising edge of W or E. The addresses must be held valid
throughout the cycle. E or W must return high for a minimum of t
from chip enable or
EHAX
t
from WRITE enable prior to the initiation of another READ or WRITE cycle. Data-in
WHAX
must be valid t
prior to the end of WRITE and remain valid for t
afterward. G
DVWH
WHDX
should be kept high during WRITE cycles to avoid bus contention; although, if the output bus
has been activated by a low on E and G a low on W will disable the outputs t
falls.
after W
WLQZ
Figure 5.
WRITE enable controlled, WRITE AC waveform
tAVAV
VALID
A0-A16
tAVWH
tAVEL
tWHAX
E
tWLWH
tAVWL
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
Figure 6.
Chip enable controlled, WRITE AC waveforms
tAVAV
A0-A16
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02383
Doc ID 5746 Rev 6
9/23
Operation modes
Table 4.
M48T128Y, M48T128V
M48T128V
WRITE mode AC characteristics
Parameter(1)
M48T128Y
–70
Symbol
–85
Unit
Min
Max
Min
Max
tAVAV
tAVWL
tAVEL
WRITE cycle time
70
0
85
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address valid to WRITE enable low
Address valid to chip enable low
WRITE enable pulse width
0
0
tWLWH
tELEH
tWHAX
tEHAX
tDVWH
tDVEH
tWHDX
tEHDX
50
55
5
60
65
5
Chip enable low to chip enable 1 high
WRITE enable high to address transition
Chip enable high to address transition
Input valid to WRITE enable high
Input valid to chip enable high
10
30
30
5
15
35
35
5
WRITE enable high to input transition
Chip enable high to input transition
WRITE enable low to output Hi-Z
Address valid to WRITE enable high
Address valid to chip enable high
WRITE enable high to output transition
10
15
(2)(3)
tWLQZ
25
30
tAVWH
60
60
5
70
70
5
tAVEH
(2)(3)
tWHQX
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where
noted).
2. CL = 5 pF.
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
2.3
Data retention mode
With valid V applied, the M48T128Y/V operates as a conventional BYTEWIDE™ static
CC
RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write
protecting itself when V falls within the V
(max), V
(min) window. All outputs
CC
PFD
PFD
become high impedance, and all inputs are treated as “Don't care.”
Note:
A power failure during a WRITE cycle may corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's content. At voltages below V
(min), the
PFD
user can be assured the memory will be in a write protected state, provided the V fall time
CC
is not less than t . The M48T128Y/V may respond to transient noise spikes on V that
F
CC
reach into the deselect window during the time the device is sampling V . Therefore,
CC
decoupling of the power supply lines is recommended.
When V drops below V , the control circuit switches power to the internal battery,
CC
SO
preserving data and powering the clock. The internal energy source will maintain data in the
M48T128Y/V for an accumulated period of at least 10 years at room temperature. As
system power rises above V , the battery is disconnected, and the power supply is
SO
switched to external V . Deselect continues for t
after V reaches V
(max).
CC
REC
CC
PFD
10/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Clock operations
3
Clock operations
3.1
Reading the clock
®
Updates to the TIMEKEEPER registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT™ TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, D6 in the control register (1FFF8h).
As long as a '1' remains in that position, updating is halted. After a halt is issued, the
registers reflect the count; that is, the day, date, and time that were current at the moment
the halt command was issued. All of the TIMEKEEPER registers are updated
simultaneously. A halt will not interrupt an update in progress. Updating is within a second
after the bit is reset to a '0.'
3.2
3.3
Setting the clock
Bit D7 of the control register (1FFF8h) is the WRITE bit. Setting the WRITE bit to a '1,' like
the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them
with the correct day, date, and time data in 24-hour BCD format (see Table 5 on page 12).
Resetting the WRITE bit to a '0' then transfers the values of all time registers 1FFFFh-
1FFF9h to the actual TIMEKEEPER counters and allows normal operation to resume. After
the WRITE bit is reset, the next clock update will occur one second later.
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The STOP bit is located at bit D7 within 1FFF9h. Setting it to a '1' stops the
oscillator. The M48T128Y/V is shipped from STMicroelectronics with the STOP bit set to a
'1.' When reset to a '0,' the M48T128Y/V oscillator starts after one second.
Doc ID 5746 Rev 6
11/23
Clock operations
Table 5.
M48T128Y, M48T128V
Register map
Data
D4
Function/range
BCD format
Address
D7
D6
D5
D3
D2
D1
Year
D0
1FFFFh
1FFFEh
1FFFDh
1FFFCh
1FFFBh
1FFFAh
1FFF9h
1FFF8h
10 years
Year
Month
Date
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 M
0
Month
Date
10 date
0
FT
0
0
0
Day
Day
0
10 hours
10 minutes
Hours
Minutes
Seconds
Hours
Minutes
Seconds
Control
0
ST
W
10 seconds
S
R
Calibration
Keys:
S = SIGN bit
R = READ bit
W = WRITE bit
ST = STOP bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
3.4
Calibrating the clock
The M48T128Y/V is driven by a quartz controlled oscillator with a nominal frequency of
32,768 Hz. The devices are factory calibrated at 25 °C and tested for accuracy. Clock
accuracy will not exceed 35 ppm (parts per million) oscillator frequency error at 25 °C, which
equates to about 1.53 minutes per month. When the Calibration circuit is properly
employed, accuracy improves to better than +1/–2 ppm at 25 °C. The oscillation rate of
crystals changes with temperature (see Figure 7 on page 13). The M48T128Y/V design
employs periodic counter correction. The calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 128 stage, as shown in Figure 8 on page 13.
The number of times pulses are blanked (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five calibration bits found in the
control register. Adding counts speeds the clock up, subtracting counts slows the clock
down. The calibration bits occupy the five lower order bits (D4-D0) in the control register
1FFF8h. These bits can be set to represent any value between 0 and 31 in binary form. Bit
D5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration
occurs within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step
has the effect of adding 512 or subtracting 256 oscillator cycles for every 125, 829, 120
actual oscillator cycles, that is +4.068 or –2.034 ppm of adjustment per calibration step in
the calibration register. Assuming that the oscillator is running at exactly 32,768 Hz, each of
the 31 increments in the calibration byte would represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75 minutes per month.
12/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Clock operations
One method is available for ascertaining how much calibration a given M48T128Y/V may
require. This involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time.
Calibration values, including the number of seconds lost or gained in a given period, can be
found in the STMicroelectronics application note, “TIMEKEEPER calibration.”
This allows the designer to give the end user the ability to calibrate the clock as the
environment requires, even if the final product is packaged in a non-user serviceable
enclosure. The designer could provide a simple utility that accesses the calibration byte. For
example, a deviation of 21 seconds slow over a period of 30 days would indicate a –8 ppm
oscillator frequency error, requiring a +2(WR100010) to be loaded into the calibration byte
for correction.
Figure 7.
Crystal accuracy across temperature
ppm
20
0
-20
-40
-60
-80
-100
2
ΔF
F
ppm
C2
= -0.038
(T - T0)
10%
T0 = 25 °C
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
°C
AI02124
Figure 8.
Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Doc ID 5746 Rev 6
13/23
Clock operations
M48T128Y, M48T128V
3.5
VCC noise and negative going transients
I
transients, including those produced by output switching, can produce voltage
CC
fluctuations, resulting in spikes on the V bus. These transients can be reduced if
CC
capacitors are used to store energy which stabilizes the V bus. The energy stored in the
CC
bypass capacitors will be released as low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in
Figure 9) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal SRAM operation, power cycling can
generate negative voltage spikes on V that drive it to values below V by as much as
CC
SS
one volt. These negative spikes can cause data corruption in the SRAM while in battery
backup mode. To protect from these voltage spikes, it is recommended to connect a
Schottky diode from V to V (cathode connected to V , anode to V ). Schottky diode
CC
SS
CC
SS
1N5817 is recommended for through hole and MBRS120T3 is recommended for surface
mount.
Figure 9.
Supply voltage protection
V
CC
V
CC
0.1µF
DEVICE
V
SS
AI02169
14/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Maximum ratings
4
Maximum ratings
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 6.
Symbol
Absolute maximum ratings
Parameter
Value
Unit
TA
Ambient operating temperature
0 to 70
–40 to 85
260
°C
°C
°C
V
TSTG
Storage temperature (VCC off, oscillator off)
Lead solder temperature for 10 seconds
Input or output voltages
(1)(2)
TSLD
VIO
–0.3 to 7
–0.3 to 7
–0.3 to 4.6
20
M48T128Y
M48T128V
V
VCC
Supply voltage
V
IO
Output current
mA
W
PD
Power dissipation
1
1. Soldering temperature of the IC leads is to not exceed 260 °C for 10 seconds. In order to protect the lithium
battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 °C.
Furthermore, the devices shall not be exposed to IR reflow.
2. For DIP packaged devices, ultrasonic vibrations should not be used for post-solder cleaning to avoid
damaging the crystal.
Caution:
Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup
mode.
Doc ID 5746 Rev 6
15/23
DC and AC parameters
M48T128Y, M48T128V
5
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC characteristic
tables are derived from tests performed under the measurement conditions listed in the
relevant tables. Designers should check that the operating conditions in their projects match
the measurement conditions when using the quoted parameters.
Table 7.
Operating and AC measurement conditions
Parameter
Supply voltage (VCC
M48T128Y
M48T128V
Unit
)
4.5 to 5.5
0 to 70
100
3.0 to 3.6
0 to 70
50
V
°C
pF
ns
V
Ambient operating temperature (TA)
Load capacitance (CL)
Input rise and fall times
≤ 5
≤ 5
Input pulse voltages
0 to 3
1.5
0 to 3
1.5
Input and output timing ref. voltages
V
Note:
Output Hi-Z is defined as the point where data is no longer driven.
Figure 10. AC testing load circuit
650Ω
DEVICE
UNDER
TEST
1.75V
C
= 100pF
L
or 50pF(1)
C
includes JIG capacitance
L
AI03630
1. 50 pF for M48T128V.
Table 8.
Symbol
CIN
Capacitance
Parameter(1)(2)
Input capacitance
Input / output capacitance
Min
Max
Unit
-
-
20
20
pF
pF
(3)
CIO
1. Effective capacitance measured with power supply at 5 V. Sampled only, not 100% tested.
2. At 25 °C, f = 1 MHz.
3. Outputs deselected.
16/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
DC and AC parameters
M48T128V
Table 9.
Symbol
ILI
DC characteristics
M48T128Y
–70
Parameter
Test condition(1)
–85
Unit
Min
Max
Min
Max
Input leakage current
Output leakage current
Supply current
0 V ≤ VIN ≤ VCC
0 V ≤ VOUT ≤ VCC
Outputs open
E = VIH
2
2
2
µA
µA
mA
mA
mA
V
(2)
ILO
2
ICC
ICC1
ICC2
VIL
95
50
4
Supply current (standby) TTL
Supply current (standby) CMOS
Input low voltage
8
4
E = VCC – 0.2 V
3
–0.3
2.2
0.8
–0.3
2.2
0.4
VIH
Input high voltage
VCC + 0.3
0.4
VCC + 0.3
0.4
V
VOL
VOH
Output low voltage
IOL = 2.1 mA
IOH = –1 mA
V
Output high voltage
2.4
2.2
V
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. Outputs deselected.
Doc ID 5746 Rev 6
17/23
DC and AC parameters
M48T128Y, M48T128V
Figure 11. Power down/up mode AC waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SS
tDR
tF
tREC
tFB
tRB
DON'T CARE
RECOGNIZED
RECOGNIZED
INPUTS
HIGH-Z
OUTPUTS
VALID
VALID
AI03612
Table 10. Power down/up AC characteristics
Symbol
Parameter(1)
Min
Max
Unit
(2)
tF
VPFD (max) to VPFD (min) VCC fall time
VPFD (min) to VSS VCC fall time
300
10
0
µs
µs
µs
µs
ms
(3)
tFB
tR
VPFD (min) to VPFD (max) VCC rise time
VSS to VPFD (min) VCC rise time
VPFD (max) to inputs recognized
tRB
1
tREC
40
200
1. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
V
CC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
Table 11. Power down/up trip points DC characteristics
Symbol
Parameter(1)(2)
Min
Typ
Max
Unit
M48T128Y
M48T128V
M48T128Y
M48T128V
4.1
2.7
4.35
2.9
4.5
3.0
V
VPFD
Power-fail deselect voltage
V
3.0
V
V
VSO
Battery backup switchover voltage
Expected data retention time
V
PFD – 100 mV
(3)
tDR
10
YEARS
1. All voltages referenced to VSS
.
2. Valid for ambient operating temperature: TA = 0 to 70 °C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where noted).
3. At 25 °C; VCC = 0 V.
18/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Package mechanical data
6
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
®
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at: www.st.com.
®
ECOPACK is an ST trademark.
Figure 1. PMDIP32 – 32-pin plastic module DIP, package outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Note:
Drawing is not to scale.
Table 12. PMDIP32 – 32-pin plastic module DIP, package mechanical data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
A1
B
9.27
0.38
9.52
–
0.365
0.015
0.017
0.008
1.670
0.710
0.090
0.375
–
0.43
0.59
0.33
43.18
18.80
2.79
0.023
0.013
1.700
0.740
0.110
C
0.20
D
42.42
18.03
2.29
E
e1
e3
eA
L
38.1
1.5
14.99
3.05
1.91
32
16.00
3.81
2.79
0.590
0.120
0.075
32
0.630
0.150
0.110
S
N
Doc ID 5746 Rev 6
19/23
Environmental information
M48T128Y, M48T128V
7
Environmental information
Figure 12. Recycling symbols
This product contains a non-rechargeable lithium (lithium carbon monofluoride chemistry)
button cell battery fully encapsulated in the final product.
Recycle or dispose of batteries in accordance with the battery manufacturer's instructions
and local/national disposal and recycling regulations.
Please refer to the following web site address for additional information regarding
compliance statements and waste recycling.
Go to www.st.com/nvram, then select "Lithium Battery Recycling" from "Related Topics".
20/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
Part numbering
8
Part numbering
Table 13. Ordering information scheme
Example:
M48T
128Y
–70
PM
1
Device type
M48T
Supply voltage and write protect voltage
128Y = VCC = 4.5 to 5.5 V; VPFD = 4.1 to 4.5 V
128V(1) = VCC = 3.0 to 3.6 V; VPFD = 2.7 to 3.0 V
Speed
–70 = 70 ns (128Y)
–85 = 85 ns (128V)
Package
PM = PMDIP32
Temperature range
1 = 0 to 70°C
Shipping method
blank = Ecopack® package, tubes
1. Contact local ST sales office for availability of 3.3 V version.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Doc ID 5746 Rev 6
21/23
Revision history
M48T128Y, M48T128V
9
Revision history
Table 14. Document revision history
Date
Revision
Changes
Jun-1998
31-Jan-2000
30-Mar-2000
1
First issue
1.1
1.2
Calibrating the clock paragraph changed
Storage temperature changed (Table 6)
Reformatted; temperature information added to tables (Table 8, 9, 3, 4,
10, 11)
20-Jul-2001
2
21-Sep-2001
23-May-2002
07-Aug-2002
28-Mar-2003
06-Aug-2004
22-Feb-2005
2.1
2.2
2.3
3
Corrected speed grade in ordering information
Add countries to disclaimer; add marketing status
Refine marketing status text
v2.2 template applied; test condition updated (Table 11)
Reformatted; updated register map (Table 5)
IR reflow update (Table 6)
4
5
Updated Features, Section 4, Table 12, 13; added ECOPACK® text to
Section 6; added Section 7: Environmental information; reformatted
document.
18-Jun-2010
6
22/23
Doc ID 5746 Rev 6
M48T128Y, M48T128V
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Doc ID 5746 Rev 6
23/23
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