M48T129V-70PM1 [STMICROELECTRONICS]
3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM; 3.3V - 5V 1兆位128KB X8 TIMEKEEPER SRAM
| 型号： | M48T129V-70PM1 |
| 厂家： | 
ST |
| 描述： | 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| 文件： | 总22页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T129Y
M48T129V
3.3V-5V 1 Mbit (128Kb x8) TIMEKEEPER SRAM
■ INTEGRATED ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL CONTROL
CIRCUIT, BATTERY AND CRYSTAL
■ YEAR 2000 COMPLIANT
■ BCD CODED CENTURY, YEAR, MONTH,
DAY, DATE, HOURS, MINUTES, and
SECONDS
32
1
PMDIP32 (PM)
Module
■ BATTERY LOW WARNING FLAG
■ AUTOMATIC POWER-FAIL CHIP DESELECT
SNAPHAT (SH)
Battery
and WRITE PROTECTION
■ TWO WRITE PROTECT VOLTAGES:
(V
= Power-fail Deselect Voltage)
PFD
– M48T129Y: 4.2V ≤ V
≤ 4.5V
≤ 3.0V
PFD
PFD
– M48T129V: 2.7V ≤ V
■ CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
■ SOFTWARE CONTROLLED CLOCK
CALIBRATION for HIGH ACCURACY
APPLICATIONS
TSOP32
(8 x 20mm)
SOH44
Surface Mount Chip Set Solution (CS)
■ 10 YEARS of DATA RETENTION and CLOCK
OPERATION in the ABSENCE of POWER
■ SELF CONTAINED BATTERY and CRYSTAL
in DIP PACKAGE
Figure 1. Logic Diagram
■ MICROPROCESSOR POWER-ON RESET
V
(Valid even during battery back-up mode)
CC
■ PROGRAMMABLE ALARM OUTPUT ACTIVE
in BATTERY BACK-UP MODE
17
8
■ SURFACE MOUNT CHIP SET PACKAGING
INCLUDES a 44-PIN SOIC and a 32-LEAD
TSOP (SNAPHAT TOP TO BE ORDERED
SEPARATELY)
A0-A16
DQ0-DQ7
W
E
M48T129Y
M48T129V
RST
■ SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP WHICH
CONTAINS the BATTERY and CRYSTAL
IRQ/FT
G
■ SNAPHAT HOUSING (BATTERY/CRYSTAL)
IS REPLACEABLE
V
SS
AI02260
April 2000
1/22
M48T129Y, M48T129V
Figure 2. DIP Connections
Table 1. Signal Names
A0-A16
Address Inputs
RST
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
DQ0-DQ7
Data Inputs / Outputs
Chip Enable Input
CC
31 A15
E
30 IRQ/FT
29
W
G
Output Enable Input
Write Enable Input
28 A13
27 A8
A6
W
A5
26 A9
RST
Reset Output (open drain)
A4
M48T129Y 25 A11
M48T129V
A3
24
23 A10
22
G
Interrupt / Frequency Test Output
(open drain)
IRQ/FT
A2 10
A1 11
E
V
V
Supply Voltage
Ground
CC
SS
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
V
16
SS
AI02261
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Value
0 to 70
Unit
°C
°C
V
T
A
T
Storage Temperature (V Off, Oscillator Off)
–40 to 85
STG
CC
V
–0.3 to V +0.3
Input or Output Voltages
Supply Voltage
IO
CC
M48T129Y
M48T129V
–0.3 to 7.0
V
V
CC
–0.3 to 4.6
V
I
Output Current
20
1
mA
W
O
P
Power Dissipation
D
Note: 1. Stresses greater than those listed under ”Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
DESCRIPTION
For surface mount environments ST provides a
Chip Set solution consisting of a 44 pin 330mil
SOIC TIMEKEEPER Supervisor (M48T201V/Y)
and a 32 pin TSOP (8 x 20mm) LPSRAM
(M68Z128/W) packages.
The 44 pin 330mil SOIC provides sockets with
gold plated contacts at both ends for direct con-
nection to a separate SNAPHAT housing contain-
ing the battery.
The M48T129Y/V TIMEKEEPER RAM is a 128Kb
x 8 non-volatile static RAM and real time clock,
with programmable alarms and a watchdog timer.
The special DIP package provides a fully integrat-
ed battery back-up memory and real time clock so-
lution. The M48T129Y/V directly replaces industry
standard 128Kb x 8 SRAM. It also provides the
non-volatility of Flash without any requirement for
special write timing or limitations on the number of
writes that can be performed.
The unique design allows the SNAPHAT battery
package to be mounted on top of the SOIC pack-
age after the completion of the surface mount pro-
2/22
M48T129Y, M48T129V
Figure 3. Block Diagram
16 x 8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
RST
IRQ/FT
POWER
A0-A16
131,056 x 8
SRAM ARRAY
LITHIUM
CELL
DQ0-DQ7
VOLTAGE SENSE
AND
E
V
PFD
W
G
SWITCHING
CIRCUITRY
V
V
CC
SS
AI02583
cess. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to
the high temperatures required for device surface-
mounting. The SNAPHAT housing is keyed to pre-
vent reverse insertion.
1FFF8h is the clock control register. This byte con-
trols user access to the clock information and also
stores the clock calibration setting.
Byte 1FFF7h contains the watchdog timer setting.
The watchdog timer can generate either a reset or
an interrupt, depending on the state of the Watch-
dog Steering bit (WDS). Bytes 1FFF6h-1FFF2h in-
clude bits that, when programmed, provide for
clock alarm functionality. Alarms are activated
when the register content matches the month,
date, hours, minutes, and seconds of the clock
registers. Byte 1FFF1h contains century informa-
tion. Byte 1FFF0h contains additional flag informa-
tion pertaining to the watchdog timer, the alarm
condition and the battery status. The M48T129Y/V
also has its own Power-Fail Detect circuit. This
control circuitry constantly monitors the supply
voltage for an out of tolerance condition. When
The SNAPHAT battery package is shipped sepa-
rately in plastic anti-static tubes or in Tape & Reel
form. The part number is ”M4Txx-BR12SH1”.
The 32 pin 600 mil DIP Hybrid houses a controller
chip, SRAM, quartz crystal, and a long life lithium
button cell in a single package.
Figure 3 illustrates the static memory array and the
quartz controlled clock oscillator. The clock loca-
tions contain the century, year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year), 30, and 31 day
months are made automatically. The nine clock
bytes (1FFFFh-1FFF9h and 1FFF1h) are not the
actual clock counters, they are memory locations
consisting of BiPORT read/write memory cells
within the static RAM array.
The M48T129Y/V includes a clock control circuit
which updates the clock bytes with current infor-
mation once per second. The information can be
accessed by the user in the same manner as any
other location in the static memory array. Byte
V
is out of tolerance, the circuit write protects
CC
the TIMEKEEPER register data and external
SRAM, providing data security in the midst of un-
predictable system operation. As V
falls, the
CC
control circuitry automatically switches to the bat-
tery, maintaining data and clock operation until
valid power is restored.
3/22
M48T129Y, M48T129V
(1)
Figure 4. Hardware Hookup for SMT Chip Set
SNAPHAT (3)
BATTERY/CRYSTAL
A0-A16
A0-A16
32,768 Hz
CRYSTAL
V
V
OUT
CC
0.1µF
LITHIUM
CELL
M48T201Y/V (2)
5V
V
CC
M68Z128/W (2)
E
0.1µF
W
G
ECON
E
W
G
WDI
GCON
RST
RSTIN1
RSTIN2
IRQ/FT
SQW
V
SS
V
SS
DQ0-DQ7
DQ0-DQ7
AI03632
Note: 1. For pin connections, see individual data sheets for M48T201Y/V and M68Z128/W at www.st.com.
2. For 5V, M48T129Y (M48T201Y + M68Z128). For 3.3V, M48T129V (M48T201V + M68Z128W).
3. SNAPHAT Top ordered separately.
READ MODE
Data Hold Time) but will go indeterminate until the
next Address Access.
The M48T129Y/V is in the Read Mode whenever
W (Write Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed. Valid data will be
WRITE MODE
The M48T129Y/V is in the Write Mode whenever
W (Write Enable) and E (Chip Enable) are low
state after the address inputs are stable.
available at the Data I/O pins within t
(Ad-
AVQV
dress Access Time) after the last address input
signal is stable, providing the E and G access
times are also satisfied. If the E and G access
times are not met, valid data will be available after
The start of a write is referenced from the latter oc-
curring falling edge of W orE. A write is terminated
by the earlier rising edge of W or E. The addresses
must be held valid throughout the cycle. E or W
the latter of the Chip Enable Access Times (t
)
ELQV
must return high for a minimum of t
from Chip
EHAX
or Output Enable Access Time (t
).
GLQV
Enable or t
from Write Enable prior to the ini-
WHAX
tiation of another read or write cycle. Data-in must
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activat-
be valid t
valid for t
prior to the end of write and remain
afterward. G should be kept high
DVWH
WHDX
ed before t
, the data lines will be driven to an
AVQV
during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a
low on E and G a low on W will disable the outputs
indeterminate state until t
. If the Address In-
AVQV
puts are changed while E and G remain active,
output data will remain valid for t (Output
AXQX
t
after W falls.
WLQZ
4/22
M48T129Y, M48T129V
(1)
Table 3. Operating Modes
V
Mode
Deselect
Write
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
X
High Z
IH
4.5V to 5.5V
or
3.0V to 3.6V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
OUT
Read
Active
IL
V
Read
High Z
High Z
High Z
Active
IH
(2)
Deselect
X
X
X
CMOS Standby
V
to V
(min)
PFD
SO
(2)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: 1. X = V or V ; V = Battery Back-up Switchover Voltage.
SO
IH
IL
2. See Table 7 for details.
DATA RETENTION MODE
Table 4. AC Measurement Conditions
With valid V applied, the M48T129Y/V operates
CC
Input Rise and Fall Times
≤ 5ns
0 to 3V
1.5V
as a conventional BYTEWIDE
static RAM.
Input Pulse Voltages
Should the supply voltage decay, the RAM will au-
tomatically deselect, write protecting itself when
Input and Output Timing Ref. Voltages
V
falls between V
(max), V
(min) win-
CC
PFD
PFD
Note that Output Hi-Z is defined as the point where data is no longer
driven.
dow. All outputs become high impedance and all
inputs are treated as ”don’t care”.
Note: A power failure during a write cycle may cor-
rupt data at the current addressed location, but
does not jeopardize the rest of the RAM’s content.
Figure 5. AC Testing Load Circuit
At voltages below V
(min), the memory will be
PFD
in a write protected state, provided the V
fall
CC
time is not less than t . The M48T129Y/V may re-
F
650Ω
spond to transient noise spikes on V that cross
CC
DEVICE
into the deselect window during the time the de-
UNDER
TEST
vice is sampling V . Therefore, decoupling of the
CC
power supply lines is recommended.
When V
drops below V , the control circuit
SO
CC
1.75V
C
= 100pF
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T129Y/V for
an accumulated period of at least 10 years at room
L
temperature. As system power rises above V
,
SO
the battery is disconnected, and the power supply
is switched to external V . Deselect continues for
CC
C
includes JIG capacitance
L
AI01803C
t
after V reaches V
(max). For a further
REC
CC
PFD
more detailed review of lifetime calculations,
please see Application Note AN1012.
Note: Excluding open drain output pins
TIMEKEEPER REGISTERS
The M48T129Y/V offers 16 internal registers
which contain TIMEKEEPER, Alarm, Watchdog,
Interrupt, Flag, and Control data. These registers
are memory locations which contain external (user
accessible) and internal copies of the data (usually
referred to as BiPORT TIMEKEEPER cells). The
external copies are independent of internal func-
tions except that they are updated periodically by
the simultaneous transfer of the incremented inter-
nal copy. TIMEKEEPER and Alarm Registers
store data in BCD.
5/22
M48T129Y, M48T129V
CLOCK OPERATIONS
Reading the Clock
a ’1’ stops the oscillator. When reset to a ’0’, the
M48T129Y/V oscillator starts within one second.
Note: It is not necessary to set the WRITE bit
when setting or resetting the FREQUENCY TEST
bit (FT) or the STOP bit (ST).
Updates to the TIMEKEEPER registers should be
halted before clock data is read to prevent reading
data in transition. Because the BiPORT TIME-
KEEPER cells in the RAM array are only data reg-
isters, and not the actual clock counters, updating
the registers can be halted without disturbing the
clock itself.
Updating is halted when a ’1’ is written to the
READ bit, D6 in the Control Register (1FFF8h). As
long as a ’1’ remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating occurs 1 second af-
ter the READ bit is reset to a ’0’.
SETTING ALARM CLOCK
Registers 1FFF6h-1FFF2h contain the alarm set-
tings. The alarm can be configured to go off at a
prescribed time on a specific month, date, hour,
minute, or second or repeat every month, day,
hour, minute, or second. It can also be pro-
grammed to go off while the M48T129Y/V is in the
battery back-up to serve as a system wake-up call.
Bits RPT5-RPT1 putthe alarm in the repeat mode
of operation. Table 12 shows the possible config-
urations. Codes not listed in the table default to the
once per second mode to quickly alert the user of
an incorrect alarm setting.
Note: User must transition address (or toggle Chip
Enable) to see Flag Bit change.
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the
WRITE bit. Setting the WRITE bit to a ’1’, like the
READ bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 11).
When the clock information matches the alarm
clock settings based on the match criteria defined
by RPT5-RPT1, the AF (Alarm Flag) is set. If AFE
(Alarm Flag Enable) is also set, the alarm condi-
tion activates the IRQ/FT pin. To disable alarm,
write ’0’ to the Alarm Date register and RPT1-4.
The IRQ/FT output is cleared by a read to the
Flags register as shown in Figure 12. A subse-
quent read of the Flags register will reset the
Alarm Flag (D6; Register 1FFF0h).
Resetting the WRITE bit to a ’0’ then transfers the
values of all time registers (1FFFFh-1FFF9h,
1FFF1h) to theactual TIMEKEEPER counters and
allows normal operation to resume. After the
WRITE bit is reset, the next clock update will occur
approximately one second later.
Note: Upon power-up following a power failure,
both the WRITE bit and the READ bit will be reset
to ’0’.
The IRQ/FT pin can also be activated in the bat-
tery back-up mode. The IRQ/FT will go low if an
alarm occurs and both ABE (Alarm in Battery
Back-up Mode Enable) and AFE are set. The ABE
and AFE bits are reset during power-up, therefore
an alarm generated during power-up will only set
AF. The user can read the Flag Register at system
boot-up to determine if an alarm was generated
while the M48T129Y/V was in the deselect mode
during power-up. Figure 13 illustrates the back-up
mode alarm timing.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
bit is located at Bit D7 within 1FFF9h. Setting it to
6/22
M48T129Y, M48T129V
(1)
Table 5. Capacitance
A
(T = 25 °C, f = MHz)
Symbol
Parameter
Test Condition
Min
Max
Unit
C
V
= 0V
= 0V
Input Capacitance
20
pF
IN
(2)
IN
V
Input / Output Capacitance
20
pF
C
IO
OUT
Note: 1. Effective capacitance measured with power supply at 5V (M48T129Y) or 3.3V (M48T129V). Sampled only, not 100% tested.
2. Outputs deselected.
Table 6A. DC Characteristics
(T = 0 to 70 °C; V = 4.5V to 5.5V)
A
CC
Symbol
Parameter
Test Condition
0V ≤ V ≤ V
Min
Max
Unit
(1)
Input Leakage Current
±2
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
Output Leakage Current
Supply Current
±2
95
8
µA
mA
mA
mA
V
I
OUT
LO
I
Outputs open
CC
I
I
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Input Low Voltage
CC1
CC2
IH
E = V –0.2V
4
CC
–0.3
2.2
0.8
V
IL
V
V
V
+ 0.3
CC
Input High Voltage
V
IH
I
= 2.1mA
= –1mA
Output Low Voltage
0.4
V
OL
OL
V
I
OH
Output High Voltage
2.4
V
OH
Note: 1. Outputs deselected.
Table 6B. DC Characteristics
(T = 0 to 70 °C; V = 3.0V to 3.6V)
A
CC
Symbol
Parameter
Test Condition
Min
Max
Unit
(1)
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
±2
µA
I
IN
CC
LI
(1)
0V ≤ V
≤ V
CC
±2
µA
I
OUT
LO
I
Supply Current
Outputs open
E = V
50
4
mA
mA
mA
CC
I
I
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
CC1
CC2
IH
E = V –0.2V
3
CC
Input Low Voltage
–0.3
2.2
0.4
V
V
IL
V
V
+ 0.3
CC
Input High Voltage
Output Low Voltage
Output High Voltage
V
V
V
IH
V
OL
I
= 2.1mA
= –1mA
0.4
OL
V
OH
I
OH
2.2
Note: 1. Outputs deselected.
7/22
M48T129Y, M48T129V
Figure 6. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SO
tF
tR
tFB
tRB
DON’T CARE
tREC
RECOGNIZED
RECOGNIZED
INPUTS
HIGH-Z
OUTPUTS
RST
VALID
VALID
AI01805
(1)
Table 7. Power Down/Up Trip Points DC Characteristics
A
(T = 0 to 70 °C)
Symbol
Parameter
Power-fail Deselect Voltage
Min
4.2
2.7
Typ
4.35
2.9
Max
4.5
Unit
V
M48T129Y
M48T129V
M48T129Y
M48T129V
V
PFD
3.0
V
3.0
V
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
SO
V
–100mV
V
PFD
(2)
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. At 25°C.
Table 8. Power Down/Up AC Characteristics
(T = 0 to 70 °C)
A
Symbol
Parameter
Min
Max
Unit
(1)
V
(max) to V
(min) V
Fall Time
CC
300
10
150
10
1
µs
µs
µs
µs
µs
ms
t
PFD
PFD
PFD
PFD
F
M48T129Y
M48T129V
(2)
V
(min) to V
(min) to V
V Fall Time
SS CC
t
FB
t
V
V
V
(max) V Rise Time
PFD CC
R
t
to V
(min) V Rise Time
PFD CC
RB
SS
t
(max) to RST High
40
200
REC
PFD
Note: 1. V
(max) to V
(min).
(min) fall time of less than t mayresult in deselection/write protection not occurring until50µs after V passes
PFD F CC
PFD
PFD
PFD
V
2. V
(min) to V fall time of less than t may cause corruption of RAM data.
SS FB
8/22
M48T129Y, M48T129V
Table 9. Read Mode AC Characteristics
(T = 0 to 70 °C)
A
M48T129Y
-70
M48T129V
Symbol
Parameter
-85
Unit
Min
Max
Min
Max
t
Read Cycle Time
70
85
ns
ns
ns
AVAV
(1)
(1)
(1)
(2)
(2)
(2)
(2)
(1)
Address Valid to Output Valid
70
70
40
85
85
55
t
AVQV
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
ELQV
GLQV
ns
ns
ns
ns
ns
ns
t
5
5
5
5
t
ELQX
t
t
GLQX
EHQZ
25
25
30
30
t
GHQZ
5
5
t
AXQX
Note: 1. C = 100pF.
L
2. C = 5pF.
L
Figure 7. Address Controlled, Read Mode AC Waveforms
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02324
9/22
M48T129Y, M48T129V
Table 10. Write Mode AC Characteristics
(T = 0 to 70 °C)
A
M48T129Y
-70
M48T129V
-85
Symbol
Parameter
Unit
Min
Max
Min
Max
t
Write Cycle Time
70
0
85
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Write Enable Low
Address Valid to Chip Enable Low
Write Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
5
60
65
5
WLWH
t
Chip Enable Low to Chip Enable High
Write Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to Write Enable High
Input Valid to Chip Enable High
ELEH
WHAX
t
t
10
30
30
5
15
35
35
5
EHAX
t
DVWH
t
DVEH
t
Write Enable High to Input Transition
Chip Enable High to Input Transition
WHDX
t
10
15
EHDX
(1, 2)
Write Enable Low to Output Hi-Z
Address Valid to Write Enable High
Address Valid to Chip Enable High
Write Enable High to Output Transition
25
30
ns
ns
ns
ns
t
WLQZ
t
60
60
5
70
70
5
AVWH
t
AVEH
(1, 2)
t
WHQX
Note: 1. C = 5pF.
L
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
WATCHDOG TIMER
the watchdog will activate the IRQ/FT pin when
timed-out. When WDS is set to a ’1’, the watchdog
will output a negative pulse on the RST pin for 40
to 200 ms. The Watchdog register and the FT bit
will reset to a ’0’ at the end of a Watchdog time-out
when the WDS bit is set to a ’1’. The watchdog tim-
er can be reset by having the original time-out pe-
riod re-written into the Watchdog Register,
effectively restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT pin. This will also dis-
able the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
1FFF0h). The watchdog function is automatically
disabled upon power-down and the Watchdog
Register is cleared. If the watchdog function is set
to output to the IRQ/FT pin and the frequency test
function is activated, the watchdog or alarm func-
tion prevails and the frequency test function is de-
nied.
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address
1FFF7h. Bits BMB4-BMB0 store abinary multiplier
and the two lower order bits RB1-RB0 select the
resolution, where 00 = 1/16 second, 01 = 1/4 sec-
ond, 10 = 1 second, and 11 = 4 seconds. The
amount of time-out is then determined to be the
multiplication of the five bit multiplier value with the
resolution. (For example: writing 00001110 in the
Watchdog Register = 3*1 or 3 seconds).
Note: Accuracy of timer is within ± the selected
resolution.
If the processor does not reset the timer within the
specified period, the M48T129Y/V sets the WDF
(Watchdog Flag) and generates a watchdog inter-
rupt or a microprocessor reset. WDF is reset by
reading the Flags Register (Address 1FFF0h). The
most significantbit of the Watchdog Register is the
Watchdog Steering Bit (WDS). When set to a ’0’,
10/22
M48T129Y, M48T129V
Figure 8. Chip Enable or Output Enable Controlled, Read Mode AC Waveforms
tAVAV
VALID
A0-A16
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Figure 9. Write Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DATA INPUT
tDVWH
DQ0-DQ7
AI02382
11/22
M48T129Y, M48T129V
Figure 10. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A16
E
VALID
tELEH
tAVEL
tEHAX
tAVWL
W
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02582
POWER-ON RESET
tion bits occupy the five lower order bits (D4-D0) in
the Control Register 1FFF8h. These bits can be
set to represent any value between 0 and 31 in bi-
nary form. Bit D5 is a Sign bit; ’1’ indicates positive
calibration, ’0’ indicates negative calibration. Cali-
bration occurs within a 64 minute cycle. The first
62 minutes in the cycle may, once per minute,
have one second either shortened by 128 or
lengthened by 256 oscillator cycles. If a binary ’1’
is loaded into the register, only the first 2 minutes
in the 64 minute cycle will be modified; if a binary
6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125, 829, 120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month. Figure 11 illustrates a TIME-
KEEPER calibration waveform.
The M48T129Y/V continuously monitors V
.
CC
When V
falls to the power fail detect trip point,
CC
the RSTpulls low (open drain) and remains low on
power-up for 40 to 200ms after V passes V
.
PFD
CC
The RST pin is an open drain output and an appro-
priate pull-up resistor to V should be chosen to
control the rise time.
CC
CALIBRATING THE CLOCK
The M48T129Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not ex-
ceed 35 ppm (parts per million) oscillator frequen-
cy error at 25°C, which equates to about * 1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than +4 ppm at 25°C. The oscillation rate of crys-
tals changes with temperature. The M48T129Y/V
design employs periodic counter correction. The
calibration circuit adds or subtracts counts from
the oscillator divider circuit at the divide by 256
stage, as shown in Figure 11.
The number of times pulses which are blanked
(subtracted, negative calibration) or split (added,
positive calibration) depends upon the value load-
ed into the five Calibration bits found in the Control
Register. Adding counts speeds the clock up, sub-
tracting counts slows the clock down.The Calibra-
Two methods are available for ascertaining how
much calibration a given M48T129Y/V may re-
quire. The first involves setting the clock, letting it
run for a month and comparing it to a known accu-
rate reference and recording deviation over a fixed
period of time.
12/22
M48T129Y, M48T129V
Table 11. TIMEKEEPER Register Map
Address
Data
Function/Range
BCD Format
D7
D6
D5
D4
D3
D2
D1
D0
1FFFFh
1FFFEh
1FFFDh
1FFFCh
1FFFBh
1FFFAh
1FFF9h
1FFF8h
1FFF7h
1FFF6h
1FFF5h
1FFF4h
1FFF3h
1FFF2h
1FFF1h
1FFF0h
10 Years
Year
Month
Date
Year
Month
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 M.
0
10 Date
Date
0
FT
0
0
0
Day of Week
Day
0
10 Hours
Hours (24 Hours Format)
Minutes
Hour
0
10 Minutes
10 Seconds
S
Minutes
Seconds
Control
Watchdog
A Month
A Date
A Hours
A Minutes
A Seconds
Century
Flags
ST
W
Seconds
R
Calibration
WDS BMB4 BMB3 BMB2 BMB1 BMB0
RB1
RB0
AFE
0
ABE
Al 10 Date
Al 10 Hours
Al 10M
Alarm Month
Alarm Date
01-12
01-31
00-23
00-59
00-59
00-99
RPT4 RPT5
RPT3
RPT2
RPT1
0
Alarm Hours
Alarm Minutes
Alarm Seconds
100 Year
Alarm 10 Minutes
Alarm 10 Seconds
1000 Year
WDF
AF
0
BL
Y
Y
Y
Y
Keys: S = SIGN Bit
FT = FREQUENCY TEST Bit
AF = Alarm Flag
WDS = Watchdog Steering Bit
R = READ Bit
BMB0-BMB4 = Watchdog Multiplier Bits
RB0-RB1 = Watchdog Resolution Bits
AFE = Alarm Flag Enable
ABE = Alarm in Battery Back-up Mode Enable
RPT1-RPT5 = Alarm Repeat Mode Bits
WDF = Watchdog Flag
W = WRITE Bit
ST = STOP Bit
0 = Must be set to zero
Y = ’1’ or ’0’
BL = Battery Low
Figure 11. Calibration Waveform
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
13/22
M48T129Y, M48T129V
Figure 12. Alarm Interrupt Reset Waveform
15ns Min
ADDRESS 1FF0h
AD0-AD7
ACTIVE FLAG BIT
IRQ/FT
HIGH-Z
AI02581
Figure 13. Back-up Mode Alarm Waveforms
tREC
V
V
V
CC
PFD
PFD
(max)
(min)
V
SO
AFE bit in Interrupt Register
AF bit in Flags Register
IRQ/FT
HIGH-Z
HIGH-Z
AI01678C
Calibration values, including the number of sec-
onds lost or gained in a given period, can be found
in Application Note: TIMEKEEPER CALIBRA-
TION. This allows the designer to give the end
user the ability to calibrate the clock as the envi-
ronment requires, even if the final product is pack-
aged in a non-user serviceable enclosure. The
designer could provide a simple utility that access-
es the Calibration byte.
The second approach is better suited to a manu-
facturing environment, and involves the use of the
IRQ/FT pin. The pin will toggle at 512Hz, when the
Stop bit (ST, D7 of 1FFF9h) is ’0’,the Frequency
Test bit (FT, D6 of 1FFFCh) is ’1’, the Alarm Flag
Enable bit (AFE, D7 of 1FFF6h) is ’0’, and the
Watchdog Steering bit (WDS, D7 of 1FFF7h) is ’1’
or the Watchdog Register (1FFF7h=0) is reset.
Note: A 4 second settling time must be allowed
before reading the 512Hz output.
Any deviation from 512Hz indicates the degree
and direction of oscillator frequency shift at the test
temperature. For example,
a
reading of
512.010124Hz would indicate a +20 ppm oscillator
frequency error, requiring a–10 (WR001010)to be
loaded into the Calibration Byte for correction.
Note that setting or changing the Calibration Byte
does not affect the Frequency test output frequen-
cy.
14/22
M48T129Y, M48T129V
Table 12. Alarm Repeat Modes
RPT4
RPT3
RPT2
RPT1
Alarm Activated
Once per Second
Once per Minute
Once per Hour
1
1
1
1
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
Once per Day
Once per Month
Figure 14. Supply Voltage Protection
If a battery low indication is generated during the
24-hour interval check, this indicates that the bat-
tery is near end of life. However, data is not com-
promised due to the fact that a nominal V
supplied.
The M48T129Y/V only monitors the battery when
is
CC
V
CC
a nominal V isapplied to the device. Thus appli-
CC
V
CC
cations which require extensive durations in the
battery back-up mode should be powered-up peri-
odically (at least once every few months) in order
for this technique to be beneficial. Additionally, if a
battery low is indicated, data integrity should be
verified upon power-up via a checksum or other
technique.
0.1µF
DEVICE
V
SS
POWER-ON DEFAULTS
AI02169
Upon application of power to the device, the fol-
lowing register bits are set to a ’0’ state: WDS,
BMB0-BMB4, RB0,RB1, AFE, ABE, W, R and FT.
POWER SUPPLY DECOUPLING
and UNDERSHOOT PROTECTION
The IRQ/FT pin is an open drain output which re-
I
transients, including those produced by output
CC
quires a pull-up resistor to V for proper opera-
CC
switching, can produce voltage fluctuations, re-
tion. A 500-10k resistor is recommended in order
to control the rise time. The FT bit is cleared on
power-up.
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy, which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (see Figure 14) is
recommended in order to provide the needed fil-
tering. In addition to transients that are caused by
normal SRAM operation, power cycling can gener-
BATTERY LOW WARNING
The M48T129Y/V automatically performs battery
voltage monitoring upon power-up and at factory-
programmed time intervals of approximately 24
hours. The Battery Low (BL) bit, Bit D4 of Flags
Register 1FFF0h, will be asserted if the battery
voltage is found to be less than approximately
2.5V.
ate negative voltage spikes on V that drive it to
CC
values below V by as much as one volt. These
SS
If a battery lowis generated during a power-up se-
quence, this indicates that the battery is below ap-
proximately 2.5 volts and may not be able to
maintain data integrity in the SRAM. Data should
be considered suspect and verified as correct.
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, ST recommends con-
necting a schottky diode from V to V (cathode
CC
SS
connected to V , anode to V ). (Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount).
15/22
M48T129Y, M48T129V
Table 13. Ordering Information Scheme
Example:
M48T129Y
-70 PM
1
Device Type
M48T
Supply Voltage and Write Protect Voltage
129Y = V
129V = V
= 4.5V to 5.5V; V
= 3.0V to 3.6V; V
= 4.2V to 4.5V
= 2.7V to 3.0V
CC
CC
PFD
PFD
Speed
-70 = 70ns
-85 = 85ns
Package
PM = PMDIP32
(1)
CS = Surface Mount Chip Set solution M48T201Y/V (SOH44) + M68Z128/W (TSOP32)
Temperature Range
1 = 0 to 70 °C
Note: 1. The SOIC package (SOH44) requires the battery package (SNAPHAT) which is ordered separately under the part number
”M4Txx-BR12SH1” in plastic tube or ”M4Txx-BR12SH1TR” in Tape & Reel form.
Caution: Do not place the SNAPHAT battery package ”M4Txx-BR12SH1” in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the ST Sales Office nearest to you.
Table 14. Revision History
Date
Revision Details
April 2000
Chipset datasheet - First Issue
16/22
M48T129Y, M48T129V
Table 15. PMDIP32 - 32 pin Plastic Module DIP, Package Mechanical Data
mm
inches
Symb
Typ
Min
9.27
0.38
0.43
0.20
42.42
18.03
2.29
34.29
14.99
3.05
1.91
32
Max
9.52
–
Typ
Min
Max
0.375
–
A
A1
B
0.365
0.015
0.017
0.008
1.670
0.710
0.090
1.350
0.590
0.120
0.075
32
0.59
0.33
43.18
18.80
2.79
41.91
16.00
3.81
2.79
0.023
0.013
1.700
0.740
0.110
1.650
0.630
0.150
0.110
C
D
E
e1
e3
eA
L
S
N
Figure 15. PMDIP32 - 32 pin Plastic Module DIP, Package Outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Drawing is not to scale.
17/22
M48T129Y, M48T129V
Table 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data
mm
Min
inch
Min
Symbol
Typ
Max
1.200
0.150
1.050
0.270
0.210
20.200
18.500
–
Typ
Max
0.0472
0.0059
0.0413
0.0106
0.0083
0.7953
0.7283
–
A
A1
A2
B
0.050
0.950
0.150
0.100
19.800
18.300
–
0.0020
0.0374
0.0059
0.0039
0.7795
0.7205
–
C
D
D1
e
0.500
0.0197
E
7.900
0.500
0°
8.100
0.700
5°
0.3110
0.0197
0°
0.3189
0.0276
5°
L
α
CP
N
0.100
0.0039
32
1.3
Figure 16. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
18/22
M48T129Y, M48T129V
Table 17. SH - 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
9.78
7.24
6.99
0.38
0.56
21.84
14.99
15.95
3.61
2.29
Typ
Max
A
A1
A2
A3
B
0.385
0.285
0.275
0.015
0.022
0.860
0.590
0.628
0.142
0.090
6.73
6.48
0.265
0.255
0.46
21.21
14.22
15.55
3.20
0.018
0.835
0.560
0.612
0.126
0.080
D
E
eA
eB
L
2.03
Figure 17. SH - 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
eA
D
B
L
eB
E
SHTK-A
Drawing is not to scale.
19/22
M48T129Y, M48T129V
Table 18. SH - 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
10.54
8.51
Typ
Max
A
A1
A2
A3
B
0.415
.0335
0.315
0.015
0.022
0.860
.0710
0.628
0.142
0.090
8.00
7.24
0.315
0.285
8.00
0.38
0.46
21.21
17.27
15.55
3.20
0.56
0.018
0.835
0.680
0.612
0.126
0.080
D
21.84
18.03
15.95
3.61
E
eA
eB
L
2.03
2.29
Figure 18. SH - 4-pin SNAPHAT Housing for 120 mAh Battery & Crystal, Package Outline
A2
A1
A
A3
L
eA
D
B
eB
E
SHTK-A
Drawing is not to scale.
20/22
M48T129Y, M48T129V
Table 19. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT,
Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
3.05
0.36
2.69
0.46
0.32
18.49
8.89
–
Typ
Max
0.120
0.014
0.106
0.018
0.012
0.728
0.350
–
A
A1
A2
B
0.05
2.34
0.36
0.15
17.71
8.23
–
0.002
0.092
0.014
0.006
0.697
0.324
–
C
D
E
e
eB
H
0.81
0.032
3.20
11.51
0.41
0°
3.61
12.70
1.27
8°
0.126
0.453
0.016
0°
0.142
0.500
0.050
8°
L
α
N
44
44
CP
0.10
0.004
Figure 19. SOH44 - 44 lead Plastic Small Outline, 4-socket battery, SNAPHAT, Package Outline
A2
A
C
eB
B
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Drawing is not to scale.
21/22
M48T129Y, M48T129V
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
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22/22
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