M48T128V-85PM1TR [STMICROELECTRONICS]
3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM; 3.3V - 5V 1兆位128KB X8 TIMEKEEPER SRAM
| 型号： | M48T128V-85PM1TR |
| 厂家： | 
ST |
| 描述： | 3.3V-5V 1 Mbit 128Kb x8 TIMEKEEPER SRAM |
| 文件： | 总22页 (文件大小：343K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M48T128Y
M48T128V*
®
5.0 or 3.3V, 1 Mbit (128 Kb x 8) TIMEKEEPER SRAM
FEATURES SUMMARY
■
INTEGRATED, ULTRA LOW POWER SRAM,
REAL TIME CLOCK, POWER-FAIL
CONTROL CIRCUIT, BATTERY, AND
CRYSTAL
Figure 1. 32-pin PMDIP Module
■
■
■
BCD CODED YEAR, MONTH, DAY, DATE,
HOURS, MINUTES, AND SECONDS
AUTOMATIC POWER-FAIL CHIP
DESELECT AND WRITE PROTECTION
WRITE PROTECT VOLTAGES
(V
–
= Power-fail Deselect Voltage):
PFD
M48T128Y: V = 4.5 to 5.5V
CC
4.1V ≤ V
≤ 4.5V
PFD
–
M48T128V*: V = 3.0 to 3.6V
CC
32
2.7V ≤ V
≤ 3.0V
PFD
1
■
■
CONVENTIONAL SRAM OPERATION;
UNLIMITED WRITE CYCLES
SOFTWARE CONTROLLED CLOCK
CALIBRATION FOR HIGH ACCURACY
APPLICATIONS
PMDIP32 (PM)
Module
■
10 YEARS OF DATA RETENTION AND
CLOCK OPERATION IN THE ABSENCE OF
POWER
■
■
SELF-CONTAINED BATTERY AND
CRYSTAL IN THE DIP PACKAGE
PIN AND FUNCTION COMPATIBLE WITH
JEDEC STANDARD 128K x 8 SRAMs
* Contact local ST sales office for availability of 3.3V version.
February 2005
1/22
M48T128Y, M48T128V*
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. 32-pin PMDIP Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
OPERATION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. READ Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. READ Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 6. WRITE Enable Controlled, WRITE AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Chip Enable Controlled, WRITE AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
CLOCK OPERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Reading the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Calibrating the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 9. Clock Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
V
CC
Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.Supply Voltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 10. Power Down/Up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Power Down/Up Trip Points DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2/22
M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.PMDIP32 – 32-pin Plastic Module DIP, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data . . . . . . . . . . . . . . . . 19
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 13. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 14. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3/22
M48T128Y, M48T128V*
SUMMARY DESCRIPTION
®
The M48T128Y/V TIMEKEEPER RAM is a
128Kb x 8 non-volatile static RAM and real time
clock. The special DIP package provides a fully in-
tegrated battery back-up memory and real time
clock solution. The M48T128Y/V directly replaces
industry standard 128Kb x 8 SRAM.
It also provides the non-volatility of Flash without
any requirement for special WRITE timing or limi-
tations on the number of WRITEs that can be per-
formed. The 32-pin, 600mil DIP Hybrid houses a
controller chip, SRAM, quartz crystal, and a long
life lithium button cell in a single package.
Figure 2. Logic Diagram
Table 1. Signal Names
V
A0-A16
Address Inputs
Data Inputs / Outputs
Chip Enable
CC
DQ0-DQ7
17
8
E
A0-A16
DQ0-DQ7
G
W
Output Enable
WRITE Enable
Supply Voltage
Ground
W
E
M48T128Y
M48T128V
V
CC
V
G
SS
NC
Not Connected Internally
V
SS
AI02244
Figure 3. DIP Connections
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32
V
CC
31 A15
30 NC
29
W
28 A13
27 A8
A6
A5
26 A9
A4
M48T128Y 25 A11
M48T128V
A3
24
23 A10
22
G
A2 10
A1 11
E
A0 12
21 DQ7
20 DQ6
19 DQ5
18 DQ4
17 DQ3
DQ0 13
DQ1 14
DQ2 15
V
16
SS
AI02245
4/22
M48T128Y, M48T128V*
Figure 4. Block Diagram
8 x 8
TIMEKEEPER
REGISTERS
OSCILLATOR AND
CLOCK CHAIN
32,768 Hz
CRYSTAL
A0-A16
POWER
DQ0-DQ7
131,064 x 8
SRAM ARRAY
LITHIUM
CELL
E
VOLTAGE SENSE
AND
W
G
V
PFD
SWITCHING
CIRCUITRY
V
V
CC
SS
AI01804
5/22
M48T128Y, M48T128V*
OPERATION MODES
Figure 4., page 5 illustrates the static memory ar-
ray and the quartz controlled clock oscillator. The
clock locations contain the year, month, date, day,
hour, minute, and second in 24 hour BCD format.
Corrections for 28, 29 (leap year - valid until 2100),
30, and 31 day months are made automatically.
Byte 1FFF8h is the clock control register. This byte
controls user access to the clock information and
also stores the clock calibration setting. The seven
clock bytes (1FFFFh - 1FFF8h) are not the actual
clock counters, they are memory locations consist-
ing of BiPORT™ READ/WRITE memory cells
within the static RAM array. The M48T128Y/V in-
cludes a clock control circuit which updates the
clock bytes with current information once per sec-
ond. The information can be accessed by the user
in the same manner as any other location in the
static memory array. The M48T128Y/V also has its
own Power-Fail Detect circuit. This control circuitry
constantly monitors the supply voltage for an out
of tolerance condition. When V
is out of toler-
CC
®
ance, the circuit write protects the TIMEKEEPER
Register data and external SRAM, providing data
security in the midst of unpredictable system oper-
ation. As V
falls below the Battery Back-up
CC
Switchover Voltage (V ), the control circuitry au-
SO
tomatically switches to the battery, maintaining
data and clock operation until valid power is re-
stored.
Table 2. Operating Modes
V
Mode
Deselect
WRITE
READ
E
G
X
X
W
DQ0-DQ7
Power
Standby
Active
CC
V
IH
X
High Z
4.5 to 5.5V
or
3.0 to 3.6V
V
V
V
V
D
IL
IL
IL
IL
IH
IH
IN
V
V
V
D
Active
IL
OUT
V
IH
READ
High Z
High Z
High Z
Active
(1)
Deselect
X
X
X
CMOS Standby
V
SO
to V
(min)
PFD
(1)
Deselect
X
X
X
Battery Back-up Mode
≤ V
SO
Note: X = V or V ; V = Battery Back-up Switchover Voltage.
IH
IL
SO
1. See Table 11., page 18 for details.
6/22
M48T128Y, M48T128V*
READ Mode
The M48T128Y/V is in the READ Mode whenever
W (WRITE Enable) is high and E (Chip Enable) is
low. The unique address specified by the 17 Ad-
dress Inputs defines which one of the 131,072
bytes of data is to be accessed.
able after the latter of the Chip Enable Access
Times (t ) or Output Enable Access Time
ELQV
(t
). The state of the eight three-state Data I/O
GLQV
signals is controlled by E and G. If the outputs are
activated before t , the data lines will be driven
AVQV
to an indeterminate state until t
. If the Ad-
AVQV
Valid data will be available at the Data I/O pins
dress Inputs are changed while E and G remain
active, output data will remain valid for t (Out-
within t
(Address Access Time) after the last
AVQV
AXQX
address input signal is stable, providing the E and
G access times are also satisfied. If the E and G
access times are not met, valid data will be avail-
put Data Hold Time) but will go indeterminate until
the next Address Access.
Figure 5. READ Mode AC Waveforms
tAVAV
VALID
A0-A16
tAVQV
tELQV
tAXQX
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA OUT
AI01197
Note: WE = High.
Table 3. READ Mode AC Characteristics
M48T128Y
–70
M48T128V
–85
(1)
Symbol
Unit
Parameter
Min
Max
Min
Max
t
READ Cycle Time
70
85
ns
ns
ns
ns
ns
AVAV
t
Address Valid to Output Valid
70
70
40
85
85
55
AVQV
t
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
Chip Enable Low to Output Transition
ELQV
t
GLQV
(2)
5
5
5
5
t
ELQX
GLQX
EHQZ
(2)
(2)
(2)
Output Enable Low to Output Transition
Chip Enable High to Output Hi-Z
ns
ns
ns
ns
t
t
25
25
30
30
Output Enable High to Output Hi-Z
Address Transition to Output Transition
t
GHQZ
t
10
5
AXQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
7/22
M48T128Y, M48T128V*
WRITE Mode
The M48T128Y/V is in the WRITE Mode whenever
W (WRITE Enable) and E (Chip Enable) are low
state after the address inputs are stable.
The start of a WRITE is referenced from the latter
occurring falling edge of W or E. A WRITE is termi-
nated by the earlier rising edge of W or E. The ad-
dresses must be held valid throughout the cycle. E
Chip Enable or t
the initiation of another READ or WRITE cycle.
Data-in must be valid t prior to the end of
WRITE and remain valid for t
should be kept high during WRITE cycles to avoid
bus contention; although, if the output bus has
been activated by a low on E and G a low on W will
from WRITE Enable prior to
WHAX
DVWH
afterward. G
WHDX
disable the outputs t
after W falls.
WLQZ
or W must return high for a minimum of t
from
EHAX
Figure 6. WRITE Enable Controlled, WRITE AC Waveform
tAVAV
A0-A16
VALID
tAVWH
tAVEL
tAVWL
tWHAX
E
tWLWH
W
tWLQZ
tWHQX
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI02382
Figure 7. Chip Enable Controlled, WRITE AC Waveforms
tAVAV
A0-A16
VALID
tAVEH
tELEH
tAVEL
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI02383
8/22
M48T128Y, M48T128V*
Table 4. WRITE Mode AC Characteristics
M48T128Y
–70
M48T128V
(1)
Symbol
–85
Unit
Parameter
Min
Max
Min
85
0
Max
t
WRITE Cycle Time
70
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
t
Address Valid to WRITE Enable Low
Address Valid to Chip Enable Low
WRITE Enable Pulse Width
AVWL
t
0
0
AVEL
t
50
55
5
60
65
5
WLWH
t
Chip Enable Low to Chip Enable 1 High
WRITE Enable High to Address Transition
Chip Enable High to Address Transition
Input Valid to WRITE Enable High
Input Valid to Chip Enable High
ELEH
t
WHAX
t
10
30
30
5
15
35
35
5
EHAX
t
DVWH
t
DVEH
t
WRITE Enable High to Input Transition
Chip Enable High to Input Transition
WHDX
t
10
15
EHDX
(2,3)
WRITE Enable Low to Output Hi-Z
Address Valid to WRITE Enable High
Address Valid to Chip Enable High
WRITE Enable High to Output Transition
25
30
ns
ns
ns
ns
t
WLQZ
t
60
60
5
70
70
5
AVWH
t
AVEH
(2,3)
t
WHQX
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. C = 5pF.
L
3. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
9/22
M48T128Y, M48T128V*
Data Retention Mode
With valid V applied, the M48T128Y/V operates
spikes on V that reach into the deselect window
CC
CC
as a conventional BYTEWIDE™ static RAM.
Should the supply voltage decay, the RAM will au-
tomatically power-fail deselect, write protecting it-
during the time the device is sampling V . There-
CC
fore, decoupling of the power supply lines is rec-
ommended.
self when V
falls within the V
(max), V
CC
PFD PFD
When V
drops below V , the control circuit
SO
CC
(min) window. All outputs become high imped-
ance, and all inputs are treated as “Don't care.”
Note: A power failure during a WRITE cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM's con-
switches power to the internal battery, preserving
data and powering the clock. The internal energy
source will maintain data in the M48T128Y/V for
an accumulated period of at least 10 years at room
temperature. As system power rises above V
,
SO
tent. At voltages below V
assured the memory will be in a write protected
(min), the user can be
the battery is disconnected, and the power supply
is switched to external V . Deselect continues for
PFD
CC
state, provided the V fall time is not less than t .
t
after V reaches V
(max).
CC
F
REC
CC
PFD
The M48T128Y/V may respond to transient noise
10/22
M48T128Y, M48T128V*
CLOCK OPERATIONS
Reading the Clock
®
Updates to the TIMEKEEPER registers should
be halted before clock data is read to prevent
reading data in transition. The BiPORT™ TIME-
KEEPER cells in the RAM array are only data reg-
isters and not the actual clock counters, so
updating the registers can be halted without dis-
turbing the clock itself.
Updating is halted when a '1' is written to the
READ Bit, D6 in the Control Register (1FFF8h). As
long as a '1' remains in that position, updating is
halted. After a halt is issued, the registers reflect
the count; that is, the day, date, and time that were
current at the moment the halt command was is-
sued. All of the TIMEKEEPER registers are updat-
ed simultaneously. A halt will not interrupt an
update in progress. Updating is within a second af-
ter the bit is reset to a '0.'
READ Bit, halts updates to the TIMEKEEPER reg-
isters. The user can then load them with the cor-
rect day, date, and time data in 24 hour BCD
format (see Table 5., page 11). Resetting the
WRITE Bit to a '0' then transfers the values of all
time registers 1FFFFh-1FFF9h to the actual TIME-
KEEPER counters and allows normal operation to
resume. After the WRITE Bit is reset, the next
clock update will occur one second later.
Stopping and Starting the Oscillator
The oscillator may be stopped at any time. If the
device is going to spend a significant amount of
time on the shelf, the oscillator can be turned off to
minimize current drain on the battery. The STOP
Bit is located at Bit D7 within 1FFF9h. Setting it to
a '1' stops the oscillator. The M48T128Y/V is
shipped from STMicroelectronics with the STOP
Bit set to a '1.' When reset to a '0,' the M48T128Y/
V oscillator starts after one second.
Setting the Clock
Bit D7 of the Control Register (1FFF8h) is the
WRITE Bit. Setting the WRITE Bit to a '1,' like the
Table 5. Register Map
Data
Function/Range
BCD Format
Address
D7
D6
D5
D4
10 M
0
D3
D2
D1
D0
1FFFFh
1FFFEh
1FFFDh
1FFFCh
1FFFBh
1FFFAh
1FFF9h
1FFF8h
10 Years
Year
Month
Date
Year
Month
Date
00-99
01-12
01-31
01-07
00-23
00-59
00-59
0
0
0
0
0
10 Date
0
FT
0
0
0
Day
Hours
Day
0
10 Hours
Hours
Minutes
Seconds
Control
0
10 Minutes
10 Seconds
S
Minutes
ST
W
Seconds
R
Calibration
Keys: S = SIGN Bit
R = READ Bit
W = WRITE Bit
ST = STOP Bit
0 = Must be set to '0'
Z = '0' and are Read only
Y = '1' or '0'
11/22
M48T128Y, M48T128V*
Calibrating the Clock
The M48T128Y/V is driven by a quartz controlled
oscillator with a nominal frequency of 32,768Hz.
The devices are factory calibrated at 25°C and
tested for accuracy. Clock accuracy will not ex-
ceed 35 ppm (parts per million) oscillator frequen-
cy error at 25°C, which equates to about ±1.53
minutes per month. When the Calibration circuit is
properly employed, accuracy improves to better
than +1/–2 ppm at 25°C. The oscillation rate of
crystals changes with temperature (see Figure
8., page 13). The M48T128Y/V design employs
periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider
circuit at the divide by 128 stage, as shown in Fig-
ure 9., page 13.
The number of times pulses are blanked (subtract-
ed, negative calibration) or split (added, positive
calibration) depends upon the value loaded into
the five Calibration bits found in the Control Regis-
ter. Adding counts speeds the clock up, subtract-
ing counts slows the clock down. The Calibration
bits occupy the five lower order bits (D4-D0) in the
Control Register 1FFF8h. These bits can be set to
represent any value between 0 and 31 in binary
form. Bit D5 is a Sign Bit; '1' indicates positive cal-
ibration, '0' indicates negative calibration. Calibra-
tion occurs within a 64 minute cycle. The first 62
minutes in the cycle may, once per minute, have
one second either shortened by 128 or lengthened
by 256 oscillator cycles. If a binary '1' is loaded into
the register, only the first 2 minutes in the 64
minute cycle will be modified; if a binary 6 is load-
ed, the first 12 will be affected, and so on. There-
fore, each calibration step has the effect of adding
512 or subtracting 256 oscillator cycles for every
125, 829, 120 actual oscillator cycles, that is
+4.068 or –2.034 ppm of adjustment per calibra-
tion step in the calibration register. Assuming that
the oscillator is running at exactly 32,768Hz, each
of the 31 increments in the Calibration byte would
represent +10.7 or –5.35 seconds per month
which corresponds to a total range of +5.5 or –2.75
minutes per month.
One method is available for ascertaining how
much calibration a given M48T128Y/V may re-
quire. This involves setting the clock, letting it run
for a month and comparing it to a known accurate
reference and recording deviation over a fixed pe-
riod of time.
Calibration values, including the number of sec-
onds lost or gained in a given period, can be found
in the STMicroelectronics Application Note,
“TIMEKEEPER CALIBRATION.”
This allows the designer to give the end user the
ability to calibrate the clock as the environment re-
quires, even if the final product is packaged in a
non-user serviceable enclosure. The designer
could provide a simple utility that accesses the
Calibration byte. For example, a deviation of 21
seconds slow over a period of 30 days would indi-
cate a –8 ppm oscillator frequency error, requiring
a +2(WR100010) to be loaded into the Calibration
Byte for correction.
12/22
M48T128Y, M48T128V*
Figure 8. Crystal Accuracy Across Temperature
ppm
20
0
-20
-40
2
∆F
F
ppm
C2
= -0.038
(T - T0) ± 10%
-60
-80
T0 = 25 °C
-100
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70
AI02124
°C
Figure 9. Clock Calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
13/22
M48T128Y, M48T128V*
V
Noise And Negative Going Transients
Figure 10. Supply Voltage Protection
CC
I
transients, including those produced by output
CC
switching, can produce voltage fluctuations, re-
sulting in spikes on the V bus. These transients
CC
can be reduced if capacitors are used to store en-
ergy which stabilizes the V
bus. The energy
CC
stored in the bypass capacitors will be released as
low going spikes are generated or energy will be
absorbed when overshoots occur. A ceramic by-
pass capacitor value of 0.1µF (as shown in Figure
10) is recommended in order to provide the need-
ed filtering.
V
CC
V
CC
0.1µF
DEVICE
In addition to transients that are caused by normal
SRAM operation, power cycling can generate neg-
ative voltage spikes on V
that drive it to values
V
CC
SS
below V by as much as one volt. These negative
SS
spikes can cause data corruption in the SRAM
while in battery backup mode. To protect from
these voltage spikes, it is recommended to con-
AI02169
nect a schottky diode from V
to V
(cathode
CC
SS
connected to V , anode to V ). Schottky diode
CC
SS
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
14/22
M48T128Y, M48T128V*
MAXIMUM RATING
Stressing the device above the rating listed in the
“Absolute Maximum Ratings” table may cause
permanent damage to the device. These are
stress ratings only and operation of the device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Exposure to Absolute Maximum Rat-
ing conditions for extended periods may affect de-
vice
reliability.
Refer
also
to
the
STMicroelectronics SURE Program and other rel-
evant quality documents.
Table 6. Absolute Maximum Ratings
Symbol
Parameter
Ambient Operating Temperature
Value
0 to 70
Unit
°C
T
A
T
Storage Temperature (V Off, Oscillator Off)
–40 to 85
°C
STG
CC
(1)
Lead Solder Temperature for 10 seconds
Input or Output Voltages
260
°C
T
SLD
V
–0.3 to 7
–0.3 to 7
–0.3 to 4.6
20
V
V
IO
M48T128Y
M48T128V
V
Supply Voltage
CC
I
Output Current
mA
W
O
P
Power Dissipation
1
D
Note: 1. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
No preheat above 150°C, or direct exposure to IR reflow (or IR preheat) allowed, to avoid damaging the Lithium battery.
CAUTION: Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up mode.
15/22
M48T128Y, M48T128V*
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, as well as the DC and AC
characteristics of the device. The parameters in
the following DC and AC Characteristic tables are
derived from tests performed under the Measure-
ment Conditions listed in the relevant tables. De-
signers should check that the operating conditions
in their projects match the measurement condi-
tions when using the quoted parameters.
Table 7. Operating and AC Measurement Conditions
Parameter
Supply Voltage (V
M48T128Y
M48T128V
3.0 to 3.6
0 to 70
50
Unit
V
)
4.5 to 5.5
0 to 70
100
CC
Ambient Operating Temperature (T )
°C
pF
ns
V
A
Load Capacitance (C )
L
Input Rise and Fall Times
≤ 5
≤ 5
Input Pulse Voltages
0 to 3
1.5
0 to 3
1.5
Input and Output Timing Ref. Voltages
V
Note: Output Hi-Z is defined as the point where data is no longer driven.
Figure 11. AC Testing Load Circuit
650Ω
DEVICE
UNDER
TEST
1.75V
C
= 100pF
L
or 50pF(1)
C
includes JIG capacitance
L
AI03630
Note: 50pF for M48T128V.
Table 8. Capacitance
Symbol
(1,2)
Min
Max
Unit
pF
Parameter
C
Input Capacitance
Input / Output Capacitance
20
20
IN
(3)
pF
C
IO
Note: 1. Effective capacitance measured with power supply at 5V. Sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
16/22
M48T128Y, M48T128V*
Table 9. DC Characteristics
M48T128Y
–70
M48T128V
(1)
Symbol
Parameter
–85
Unit
Test Condition
Min
Max
Min
Max
I
0V ≤ V ≤ V
Input Leakage Current
Output Leakage Current
Supply Current
±2
±2
95
±2
µA
µA
LI
IN
CC
(2)
0V ≤ V
≤ V
CC
±2
50
I
OUT
LO
I
Outputs open
mA
CC
Supply Current (Standby)
TTL
I
E = V
8
4
mA
mA
CC1
IH
Supply Current (Standby)
CMOS
I
E = V – 0.2V
4
3
CC2
CC
V
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
–0.3
2.2
0.8
–0.3
2.2
0.4
V
V
V
V
IL
V
IH
V
+ 0.3
V
+ 0.3
CC
CC
V
OL
I
= 2.1mA
= –1mA
0.4
0.4
OL
V
OH
I
OH
2.4
2.2
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. Outputs deselected.
17/22
M48T128Y, M48T128V*
Figure 12. Power Down/Up Mode AC Waveforms
V
CC
V
V
V
(max)
(min)
PFD
PFD
SS
tDR
tF
tREC
tFB
tRB
DON'T CARE
RECOGNIZED
RECOGNIZED
INPUTS
HIGH-Z
OUTPUTS
VALID
VALID
AI03612
Table 10. Power Down/Up AC Characteristics
(1)
Symbol
Min
Max
Unit
Parameter
(2)
V
(max) to V
(min) to V
(min) V Fall Time
300
µs
t
PFD
PFD
PFD
PFD
CC
F
(3)
V
V
V
V
V
Fall Time
10
0
µs
µs
µs
ms
t
SS CC
FB
t
(min) to V
(max) V Rise Time
PFD CC
R
t
to V
(min) V Rise Time
PFD CC
1
RB
SS
t
(max) to Inputs Recognized
40
200
REC
PFD
Note: 1. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
2. V
(max) to V
(min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after V pass-
PFD CC
PFD
es V
(min).
PFD
3. V
(min) to V fall time of less than t may cause corruption of RAM data.
PFD
SS FB
Table 11. Power Down/Up Trip Points DC Characteristics
(1,2)
Symbol
Min
Typ
Max
Unit
Parameter
M48T128Y
M48T128V
M48T128Y
M48T128V
4.1
2.7
4.35
2.9
4.5
3.0
V
V
V
V
V
Power-fail Deselect Voltage
PFD
3.0
V
Battery Back-up Switchover Voltage
Expected Data Retention Time
SO
V
–100mV
PFD
(3)
10
YEARS
t
DR
Note: 1. All voltages referenced to V
.
SS
2. Valid for Ambient Operating Temperature: T = 0 to 70°C; V = 4.5 to 5.5V or 3.0 to 3.6V (except where noted).
A
CC
3. At 25°C; V = 0V.
CC
18/22
M48T128Y, M48T128V*
PACKAGE MECHANICAL INFORMATION
Figure 13. PMDIP32 – 32-pin Plastic Module DIP, Package Outline
A
A1
e1
L
C
eA
S
B
e3
D
N
1
E
PMDIP
Note: Drawing is not to scale.
Table 12. PMDIP32 – 32-pin Plastic Module DIP, Package Mechanical Data
mm
inches
Min
Symb
Typ
Min
9.27
0.38
0.43
0.20
42.42
18.03
2.29
34.29
14.99
3.05
1.91
32
Max
9.52
–
Typ
Max
0.375
–
A
A1
B
0.365
0.015
0.017
0.008
1.670
0.710
0.090
1.350
0.590
0.120
0.075
32
0.59
0.33
43.18
18.80
2.79
41.91
16.00
3.81
2.79
0.023
0.013
1.700
0.740
0.110
1.650
0.630
0.150
0.110
C
D
E
e1
e3
eA
L
S
N
19/22
M48T128Y, M48T128V*
PART NUMBERING
Table 13. Ordering Information Scheme
Example:
M48T
128Y
–70
PM
1
TR
Device Type
M48T
Supply Voltage and Write Protect Voltage
128Y = V = 4.5 to 5.5V; V
= 4.1 to 4.5V
CC
PFD
(1)
128V = V = 3.0 to 3.6V; V
= 2.7 to 3.0V
PFD
CC
Speed
–70 = 70ns (128Y)
–85 = 85ns (128V)
Package
PM = PMDIP32
Temperature Range
1 = 0 to 70°C
Shipping Method for SOIC
blank = Tubes
TR = Tape & Reel
Note: 1. Contact local ST sales office for availability of 3.3V version.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office
nearest you.
20/22
M48T128Y, M48T128V*
REVISION HISTORY
Table 14. Document Revision History
Date
Version
1.0
Revision Details
June 1998
01/31/00
03/30/00
07/20/01
09/21/01
05/23/02
08/07/02
28-Mar-03
06-Aug-04
22-Feb-05
First Issue
1.1
Calibrating The Clock Paragraph changed
Storage Temperature changed (Table 6)
1.2
2.0
Reformatted; temperature information added to tables (Table 8, 9, 3, 4, 10, 11)
Corrected speed grade in ordering information
Add countries to disclaimer; add marketing status
Refine marketing status text
2.1
2.2
2.3
3.0
v2.2 template applied; test condition updated (Table 11)
Reformatted; updated Register Map (Table 5)
IR reflow update (Table 6)
4.0
5.0
21/22
M48T128Y, M48T128V*
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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22/22
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