M34E02-FDW1T [STMICROELECTRONICS]
2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs; 2千位串行I2C总线EEPROM串行存在检测的DDR2 DIMM内存模块
| 型号： | M34E02-FDW1T |
| 厂家： | 
ST |
| 描述： | 2 Kbit Serial IC Bus EEPROM Serial Presence Detect for DDR2 DIMMs |
| 文件： | 总23页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M34E02
2 Kbit Serial I²C Bus EEPROM
Serial Presence Detect for DDR2 DIMMs
FEATURES SUMMARY
■
■
■
■
■
■
■
■
■
■
■
Software Data Protection for lower 128 bytes
Figure 1. Packages
Two Wire I2C Serial Interface
100kHz Transfer Rates
1.7 to 3.6V Single Supply Voltage:
BYTE and PAGE WRITE (up to 16 bytes)
RANDOM and SEQUENTIAL READ Modes
Self-Timed Programming Cycle
Automatic Address Incrementing
Enhanced ESD/Latch-Up Protection
More than 1 Million Erase/Write Cycles
More than 40 Year Data Retention
UFDFPN8 (MB)
2x3mm² (MLP)
TSSOP8 (DW)
4.4x3mm²
November 2004
1/23
M34E02
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TSSOP and MLP Connections (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset: VCC Lock-Out Write Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus . . . . . . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Result of Setting the Write Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Setting the Write-Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SWP and CWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
PSWP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Setting the Write Protection (WC = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. Write Mode Sequences in a Non Write-Protected Area . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 9. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 10.Read Mode Sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/23
M34E02
USE WITHIN A DDR2 DIMM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. DRAM DIMM Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Programming the M34E02 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DDR2 DIMM Isolated. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
DDR2 DIMM Inserted in the Application Mother Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 5. Acknowledge when Writing Data or Defining the Write-protection
(Instructions with R/W bit=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Acknowledge when Reading the Write Protection (Instructions with R/W bit=1). . . . . . . 13
Figure 11.Serial Presence Detect Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 12.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 10. Input Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 13.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Mechanical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 20
Table 14. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 20
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/23
M34E02
SUMMARY DESCRIPTION
The M34E02 is a 2 Kbit serial EEPROM memory
able to lock permanently the data in its first half
(from location 00h to 7Fh). This facility has been
designed specifically for use in DRAM DIMMs
(dual interline memory modules) with Serial
Presence Detect. All the information concerning
the DRAM module configuration (such as its
access speed, its size, its organization) can be
kept write protected in the first half of the memory.
This bottom half of the memory area can be write-
protected using two different software write
protection mechanisms. By sending the device a
specific sequence, the first 128 bytes of the
memory become write protected: permanently or
resetable. In addition, the device allows the entire
memory area to be write protected, using the WC
input (for example by tieing this input to VCC).
Device Select Code and RW bit (as described in
Table 2), terminated by an acknowledge bit.
When writing data to the memory, the memory
inserts an acknowledge bit during the 9th bit time,
following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
in the same way. Data transfers are terminated by
a STOP condition after an Ack for WRITE, and
after a NoAck for READ.
Figure 3. TSSOP and MLP Connections (Top
View)
M34E02
These I2C-compatible electrically erasable
programmable memory (EEPROM) devices are
organized as 256x8 bits.
E0
E1
E2
1
2
3
4
8
V
CC
WC
7
6
SCL
SDA
Figure 2. Logic Diagram
V
5
SS
AI09021
V
CC
Note: 1. See the pages after page 19 for package dimensions,
and how to identify pin-1.
3
E0-E2
SDA
Table 1. Signal Names
M34E02
E0, E1, E2
SDA
Chip Enable
Serial Data
Serial Clock
Write Control
Supply Voltage
Ground
SCL
WC
SCL
WC
V
SS
V
V
CC
SS
AI09020
I2C uses a two wire serial interface, comprising a
bi-directional data line and a clock line. The device
carries a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I2C bus definition to
access the memory area and a second Device
Type Identifier Code (0110) to define the
protection. These codes are used together with
the voltage level applied on the three chip enable
inputs (E2, E1, E0).
The device behaves as a slave device in the I2C
protocol, with all memory operations synchronized
by the serial clock. Read and Write operations are
initiated by a START condition, generated by the
bus master. The START condition is followed by a
Power On Reset: VCC Lock-Out Write Protect
In order to prevent data corruption and inadvertent
Write operations during power up, a Power On
Reset (POR) circuit is included. At Power-on, the
internal reset is held active until VCC has reached
the POR threshold value, and all operations are
disabled – the device will not respond to any
command. In the same way, when VCC drops from
the operating voltage, below the POR threshold
value, all operations are disabled and the device
will not respond to any command.
A stable and valid VCC (as defined in Table 8) must
be applied before applying any logic signal.
4/23
M34E02
SIGNAL DESCRIPTION
Serial Clock (SCL)
Chip Enable (E0, E1, E2)
This input signal is used to strobe all data in and
out of the device. In applications where this signal
is used by slave devices to synchronize the bus to
a slower clock, the bus master must have an open
drain output, and a pull-up resistor can be con-
nected from Serial Clock (SCL) to VCC. (Figure 4
indicates how the value of the pull-up resistor can
be calculated). In most applications, though, this
method of synchronization is not employed, and
so the pull-up resistor is not necessary, provided
that the bus master has a push-pull (rather than
open drain) output.
These input signals are used to set the value that
is to be looked for on the three least significant bits
(b3, b2, b1) of the 7-bit Device Select Code. In the
end application, E0, E1 and E2 must be directly
(not through a pull-up or pull-down resistor) con-
nected to VCC or VSS to establish the Device Se-
lect Code. When these inputs are not connected,
an internal pull-down circuitry makes (E0,E1,E2) =
(0,0,0).
The E0 input is used to detect the VHV voltage,
when decoding an SWP or CWP instruction.
Write Control (WC)
Serial Data (SDA)
This input signal is provided for protecting the con-
tents of the whole memory from inadvertent write
operations. Write Control (WC) is used to enable
(when driven Low) or disable (when driven High)
write instructions to the entire memory area or to
the Protection Register.
When Write Control (WC) is tied Low or left
unconnected, the write protection of the first half of
the memory is determined by the status of the
Protection Register.
This bi-directional signal is used to transfer data in
or out of the device. It is an open drain output that
may be wire-OR’ed with other open drain or open
collector signals on the bus. A pull up resistor must
be connected from Serial Data (SDA) to VCC. (Fig-
ure 4 indicates how the value of the pull-up resistor
can be calculated).
Figure 4. Maximum RL Value versus Bus Capacitance (CBUS) for an I2C Bus
V
CC
20
16
12
R
R
L
L
SDA
MASTER
C
BUS
8
SCL
fc = 100kHz
4
0
fc = 400kHz
C
BUS
10
100
(pF)
1000
C
BUS
AI01665
5/23
M34E02
Figure 5. I2C Bus Protocol
SCL
SDA
SDA
Input
SDA
Change
START
Condition
STOP
Condition
1
2
3
7
8
9
SCL
SDA
ACK
MSB
START
Condition
1
2
3
7
8
9
SCL
SDA
MSB
ACK
STOP
Condition
AI00792B
Table 2. Device Select Code
Chip Enable Signals
Device Type Identifier
Chip Enable Bits
RW
1
b6
0
b5
1
b4
0
b3
E2
b2
E1
b1
E0
b0
b7
1
Memory Area Select Code
E2
E1
E0
RW
2
(two arrays)
V
V
V
Set Write Protection (SWP)
Clear Write Protection (CWP)
Permanently Set Write
0
0
0
1
1
1
0
0
SS
SS
HV
HV
V
SS
V
V
CC
E2
E1
E0
E2
E1
E0
0
2
Protection (PSWP)
0
1
1
0
V
V
V
V
V
Read SWP
Read CWP
0
0
0
1
1
1
1
1
1
SS
SS
HV
HV
V
SS
CC
2
E2
E1
E0
E2
E1
E0
Read PSWP
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.
6/23
M34E02
DEVICE OPERATION
The device supports the I2C protocol. This is sum-
marized in Figure 5. Any device that sends data on
to the bus is defined to be a transmitter, and any
device that reads the data to be a receiver. The
device that controls the data transfer is known as
the bus master, and the other as the slave device.
A data transfer can only be initiated by the bus
master, which will also provide the serial clock for
synchronization. The memory device is always a
slave in all communication.
Data Input
During data input, the device samples Serial Data
(SDA) on the rising edge of Serial Clock (SCL).
For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
en Low.
Memory Addressing
To start communication between the bus master
and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
sends the Device Select Code, shown in Table 2
(on Serial Data (SDA), most significant bit first).
The Device Select Code consists of a 4-bit Device
Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
bit Device Type Identifier is 1010b; to access the
write-protection settings, it is 0110b.
Start Condition
Start is identified by a falling edge of Serial Data
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given.
Stop Condition
Stop is identified by a rising edge of Serial Data
(SDA) while Serial Clock (SCL) is stable and driv-
en High. A Stop condition terminates communica-
tion between the device and the bus master. A
Read command that is followed by NoAck can be
followed by a Stop condition to force the device
into the Stand-by mode. A Stop condition at the
end of a Write command triggers the internal EE-
PROM Write cycle.
Up to eight memory devices can be connected on
a single I2C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
When the Device Select Code is received, the
device only responds if the Chip Enable Address
is the same as the value on the Chip Enable (E0,
E1, E2) inputs.
The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
Acknowledge Bit (ACK)
If a match occurs on the Device Select code, the
corresponding device gives an acknowledgment
on Serial Data (SDA) during the 9th bit time. If the
device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be
bus master or slave device, releases Serial Data
(SDA) after sending eight bits of data. During the
9th clock pulse period, the receiver pulls Serial
Data (SDA) Low to acknowledge the receipt of the
eight data bits.
Table 3. Operating Modes
1
Mode
RW bit
Bytes
Initial Sequence
WC
X
Current Address Read
1
0
1
1
0
0
1
START, Device Select, RW = 1
X
START, Device Select, RW = 0, Address
reSTART, Device Select, RW = 1
Similar to Current or Random Address Read
START, Device Select, RW = 0
Random Address Read
1
X
Sequential Read
Byte Write
X
≥ 1
1
VIL
VIL
Page Write
≤ 16
START, Device Select, RW = 0
Note: 1. X = VIH or VIL.
7/23
M34E02
Figure 6. Result of Setting the Write Protection
FFh
Standard
Array
FFh
Standard
Array
Memory
80h
80h
7Fh
Area
7Fh
Write
Protected
Array
Standard
Array
00h
00h
Default EEPROM memory area
state before write access
to the Protect Register
State of the EEPROM memory
area after write access
to the Protect Register
AI01936C
Setting the Write-Protection
SWP and CWP. If the software write-protection
has been set with the SWP instruction, it can be
cleared again with a CWP instruction.
The M34E02 has a hardware write-protection
feature, using the Write Control (WC) signal. This
signal can be driven High or Low, and must be
held constant for the whole instruction sequence.
When Write Control (WC) is held High, the whole
memory array (addresses 00h to FFh) is write
protected. When Write Control (WC) is held Low,
the write protection of the memory array is
dependent on whether software write-protection
has been set.
Software write-protection allows the bottom half of
the memory area (addresses 00h to 7Fh) to be
write protected irrespective of subsequent states
of the Write Control (WC) signal.
Software write-protection is handled by three in-
structions:
– SWP: Set Write Protection
– CWP: Clear Write Protection
– PSWP: Permanently Set Write Protection
The two instructions (SWP and CWP) have the
same format as a Byte Write instruction, but with a
different Device Type Identifier (as shown in Table
2). Like the Byte Write instruction, it is followed by
an address byte and a data byte, but in this case
the contents are all “Don’t Care” (Figure 7). Anoth-
er difference is that the voltage, VHV, must be ap-
plied on the E0 pin, and specific logical levels must
be applied on the other two (E1 and E2, as shown
in Table 2).
PSWP. If the software write-protection has been
set with the PSWP instruction, the first 128 bytes
of the memory are permanently write-protected.
This write-protection cannot be cleared by any in-
struction, or by power-cycling the device, and re-
gardless the state of Write Control (WC). Also,
once the PSWP instruction has been successfully
executed, the M34E02 no longer acknowledges
any instruction (with a Device Type Identifier of
0110) to access the write-protection settings.
The level of write-protection (set or cleared) that
has been defined using these instructions, re-
mains defined even after a power cycle.
Figure 7. Setting the Write Protection (WC = 0)
BUS ACTIVITY
MASTER
CONTROL
BYTE
WORD
ADDRESS
DATA
SDA LINE
BUS ACTIVITY
ACK
ACK
ACK
VALUE
VALUE
(DON'T CARE) (DON'T CARE)
AI01935B
8/23
M34E02
Figure 8. Write Mode Sequences in a Non Write-Protected Area
ACK
ACK
ACK
ACK
BYTE WRITE
DEV SEL
BYTE ADDR
DATA IN
R/W
ACK
BYTE ADDR
ACK
PAGE WRITE
DEV SEL
ACK
DATA IN 1
DATA IN 2
R/W
ACK
DATA IN N
AI01941
Write Operations
replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown
in Figure 8.
Following a Start condition the bus master sends
a Device Select Code with the RW bit reset to 0.
The device acknowledges this, as shown in Figure
8, and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10th bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC) is Low. If the addressed loca-
tion is hardware write-protected, the device replies
to the data byte with NoAck, and the locations are
not modified. After each byte is transferred, the in-
ternal byte address counter (the 4 least significant
address bits only) is incremented. The transfer is
terminated by the bus master generating a Stop
condition.
Byte Write
After the Device Select Code and the address
byte, the bus master sends one data byte. If the
addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and
the location is not modified. If, instead, the ad-
dressed location is not Write-protected, the device
9/23
M34E02
Figure 9. Write Cycle Polling Flowchart using ACK
WRITE Cycle
in Progress
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
NO
First byte of instruction
with RW = 0 already
decoded by the device
YES
Next
Operation is
Addressing the
Memory
NO
YES
Send Address
and Receive ACK
ReSTART
START
NO
YES
STOP
Condition
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Continue the
Continue the
Random READ Operation
WRITE Operation
AI01847C
Minimizing System Delays by Polling On ACK
The sequence, as shown in Figure 9, is:
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first byte
of the new instruction).
The maximum Write time (t ) is shown in Table
w
12, but the typical time is shorter. To make use of
this, a polling sequence can be used by the bus
master.
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the bus
master goes back to Step 1. If the device has
terminated the internal Write cycle, it responds
with an Ack, indicating that the device is ready
to receive the second part of the instruction (the
first byte of this instruction having been sent
during Step 1).
10/23
M34E02
Figure 10. Read Mode Sequences
ACK
NO ACK
DATA OUT
CURRENT
ADDRESS
READ
DEV SEL
R/W
ACK
ACK
ACK
NO ACK
DATA OUT
RANDOM
ADDRESS
READ
DEV SEL *
BYTE ADDR
DEV SEL *
R/W
R/W
ACK
ACK
ACK
NO ACK
DATA OUT N
SEQUENTIAL
CURRENT
READ
DEV SEL
DATA OUT 1
R/W
ACK
ACK
ACK
ACK
SEQUENTIAL
RANDOM
READ
DEV SEL *
BYTE ADDR
DEV SEL * DATA OUT 1
R/W
R/W
ACK
NO ACK
DATA OUT N
AI01942
st
rd
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1 and 3 bytes) must be identical.
Read Operations
and outputs the contents of the addressed byte.
The bus master must not acknowledge the byte,
and terminates the transfer with a Stop condition.
Read operations are performed independently of
whether hardware or software protection has been
set.
Current Address Read
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 10) but without sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
RW bit set to 1. The device acknowledges this,
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 10, without acknowledging the
byte.
11/23
M34E02
Sequential Read
Table 4. DRAM DIMM Connections
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 10.
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
DIMM Position
E2
E1
E0
V
V
SS
V
SS
0
1
2
3
4
5
6
7
SS
SS
SS
SS
V
V
V
V
V
V
V
SS
CC
V
V
CC
CC
SS
V
CC
V
V
V
V
CC
CC
CC
CC
SS
SS
SS
CC
V
V
V
V
V
SS
CC
CC
V
V
CC
Acknowledge in Read Mode
Programming the M34E02
The situations in which the M34E02 is pro-
grammed can be considered under two headings:
– when the DDR2 DIMM is isolated (not inserted
on the PCB motherboard)
– when the DDR2 DIMM is inserted on the PCB
motherboard
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9th bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
DDR2 DIMM Isolated. With specific program-
ming equipment, it is possible to define the
M34E02 content, using Byte and Page Write in-
structions, and its write-protection using the SWP
and CWP instructions. To issue the SWP and
CWP instructions, the DDR2 DIMM must be insert-
ed in the DDR2-specific slot where the E0 signal
can be driven to VHV during the whole instruction.
This programming step is mainly intended for use
by DDR2 DIMM makers, whose end application
manufacturers will want to clear this write-protec-
tion with the CWP on their own specific program-
ming equipment, to modify the lower 128 Bytes,
and finally to set permanently the write-protection
with the PSWP instruction.
DDR2 DIMM Inserted in the Application Mother
Board. As the final application cannot drive the
E0 pin to VHV, the only possible action is to freeze
the write-protection with the PSWP instruction.
Table 5 and Table 6 show how the Ack bits can be
used to identify the write-protection status.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
USE WITHIN A DDR2 DIMM
In the application, the M34E02 is soldered directly
in the printed circuit module. The three Chip
Enable inputs (E0, E1, E2) must be connected to
VSS or VCC directly (that is without using a pull-up
or pull-down resistor) through the DIMM socket
(see Table 4.). The pull-up resistors needed for
normal behavior of the I2C bus are connected on
the I2C bus of the mother-board (as shown in
Figure 11).
The Write Control (WC) of the M34E02 can be left
unconnected. However, connecting it to VSS is
recommended, to maintain full read and write
access.
12/23
M34E02
Table 5. Acknowledge when Writing Data or Defining the Write-protection
(Instructions with R/W bit=0)
Write
Cycle
(t )
W
WC
Input
Level
Status
Instruction
Ack
Address
Ack
Data Byte
Ack
Not
significant
Not
significant
PSWP, SWP or CWP NoAck
NoAck
Ack
NoAck
NoAck
NoAck
Ack
No
No
No
Yes
Yes
No
No
No
Permanently
protected
X
Page or Byte Write in
Ack
Address
Data
lower 128 Bytes
Not
significant
Not
significant
SWP
CWP
NoAck
Ack
NoAck
Ack
Not
significant
Not
significant
Not
significant
Not
significant
0
1
PSWP
Ack
Ack
Ack
Page or Byte Write in
lower 128 Bytes
Ack
Address
Ack
Data
NoAck
NoAck
NoAck
Protected with
SWP
Not
significant
Not
significant
SWP
CWP
NoAck
Ack
NoAck
Ack
Not
significant
Not
significant
Not
significant
Not
significant
PSWP
Ack
Ack
Ack
Ack
Ack
Ack
Ack
Ack
Ack
Ack
Ack
Ack
NoAck
NoAck
Ack
No
No
Page or Byte Write
PSWP, SWP or CWP
Page or Byte Write
PSWP, SWP or CWP
Page or Byte Write
Address
Data
Not
significant
Not
significant
0
1
Yes
Yes
No
Address
Data
Ack
Not Protected
Not
significant
Not
significant
NoAck
NoAck
Address
Data
No
Table 6. Acknowledge when Reading the Write Protection (Instructions with R/W bit=1)
Status
Instruction
Ack
Address
Ack
Data byte
Ack
Permanently
protected
PSWP, SWP or CWP
NoAck
Not significant
NoAck
Not significant
NoAck
SWP
CWP
NoAck
Ack
Not significant
Not significant
Not significant
Not significant
NoAck
NoAck
NoAck
NoAck
Not significant
Not significant
Not significant
Not significant
NoAck
NoAck
NoAck
NoAck
Protected with
SWP
PSWP
Ack
Not Protected
PSWP, SWP or CWP
Ack
13/23
M34E02
Figure 11. Serial Presence Detect Block Diagram
R = 4.7kΩ
DIMM Position 7
E2
E1
E0 SCL SDA
V
CC
DIMM Position 6
DIMM Position 5
DIMM Position 4
DIMM Position 3
DIMM Position 2
DIMM Position 1
DIMM Position 0
E2
E1
E0 SCL SDA
V
V
SS
CC
E2
E1
E0 SCL SDA
V
V
V
CC
CC
SS
E2
E1
E0 SCL SDA
V
V
SS
CC
E2
E1
E1
E0 SCL SDA
V
V
CC
SS
E2
E0 SCL SDA
V
V
V
SS
SS
CC
E2
E1
E0 SCL SDA
V
V
CC
SS
E2
E1
E0 SCL SDA
V
SS
SCL line
SDA line
From the motherboard
I2C master controller
AI01937
Note: 1. E0, E1 and E2 are wired at each DIMM socket in a binary sequence for a maximum of 8 devices.
2. Common clock and common data are shared across all the devices.
3. Pull-up resistors are required on all SDA and SCL bus lines (typically 4.7 kΩ) because these lines are open drain when used as
outputs.
14/23
M34E02
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Parameter
Min.
Max.
Unit
°C
Storage Temperature
–65
150
1
1
TLEAD
°C
Lead Temperature during Soldering
Input or Output range
See note
E0
Others
–0.50
–0.50
10.0
6.5
VIO
V
VCC
Supply Voltage
–0.5
6.5
V
V
2
VESD
–4000
4000
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020B (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
15/23
M34E02
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 8. Operating Conditions
Symbol
Parameter
Min.
1.7
0
Max.
3.6
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
70
°C
Table 9. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
100
L
Input Rise and Fall Times
Input Levels
50
0.2V to 0.8V
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Levels
V
CC
Figure 12. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.3V
CC
0.2V
CC
AI00825B
Table 10. Input Parameters
1,2
Symbol
CIN
Test Condition
Min.
Max.
Unit
pF
Parameter
Input Capacitance (SDA)
Input Capacitance (other pins)
8
6
CIN
pF
Ei (E0, E1, E2) Input
Impedance
ZEiL
ZEiH
VIN < 0.3VCC
VIN > 0.7VCC
30
kΩ
kΩ
Ei (E0, E1, E2) Input
Impedance
800
ZWCL
ZWCH
WC Input Impedance
WC Input Impedance
V
V
IN < 0.3VCC
IN > 0.7VCC
5
kΩ
kΩ
500
Pulse width ignored
(Input Filter on SCL and SDA)
tNS
Single glitch
100
ns
Note: 1. T = 25 °C, f = 400 kHz
A
2. Sampled only, not 100% tested.
16/23
M34E02
Table 11. DC Characteristics
Test Condition
(in addition to those in Table 8)
1
1
Symbol
Parameter
Unit
Min.
Max.
Input Leakage Current
(SCL, SDA)
ILI
VIN = VSS or VCC
± 2
± 2
1
µA
µA
ILO
ICC
Output Leakage Current
Supply Current
VOUT = VSS or VCC, SDA in Hi-Z
VCC =1.7V, f =100kHz (rise/fall time <
c
mA
30ns)
VIN = VSS or VCC, VCC = 3.6V
1
µA
µA
ICC1
Stand-by Supply Current
V
IN = VSS or VCC, VCC = 1.7V
0.5
Input Low Voltage
(SCL, SDA, WC)
VIL
–0.45
0.3 VCC
VCC+1
V
V
Input High Voltage
(SCL, SDA, WC)
VIH
0.7VCC
7
VHV
E0 High Voltage
V
HV – VCC ≥ 4.8V
IOL = 2.1mA, 2.2V ≤ VCC ≤ 3.6V
OL = 0.7mA, VCC = 1.7V
10
0.4
0.2
V
V
V
VOL
Output Low Voltage
I
Note: 1. Preliminary Data.
Table 12. AC Characteristics
Test conditions specified in Table 9 and 8
Parameter
Symbol
fC
Alt.
fSCL
Min.
Max.
Unit
Clock Frequency
100
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
tCHCL
tCLCH
tHIGH
tLOW
tF
Clock Pulse Width High
Clock Pulse Width Low
4000
4700
20
2
SDA Fall Time
300
tDL1DL2
tDXCX
tCLDX
tCLQX
tSU:DAT
tHD:DAT
tDH
Data In Set Up Time
250
0
Data In Hold Time
Data Out Hold Time
200
200
4700
4000
4000
4700
3
tAA
Clock Low to Next Data Valid (Access Time)
Start Condition Set Up Time
Start Condition Hold Time
Stop Condition Set Up Time
Time between Stop Condition and Next Start Condition
Write Time
3500
tCLQV
1
tSU:STA
tHD:STA
tSU:STO
tBUF
tCHDX
tDLCL
tCHDH
tDHDL
tW
tWR
10
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
17/23
M34E02
Figure 13. AC Waveforms
tCHCL
tCLCH
SCL
tDLCL
SDA In
tCHDX
tCLDX
tDXCX
SDA
tCHDH tDHDL
Change
START
Condition
START
Condition
SDA
Input
STOP
Condition
SCL
SDA In
tCHDH
STOP
tCHDX
START
Condition
tW
Write Cycle
Condition
SCL
tCLQV
tCLQX
Data Valid
SDA Out
AI00795C
18/23
M34E02
PACKAGE MECHANICAL
Figure 14. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Outline
e
b
D
L1
L3
E
E2
L
A
D2
ddd
A1
UFDFPN-01
Note: 1. Drawing is not to scale.
2. The central pad (the area E2 by D2 in the above illustration) is pulled, internally, to V . It must not be allowed to be connected to
SS
any other voltage or signal line on the PCB, for example during the soldering process.
Table 13. UFDFPN8 (MLP8) 8-lead Ultra thin Fine pitch Dual Flat Package No lead 2x3mm²,
Package Mechanical Data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
0.60
0.05
0.30
Typ.
Max.
0.024
0.002
0.012
A
A1
b
0.55
0.50
0.022
0.020
0.000
0.008
0.00
0.25
2.00
0.20
0.010
0.079
D
D2
ddd
E
1.55
1.65
0.05
0.061
0.065
0.002
3.00
0.118
E2
e
0.15
–
0.25
–
0.006
–
0.010
–
0.50
0.45
0.020
0.018
L
0.40
0.50
0.15
0.016
0.020
0.006
L1
L3
N
0.30
8
0.012
8
19/23
M34E02
Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D
8
5
c
E1
E
1
4
α
A1
L
A
A2
L1
CP
b
e
TSSOP8AM
Notes: 1. Drawing is not to scale.
Table 14. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
millimeters
Min.
inches
Min.
Symbol
Typ.
Max.
1.200
0.150
1.050
0.300
0.200
0.100
3.100
–
Typ.
Max.
0.0472
0.0059
0.0413
0.0118
0.0079
0.0039
0.1220
–
A
A1
A2
b
0.050
0.800
0.190
0.090
0.0020
0.0315
0.0075
0.0035
1.000
0.0394
c
CP
D
3.000
0.650
6.400
4.400
0.600
1.000
2.900
–
0.1181
0.0256
0.2520
0.1732
0.0236
0.0394
0.1142
–
e
E
6.200
4.300
0.450
6.600
4.500
0.750
0.2441
0.1693
0.0177
0.2598
0.1772
0.0295
E1
L
L1
α
0°
8
8°
0°
8
8°
N
20/23
M34E02
PART NUMBERING
Table 15. Ordering Information Scheme
Example:
M34E02
–
F
DW
1
T
P
Device Type
2
M34 = ASSP I C serial access EEPROM
Device Function
E02 = 2 Kbit (256 x 8) SPD (Serial Presence Detect) for DDR2
Operating Voltage
F = V = 1.7 to 3.6V (100kHz)
CC
Package
MB = UDFDFPN8 (MLP8)
DW = TSSOP8 (4.4x3mm² body size)
Temperature Range
1 = 0 to 70 °C
Option
blank = Standard Packing
T = Tape & Reel Packing
Plating Technology
blank = Standard SnPb plating
P = Lead-Free and RoHS compliant
G = Lead-Free, RoHS compliant, Sb O -free and TBBA-free
2
3
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
21/23
M34E02
REVISION HISTORY
Table 16. Revision History
Date
Rev.
Description of Revision
13-Nov-2003
1.0
First release
TSSOP8 4.4x3 package replaces TSSOP8 3x3 (MSOP8) package. Correction to sentence in
01-Dec-2003
1.1
“Setting the Write Protection”. Correction to specification of t values.
NS
Always NoACK after Address and Data bytes in Table 6. Improvement in V and V (min) in
IO
CC
Absolute Maximum Ratings table. I changed for test condition of V . MLP package
mechanical data respecified. Soldering temperature information clarified for RoHS compliant
devices.
OL
OL
29-Mar-2004
14-Apr-2004
1.2
2.0
First public release
Direct connection of E0, E1, E2 to V and V (see Chip Enable (E0, E1, E2) and USE
SS
CC
WITHIN A DDR2 DIMM paragraphs). Z and Z
parameters added to Table 10., Input
EiH
EiL
24-Nov-2004
3.0
Parameters. E0, E1, E2 removed from the Parameter descriptions of V and V in Table
IL
IH
11., DC Characteristics.
Document status promoted from Product Preview to full Datasheet.
22/23
M34E02
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