M27V320-120M6 [STMICROELECTRONICS]
32 Mbit 4Mb x8 or 2Mb x16 OTP EPROM; 32兆位4Mb的X8或X16的2Mb OTP EPROM
| 型号： | M27V320-120M6 |
| 厂家： | 
ST |
| 描述： | 32 Mbit 4Mb x8 or 2Mb x16 OTP EPROM |
| 文件： | 总15页 (文件大小：147K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27V320
32 Mbit (4Mb x8 or 2Mb x16) OTP EPROM
■ 3.3V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ ACCESS TIME: 100ns
■ BYTE-WIDE or WORD-WIDE
CONFIGURABLE
■ 32 Mbit MASK ROM REPLACEMENT
■ LOW POWER CONSUMPTION
– Active Current 30mA at 5MHz
– Standby Current 60µA
SO44 (M)
TSOP48 (N)
12 x 20 mm
■ PROGRAMMING VOLTAGE: 12V ± 0.25V
■ PROGRAMMING TIME: 50µs/word
■ ELECTRONIC SIGNATURE:
– Manufacturer Code 20h
Figure 1. Logic Diagram
– Device Code: 32h
DESCRIPTION
The M27V320 is a low voltage 32 Mbit EPROM of-
fered in the OTP range (one time programmable).
It is ideally suited for microprocessor systems re-
quiring large data or program storage. It is organ-
ised as either 4 MWords of 8 bit or 2 MWords of 16
bit. The pin-out is compatible with the 32 Mbit
Mask ROM.
V
CC
21
Q15A–1
A0-A20
E
15
The M27V320 is offered in SO44 and TSOP48
(12 x 20 mm) packages.
Q0-Q14
BYTE
M27V320
GV
PP
V
SS
AI05852
August 2002
1/15
M27V320
Figure 2. SO Connections
Figure 3. TSOP Connections
BYTE
A16
A15
A14
A13
A12
A11
A10
A9
1
48
V
V
SS
SS
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A20
A19
A8
2
Q15A–1
3
Q7
4
A9
Q14
Q6
5
A10
A11
A12
A13
A14
A15
A16
BYTE
6
Q13
Q5
7
8
Q12
Q4
9
A8
10
11
12
13
14
15
16
17
18
19
20
21
22
A19
V
V
V
CC
CC
SS
V
12
13
37
36
M27V320
SS
M27V320
A20
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
V
V
SS
Q15A–1
SS
Q11
GV
PP
Q0
Q3
Q7
Q10
Q2
Q8
Q1
Q9
Q2
Q14
Q6
Q9
Q13
Q5
Q1
Q8
Q10
Q3
Q12
Q4
Q0
GV
PP
Q11
V
CC
V
V
SS
SS
AI05853
24
25
AI05854
Table 1. Signal Names
DEVICE OPERATION
The operating modes of the M27V320 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
A0-A20
Q0-Q7
Q8-Q14
Q15A–1
E
Address Inputs
Data Outputs
Data Outputs
compatible except for V and 12V on A9 for the
PP
Electronic Signature.
Read Mode
The M27V320 has two organisations, Word-wide
and Byte-wide. The organisation is selected by the
Data Output / Address Input
Chip Enable
GV
Output Enable / Program Supply
Byte-Wide Select
PP
signal level on the BYTE pin. When BYTE is at V
IH
the Word-wide organisation is selected and the
Q15A–1 pin is used for Q15 Data Output. When
BYTE
V
Supply Voltage
CC
the BYTE pin is at V the Byte-wide organisation
IL
is selected and the Q15A–1 pin is used for the Ad-
dress Input A–1. When the memory is logically re-
garded as 16 bit wide, but read in the Byte-wide
V
Ground
SS
NC
Not Connected Internally
organisation, then with A–1 at V the lower 8 bits
IL
of the 16 bit data are selected and with A–1 at V
the upper 8 bits of the 16 bit data are selected.
IH
2/15
M27V320
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Unit
°C
°C
°C
V
(3)
T
A
Ambient Operating Temperature
T
Temperature Under Bias
Storage Temperature
Input or Output Voltage (except A9)
Supply Voltage
BIAS
T
STG
(2)
V
IO
V
CC
–2 to 7
V
(2)
A9 Voltage
–2 to 13.5
–2 to 14
V
V
A9
V
Program Supply Voltage
V
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
GV
E
BYTE
A9
X
Q15A–1
Q14-Q8
Data Out
Hi-Z
Q7-Q0
Data Out
Data Out
Data Out
Hi-Z
PP
V
V
IL
V
IH
Read Word-wide
Read Byte-wide Upper
Read Byte-wide Lower
Output Disable
Program
Data Out
IL
V
V
V
V
V
V
V
IL
V
IL
V
X
IL
IL
IL
IL
IH
V
IL
X
Hi-Z
IL
X
X
Hi-Z
Data In
Hi-Z
Hi-Z
IH
PP
PP
V
Pulse
V
V
V
V
X
Data In
Hi-Z
Data In
Hi-Z
IL
IH
IH
V
Program Inhibit
Standby
X
IH
V
X
X
X
Hi-Z
Hi-Z
Hi-Z
IH
V
IL
V
IL
V
V
ID
Electronic Signature
Code
Codes
Codes
IH
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
Q4
0
Q3
Q2
0
Q1
0
Q0
0
Hex Data
20h
V
IL
1
1
0
0
V
0
0
1
0
1
0
32h
IH
Note: Outputs Q15-Q8 are set to '0'.
3/15
M27V320
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 4. AC Testing Input Output Waveform
Figure 5. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
10
Unit
pF
C
IN
V
= 0V
= 0V
IN
C
V
OUT
12
pF
OUT
Note: 1. Sampled only, not 100% tested.
The M27V320 has two control functions, both of
which must be logically active in order to obtain
data at the outputs. In addition the Word-wide or
Byte-wide organisation must be selected.
output after a delay of t
from the falling edge
GLQV
of GV , assuming that E has been low and the
PP
addresses have been stable for at least t
-
AVQV
t
.
GLQV
Chip Enable (E) is the power control and should be
Standby Mode
used for device selection. Output Enable (GV ) is
PP
The M27V320 has standby mode which reduces
the supply current from 50mA to 100µA. The
M27V320 is placed in the standby mode by apply-
ing a CMOS high signal to the E input. When in the
standby mode, the outputs are in a high imped-
the output control and should be used to gate data
to the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
dress access time (t
) is equal to the delay
). Data is available at the
AVQV
from E to output (t
ELQV
ance state, independent of the GV input.
PP
4/15
M27V320
(1)
Table 7. Read Mode DC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%; V = V
)
A
CC
PP
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
LO
0V ≤ V
≤ V
OUT CC
±10
µA
E = V , GV = V , I = 0mA,
IL OUT
IL
PP
I
Supply Current
30
mA
CC
f = 5MHz, V ≤ 3.6V
CC
I
I
1
2
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
CC
IH
E > V – 0.2V, V ≤ 3.6V
60
10
CC
CC
CC
I
V
= V
PP CC
PP
V
0.2V
CC
Input Low Voltage
–0.6
V
V
V
V
IL
(2)
0.7V
V
+ 0.5
CC
Input High Voltage
V
CC
IH
V
V
I
= 2.1mA
Output Low Voltage
0.4
OL
OL
I
= –400µA
Output High Voltage TTL
2.4
.
OH
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
CC
PP
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
Two Line Output Control
System Considerations
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current I
CC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E.
The magnitude of the transient current peaks is
dependent on the capacitive and inductive loading
of the device outputs. The associated transient
voltage peaks can be suppressed by complying
with the two line output control and by properly se-
lected decoupling capacitors. It is recommended
that a 0.1µF ceramic capacitor is used on every
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
ry device selecting function, while GV should be
PP
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
device between V
and V . This should be a
CC
SS
high frequency type of low inherent inductance
and should be placed as close as possible to the
device. In addition, a 4.7µF electrolytic capacitor
should be used between V
and V for every
CC
SS
eight devices. This capacitor should be mounted
near the power supply connection point. The pur-
pose of this capacitor is to overcome the voltage
drop caused by the inductive effects of PCB trac-
es.
5/15
M27V320
(1)
Table 8. Read Mode AC Characteristics
(T = 0 to 70°C or –40 to 85°C; V = 3.3V ± 10%)
A
CC
M27V320
-120
Test
Condition
Unit
(3)
Symbol
Alt
Parameter
-150
-100
Min Max Min Max Min Max
E = V ,
IL
t
t
ACC
Address Valid to Output Valid
BYTE High to Output Valid
100
100
120
120
150
150
ns
ns
AVQV
GV = V
PP
IL
E = V ,
IL
t
t
ST
BHQV
GV = V
PP
IL
t
t
GV = V
Chip Enable Low to Output Valid
Output Enable Low to Output Valid
100
45
120
50
150
60
ns
ns
ELQV
CE
PP
IL
t
t
E = V
GLQV
OE
IL
E = V ,
IL
(2)
t
BYTE Low to Output Hi-Z
45
45
45
50
50
50
50
50
50
ns
ns
ns
t
STD
BLQZ
GV = V
PP
IL
(2)
t
GV = V
Chip Enable High to Output Hi-Z
0
0
0
0
0
0
t
DF
PP
IL
EHQZ
Output Enable High to Output
Hi-Z
(2)
t
E = V
t
DF
IL
GHQZ
E = V ,
Address Transition to Output
Transition
IL
t
t
5
5
5
5
5
ns
ns
AXQX
OH
GV = V
PP
IL
E = V ,
IL
t
t
BYTE Low to Output Transition
5
BLQX
OH
GV = V
PP
IL
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
CC
PP
PP.
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed AC measurement conditions.
Figure 6. Word-Wide Read Mode AC Waveforms
VALID
VALID
A0-A20
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
GV
PP
tELQV
Hi-Z
Q0-Q15
AI02207
Note: BYTE = V
.
IH
6/15
M27V320
Figure 7. Byte-Wide Read Mode AC Waveforms
VALID
VALID
A0-A20
tAVQV
tAXQX
E
tEHQZ
tGHQZ
tGLQV
GV
PP
tELQV
Hi-Z
Q0-Q7
AI02218
Note: BYTE = V .
IL
Figure 8. BYTE Transition AC Waveforms
A0-A20
VALID
A–1
VALID
tAVQV
tAXQX
BYTE
tBHQV
Q0-Q7
tBLQX
Q8-Q15
tBLQZ
DATA OUT
Hi-Z
DATA OUT
AI02219
Note: E = V ; GV = V .
IL
PP
IL
7/15
M27V320
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
V
IL
≤ V ≤ V
Input Leakage Current
Supply Current
LI
IN
IH
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
IL
–0.3
2.4
0.8
V
V
+ 0.5
V
IH
CC
V
OL
I
OL
= 2.1mA
0.4
V
V
OH
I
= –2.5mA
3.5
V
OH
V
11.5
12.5
V
ID
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 10. MARGIN MODE AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
t
t
t
V
High to V High
A9 PP
µs
µs
µs
µs
µs
µs
µs
A9HVPH
AS9
t
V
V
High to Chip Enable Low
PP
2
VPHEL
VPS
AS10
AS10
t
t
t
t
High to Chip Enable High (Set)
Low to Chip Enable High (Reset)
1
A10HEH
A10
t
t
V
A10
1
A10LEH
Chip Enable Transition to V
Transition
1
EXA10X
AH10
A10
t
t
Chip Enable Transition to V Transition
PP
2
EXVPX
VPH
t
t
V
Transition to V Transition
PP A9
2
VPXA9X
AH9
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
Programming
is in the programming mode when V input is at
PP
12.5V, GV is at V and E is pulsed to V . The
PP
IH
IL
When delivered, all bits of the M27V320 are in the
'1' state. Data is introduced by selectively pro-
gramming '0's into the desired bit locations. Al-
though only '0's will be programmed, both '1's and
'0's can be present in the data word. The M27V320
data to be programmed is applied to 16 bits in par-
allel to the data output pins. The levels required for
the address and data inputs are TTL. V is spec-
CC
ified to be 6.25V ± 0.25V.
8/15
M27V320
(1)
Table 11. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
1
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
t
t
t
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
AVEL
AS
t
1
QVEL
DS
t
t
t
V
V
V
High to Chip Enable Low
High to Chip Enable Low
Rise Time
2
VCHEL
VCS
CC
PP
PP
t
1
VPHEL
OES
t
t
PRT
50
45
2
VPLVPH
t
t
PW
Chip Enable Program Pulse Width (Initial)
Chip Enable High to Input Transition
55
ELEH
t
t
DH
EHQX
t
t
Chip Enable High to V Transition
2
EHVPX
OEH
PP
t
t
VR
V
PP
Low to Chip Enable Low
1
VPLEL
t
t
Chip Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Chip Enable High to Address Transition
1
ELQV
DV
(2)
t
0
0
130
ns
ns
t
DFP
EHQZ
t
t
AH
EHAX
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Figure 9. MARGIN MODE AC Waveforms
V
CC
A8
A9
tA9HVPH
tVPXA9X
GV
E
PP
tVPHEL
tEXVPX
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
9/15
M27V320
Figure 10. Programming and Verify Modes AC Waveforms
VALID
A0-A20
Q0-Q15
tAVEL
tQVEL
tEHAX
tEHQZ
DATA IN
DATA OUT
tEHQX
V
CC
tVCHEL
tVPHEL
tEHVPX
tELQV
GV
PP
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI02205
Note: BYTE = V ; GV High level = 12V.
IH
PP
Figure 11. Programming Flowchart
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 100 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 11). During
programing and verify operation a MARGIN
MODE circuit must be activated to guarantee that
each cell is programed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides the necessary margin to
each programmed cell.
V
= 6.25V, V
= 12V
PP
CC
SET MARGIN MODE
n = 0
E = 50µs Pulse
NO
NO
++n
= 25
VERIFY
++ Addr
Program Inhibit
Programming of multiple M27V320s in parallel
with different data is also easily accomplished. Ex-
YES
YES
cept for E, all like inputs including GV of the par-
allel M27V320 may be common. A TTL low level
PP
Last
Addr
NO
FAIL
pulse applied to a M27V320's E input and V at
PP
12V, will program that M27V320. A high level E in-
put inhibits the other M27V320s from being pro-
grammed.
YES
RESET MARGIN MODE
Program Verify
CHECK ALL WORDS
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with
BYTE = V
IH
1st: V
2nd: V
= 5V
= 3V
CC
CC
GV at V . Data should be verified with t af-
PP
IL
ELQV
AI05820
ter the falling edge of E.
10/15
M27V320
Electronic Signature
12.5V on address line A9 of the M27V320, with
V
= V = 5V. Two identifier bytes may then be
PP
CC
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27V320. To activate the ES mode,
the programming equipment must force 11.5V to
sequenced from the device outputs by toggling ad-
dress line A0 from V to V . All other address
IL
IH
lines must be held at V during Electronic Signa-
IL
ture mode.
Byte 0 (A0 = V ) represents the manufacturer
IL
code and byte 1 (A0 = V ) the device identifier
IH
code. For the STMicroelectronics M27V320, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q7 to Q0.
11/15
M27V320
Table 12. Ordering Information Scheme
Example:
M27V320
-100 M
1
Device Type
M27
Supply Voltage
V = 3.3V ± 10%
Device Function
320 = 32 Mbit (4Mb x 8 or 2Mb x 16)
Speed
(1)
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
Package
M = SO44
N = TSOP48: 12 x 20 mm
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 13. Revision History
Date
Version
1.0
Revision Details
December 2001
26-Aug-2002
First Issue
Document status moved to Data Sheet
1.1
12/15
M27V320
Table 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
2.80
0.1102
0.10
2.20
0.35
0.10
0.0039
0.0866
0.0138
0.0039
2.30
0.40
0.15
2.40
0.50
0.20
0.08
28.40
–
0.0906
0.0157
0.0059
0.0945
0.0197
0.0079
0.0030
1.1181
–
C
CP
D
28.20
1.27
28.00
–
1.1102
0.0500
0.5236
0.6299
0.0315
1.1024
–
e
E
13.30
16.00
0.80
13.20
15.75
13.50
16.25
0.5197
0.6201
0.5315
0.6398
EH
L
α
8°
8°
N
44
44
Figure 12. SO44 - 44 lead Plastic Small Outline, 525 mils body width, Package Outline
A2
A
C
b
e
CP
D
N
E
EH
1
A1
α
L
SO-d
Drawing is not to scale.
13/15
M27V320
Table 15. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
1.20
0.15
1.05
0.27
0.21
0.10
20.20
18.50
12.10
-
Typ
Max
0.047
0.006
0.041
0.011
0.008
0.004
0.795
0.728
0.476
-
A
A1
A2
B
0.05
0.95
0.17
0.10
0.002
0.037
0.007
0.004
C
CP
D
19.80
18.30
11.90
-
0.780
0.720
0.469
-
D1
E
e
0.50
0.020
L
0.50
0°
0.70
5°
0.020
0°
0.028
5°
α
N
48
48
Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20 mm, Package Outline
A2
1
N
e
E
B
N/2
D1
D
A
CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
α
L
14/15
M27V320
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is registered trademark of STMicroelectronics
All other names are the property of their respective owners
2002 STMicroelectronics - All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Austalia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta -
Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States
www.st.com
15/15
相关型号：
©2020 ICPDF网 联系我们和版权申明