M27V322-100F1 [STMICROELECTRONICS]
32 Mbit 2Mb x16 Low Voltage UV EPROM and OTP EPROM; 32兆位的2Mb x16的低电压UV EPROM和OTP EPROM
| 型号： | M27V322-100F1 |
| 厂家： | 
ST |
| 描述： | 32 Mbit 2Mb x16 Low Voltage UV EPROM and OTP EPROM |
| 文件： | 总13页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M27V322
32 Mbit (2Mb x16) Low Voltage UV EPROM and OTP EPROM
■ 3.3V ± 10% SUPPLY VOLTAGE in READ
OPERATION
■ READ ACCESS TIME
– 100ns at V = 3.0V to 3.6V
CC
■ PIN COMPATIBLE WITH M27C322
■ WORD-WIDE CONFIGURABLE
■ 32 Mbit MASK ROM REPLACEMENT
■ LOW POWER CONSUMPTION
– Active Current 30mA at 5MHz
– Stand-by Current 60µA
42
42
1
1
FDIP42W (F)
PDIP42 (P)
■ PROGRAMMING VOLTAGE: 12V ± 0.25V
■ PROGRAMMING TIME: 50µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
Figure 1. Logic Diagram
– Device Code: 0034h
DESCRIPTION
The M27V322 is a 32 Mbit EPROM offered in the
UV range (ultra violet erase) and OTP range. It is
ideally suited for microprocessor systems requir-
ing large data or program storage. It is organised
as 2 MWords of 16 bit. The pin-out is compatible
with a 32 Mbit Mask ROM.
V
CC
21
16
The FDIP42W (window ceramic frit-seal package)
has a transparent lid which allows the user to ex-
pose the chip to ultraviolet light to erase the bit pat-
tern. A new pattern can then be written rapidly to
the device by following the programming proce-
dure.
For applications where the content is programmed
only one time and erasure is not required, the
M27V322 is offered in PDIP42 package.
A0-A20
Q0-Q15
E
M27V322
GV
PP
V
SS
AI03050
March 2000
1/13
M27V322
Figure 2A. DIP Connections
Table 1. Signal Names
A0-A20
Q0-Q15
E
Address Inputs
A18
A17
A7
1
2
3
4
5
6
7
8
9
42 A19
41 A8
Data Outputs
40 A9
Chip Enable
A6
39 A10
38 A11
37 A12
36 A13
35 A14
34 A15
33 A16
32 A20
GV
Output Enable / Program Supply
Supply Voltage
Ground
PP
A5
A4
V
CC
A3
A2
V
SS
A1
A0 10
M27V322
E
11
12
13
from E to output (t
output after a delay of t
). Data is available at the
ELQV
V
31
V
SS
from the falling edge
SS
PP
GLQV
of GV , assuming that E has been low and the
GV
30 Q15
29 Q7
28 Q14
27 Q6
26 Q13
25 Q5
24 Q12
23 Q4
PP
addresses have been stable for at least t
-
AVQV
Q0 14
Q8 15
Q1 16
Q9 17
Q2 18
t
.
GLQV
Standby Mode
The M27V322 has a standby mode which reduces
the supply current from 30mA to 30µA. The
M27V322 is placed in the standby mode by apply-
ing a CMOS high signal to the E input.When in the
standby mode, the outputs are in a high imped-
Q10 19
Q3 20
ance state, independent of the GV input.
PP
Q11 21
22
V
CC
Two Line Output Control
AI03051
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
DEVICE OPERATION
The operating modes of the M27V322 are listed in
the Operating Modes Table. A single power supply
is required in the read mode. All inputs are TTL
compatible except for V and 12V on A9 for the
Electronic Signature.
PP
For the most efficient use of these two control
lines, E should be decoded and used as the prima-
Read Mode
ry device selecting function, while GV should be
PP
The M27V322 has a word-wide organization. Chip
Enable (E) is the power control and should be
used for device selection. Output Enable (G) is the
output control and should be used to gate data to
the output pins independent of device selection.
Assuming that the addresses are stable, the ad-
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
mode and that the output pins are only active
when data is required from a particular memory
device.
dress access time (t
) is equal to the delay
AVQV
2/13
M27V322
(1)
Table 2. Absolute Maximum Ratings
Symbol
Parameter
Value
Unit
°C
°C
°C
V
(3)
T
A
–40 to 125
–50 to 125
–65 to 150
–2 to 7
Ambient Operating Temperature
T
Temperature Under Bias
BIAS
T
STG
Storage Temperature
(2)
Input or Output Voltage (except A9)
V
IO
V
Supply Voltage
–2 to 7
–2 to 13.5
–2 to 14
V
V
V
CC
(2)
A9 Voltage
V
A9
V
Program Supply Voltage
PP
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is V
3. Depends on range.
+0.5V with possible overshoot to V
+2V for a period less than 20ns.
CC
CC
Table 3. Operating Modes
Mode
GV
E
A9
X
Q15-Q0
Data Out
Hi-Z
PP
V
IL
V
IL
Read
V
IL
V
IH
Output Disable
Program
X
V
IL
Pulse
V
X
Data In
Hi-Z
PP
PP
V
V
Program Inhibit
Standby
X
IH
IH
V
X
X
Hi-Z
V
IL
V
IL
V
ID
Electronic Signature
Codes
Note: X = V or V , V = 12V ± 0.5V.
IH IL ID
Table 4. Electronic Signature
Identifier
Manufacturer’s Code
Device Code
A0
Q7
0
Q6
0
Q5
1
Q4
Q3
0
Q2
0
Q1
0
Q0
0
Hex Data
V
IL
0
1
20h
34h
V
0
0
1
0
1
0
0
IH
Note: Outputs Q15-Q8 are set to '0'.
3/13
M27V322
Table 5. AC Measurement Conditions
High Speed
≤ 10ns
Standard
≤ 20ns
Input Rise and Fall Times
Input Pulse Voltages
0 to 3V
1.5V
0.4V to 2.4V
0.8V and 2V
Input and Output Timing Ref. Voltages
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
High Speed
1N914
3V
1.5V
3.3kΩ
0V
DEVICE
UNDER
TEST
OUT
Standard
C
L
2.4V
2.0V
0.8V
0.4V
C
C
C
= 30pF for High Speed
= 100pF for Standard
includes JIG capacitance
L
L
L
AI01822
AI01823B
(1)
Table 6. Capacitance
Symbol
(T = 25 °C, f = 1 MHz)
A
Parameter
Input Capacitance
Output Capacitance
Test Condition
Min
Max
10
Unit
pF
C
V
= 0V
= 0V
IN
IN
C
OUT
V
OUT
12
pF
Note: 1. Sampled only, not 100% tested.
System Considerations
put control and by properly selected decoupling
capacitors. It is recommended that a 0.1µF ceram-
The power switching characteristics of Advanced
CMOS EPROMs require careful decoupling of the
supplies to the devices. The supply current ICC
has three segments of importance to the system
designer: the standby current, the active current
and the transient peaks that are produced by the
falling and rising edges of E. The magnitude of the
transient current peaks is dependent on the ca-
pacitive and inductive loading of the device out-
puts. The associated transient voltage peaks can
be suppressed by complying with the two line out-
ic capacitor is used on every device between V
CC
and V . This should be a high frequency type of
SS
low inherent inductance and should be placed as
close as possible to the device. In addition, a
4.7µF electrolytic capacitor should be used be-
tween V
and V for every eight devices. This
CC
SS
capacitor should be mounted near the power sup-
ply connection point. The purpose of this capacitor
is to overcome the voltage drop caused by the in-
ductive effects of PCB traces.
4/13
M27V322
(1)
Table 7. Read Mode DC Characteristics
(T = –40 to 85 °C or 0 to 70 °C; V = 3.3V ± 10%; V = V
)
A
CC
PP
CC
Symbol
Parameter
Input Leakage Current
Output Leakage Current
Test Condition
Min
Max
±1
Unit
µA
I
0V ≤ V ≤ V
LI
IN
CC
I
0V ≤ V ≤ V
OUT CC
±10
µA
LO
E = V , GV = V , I = 0mA,
IL OUT
IL
PP
I
Supply Current
30
mA
CC
f = 5MHz
I
I
1
2
E = V
Supply Current (Standby) TTL
Supply Current (Standby) CMOS
Program Current
1
mA
µA
µA
V
CC
IH
E > V – 0.2V
60
10
CC
CC
I
V
= V
PP CC
PP
V
0.2V
CC
Input Low Voltage
–0.6
IL
(2)
0.7V
V
CC
+ 0.5
Input High Voltage
V
V
V
V
CC
IH
V
V
I
= 2.1mA
Output Low Voltage
0.4
OL
OL
I
= –400µA
OH
Output High Voltage TTL
2.4
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Maximum DC voltage on Output is V +0.5V.
CC
(1)
Table 8. Read Mode AC Characteristics
(T = –40 to 85 °C or 0 to 70 °C; V = 3.3V ± 10%; V = V
)
A
CC
PP
CC
M27V322
-120
(3)
Symbol
Alt
Parameter
Test Condition
-150
Unit
-100
Min Max Min Max Min Max
t
t
E = V , G = V
Address Valid to Output Valid
100
100
120
120
150
150
ns
ns
AVQV
ACC
IL
IL
t
t
G = V
IL
Chip Enable Low to Output Valid
ELQV
CE
Output Enable Low to Output
Valid
t
t
E = V
IL
50
45
45
60
50
50
60
50
50
ns
ns
ns
GLQV
OE
(2)
t
G = V
Chip Enable High to Output Hi-Z
0
0
0
0
0
0
t
DF
DF
IL
EHQZ
GHQZ
Output Enable High to Output
Hi-Z
(2)
t
E = V
t
IL
Address Transition to Output
Transition
t
t
E = V , G = V
IL IL
5
5
5
ns
AXQX
OH
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V
PP
CC
PP
2. Sampled only, not 100% tested.
3. Speed obtained with High Speed measurement conditions.
5/13
M27V322
Figure 5. Read Mode AC Waveforms
VALID
tGLQV
VALID
A0-A20
tAVQV
tAXQX
E
tEHQZ
tGHQZ
GV
PP
tELQV
Hi-Z
Q0-Q15
AI02207
(1)
Table 9. Programming Mode DC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12V ± 0.25V)
A
CC
PP
Symbol
Parameter
Test Condition
Min
Max
±10
50
Unit
µA
mA
mA
V
I
V
≤ V ≤ V
Input Leakage Current
Supply Current
LI
IL
IN
IH
I
CC
I
PP
E = V
Program Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage TTL
A9 Voltage
50
IL
V
–0.3
2.4
0.8
IL
V
IH
V
+ 0.5
CC
V
V
OL
I
= 2.1mA
OL
0.4
V
V
OH
I
= –2.5mA
3.5
V
OH
V
ID
11.5
12.5
V
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
6/13
M27V322
(1)
Table 10. MARGIN MODE AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
2
Max
Unit
µs
t
t
V
High to V High
A9 PP
A9HVPH
AS9
t
t
V
High to Chip Enable Low
PP
2
µs
VPHEL
VPS
AS10
AS10
AH10
t
t
t
t
V
A10
High to Chip Enable High (Set)
Low to Chip Enable High (Reset)
1
µs
A10HEH
t
V
A10
1
µs
A10LEH
t
Chip Enable Transition to V
Transition
1
µs
EXA10X
A10
t
t
Chip Enable Transition to V Transition
PP
2
µs
EXVPX
VPH
t
t
V Transition to V Transition
PP A9
2
µs
VPXA9X
AH9
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
(1)
Table 11. Programming Mode AC Characteristics
(T = 25 °C; V = 6.25V ± 0.25V; V = 12V ± 0.25V)
A
CC
PP
Symbol
Alt
Parameter
Test Condition
Min
1
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
µs
t
t
t
Address Valid to Chip Enable Low
Input Valid to Chip Enable Low
AVEL
AS
t
1
QVEL
DS
t
t
V
V
V
High to Chip Enable Low
High to Chip Enable Low
Rise Time
2
VCHEL
VCS
CC
PP
PP
t
t
1
VPHEL
OES
t
t
PRT
50
45
2
VPLVPH
t
t
PW
Chip Enable Program Pulse Width (Initial)
Chip Enable High to Input Transition
55
ELEH
t
t
DH
EHQX
t
t
Chip Enable High to V Transition
2
EHVPX
OEH
PP
t
t
VR
V
Low to Chip Enable Low
PP
1
VPLEL
t
t
DV
Chip Enable Low to Output Valid
Chip Enable High to Output Hi-Z
Chip Enable High to Address Transition
1
ELQV
(2)
t
0
0
130
ns
ns
t
DFP
EHQZ
t
t
AH
EHAX
Note: 1. V must be applied simultaneously with or before V and removed simultaneously or after V .
PP
CC
PP
2. Sampled only, not 100% tested.
Programming
olet light (UV EPROM). The M27V322 is in the
programming mode when V input is at 12.V,
PP
When delivered (and after each erasure for UV
EPROM), all bits of the M27V322 are in the "1"
state. Data is introduced by selectively program-
ming "0"s into the desired bit locations. Although
only "0"s will be programmed, both "1"s and "0"s
can be present in the data word. The only way to
change a "0" to a "1" is by die exposition to ultravi-
GV is at V and E is pulsed to V . The data to
PP
IH
IL
be programmed is applied to 16 bits in parallel to
the data output pins. The levels required for the
address and data inputs are TTL. V is specified
CC
to be 6.25V ± 0.25V.
7/13
M27V322
Figure 6. MARGIN MODE AC Waveforms
V
CC
A8
A9
tA9HVPH
tVPXA9X
GV
E
PP
tVPHEL
tEXVPX
tA10HEH
tEXA10X
A10 Set
A10 Reset
tA10LEH
AI00736B
Note: A8 High level = 5V; A9 High level = 12V.
Figure 7. Programming and Verify Modes AC Waveforms
VALID
A0-A20
Q0-Q15
tAVEL
tQVEL
tEHAX
DATA IN
DATA OUT
tEHQX
tEHQZ
V
CC
tVCHEL
tVPHEL
tEHVPX
tELQV
GV
PP
tVPLEL
E
tELEH
PROGRAM
VERIFY
AI02205
Note: BYTE = V
8/13
.
IH
M27V322
Figure 8. Programming Flowchart
GV at V . Data should be verified with t
ter the falling edge of E.
On-Board Programming
af-
PP
IL
ELQV
V
= 6.25V, V
= 12V
PP
CC
The M27V322 can be directly programmed in the
application circuit. See the relevant Application
Note AN620.
SET MARGIN MODE
n = 0
Electronic Signature
The Electronic Signature (ES) mode allows the
reading out of a binary code from an EPROM that
will identify its manufacturer and type. This mode
is intended for use by programming equipment to
automatically match the device to be programmed
with its corresponding programming algorithm.
The ES mode is functional in the 25°C ± 5°C am-
bient temperature range that is required when pro-
gramming the M27V322. To activate the ES mode,
the programming equipment must force 11.5V to
12.5V on address line A9 of the M27V322, with
E = 50µs Pulse
NO
NO
++n
= 25
VERIFY
++ Addr
YES
YES
Last
NO
FAIL
Addr
V
= V = 5V. Two identifier bytes may then be
PP
CC
YES
sequenced from the device outputs by toggling ad-
dress line A0 from V to V . All other address
IL
IH
RESET MARGIN MODE
lines must be held at V during Electronic Signa-
IL
ture mode.
CHECK ALL WORDS
Byte 0 (A0 = V ) represents the manufacturer
IL
1st: V
= 5V
= 3V
CC
2nd: V
code and byte 1 (A0 = V ) the device identifier
IH
CC
code. For the STMicroelectronics M27V322, these
two identifier bytes are given in Table 4 and can be
read-out on outputs Q0 to Q7.
AI03059B
ERASURE OPERATION (applies to UV EPROM)
The erasure characteristics of the M27V322 is
such that erasure begins when the cells are ex-
posed to light with wavelengths shorter than ap-
proximately 4000 Å. It should be noted that
sunlight and some type of fluorescent lamps have
wavelengths in the 3000-4000 Å range. Research
shows that constant exposure to room level fluo-
rescent lighting could erase a typical M27V322 in
about 3 years, while it would take approximately 1
week to cause erasure when exposed to direct
sunlight. If the M27V322 is to be exposed to these
types of lighting conditions for extended periods of
time, it is suggested that opaque labels be put over
the M27V322 window to prevent unintentional era-
sure. The recommended erasure procedure for
M27V322 is exposure to short wave ultraviolet
light which has a wavelength of 2537 Å. The inte-
grated dose (i.e. UV intensity x exposure time) for
PRESTO III Programming Algorithm
The PRESTO III Programming Algorithm allows
the whole array to be programed with a guaran-
teed margin in a typical time of 100 seconds. Pro-
gramming with PRESTO III consists of applying a
sequence of 50µs program pulses to each word
until a correct verify occurs (see Figure 8). During
programing and verify operation a MARGIN
MODE circuit must be activated to guarantee that
each cell is programed with enough margin. No
overprogram pulse is applied since the verify in
MARGIN MODE provides the necessary margin to
each programmed cell.
Program Inhibit
Programming of multiple M27V322s in parallel
with different data is also easily accomplished. Ex-
cept for E, all like inputs including GV of the par-
PP
2
erasure should be a minimum of 30 W-sec/cm .
allel M27V322 may be common. A TTL low level
pulse applied to a M27V322's E input and V at
12V, will program that M27V322. A high level E in-
put inhibits the other M27V322s from being pro-
grammed.
The erasure time with this dosage is approximate-
ly 30 to 40 minutes using an ultraviolet lamp with
PP
2
12000 µW/cm power rating. The M27V322
should be placed within 2.5cm (1 inch) of the lamp
tubes during the erasure. Some lamps have a filter
on their tubes which should be removed before
erasure.
Program Verify
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
ly programmed. The verify is accomplished with
9/13
M27V322
Table 12. Ordering Information Scheme
Example:
M27V322
-100 X
F
1
Device Type
M27
Supply Voltage
V = 3.3V ±10%
Device Function
322 = 32 Mbit (2Mb x16)
Speed
(1)
-100 = 100 ns
-120 = 120 ns
-150 = 150 ns
V
Tolerance
CC
blank = 3.3V ±10%
X = 3.3V ±5%
Package
F = FDIP42W
P = PDIP42
Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C
Note: 1. High Speed, see AC Characteristics section for further information.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.
Table 13. Revision History
Date
July 1999
Revision Details
First Issue
Programming Flowchart changed (Figure 8)
02/09/00
PRESTO III Programming Algorithm paragraph changed
FDIP42W Package Dimension, L Max added (Table 14)
10/13
M27V322
Table 14. FDIP42W - 42 pin Ceramic Frit-seal DIP with window, Package Mechanical Data
mm
Min
inches
Min
Symb
Typ
Max
5.72
1.40
4.57
4.50
0.56
–
Typ
Max
0.225
0.055
0.180
0.177
0.022
–
A
A1
A2
A3
B
0.51
3.91
3.89
0.41
–
0.020
0.154
0.153
0.016
–
B1
C
1.45
0.057
0.23
54.41
–
0.30
54.86
–
0.009
2.142
–
0.012
2.160
–
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e
14.50
–
14.90
–
0.571
–
0.587
–
2.54
0.100
0.590
eA
eB
L
14.99
–
–
–
–
16.18
3.18
1.52
–
18.03
4.10
2.49
–
0.637
0.125
0.060
–
0.710
0.161
0.098
–
S
K
8.00
0.315
0.630
K1
α
16.00
–
–
–
–
4°
11°
4°
11°
N
42
42
Figure 9. FDIP42W - 42 pin Ceramic Frit-seal DIP with window, Package Outline
A2
A3
A
L
A1
e1
α
B1
B
C
eA
eB
D2
D
S
N
1
K
E1
E
K1
FDIPW-b
Note: Drawing is not to scale.
11/13
M27V322
Table 15. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Mechanical Data
Symb
mm
Min
–
inches
Min
–
Typ
Max
5.08
–
Typ
Max
0.200
–
A
A1
A2
B
0.25
3.56
0.38
1.27
0.20
52.20
–
0.010
0.140
0.015
0.050
0.008
2.055
–
4.06
0.53
1.65
0.36
52.71
–
0.160
0.021
0.065
0.014
2.075
–
B1
C
D
D2
E
50.80
15.24
2.000
0.600
–
–
–
–
E1
e1
eA
eB
L
13.59
–
13.84
–
0.535
–
0.545
–
2.54
0.100
0.590
14.99
–
–
–
–
15.24
3.18
0.86
0°
17.78
3.43
1.37
10°
0.600
0.125
0.034
0°
0.700
0.135
0.054
10°
S
α
N
42
42
Figure 10. PDIP42 - 42 pin Plastic DIP, 600 mils width, Package Outline
A2
A
L
A1
e1
α
C
B1
B
eA
eB
D2
D
S
N
1
E1
E
PDIP
Note: Drawing is not to scale.
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M27V322
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