M25PE10-VMN6TP [STMICROELECTRONICS]
1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out; 1和2兆位，低电压，页面可擦除串行闪存产品与字节变性， 33兆赫的SPI总线，标准引脚输出
| 型号： | M25PE10-VMN6TP |
| 厂家： | 
ST |
| 描述： | 1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out |
| 文件： | 总37页 (文件大小：483K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25PE20
M25PE10
1 and 2 Mbit, Low Voltage, Page-Erasable Serial Flash Memories
with Byte-Alterability, 33 MHz SPI Bus, Standard Pin-out
FEATURES SUMMARY
■
■
■
■
Industrial Standard SPI Pin-out
1 or 2 Mbit of Page-Erasable Flash Memory
Page Write (up to 256 Bytes) in 11ms (typical)
Page Program (up to 256 Bytes) in 1.2ms
(typical)
Figure 1. Packages
■
■
■
■
■
■
■
Page Erase (256 Bytes) in 10ms (typical)
Sector Erase (512 Kbit)
2.7 to 3.6V Single Supply Voltage
SPI Bus Compatible Serial Interface
33MHz Clock Rate (maximum)
Deep Power-down Mode 1µA (typical)
Electronic Signature
VDFPN8 (MP)
6x5mm (MLP8)
–
JEDEC Standard Two-Byte Signature
(8012h for M25PE20
8011h for M25PE10)
More than 100,000 Write Cycles
More than 20 Year Data Retention
8
■
■
■
Hardware Write Protection of the Top Sector
(64KB)
1
■
Packages
SO8N (MN)
–
ECOPACK® (RoHS compliant)
150 mil width
October 2005
1/37
M25PE10, M25PE20
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sharing the Overhead of Modifying Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
An Easy Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
A Fast Way to Modify Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page Write (PW). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Page Erase (PE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Release from Deep Power-down (RDP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/37
M25PE10, M25PE20
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3/37
M25PE10, M25PE20
Table 1. Signal Names
SUMMARY DESCRIPTION
The M25PE20 and M25PE10 are 2 Mbit (256K x 8
bit) and 1 Mbit (128K x8 bit) Serial Paged Flash
Memories, respectively. They are accessed by a
high speed SPI-compatible bus.
The memories can be written or programmed 1 to
256 Bytes at a time, using the Page Write or Page
Program instruction. The Page Write instruction
consists of an integrated Page Erase cycle fol-
lowed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors,
each containing 256 pages. Each page is 256
Bytes wide. Thus, the whole memory can be
viewed as consisting of 1024 pages, or 262,144
Bytes.
C
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
D
Q
S
TSL
Reset
Top Sector Lock
Reset
V
Supply Voltage
Ground
CC
V
SS
The M25PE10 memory is organized as 2 sectors,
each containing 256 pages. Each page is 256
Bytes wide. Thus, the whole memory can be
viewed as consisting of 512 pages, or 131, 072
Bytes.
Figure 3. VDFPN AND SO Connections
The memories can be erased a page at a time, us-
ing the Page Erase instruction, or a sector at a
time, using the Sector Erase instruction.
The top sector of the memories can be Write Pro-
tected by Hardware (TSL).
In order to meet environmental requirements, ST
offers these devices in ECOPACK® packages.
ECOPACK® packages are Lead-free and RoHS
compliant.
M25PE20
M25PE10
S
Q
1
2
3
4
8
7
6
5
V
CC
Reset
TSL
C
D
V
SS
AI09715
ECOPACK is an ST trademark. ECOPACK speci-
fications are available at: www.st.com.
Figure 2. Logic Diagram
V
Note: 1. There is an exposed die paddle on the underside of the
CC
MLP8 package. This is pulled, internally, to V , and
SS
must not be allowed to be connected to any other voltage
or signal line on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
D
C
S
Q
M25PE20
M25PE10
TSL
Reset
V
SS
AI09713
4/37
M25PE10, M25PE20
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Select (S) Low selects the device, placing it in the
Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Serial Data Input (D). This input signal is used to
transfer data serially into the device. It receives in-
structions, addresses, and the data to be pro-
grammed. Values are latched on the rising edge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Read,
Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is
not the Deep Power-down mode). Driving Chip
Reset (Reset). The Reset (Reset) input provides
a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is
in the normal operating mode. When Reset (Re-
set) is driven Low, the memory will enter the Reset
mode. In this mode, the output is high impedance.
Driving Reset (Reset) Low while an internal oper-
ation is in progress will affect this operation (write,
program or erase cycle) and data may be lost.
Top Sector Lock (TSL). This input signal puts
the device in the Hardware Protected mode, when
Top Sector Lock (TSL) is connected to V , caus-
SS
ing the top 256 pages (upper addresses) of the
memory to become read-only (protected from
write, program and erase operations).
When Top Sector Lock (TSL) is connected to V
,
CC
the top 256 pages of memory behave like the other
pages of memory.
5/37
M25PE10, M25PE20
SPI MODES
These devices can be driven by a microcontroller
with its SPI peripheral running in either of the two
following modes:
is available from the falling edge of Serial Clock
(C).
The difference between the two modes, as shown
in Figure 5., is the clock polarity when the bus
master is in Standby mode and not transferring da-
ta:
–
–
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
–
–
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Devices on the SPI Bus
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
C
Q
D
C
Q
D
C Q D
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
CS3 CS2 CS1
S
S
S
TSL RP
TSL RP
TSL
RP
AI10741B
Note: The Top Sector Lock (TSL) signal should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
CPOL CPHA
C
C
0
1
0
1
D
MSB
Q
MSB
AI01438B
6/37
M25PE10, M25PE20
OPERATING FEATURES
Sharing the Overhead of Modifying Data
To write or program one (or more) data Bytes, two
instructions are required: Write Enable (WREN),
which is one Byte, and a Page Write (PW) or Page
Program (PP) sequence, which consists of four
Bytes plus data. This is followed by the internal cy-
–
–
when the designer knows that the page has
already been erased by an earlier Page Erase
(PE) or Sector Erase (SE) instruction. This is
useful, for example, when storing a fast
stream of data, having first performed the
erase cycle when time was available
cle (of duration t
or t ).
when the designer knows that the only
PW
PP
changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has
the additional advantage of minimising the
number of unnecessary erase operations, and
the extra stress incurred by each page.
To share this overhead, the Page Write (PW) or
Page Program (PP) instruction allows up to 256
Bytes to be programmed (changing bits from 1 to
0) or written (changing bits to 0 or 1) at a time, pro-
vided that they lie in consecutive addresses on the
same page of memory.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Page Program (PP) and AC Characteristics
(33MHz operation)).
An Easy Way to Modify Data
The Page Write (PW) instruction provides a con-
venient way of modifying data (up to 256 contigu-
ous Bytes at a time), and simply requires the start
address, and the new data in the instruction se-
quence.
Polling During a Write, Program or Erase Cycle
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, and then transmitting
the instruction Byte, three address Bytes (A23-A0)
and at least one data Byte, and then driving Chip
Select (S) High. While Chip Select (S) is being
held Low, the data Bytes are written to the data
buffer, starting at the address given in the third ad-
dress Byte (A7-A0). When Chip Select (S) is driv-
en High, the Write cycle starts. The remaining,
unchanged, Bytes of the data buffer are automati-
cally loaded with the values of the corresponding
Bytes of the addressed memory page. The ad-
dressed memory page then automatically put into
an Erase cycle. Finally, the addressed memory
page is programmed with the contents of the data
buffer.
A further improvement in the write, program or
erase time can be achieved by not waiting for the
worst case delay (t , t , t , or t ). The Write
PW PP PE
SE
In Progress (WIP) bit is provided in the Status
Register so that the application program can mon-
itor its value, polling it to establish when the previ-
ous cycle is complete.
Reset
An internal Power-On Reset circuit helps protect
against inadvertent data writes. Addition protec-
tion is provided by driving Reset (Reset) Low dur-
ing the Power-on process, and only driving it High
when V
has reached the correct voltage level,
CC
V
(min).
CC
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode.
All of this buffer management is handled internally,
and is transparent to the user. The user is given
the facility of being able to alter the contents of the
memory on a Byte-by-Byte basis.
When Chip Select (S) is High, the device is dese-
lected, but could remain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write). The device then goes in to the
Standby Power mode. The device consumption
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all con-
secutive targeted Bytes in a single sequence ver-
sus using several Page Write (PW) sequences
with each containing only a few Bytes (see Page
Write (PW) and AC Characteristics (33MHz oper-
ation)).
drops to I
.
CC1
The Deep Power-down mode is entered when the
specific instruction (the Deep Power-down (DP) in-
struction) is executed. The device consumption
A Fast Way to Modify Data
The Page Program (PP) instruction provides a fast
way of modifying data (up to 256 contiguous Bytes
at a time), provided that it only involves resetting
bits to 0 that had previously been set to 1.
drops further to I
. The device remains in this
CC2
mode until the Release from Deep Power-down in-
struction is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in active use, to protect the
This might be:
–
when the designer is programming the device
for the first time
7/37
M25PE10, M25PE20
device from inadvertent Write, Program or Erase
instructions.
pulses that is a multiple of eight, before they
are accepted for execution.
Status Register
■
All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
The Status Register contains two status bits that
can be read by the Read Status Register (RDSR)
instruction.
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle.
–
–
–
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction comple-
tion
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
–
–
–
–
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Table 2. Status Register Format
b7
0
b0
0
0
0
0
0
WEL WIP
■
The Hardware Protected mode is entered
when Top Sector Lock (TSL) is driven Low,
causing the top 256 pages of memory to
become read-only. When Top Sector Lock
(TSL) is driven High, the top 256 pages of
memory behave like the other pages of
memory
The Reset (Reset) signal can be driven Low to
protect the contents of the memory during any
critical time, not just during Power-up and
Power-down.
In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software protection from inadvertent
Write, Program and Erase instructions while
the device is not in active use.
Note: WEL and WIP are volatile read-only bits (WEL is set and re-
set by specific instructions; WIP is automatically set and re-
set by the internal logic of the device).
Protection Modes
The environments where non-volatile memory de-
vices are used can be very noisy. No SPI device
can operate correctly in the presence of excessive
noise. To help combat this, the M25PE10 and
M25PE20 feature the following data protection
mechanisms:
■
■
■
Power On Reset and an internal timer (t
)
PUW
can provide protection against inadvertent
changes while the power supply is outside the
operating specification.
■
Program, Erase and Write instructions are
checked that they consist of a number of clock
8/37
M25PE10, M25PE20
MEMORY ORGANIZATION
The M25PE20 memory is organized as:
Table 3. M25PE20 Memory Organization
■
■
■
1024 pages (256 Bytes each).
262,144 Bytes (8 bits each)
4 sectors (512 Kbits, 65536 Bytes each)
Sector
Address Range
30000h
3
2
1
0
3FFFFh
2FFFFh
1FFFFh
0FFFFh
20000h
10000h
00000h
The M25PE10 memory is organized as:
■
■
■
512 pages (256 Bytes each).
131,074 Bytes (8 bits each)
2 sectors (512 Kbits, 65536 Bytes each)
Table 4. M25PE10 Memory Organization
In the M25PE20 and M25PE10, each page can be
individually:
Sector
Address Range
–
programmed (bits are programmed from 1 to
0)
erased (bits are erased from 0 to 1)
1
0
10000h
00000h
1FFFFh
0FFFFh
–
–
written (bits are changed to either 0 or 1)
The device is Page or Sector Erasable (bits are
erased from 0 to 1).
9/37
M25PE10, M25PE20
Figure 6. M25PE20 Block Diagram
Reset
High Voltage
Generator
TSL
S
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
3FF00h
2FFFFh
3FFFFh
Top 256 Pages can
be made read-only
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI07402
10/37
M25PE10, M25PE20
Figure 7. M25PE10 Block Diagram
Reset
High Voltage
Generator
TSL
S
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
1FF00h
1FFFFh
Top 256 Pages can
be made read-only
FFFFh
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI10814
11/37
M25PE10, M25PE20
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significant bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-Byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
quence. Chip Select (S) can be driven High after
any bit of the data-out sequence is being shifted
out.
In the case of a Page Write (PW), Page Program
(PP), Page Erase (PE), Sector Erase (SE), Write
Enable (WREN), Write Disable (WRDI), Deep
Power-down (DP) or Release from Deep Power-
down (RDP) instruction, Chip Select (S) must be
driven High exactly at a Byte boundary, otherwise
the instruction is rejected, and is not executed.
That is, Chip Select (S) must driven High when the
number of clock pulses after Chip Select (S) being
driven Low is an exact multiple of eight.
All attempts to access the memory array during a
Write cycle, Program cycle or Erase cycle are ig-
nored, and the internal Write cycle, Program cycle
or Erase cycle continues unaffected.
The instruction set is listed in Table 5.
Every instruction sequence starts with a one-Byte
instruction code. Depending on the instruction,
this might be followed by address Bytes, or by data
Bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read) or Read
Status Register (RDSR) instruction, the shifted-in
instruction sequence is followed by a data-out se-
Table 5. Instruction Set
Address Dummy
Data
Bytes
Instruction
Description
Write Enable
One-Byte Instruction Code
Bytes
Bytes
WREN
WRDI
RDID
0000 0110
0000 0100
1001 1111
0000 0101
0000 0011
0000 1011
0000 1010
0000 0010
1101 1011
1101 1000
1011 1001
1010 1011
06h
04h
9Fh
05h
03h
0Bh
0Ah
02h
DBh
D8h
B9h
ABh
0
0
0
0
3
3
3
3
3
3
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Write Disable
Read Identification
Read Status Register
Read Data Bytes
1 to 3
1 to ∞
1 to ∞
1 to ∞
1 to 256
1 to 256
0
RDSR
READ
FAST_READ Read Data Bytes at Higher Speed
PW
PP
Page Write
Page Program
PE
Page Erase
SE
Sector Erase
0
DP
Deep Power-down
Release from Deep Power-down
0
RDP
0
12/37
M25PE10, M25PE20
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8.)
sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set pri-
or to every Page Write (PW), Page Program (PP),
Page Erase (PE), and Sector Erase (SE) instruc-
tion.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 8. Write Enable (WREN) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
–
–
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Page Erase (PE) instruction completion
Sector Erase (SE) instruction completion
Figure 9. Write Disable (WRDI) Instruction Sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
13/37
M25PE10, M25PE20
Read Identification (RDID)
The device is first selected by driving Chip Select
(S) Low. Then, the 8-bit instruction code for the in-
struction is shifted in. This is followed by the 24-bit
device identification, stored in the memory, being
shifted out on Serial Data Output (Q), each bit be-
ing shifted out during the falling edge of Serial
Clock (C).
The Read Identification (RDID) instruction allows
the 8-bit manufacturer identification to be read, fol-
lowed by two Bytes of device identification. The
manufacturer identification is assigned by JEDEC,
and has the value 20h for STMicroelectronics. The
device identification is assigned by the device
manufacturer, and indicates the memory type in
the first Byte (80h), and the memory capacity of
the device in the second Byte (12h for the
M25PE20 and 11h for the M25PE10).
The instruction sequence is shown in Figure 10..
The Read Identification (RDID) instruction is termi-
nated by driving Chip Select (S) High at any time
during data output.
Any Read Identification (RDID) instruction while
an Erase or Program cycle is in progress, is not
decoded, and has no effect on the cycle that is in
progress.
When Chip Select (S) is driven High, the device is
put in the Standby Power mode. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Table 6. Read Identification (RDID) Data-Out Sequence
Device Identification
Manufacturer Identification
Memory Type
Memory Capacity
12h (M25PE20)
11h (M25PE10)
20h
20h
80h
80h
Figure 10. Read Identification (RDID) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 16 18
28 29 30 31
C
D
Instruction
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809
14/37
M25PE10, M25PE20
Read Status Register (RDSR)
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write, Program
or Erase cycle. When set to 1, such a cycle is in
progress, when reset to 0 no such cycle is in
progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write, Program or Erase instruction
is accepted.
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write cycle is in progress.
When one of these cycles is in progress, it is rec-
ommended to check the Write In Progress (WIP)
bit before sending a new instruction to the device.
It is also possible to read the Status Register con-
tinuously, as shown in Figure 11.
The status bits of the Status Register are as fol-
lows:
Figure 11. Read Status Register (RDSR) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
15/37
M25PE10, M25PE20
Read Data Bytes (READ)
next higher address after each Byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes (READ) instruction.
When the highest address is reached, the address
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time during data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on
the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-Byte
address (A23-A0), each bit being latched-in during
the rising edge of Serial Clock (C). Then the mem-
ory contents, at that address, is shifted out on Se-
rial Data Output (Q), each bit being shifted out, at
a maximum frequency f , during the falling edge of
R
Serial Clock (C).
The instruction sequence is shown in Figure 12.
The first Byte addressed can be at any location.
The address is automatically incremented to the
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI03748D
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
16/37
M25PE10, M25PE20
Read Data Bytes at Higher Speed
(FAST_READ)
next higher address after each Byte of data is shift-
ed out. The whole memory can, therefore, be read
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
The device is first selected by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-Byte address (A23-A0) and a
dummy Byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency f , during the falling edge of
C
Serial Clock (C).
The instruction sequence is shown in Figure 13.
The first Byte addressed can be at any location.
The address is automatically incremented to the
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequence
and Data-Out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
3
2
1
0
D
Q
High Impedance
S
C
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI04006
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
17/37
M25PE10, M25PE20
Page Write (PW)
The Page Write (PW) instruction allows Bytes to
be written in the memory. Before it can be accept-
ed, a Write Enable (WREN) instruction must previ-
ously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Write (PW) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address Bytes and at least
one data Byte on Serial Data Input (D). The rest of
the page remains unchanged if no power failure
occurs during this write cycle.
requested addresses without having any effects
on the other Bytes of the same page.
For optimized timings, it is recommended to use
the Page Write (PW) instruction to write all con-
secutive targeted Bytes in a single sequence ver-
sus using several Page Write (PW) sequences
with each containing only a few Bytes (see AC
Characteristics (33MHz operation)).
Chip Select (S) must be driven High after the
eighth bit of the last data Byte has been latched in,
otherwise the Page Write (PW) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
The Page Write (PW) instruction performs a page
erase cycle even if only one Byte is updated.
timed Page Write cycle (whose duration is t ) is
PW
initiated. While the Page Write cycle is in progress,
the Status Register may be read to check the val-
ue of the Write In Progress (WIP) bit. The Write In
Progress (WIP) bit is 1 during the self-timed Page
Write cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the
Write Enable Latch (WEL) bit is reset.
If the 8 least significant address bits (A7-A0) are
not all zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are written
from the start address of the same page (the one
whose 8 least significant address bits (A7-A0) are
all zero). Chip Select (S) must be driven Low for
the entire duration of the sequence.
A Page Write (PW) instruction applied to a page
that is Hardware Protected is not executed.
The instruction sequence is shown in Figure 14.
Any Page Write (PW) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
If more than 256 Bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data Bytes are guaranteed to be written correctly
within the same page. If less than 256 Data Bytes
are sent to device, they are correctly written at the
Figure 14. Page Write (PW) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte n
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04045
Note: 1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
2. 1 ≤n ≤256
18/37
M25PE10, M25PE20
Page Program (PP)
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see AC Characteristics (33MHz operation)).
Chip Select (S) must be driven High after the
eighth bit of the last data Byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
The Page Program (PP) instruction allows Bytes
to be programmed in the memory (changing bits
from 1 to 0, only). Before it can be accepted, a
Write Enable (WREN) instruction must previously
have been executed. After the Write Enable
(WREN) instruction has been decoded, the device
sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address Bytes and at least
one data Byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data exceeding the ad-
dressed page boundary roll over, and are pro-
grammed from the start address of the same page
(the one whose 8 least significant address bits
(A7-A0) are all zero). Chip Select (S) must be driv-
en Low for the entire duration of the sequence.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is t
)
PP
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL)
bit is reset.
The instruction sequence is shown in Figure 15.
A Page Program (PP) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Program (PP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
If more than 256 Bytes are sent to the device, pre-
viously latched data are discarded and the last 256
data Bytes are guaranteed to be programmed cor-
rectly within the same page. If less than 256 Data
Bytes are sent to device, they are correctly pro-
grammed at the requested addresses without hav-
ing any effects on the other Bytes of the same
page.
Figure 15. Page Program (PP) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte n
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04044
Note: 1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
2. 1 ≤n ≤256
19/37
M25PE10, M25PE20
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all
bits inside the chosen page. Before it can be ac-
cepted, a Write Enable (WREN) instruction must
previously have been executed. After the Write
Enable (WREN) instruction has been decoded,
the device sets the Write Enable Latch (WEL).
The Page Erase (PE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address Bytes on Serial
Data Input (D). Any address inside the Page is a
valid address for the Page Erase (PE) instruction.
Chip Select (S) must be driven Low for the entire
duration of the sequence.
latched in, otherwise the Page Erase (PE) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, the self-timed Page Erase cycle
(whose duration is t ) is initiated. While the Page
PE
Erase cycle is in progress, the Status Register
may be read to check the value of the Write In
Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Page Erase cycle, and
is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page
that is Hardware Protected is not executed.
Any Page Erase (PE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
Figure 16. Page Erase (PE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI04046
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
20/37
M25PE10, M25PE20
Sector Erase (SE)
struction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Sector Erase cy-
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instruction has been decod-
ed, the device sets the Write Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address Bytes on Serial
Data Input (D). Any address inside the Sector (see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
cle (whose duration is t ) is initiated. While the
SE
Sector Erase cycle is in progress, the Status Reg-
ister may be read to check the value of the Write
In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Sector Erase cycle,
and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable
Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector
that contains a page that is Hardware Protected is
not executed.
Any Sector Erase (SE) instruction, while an Erase,
Program or Write cycle is in progress, is rejected
without having any effects on the cycle that is in
progress.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the
eighth bit of the last address Byte has been
latched in, otherwise the Sector Erase (SE) in-
Figure 17. Sector Erase (SE) Instruction Sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751D
Note: Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the M25PE10.
21/37
M25PE10, M25PE20
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only way to put the device in the lowest con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, while the device is not in active use,
since in this mode, the device ignores all Write,
Program and Erase instructions.
The Deep Power-down mode automatically stops
at Power-down, and the device always Powers-up
in Standby Power mode.
The Deep Power-down (DP) instruction is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
Driving Chip Select (S) High deselects the device,
and puts the device in Standby Power mode (if
there is no internal cycle currently in progress). But
this mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
subsequently reducing the standby current (from
The instruction sequence is shown in Figure 18.
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise the Deep Power-down (DP) instruc-
tion is not executed. As soon as Chip Select (S) is
driven High, it requires a delay of t before the
DP
supply current is reduced to I
Power-down mode is entered.
and the Deep
CC2
I
to I
, as specified in Table 12.).
CC1
CC2
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. This releases the device from this mode.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effects on the cycle that
is in progress.
Figure 18. Deep Power-down (DP) Instruction Sequence
S
tDP
0
1
2
3
4
5
6
7
C
D
Instruction
Standby Power Mode
Deep Power-down Mode
AI03753D
22/37
M25PE10, M25PE20
Release from Deep Power-down (RDP)
High. Sending additional clock cycles on Serial
Clock (C), while Chip Select (S) is driven Low,
cause the instruction to be rejected, and not exe-
cuted.
Once the device has entered the Deep Power-
down mode, all instructions are ignored except the
Release from Deep Power-down (RDP) instruc-
tion. Executing this instruction takes the device out
of the Deep Power-down mode.
After Chip Select (S) has been driven High,
followed by a delay, t
, the device is put in
RDP
Standby Power mode. Chip Select (S) must
remain High at least until this period is over. The
device waits to be selected, so that it can receive,
decode and execute instructions.
Any Release from Deep Power-down (RDP) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
The Release from Deep Power-down (RDP) in-
struction is entered by driving Chip Select (S) Low,
followed by the instruction code on Serial Data In-
put (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 19.
The Release from Deep Power-down (RDP) in-
struction is terminated by driving Chip Select (S)
Figure 19. Release from Deep Power-down (RDP) Instruction Sequence
S
tRDP
0
1
2
3
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode
Standby Power Mode
AI06807
23/37
M25PE10, M25PE20
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selected (that is Chip Select (S) must follow
These values are specified in Table 7.
If the delay, t , has elapsed, after V has risen
VSL
CC
the voltage applied on V ) until V reaches the
CC
CC
above V (min), the device can be selected for
CC
correct value:
READ instructions even if the t
fully elapsed.
delay is not yet
PUW
–
V
(min) at Power-up, and then for a further
CC
delay of t
VSL
As an extra protection, the Reset (Reset) signal
could be driven Low for the whole duration of the
Power-up and Power-down phases.
–
V
at Power-down
SS
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
At Power-up, the device is in the following state:
To avoid data corruption and inadvertent write op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
–
The device is in the Standby Power mode (not
the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
–
vice is held reset while V is less than the Power
CC
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC supply. Each de-
vice in a system should have the VCC rail decou-
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1 µF).
On Reset (POR) threshold value, V – all opera-
tions are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Write (PW), Page Program (PP),
Page Erase (PE) and Sector Erase (SE) instruc-
WI
At Power-down, when VCC drops from the operat-
ing voltage, to below the Power On Reset (POR)
threshold voltage, VWI, all operations are disabled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
tions until a time delay of t
has elapsed after
PUW
the moment that V rises above the V thresh-
CC
WI
old. However, the correct operation of the device
is not guaranteed if, by this time, V is still below
CC
V
(min). No Write, Program or Erase instructions
CC
should be sent until the later of:
–
–
t
t
after V passed the V threshold
CC WI
PUW
VSL
after V passed the V (min) level
CC
CC
Figure 20. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
24/37
M25PE10, M25PE20
Table 7. Power-Up Timing and V Threshold
WI
Symbol
Parameter
Min.
30
Max.
Unit
µs
1
V
(min) to S low
tVSL
CC
1
Time delay before the first Write, Program or Erase instruction
Write Inhibit Voltage
1
10
ms
V
tPUW
1
1.5
2.5
VWI
Note: 1. These parameters are characterized only, over the temperature range –40°C to +85°C.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each Byte contains
FFh). All usable Status Register bits are 0.
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Ratings
Symbol
Parameter
Min.
Max.
Unit
°C
°C
V
T
Storage Temperature
–65
150
STG
1
TLEAD
VIO
Lead Temperature during Soldering
Input and Output Voltage (with respect to Ground)
Supply Voltage
See note
–0.6
–0.6
4.0
4.0
V
V
CC
2
VESD
–2000
2000
V
Electrostatic Discharge Voltage (Human Body model)
®
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω)
25/37
M25PE10, M25PE20
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the devices. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions
Symbol
Parameter
Min.
2.7
Max.
3.6
Unit
V
V
Supply Voltage
Ambient Operating Temperature
CC
TA
–40
85
°C
Table 10. AC Measurement Conditions
Symbol
Parameter
Min.
Max.
Unit
pF
ns
V
C
Load Capacitance
30
L
Input Rise and Fall Times
5
0.2V to 0.8V
Input Pulse Voltages
CC
CC
CC
0.3V to 0.7V
Input and Output Timing Reference Voltages
V
CC
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC Measurement I/O Waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
CC
0.7V
CC
0.3V
CC
0.2V
AI00825B
Table 11. Capacitance
Symbol
COUT
Parameter
Test Condition
= 0V
Min.
Max.
Unit
pF
Output Capacitance (Q)
V
8
6
OUT
CIN
Input Capacitance (other pins)
V
= 0V
pF
IN
Note: Sampled only, not 100% tested, at T =25°C and a frequency of 20 MHz.
A
26/37
M25PE10, M25PE20
Table 12. DC Characteristics
Test Condition
(in addition to those in Table 9.)
Symbol
Parameter
Min.
Max.
Unit
ILI
Input Leakage Current
Output Leakage Current
± 2
± 2
µA
µA
ILO
Standby Current
(Standby and Reset modes)
ICC1
ICC2
S = VCC, VIN = VSS or VCC
50
µA
µA
Deep Power-down Current
S = VCC, VIN = VSS or VCC
C = 0.1VCC / 0.9.VCC at 25 MHz, Q = open
C = 0.1VCC / 0.9.VCC at 33 MHz, Q = open
S = VCC
10
6
ICC3
Operating Current (FAST_READ)
mA
8
ICC4
ICC5
VIL
Operating Current (PW)
Operating Current (SE)
Input Low Voltage
15
mA
mA
V
S = VCC
15
– 0.5
0.3VCC
VCC+0.4
0.4
VIH
Input High Voltage
0.7VCC
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 1.6 mA
V
IOH = –100 µA
VCC–0.2
V
27/37
M25PE10, M25PE20
Table 13. AC Characteristics (25MHz operation)
Test conditions specified in Table 9. and Table 10.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following
instructions: FAST_READ, PW, PP,
PE, SE, DP, RDP, WREN, WRDI,
RDSR
f
f
D.C.
25
MHz
C
C
Clock Frequency for READ
instructions
f
D.C.
20
MHz
R
(1)
t
Clock High Time
Clock Low Time
18
18
ns
ns
t
CLH
CH
(1)
t
t
CLL
CL
2
0.1
10
10
5
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Clock Slew Rate (peak to peak)
t
t
t
t
t
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
SLCH
CHSL
CSS
DVCH
CHDX
CHSH
SHCH
DSU
t
t
t
t
Data In Hold Time
5
DH
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
10
10
200
t
t
CSH
SHSL
(2)
t
Output Disable Time
15
15
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
CLQV
t
t
HO
0
CLQX
t
t
Top Sector Lock Setup Time
Top Sector Lock Hold Time
S to Deep Power-down
50
THSL
100
SHTL
(2)
3
t
DP
(2)
(3)
S High to Standby Power Mode
30
µs
t
RDP
Page Write Cycle Time (256 Bytes)
11
25
5
ms
t
PW
10.2 +
n*0.8/256
Page Write Cycle Time (n Bytes)
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
1.2
(3)
ms
t
PP
0.4 +
n*0.8/256
t
Page Erase Cycle Time
Sector Erase Cycle Time
10
1
20
5
ms
s
PE
t
SE
Note: 1. t + t must be greater than or equal to 1/ f
C
CH
CL
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
28/37
M25PE10, M25PE20
Table 14. AC Characteristics (33MHz operation)
(4)
33MHz only available for products marked since week 40 of 2005
Test conditions specified in Table 9. and Table 10.
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following
instructions: FAST_READ, PW, PP,
PE, SE, DP, RDP, WREN, WRDI,
RDSR
f
f
D.C.
33
MHz
C
C
Clock Frequency for READ
instructions
f
D.C.
20
MHz
R
(1)
t
Clock High Time
Clock Low Time
13
13
ns
ns
t
CLH
CH
(1)
t
t
CLL
CL
2
0.1
10
10
3
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Clock Slew Rate (peak to peak)
t
t
t
t
t
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
SLCH
CHSL
CSS
DVCH
CHDX
CHSH
SHCH
DSU
t
t
t
t
Data In Hold Time
5
DH
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
5
5
t
t
CSH
200
SHSL
(2)
t
Output Disable Time
12
12
t
DIS
SHQZ
t
t
V
Clock Low to Output Valid
Output Hold Time
CLQV
t
t
HO
0
CLQX
t
t
Top Sector Lock Setup Time
Top Sector Lock Hold Time
S to Deep Power-down
50
THSL
100
SHTL
(2)
3
t
DP
(2)
(3)
S High to Standby Power mode
30
µs
t
RDP
Page Write Cycle Time (256 Bytes)
11
25
5
ms
t
PW
10.2+
n*0.8/256
Page Write Cycle Time (n Bytes)
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
1.2
(3)
ms
t
PP
0.4+
n*0.8/256
t
Page Erase Cycle Time
Sector Erase Cycle Time
10
1
20
5
ms
s
PE
t
SE
Note: 1. t + t must be greater than or equal to 1/ f
C
CH
CL
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one sequence including all
the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
4. Details of how to find the date of marking are given in Application Note, AN1995.
29/37
M25PE10, M25PE20
Figure 22. Serial Input Timing
tSHSL
S
tCHSL
tSLCH
tCHSH
tSHCH
C
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
AI01447C
Figure 23. Top Sector Lock Setup and Hold Timing
TSL
tSHTL
tTHSL
S
C
D
High Impedance
Q
AI07439c
30/37
M25PE10, M25PE20
Figure 24. Output Timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449D
31/37
M25PE10, M25PE20
Table 15. Reset Timings
Test conditions specified in Table 9. and Table 10.
Symbol
Alt.
Parameter
Conditions
Min.
Typ.
Max.
Unit
(1)
t
Reset Pulse Width
10
µs
t
RST
RLRH
after any operation except
for PW, PP, PE and SE
30
µs
t
t
Reset Recovery Time After PW, PP and PE
operations
RHSL
REC
25
5
ms
s
After SE operations
Chip should have been
Chip Select High to
t
deselected before Reset is
Reset High
10
ns
SHRH
de-asserted
Note: 1. Value guaranteed by characterization, not 100% tested in production.
Figure 25. Reset AC Waveforms
S
tSHRH
tRHSL
tRLRH
Reset
AI06808
32/37
M25PE10, M25PE20
PACKAGE MECHANICAL
Figure 26. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline
D
D1
E
E1
E2
e
b
D2
θ
A
A2
L
A1 A3
VDFPN-01
Note: Drawing is not to scale.
Table 16. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.00
0.05
Typ
Max
A
A1
A2
A3
b
0.85
0.0335
0.0394
0.0020
0.00
0.35
3.20
0.0000
0.0138
0.1260
0.65
0.20
0.40
6.00
5.75
3.40
5.00
4.75
4.00
1.27
0.60
0.0256
0.0079
0.0157
0.2362
0.2264
0.1339
0.1969
0.1870
0.1575
0.0500
0.0236
0.48
3.60
4.20
0.0189
0.1417
0.1654
D
D1
D2
E
E1
E2
e
3.80
0.50
0.1496
0.0197
L
0.75
12°
0.0295
12°
θ
33/37
M25PE10, M25PE20
Figure 27. SO8 Narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
h x 45˚
A2
A
C
B
ddd
e
D
8
1
E
H
A1
α
L
SO-A
Note: Drawing is not to scale.
Table 17. SO8 Narrow – 8 lead Plastic Small Outline, 150 mils body width, Mechanical Data
millimeters
Min
inches
Min
Symbol
Typ
Max
1.75
0.25
1.65
0.51
0.25
5.00
0.10
4.00
–
Typ
Max
0.069
0.010
0.065
0.020
0.010
0.197
0.004
0.157
–
A
A1
A2
B
1.35
0.053
0.004
0.043
0.013
0.007
0.189
0.10
1.10
0.33
C
0.19
D
4.80
ddd
E
3.80
–
0.150
–
e
1.27
0.050
H
5.80
0.25
0.40
0
6.20
0.50
0.90
8
0.228
0.010
0.016
0
0.244
0.020
0.035
8
h
L
a
N
8
8
34/37
M25PE10, M25PE20
PART NUMBERING
Table 18. Ordering Information Scheme
Example:
M25PE20
–
V
MP
6
T
G
Device Type
M25PE = Page-Erasable Serial Flash Memory
Device Function
10 = 1 Mbit (128K x 8)
20 = 2 Mbit (256K x 8)
Operating Voltage
V = V = 2.7 to 3.6V
CC
Package
MN = SO8N (150 mil width)
MP = VDFPN8 6x5mm (MLP8)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHS compliant)
For a list of available options (speed, package,
etc.) or for further information on any aspect of this
device, please contact your nearest ST Sales Of-
fice.
The category of second Level Interconnect is
marked on the package and on the inner box label,
in compliance with JEDEC Standard JESD97. The
maximum ratings related to soldering conditions
are also marked on the inner box label.
35/37
M25PE10, M25PE20
REVISION HISTORY
Table 19. Document Revision History
Date
Version
Description of Revision
07-Dec-2004
0.1
Document written
Notes 1 and 2 removed from Table 18., Ordering Information Scheme. S08N silhouette
corrected in Figure 1., Packages.
21-Dec-2004
6-Oct-2005
0.2
1.0
Added Table 14., AC Characteristics (33MHz operation). Document status promoted
to full Datasheet. An Easy Way to Modify Data, A Fast Way to Modify Data, Page Write
(PW) and Page Program (PP) sections updated to explain optimal use of Page Write
and Page Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated Table 18., Ordering Information Scheme. Added Ecopack® information.
36/37
M25PE10, M25PE20
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -
Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
37/37
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