M25PE10-VMP6G [STMICROELECTRONICS]
1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout; 1和2兆位，低电压，页面可擦除串行闪存与字节变性， 50兆赫的SPI总线，标准引脚
| 型号： | M25PE10-VMP6G |
| 厂家： | 
ST |
| 描述： | 1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories with Byte-Alterability, 50 MHz SPI bus, standard pinout |
| 文件： | 总60页 (文件大小：479K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25PE20
M25PE10
1 and 2 Mbit, low voltage, Page-Erasable Serial Flash memories
with Byte-Alterability, 50 MHz SPI bus, standard pinout
Features
■ 1 or 2 Mbit of Page-Erasable Flash memory
■ 2.7 V to 3.6 V single supply voltage
■ SPI bus compatible serial interface
■ 50 MHz clock rate (maximum)
■ Page size: 256 bytes
– Page Write in 11 ms (typical)
– Page Program in 0.8 ms (typical)
– Page Erase in 10 ms (typical)
SO8N (MN)
150 mil width
■ SubSector Erase (32 Kbits)
■ Sector Erase (512 Kbits)
■ Bulk Erase (1 Mbit for the M25PE10, 2 Mbits for
the M25PE20)
■ Deep Power-down mode 1µA (typical)
■ Electronic Signature
VFQFPN8 (MP)
6 × 5 mm
– JEDEC Standard Two-Byte Signature
(8012h for M25PE20
8011h for M25PE10)
■ Software Write Protection on a 64 Kbyte sector
basis
■ More than 100 000 Write cycles
■ More than 20 year data retention
■ Hardware Write Protection of the memory area
selected using the BP0 and BP1 bits
■ Package
– ECOPACK® (RoHS compliant)
January 2007
Rev 3
1/60
www.st.com
1
Contents
M25PE20, M25PE10
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Important note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
Serial Data Output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Reset (Reset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (W) or Top Sector Lock (TSL) . . . . . . . . . . . . . . . . . . . . . . . . 9
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Sharing the overhead of modifying data . . . . . . . . . . . . . . . . . . . . . . . . . . 12
An easy way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
A fast way to modify data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 13
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Active Power, Standby Power and Deep Power-Down modes . . . . . . . . . 13
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
4.8.1
4.8.2
Protocol-related protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Specific Hardware and Software protections . . . . . . . . . . . . . . . . . . . . . 15
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.1
6.2
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2/60
M25PE20, M25PE10
Contents
6.3
6.4
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.1
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.4.2
6.4.3
6.4.4
6.5
6.6
6.7
6.8
6.9
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 31
Read Lock Register (RDLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Page Write (PW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.10 Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6.11 Write to Lock Register (WRLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
6.12 Page Erase (PE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
6.13 SubSector Erase (SSE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.14 Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6.15 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.16 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.17 Release from Deep Power-down (RDP) . . . . . . . . . . . . . . . . . . . . . . . . . . 43
7
Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
8
9
10
11
12
13
14
3/60
List of tables
M25PE20, M25PE10
List of tables
Table 1.
Table 2.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Software protection truth table (Sectors 0 to 3 for M25PE20 or sectors 0
to 1 for M25PE10, 64-Kbyte granularity) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protected area sizes for M25PE20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Protected area sizes for M25PE10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
M25PE20 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
M25PE10 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Protection modes (T9HX process only, see Important note on page 6) . . . . . . . . . . . . . . . 29
Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Lock Register In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power-up timing and VWI threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Device status after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
AC characteristics (25 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
AC characteristics (33 MHz operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
AC characteristics (50 MHz operation, T9HX (0.11µm) process) . . . . . . . . . . . . . . . . . . . 52
Reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Timings after a Reset Low pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
VFQFPN8 (MLP8), 8-lead Very thin Fine Pitch Quad Flat Package No lead,
Table 26.
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 27.
Table 28.
4/60
M25PE20, M25PE10
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram - previous T7X process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Logic diagram - new T9HX process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
VFQFPN and SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
M25PE20 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
M25PE10 block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 25
Figure 11. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 27
Figure 12. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 30
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 15. Read Lock Register (RDLR) instruction sequence and data-out Sequence. . . . . . . . . . . . 32
Figure 16. Page Write (PW) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 17. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 18. Write to Lock Register (WRLR) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Page Erase (PE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 20. SubSector Erase (SSE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 21. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 22. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 23. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 24. Release from Deep Power-down (RDP) instruction sequence. . . . . . . . . . . . . . . . . . . . . . 43
Figure 25. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 27. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 28. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 29. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 30. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 31. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline . . . . . . . . . . . 56
Figure 32. VFQFPN8 (MLP8), 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5/60
Description
M25PE20, M25PE10
1
Description
The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) Serial
Paged Flash memories, respectively. They are accessed by a high speed SPI-compatible
bus.
The memories can be written or programmed 1 to 256 Bytes at a time, using the Page Write
or Page Program instruction. The Page Write instruction consists of an integrated Page
Erase cycle followed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages. Each page is
256 Bytes wide. Thus, the whole memory can be viewed as consisting of 1024 pages, or
262,144 Bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages. Each page is
256 Bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,
072 Bytes.
The memories can be erased a page at a time, using the Page Erase instruction, a
subsector at a time, using the SubSector Erase instruction, a sector at a time, using the
Sector Erase instruction or as a whole, using the Bulk Erase instruction.
The memory can be Write Protected by either Hardware or Software using a mix of volatile
and non-volatile protection features, depending on the application needs. The protection
granularity is of 64 Kbytes (sector granularity).
In order to meet environmental requirements, ST offers the M25PE20 and M25PE10 in
ECOPACK® packages. ECOPACK® packages are Lead-free and RoHS compliant.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Important note
This datasheet details the functionality of the M25PE20 and M25PE10 devices, based on
the previous T7X process or based on the current T9HX process. Delivery of parts in T9HX
process starts from August 2007.
What are the changes?
The M25PE10/M25PE20 in T9HX process offers the following additional features:
■
■
the whole memory array is partitioned into 4-Kbyte subsectors
five new instructions: Write Status Register (WRSR), Write to Lock Register (WRLR),
Read Lock Register (RDLR), 4-Kbyte SubSector Erase (SSE) and Bulk Erase (BE)
■
■
Status Register: 3 bits can be written (BP0, BP1, SRWD)
WP input (pin 3): Write protection limits are extended, depending on the value of the
BP0, BP1, SRWD bits. The WP Write protection remains the same if bits (BP1, BP0)
are set to (0, 1) or (1, 0)
■
VFQFPN8 6 × 5 mm package added
6/60
M25PE20, M25PE10
Figure 1.
Description
Logic diagram - previous T7X Figure 2.
process
Logic diagram - new T9HX
process
V
V
CC
CC
D
Q
D
C
S
Q
C
S
M25PE20
M25PE10
M25PE10
M25PE20
W
TSL
Reset
Reset
V
V
SS
AI13808
SS
AI09713
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
Input
Output
Input
Input
Input
D
Serial Data Input
Serial Data Output
Chip Select
Q
S
TSL or W(1)
Reset
VCC
Top Sector Lock or Write Protect
Reset
Supply Voltage
Ground
VSS
1. In the previous T7X process the pin is a Top Sector Lock input whereas in the new T9HX process, the pin
is a Write Protect input (see Figure 1 and Figure 2).
Figure 3.
VFQFPN and SO connections
M25PE20
M25PE10
S
Q
1
2
3
4
8
7
6
5
V
CC
Reset
TSL or W
C
D
V
SS
AI09715b
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
SS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
V
2. See Package mechanical section for package dimensions, and how to identify pin-1.
7/60
Signal description
M25PE20, M25PE10
2
Signal description
2.1
Serial Data Output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
2.3
2.4
Serial Data Input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data Input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data Output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data Output (Q) is at high
impedance. Unless an internal Read, Program, Erase or Write cycle is in progress, the
device will be in the Standby Power mode (this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
Reset (Reset)
The Reset (Reset) input provides a hardware reset for the memory.
When Reset (Reset) is driven High, the memory is in the normal operating mode. When
Reset (Reset) is driven Low, the memory will enter the Reset mode. In this mode, the output
is high impedance.
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
2.6
Top Sector Lock (TSL)
This input signal puts the device in the Hardware Protected mode, when Top Sector Lock
(TSL) is connected to V , causing the top 256 pages (upper addresses) of the memory to
SS
become read-only (protected from write, program and erase operations).
When Top Sector Lock (TSL) is connected to V , the top 256 pages of memory behave like
CC
the other pages of memory.
8/60
M25PE20, M25PE10
Signal description
2.7
Write Protect (W) or Top Sector Lock (TSL)
■
The Write Protect function is available in the T9HX process only (see Important
note on page 6).
The Write Protect (W) input is used to freeze the size of the area of memory that is
protected against write, program and erase instructions (as specified by the values in
theBP1 and BP0 bits of the Status Register. See Section 6.4: Read Status Register
(RDSR) for a description of these bits).
■
The Top Sector Lock function is available in the T7X process only (see Important
note on page 6).
The input signal sets the device in the Hardware Protected mode, when Top Sector
Lock (TSL) is connected to V , causing the top 256 pages (upper addresses) of the
SS
memory to become read-only (protected from write, program and erase operations).
When Top Sector Lock (TSL) is connected to V , the top 256 pages of memory
CC
behave like the other pages of memory.
2.8
2.9
VCC supply voltage
V
is the supply voltage.
CC
VSS ground
V
is the reference for the V supply voltage.
CC
SS
9/60
SPI modes
M25PE20, M25PE10
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
■
■
CPOL=0, CPHA=0
CPOL=1, CPHA=1
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 5, is the clock polarity when the
bus master is in Standby mode and not transferring data:
■
■
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
Figure 4.
Bus master and memory devices on the SPI bus
V
V
SS
CC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
V
V
V
CC
C
Q
D
C
Q
D
C Q D
CC
CC
V
V
V
SS
SS
SS
SPI Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
or
or
or
TSL
TSL
TSL
AI13558
1. The Write Protect or Top Sector Lock (W or TSL) signal should be driven, High or Low as appropriate.
Figure 4 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data Output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 4) ensure
that the M25PE20 or M25PE10 is not selected if the Bus Master leaves the S line in the high
impedance state. As the Bus Master may enter a state where all inputs/outputs are in high
impedance at the same time (for example, when the Bus Master is reset), the clock line (C)
must be connected to an external pull-down resistor so that, when all inputs/outputs become
high impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S
and C do not become High at the same time, and so, that the t
requirement is met).
SHCH
The typical value of R is 100 kΩ, assuming that the time constant R*C (C = parasitic
p
p
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
10/60
M25PE20, M25PE10
SPI modes
Example: C = 50 pF, that is R*C = 5 µs <=> the application must ensure that the Bus
p
p
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 5.
SPI modes supported
CPOL CPHA
C
C
0
1
0
1
D
Q
MSB
MSB
AI01438B
11/60
Operating features
M25PE20, M25PE10
4
Operating features
4.1
Sharing the overhead of modifying data
To write or program one (or more) data Bytes, two instructions are required: Write Enable
(WREN), which is one Byte, and a Page Write (PW) or Page Program (PP) sequence, which
consists of four Bytes plus data. This is followed by the internal cycle (of duration t
or t ).
PW
PP
To share this overhead, the Page Write (PW) or Page Program (PP) instruction allows up to
256 Bytes to be programmed (changing bits from 1 to 0) or written (changing bits to 0 or 1)
at a time, provided that they lie in consecutive addresses on the same page of memory.
4.2
An easy way to modify data
The Page Write (PW) instruction provides a convenient way of modifying data (up to 256
contiguous Bytes at a time), and simply requires the start address, and the new data in the
instruction sequence.
The Page Write (PW) instruction is entered by driving Chip Select (S) Low, and then
transmitting the instruction Byte, three address Bytes (A23-A0) and at least one data Byte,
and then driving Chip Select (S) High. While Chip Select (S) is being held Low, the data
Bytes are written to the data buffer, starting at the address given in the third address Byte
(A7-A0). When Chip Select (S) is driven High, the Write cycle starts. The remaining,
unchanged, Bytes of the data buffer are automatically loaded with the values of the
corresponding Bytes of the addressed memory page. The addressed memory page then
automatically put into an Erase cycle. Finally, the addressed memory page is programmed
with the contents of the data buffer.
All of this buffer management is handled internally, and is transparent to the user. The user
is given the facility of being able to alter the contents of the memory on a Byte-by-Byte basis.
For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted Bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few Bytes (see Page Write (PW) and Table 22: AC
characteristics (50 MHz operation, T9HX (0.11µm) process)).
12/60
M25PE20, M25PE10
Operating features
4.3
A fast way to modify data
The Page Program (PP) instruction provides a fast way of modifying data (up to 256
contiguous Bytes at a time), provided that it only involves resetting bits to 0 that had
previously been set to 1.
This might be:
■
■
when the designer is programming the device for the first time
when the designer knows that the page has already been erased by an earlier Page
Erase (PE), SubSector Erase (SSE), Sector Erase (SE) or Bulk Erase (BE) instruction.
This is useful, for example, when storing a fast stream of data, having first performed
the erase cycle when time was available
■
when the designer knows that the only changes involve resetting bits to 0 that are still
set to 1. When this method is possible, it has the additional advantage of minimizing the
number of unnecessary erase operations, and the extra stress incurred by each page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Page Program (PP)
and Table 22: AC characteristics (50 MHz operation, T9HX (0.11µm) process)).
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the write, program or erase time can be achieved by not waiting for
the worst case delay (t , t , t , t , t or t ). The Write In Progress (WIP) bit is
PW PP PE BE
W
SE
provided in the Status Register so that the application program can monitor its value, polling
it to establish when the previous cycle is complete.
4.5
4.6
Reset
An internal Power-On Reset circuit helps protect against inadvertent data writes. Addition
protection is provided by driving Reset (Reset) Low during the Power-on process, and only
driving it High when V has reached the correct voltage level, V (min).
CC
CC
Active Power, Standby Power and Deep Power-Down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write). The device then goes
in to the Standby Power mode. The device consumption drops to I
.
CC1
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I . The
CC2
device remains in this mode until the Release from Deep Power-down instruction is
executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
13/60
Operating features
M25PE20, M25PE10
4.7
Status Register
The Status Register contains two status bits that can be read by the Read Status Register
(RDSR) instruction. See Section 6.4: Read Status Register (RDSR) for a detailed
description of the Status Register bits.
4.8
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25PE10 and M25PE20 feature the following data protection mechanisms:
4.8.1
Protocol-related protections
■
■
■
Power On Reset and an internal timer (t
changes while the power supply is outside the operating specification.
) can provide protection against inadvertent
PUW
Program, Erase and Write instructions are checked that they consist of a number of
clock pulses that is a multiple of eight, before they are accepted for execution.
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
–
–
–
–
Power-up
Reset (RESET) driven Low
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write to Lock Register (WRLR) instruction completion
Page Erase (PE) instruction completion
SubSector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
■
■
The Reset (Reset) signal can be driven Low to freeze and reset the internal logic. For
the specific cases of Program and Write cycles, the designer should refer to
Section 6.5: Write Status Register (WRSR), Section 6.9: Page Write (PW),
Section 6.10: Page Program (PP), Section 6.12: Page Erase (PE), Section 6.14: Sector
Erase (SE), and Section 6.13: SubSector Erase (SSE), and to Table 14: Device status
after a Reset Low pulse.
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions while
the device is not in active use.
14/60
M25PE20, M25PE10
Operating features
4.8.2
Specific Hardware and Software protections
The M25PE20/M25PE20 features a Hardware Protected mode, HPM, and two Software
Protected modes, SPM1 and SPM2, that can be combined to protect the memory array as
required. They are described below:
HPM
■
HPM in T7X process (see Important note on page 6):
The Hardware Protected mode (HPM) is entered when Top Sector Lock (TSL) is driven
Low, causing the top 256 pages of memory to become read-only. When Top Sector
Lock (TSL) is driven High, the top 256 pages of memory behave like the other pages of
memory and the protection depends on the Block Protect bits (see SPM2 below).
■
HPM in T9HX process (see Important note on page 6):
The Hardware Protected mode (HPM) is used to write-protect the non-volatile bits of
the Status Register (that is, the Block Protect bits, BP1 and BP0, and the Status
Register Write Disable bit, SRWD).
HPM is entered by driving the Write Protect (W) signal Low with the SRWD bit set to
High. This additional protection allows the Status Register to be hardware-protected.
(see also Section 6.4.4: SRWD bit)
SPM1 and SPM2
■
The first Software Protected mode (SPM1) is managed by specific Lock Registers
assigned to each 64-Kbyte sector.
The Lock Registers can be read and written using the Read Lock Register (RDLR) and
Write to Lock Register (WRLR) instructions.
In each Lock Register two bits control the protection of each sector: the Write Lock Bit
and the Lock Down Bit.
–
Write Lock Bit:
The Write Lock Bit determines whether the contents of the sector can be modified
(using the Write, Program or Erase instructions). When the Write Lock Bit is set,
‘1’, the sector is write protected – any operations that attempt to change the data
in the sector will fail. When the Write Lock Bit is reset to ‘0’, the sector is not write
protected by the Lock Register, and may be modified.
–
Lock Down Bit:
The Lock Down Bit provides a mechanism for protecting software data from simple
hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further
modification to the Write Lock and Lock Down Bits cannot be performed. A reset,
or power-up, is required before changes to these bits can be made. When the
Lock Down Bit is reset, ‘0’, the Write Lock and Lock Down Bits can be changed.
The Write Lock Bit and the Lock Down Bit are volatile and their value is reset to ‘0’ after
a Power-Down or a Reset.
15/60
Operating features
Table 2.
M25PE20, M25PE10
Software protection truth table (Sectors 0 to 3 for M25PE20 or sectors 0
to 1 for M25PE10, 64-Kbyte granularity)
Sector Lock Register
Protection status
Lock
Write
Down bit Lock bit
Sector unprotected from Program/Erase/Write operations, Protection status
reversible
0
0
1
1
0
1
0
1
Sector protected from Program/Erase/Write operations, Protection status
reversible
Sector Unprotected from Program/Erase/Write operations,
Sector Protection Status cannot be changed except by a Reset or Power-up.
Sector Protected from Program/Erase/Write operations,
Sector Protection Status cannot be changed except by a Reset or Power-up.
■
The second Software Protected mode (SPM2) uses the Block Protect (BP1, BP0,
see Section 6.4.3)) bits to allow part of the memory to be configured as read-only.
Table 3.
Protected area sizes for M25PE20
Status Register
content
Memory content
BP1 Bit BP0 Bit
Protected area
Unprotected area
0
0
1
1
0
1
0
1
none
All sectors(1) (four sectors: 0 to 3)
Lower three quarters (three sectors: 0 to 2)
Lower half (two sectors: 0 to 1)
none
Upper quarter (Sector 3)
Upper half (two sectors: 2 and 3)
All sectors (four sectors: 0 to 3)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect bits (BP1, BP0) are 0.
Table 4.
Protected area sizes for M25PE10
Status Register
content
Memory content
BP1 Bit BP0 Bit
Protected area
Unprotected area
0
0
1
1
0
1
0
1
none
All sectors(1) (two sectors: 0 and 1)
Lower half (one sector: sector 0)
Lower half (one sector: sector 0)
none
Upper half (1 sector: sector 1)
Upper half (1 sector: sector 1)
All sectors (two sectors: 0 and 1)
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect bits (BP1, BP0) are 0.
16/60
M25PE20, M25PE10
Memory organization
5
Memory organization
The M25PE20 memory is organized as:
■
■
■
■
1024 pages (256 Bytes each).
262,144 Bytes (8 bits each)
64 subsectors (32 Kbits, 4096 bytes each)
4 sectors (512 Kbits, 65536 Bytes each)
The M25PE10 memory is organized as:
■
■
■
■
512 pages (256 Bytes each).
131,074 Bytes (8 bits each)
32 subsectors (32 Kbits, 4096 bytes each)
2 sectors (512 Kbits, 65536 Bytes each)
In the M25PE20 and M25PE10, each page can be individually:
■
■
■
programmed (bits are programmed from 1 to 0)
erased (bits are erased from 0 to 1)
written (bits are changed to either 0 or 1)
The device is Page or Sector Erasable (bits are erased from 0 to 1).
Table 5.
Sector
M25PE20 memory organization
Subsector
Address range
63
3F000h
3FFFFh
3
2
1
48
47
30000h
2F000h
30FFFh
2FFFFh
32
31
20000h
1F000h
20FFFh
1FFFFh
16
15
10000h
0F000h
10FFFh
0FFFFh
4
3
2
1
0
04000h
03000h
02000h
01000h
00000h
04FFFh
03FFFh
02FFFh
01FFFh
00FFFh
0
17/60
Memory organization
Table 6.
M25PE20, M25PE10
M25PE10 memory organization
Subsector
Sector
Address range
31
1F000h
1FFFFh
1
16
15
10000h
0F000h
10FFFh
0FFFFh
4
3
2
1
0
04000h
03000h
02000h
01000h
00000h
04FFFh
03FFFh
02FFFh
01FFFh
00FFFh
0
18/60
M25PE20, M25PE10
Figure 6.
Memory organization
M25PE20 block diagram
Reset
TSL or W
S
High Voltage
Generator
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
3FF00h
3FFFFh Top 256 Pages can
be made read-only
(1)
by using the TSL pin
2FFFFh
The whole memory array
can be made read-only
on a 64 Kbyte basis
through the Lock
Registers
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI3294b
1. These features (in gray) are only available in the T7X process.
19/60
Memory organization
Figure 7.
M25PE20, M25PE10
M25PE10 block diagram
Reset
TSL or W
S
High Voltage
Generator
Control Logic
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
1FF00h
1FFFFh
Top 256 Pages can
be made read-only
by using the TSL pin
(1)
FFFFh
The whole memory array
can be made read-only
on a 64 Kbyte basis
through the Lock
Registers
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI13295b
1. These features (in gray) are only available in the T7X process.
20/60
M25PE20, M25PE10
Instructions
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data Input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-Byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data Input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 7.
Every instruction sequence starts with a one-Byte instruction code. Depending on the
instruction, this might be followed by address Bytes, or by data Bytes, or by both or none.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Status Register (RDSR) or Read to Lock Register (RDLR) instruction, the shifted-in
instruction sequence is followed by a data-out sequence. Chip Select (S) can be driven High
after any bit of the data-out sequence is being shifted out.
In the case of a Page Write (PW), Page Program (PP), Page Erase (PE), SubSector Erase
(SSE), Sector Erase (SE), Bulk Erase (BE), Write Enable (WREN), Write Disable (WRDI),
Write Status Register (WRSR), Write to Lock Register (WRLR), Deep Power-down (DP) or
Release from Deep Power-down (RDP) instruction, Chip Select (S) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is,
Chip Select (S) must driven High when the number of clock pulses after Chip Select (S)
being driven Low is an exact multiple of eight.
All attempts to access the memory array during a Write cycle, Program cycle or Erase cycle
are ignored, and the internal Write cycle, Program cycle or Erase cycle continues
unaffected.
21/60
Instructions
M25PE20, M25PE10
Table 7.
Instruction set
Description
One-byte
Addr Dummy
Data
Instruction
Instruction code bytes bytes
bytes
WREN
WRDI
Write Enable
0000 0110
0000 0100
1001 1111
0000 0101
1110 0101
0000 0001
1110 1000
0000 0011
06h
04h
9Fh
05h
E5h
01h
E8h
03h
0Bh
0Ah
02h
DBh
20h
D8h
C7h
B9h
ABh
0
0
0
0
3
0
3
3
3
3
3
3
3
3
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Write Disable
0
RDID
Read Identification
Read Status Register
Write to Lock Register
Write Status Register
Read Lock Register
Read Data Bytes
1 to 3
RDSR(1)
WRLR(1)
WRSR(1)
RDLR
1 to ∞
1
1
1
READ
1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011
1 to ∞
PW
PP
Page Write
0000 1010
0000 0010
1101 1011
0010 0000
1101 1000
1100 0111
1011 1001
1010 1011
1 to 256
Page Program
1 to 256
PE
Page Erase
0
0
0
0
0
0
SSE(1)
SubSector Erase
Sector Erase
SE
BE(1)
DP
Bulk Erase
Deep Power-down
Release from Deep Power-down
RDP
1. Instruction available only in the T9HX process (see Important note on page 6).
22/60
M25PE20, M25PE10
Instructions
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Write (PW), Page
Program (PP), Page Erase (PE), and Sector Erase (SE) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 8.
Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
23/60
Instructions
M25PE20, M25PE10
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
■
Power-up
■
■
■
■
■
■
■
■
■
Write Disable (WRDI) instruction completion
Page Write (PW) instruction completion
Page Program (PP) instruction completion
Write Status Register (WRSR) instruction completion
Write to Lock Register (WRLR) instruction completion
Page Erase (PE) instruction completion
SubSector Erase (SSE) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 9.
Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
24/60
M25PE20, M25PE10
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two Bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for STMicroelectronics. The device identification
is assigned by the device manufacturer, and indicates the memory type in the first Byte
(80h), and the memory capacity of the device in the second Byte (12h for the M25PE20 and
11h for the M25PE10).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data Output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 10.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. Once in
the Standby Power mode, the device waits to be selected, so that it can receive, decode and
execute instructions.
Table 8.
Read Identification (RDID) data-out sequence
Device Identification
Manufacturer Identification
Memory Type
Memory Capacity
20h
20h
80h
80h
12h (M25PE20)
11h (M25PE10)
Figure 10. Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 16 18
28 29 30 31
C
D
Instruction
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809
25/60
Instructions
M25PE20, M25PE10
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write cycle is in
progress. When one of these cycles is in progress, it is recommended to check the Write In
Progress (WIP) bit before sending a new instruction to the device. It is also possible to read
the Status Register continuously, as shown in Figure 11.
The status bits of the Status Register are as follows:
6.4.1
6.4.2
6.4.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write, Program
or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is
in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write, Program or Erase instruction is accepted.
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Program and Erase instructions. These bits are written with the
Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1,
BP0) bits is set to 1, the relevant memory area (as defined in Table 3) becomes protected
against Page Program (PP), Page Erase (PE), Sector Erase (SE) and SubSector Erase
(SSE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if,
and only if:
■
all Block Protect (BP1, BP0) bits are 0
■
the Lock Register protection bits are not all set (‘1’)
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. When the Status Register Write Disable (SRWD) bit is set to 1, and Write
Protect (W) is driven Low, the non-volatile bits of the Status Register (SRWD, BP1, BP0)
become read-only bits. In such a state, as the Write Status Register (WRSR) instruction is
no longer accepted for execution, the definition of the size of the Write Protected area
cannot be further modified.
(1) (2)
Table 9.
Status Register format
b7
b0
SRWD
0
0
0
BP1
BP0
WEL(3)
WIP(3)
1. SRWD = Status Register Write Protect bit; BP0, BP1 = Block Protect Bits (only available with T9HX).
2. The BP bits and the SRWD bit exist only in the T9HX process.
3. WEL (Write Enable Latch) and WIP (Write In Progress) are volatile read-only bits (WEL is set and reset by
specific instructions; WIP is automatically set and reset by the internal logic of the device).
26/60
M25PE20, M25PE10
Instructions
Figure 11. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
27/60
Instructions
M25PE20, M25PE10
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register.
Note:
The Status Register BPi and SRWD bits are available in the T9HX process only. See
Important note on page 6 for more details.
Before the Write Status Register (WRSR) instruction can be accepted, a Write Enable
(WREN) instruction must previously have been executed. After the Write Enable (WREN)
instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 12.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t ) is
W
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 3. The Write Status Register (WRSR) instruction also allows the
user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal (see Section 6.4.4).
If a Write Status Register (WRSR) instruction is interrupted by a Reset Low pulse, the
internal cycle of the Write Status Register operation (whose duration is t ) is first completed
W
(provided that the supply voltage V remains within the operating range). After that the
CC
device enters the Reset mode (see also Table 14: Device status after a Reset Low pulse
and Table 24: Timings after a Reset Low pulse).
Figure 12. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
28/60
M25PE20, M25PE10
Instructions
Table 10. Protection modes (T9HX process only, see Important note on page 6)
Memory Content
W
Signal
SRWD
Bit
Write Protection of the
Status Register
Mode
Protected Area(1) Unprotected Area(1)
1
0
0
0
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
Second
Software
Protected
(SPM2)
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
The values in the SRWD,
BP1 and BP0 bits can be
changed
instructions
1
1
Status Register is
Hardware write protected
Protected against
Page Program,
Sector Erase and
Bulk Erase
Ready to accept
Page Program and
Sector Erase
Hardware
Protected
(HPM)
0
1
The values in the SRWD,
BP1 and BP0 bits cannot
be changed
instructions
1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 3.
The protection features of the device are summarized in Table 10.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
■
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
■
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM2) by the Block Protect (BP1, BP0) bits of the Status Register,
are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
■
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
■
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM2), using the Block Protect
(BP1, BP0) bits of the Status Register, can be used.
29/60
Instructions
M25PE20, M25PE10
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-Byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data Output (Q), each bit being shifted out, at a maximum
frequency f , during the falling edge of Serial Clock (C).
R
The instruction sequence is shown in Figure 13.
The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 13. Read Data Bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
7
High Impedance
2
7
6
5
4
3
1
0
MSB
AI03748D
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
30/60
M25PE20, M25PE10
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-Byte address (A23-
A0) and a dummy Byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data Output (Q), each
bit being shifted out, at a maximum frequency f , during the falling edge of Serial Clock (C).
C
The instruction sequence is shown in Figure 14.
The first Byte addressed can be at any location. The address is automatically incremented
to the next higher address after each Byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 14. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
3
2
1
0
D
Q
S
C
High Impedance
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI04006
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
31/60
Instructions
M25PE20, M25PE10
6.8
Read Lock Register (RDLR)
Note:
The Read Lock Register (RDLR) instruction is decoded only in the T9HX process (see
Important note on page 6).
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Lock Register (RDLR) instruction is followed by a 3-byte address (A23-A0) pointing to any
location inside the concerned sector (or subsector). Each address bit is latched-in during
the rising edge of Serial Clock (C). Then the value of the Lock Register is shifted out on
Serial Data Output (Q), each bit being shifted out, at a maximum frequency f , during the
C
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 15.
The Read Lock Register (RDLR) instruction is terminated by driving Chip Select (S) High at
any time during data output.
Any Read Lock Register (RDLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Table 11. Lock Registers
Bit
Bit Name
Value
Function
b7-b4
Reserved
The Write Lock and Lock Down Bits cannot be changed. Once a
‘1’ ‘1’ is written to the Lock Down Bit it cannot be cleared to ‘0’,
except by a Reset or power-up.
Sector Lock
Down
b1
b0
The Write Lock and Lock Down Bits can be changed by writing
new values to them. (Default value).
‘0’
Write, Program and Erase operations in this sector will not be
executed. The memory contents will not be changed.
‘1’
Sector Write
Lock
Write, Program and Erase operations in this sector are executed
and will modify the sector contents. (Default value).
‘0’
Figure 15. Read Lock Register (RDLR) instruction sequence and data-out Sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Lock Register Out
High Impedance
2
7
6
5
4
3
1
0
MSB
AI10783
32/60
M25PE20, M25PE10
Instructions
6.9
Page Write (PW)
The Page Write (PW) instruction allows Bytes to be written in the memory. Before it can be
accepted, a Write Enable (WREN) instruction must previously have been executed. After the
Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch
(WEL).
The Page Write (PW) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, three address Bytes and at least one data Byte on Serial Data Input (D).
The rest of the page remains unchanged if no power failure occurs during this write cycle.
The Page Write (PW) instruction performs a page erase cycle even if only one Byte is
updated.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data exceeding
the addressed page boundary roll over, and are written from the start address of the same
page (the one whose 8 least significant address bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 16.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the
last 256 data Bytes are guaranteed to be written correctly within the same page. If less than
256 Data Bytes are sent to device, they are correctly written at the requested addresses
without having any effects on the other Bytes of the same page.
For optimized timings, it is recommended to use the Page Write (PW) instruction to write all
consecutive targeted Bytes in a single sequence versus using several Page Write (PW)
sequences with each containing only a few Bytes (see Table 22: AC characteristics (50 MHz
operation, T9HX (0.11µm) process)).
Chip Select (S) must be driven High after the eighth bit of the last data Byte has been
latched in, otherwise the Page Write (PW) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Write cycle (whose duration
is t ) is initiated. While the Page Write cycle is in progress, the Status Register may be
PW
read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is
1 during the self-timed Page Write cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Write (PW) instruction applied to a page that is Hardware Protected is not executed.
Any Page Write (PW) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
33/60
Instructions
M25PE20, M25PE10
Figure 16. Page Write (PW) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte n
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04045
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
2. 1 ≤n ≤256
34/60
M25PE20, M25PE10
Instructions
6.10
Page Program (PP)
The Page Program (PP) instruction allows Bytes to be programmed in the memory
(changing bits from 1 to 0, only). Before it can be accepted, a Write Enable (WREN)
instruction must previously have been executed. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address Bytes and at least one data Byte on Serial Data Input
(D). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data
exceeding the addressed page boundary roll over, and are programmed from the start
address of the same page (the one whose 8 least significant address bits (A7-A0) are all
zero). Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 17.
If more than 256 Bytes are sent to the device, previously latched data are discarded and the
last 256 data Bytes are guaranteed to be programmed correctly within the same page. If
less than 256 Data Bytes are sent to device, they are correctly programmed at the
requested addresses without having any effects on the other Bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted Bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few Bytes (see Table 22: AC
characteristics (50 MHz operation, T9HX (0.11µm) process)).
Chip Select (S) must be driven High after the eighth bit of the last data Byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t ) is initiated. While the Page Program cycle is in progress, the Status Register
PP
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page that is Hardware Protected is not
executed.
Any Page Program (PP) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
35/60
Instructions
M25PE20, M25PE10
Figure 17. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
C
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Data Byte 2
Data Byte 3
Data Byte n
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
D
MSB
MSB
MSB
AI04044
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
2. 1 ≤n ≤256
36/60
M25PE20, M25PE10
Instructions
6.11
Write to Lock Register (WRLR)
Note:
The Write to Lock Register (WRLR) instruction is decoded only in the T9HX process (see
Important note on page 6).
The Write to Lock Register (WRLR) instruction allows bits to be changed in the Lock
Registers. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded, the
device sets the Write Enable Latch (WEL).
The Write to Lock Register (WRLR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code, three address bytes (pointing to any address in the targeted
sector and one data byte on Serial Data Input (D). The instruction sequence is shown in
Figure 18. Chip Select (S) must be driven High after the eighth bit of the data byte has been
latched in, otherwise the Write to Lock Register (WRLR) instruction is not executed.
Lock Register bits are volatile, and therefore do not require time to be written. When the
Write to Lock Register (WRLR) instruction has been successfully executed, the Write
Enable Latch (WEL) bit is reset after a delay time less than t
minimum value.
SHSL
Any Write to Lock Register (WRLR) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 18. Write to Lock Register (WRLR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Lock Register
C
D
Instruction
24-Bit Address
Value
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
AI10784b
Table 12. Lock Register In
Sector
Bit
Value
b7-b2
b1
‘0’
All sectors
Sector Lock Down Bit Value
Sector Write Lock Bit Value
b0
37/60
Instructions
M25PE20, M25PE10
6.12
Page Erase (PE)
The Page Erase (PE) instruction sets to 1 (FFh) all bits inside the chosen page. Before it can
be accepted, a Write Enable (WREN) instruction must previously have been executed. After
the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable
Latch (WEL).
The Page Erase (PE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address Bytes on Serial Data Input (D). Any address inside the
Page is a valid address for the Page Erase (PE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 19.
Chip Select (S) must be driven High after the eighth bit of the last address Byte has been
latched in, otherwise the Page Erase (PE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Page Erase cycle (whose duration is t ) is initiated.
PE
While the Page Erase cycle is in progress, the Status Register may be read to check the
value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-
timed Page Erase cycle, and is 0 when it is completed. At some unspecified time before the
cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Page Erase (PE) instruction applied to a page that is Hardware Protected is not executed.
Any Page Erase (PE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 19. Page Erase (PE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI04046
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
38/60
M25PE20, M25PE10
Instructions
6.13
SubSector Erase (SSE)
Note:
The SubSector Erase (SSE) instruction is decoded only in the T9HX process (see Important
note on page 6).
The SubSector Erase (SSE) instruction sets to 1 (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed. After the Write Enable (WREN) instruction has been decoded, the device sets the
Write Enable Latch (WEL).
The SubSector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, and three address bytes on Serial Data Input (D). Any address inside
the SubSector (see Table 5) is a valid address for the SubSector Erase (SE) instruction.
Chip Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 21.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the SubSector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed SubSector Erase cycle (whose duration is t
) is
SSE
initiated. While the SubSector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed SubSector Erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A SubSector Erase (SSE) instruction applied to a subsector that contains a page that is
Hardware or software Protected is not executed.
Any SubSector Erase (SSE) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
If Reset (Reset) is driven Low while a SubSector Erase (SSE) cycle is in progress, the
SubSector Erase cycle is interrupted and data may not be erased correctly (see Table 14:
Device status after a Reset Low pulse). On Reset going Low, the device enters the Reset
mode and a time of t
is then required before the device can be re-selected by driving
RHSL
Chip Select (S) Low. For the value of t
see Table 24: Timings after a Reset Low pulse in
RHSL
Section 11: DC and AC parameters.
Figure 20. SubSector Erase (SSE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
2
0
1
23 22
MSB
AI12356
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
39/60
Instructions
M25PE20, M25PE10
6.14
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address Bytes on Serial Data Input (D). Any address inside the
Sector (see Table 5 or Table 6) is a valid address for the Sector Erase (SE) instruction. Chip
Select (S) must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 21.
Chip Select (S) must be driven High after the eighth bit of the last address Byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t ) is
SE
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is complete, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a sector that contains a page that is Hardware
Protected is not executed.
Any Sector Erase (SE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 21. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751D
1. Address bits A23 to A18 are Don’t Care in the M25PE20. Address bits A23 to A17 are Don’t Care in the
M25PE10.
40/60
M25PE20, M25PE10
Instructions
6.15
Bulk Erase (BE)
Note:
The Bulk Erase (BE) instruction is decoded only in the T9HX process (see Important note
on page 6).
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 22.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is t ) is initiated. While the
BE
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
Any Bulk Erase (BE) instruction, while an Erase, Program or Write cycle is in progress, is
rejected without having any effects on the cycle that is in progress. A Bulk Erase (BE)
instruction is ignored if at least one sector or subsector is write-protected (Hardware or
Software protection).
If Reset (Reset) is driven Low while a Bulk Erase (BE) cycle is in progress, the Bulk Erase
cycle is interrupted and data may not be erased correctly (see Table 14: Device status after
a Reset Low pulse). On Reset going Low, the device enters the Reset mode and a time of
t
is then required before the device can be re-selected by driving Chip Select (S) Low.
RHSL
For the value of t
see Table 24: Timings after a Reset Low pulse in Section 11: DC and
RHSL
AC parameters.
Figure 22. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Instruction
AI03752D
41/60
Instructions
M25PE20, M25PE10
6.16
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from I
to
CC1
I
, as specified in Table 19).
CC2
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. This releases the device from
this mode.
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data Input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 23.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t before the supply current is reduced
DP
to I
and the Deep Power-down mode is entered.
CC2
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 23. Deep Power-down (DP) instruction sequence
S
t
DP
0
1
2
3
4
5
6
7
C
D
Instruction
Standby Power Mode
Deep Power-down Mode
AI03753D
42/60
M25PE20, M25PE10
Instructions
6.17
Release from Deep Power-down (RDP)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down (RDP) instruction. Executing this instruction
takes the device out of the Deep Power-down mode.
The Release from Deep Power-down (RDP) instruction is entered by driving Chip Select (S)
Low, followed by the instruction code on Serial Data Input (D). Chip Select (S) must be
driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 24.
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select
(S) High. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is driven
Low, cause the instruction to be rejected, and not executed.
After Chip Select (S) has been driven High, followed by a delay, t
, the device is put in
RDP
Standby Power mode. Chip Select (S) must remain High at least until this period is over. The
device waits to be selected, so that it can receive, decode and execute instructions.
Any Release from Deep Power-down (RDP) instruction, while an Erase, Program or Write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 24. Release from Deep Power-down (RDP) instruction sequence
S
t
RDP
0
1
2
3
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode
Standby Power Mode
AI06807
43/60
Power-up and power-down
M25PE20, M25PE10
7
Power-up and power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V ) until V reaches the correct value:
CC
CC
■
■
V
V
(min) at Power-up, and then for a further delay of t
at Power-down
CC
SS
VSL
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V is less
CC
than the Power On Reset (POR) threshold value, V – all operations are disabled, and the
WI
device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Write (PW), Page Program
(PP), Page Erase (PE) and Sector Erase (SE) instructions until a time delay of t
has
PUW
elapsed after the moment that V rises above the V threshold. However, the correct
CC
WI
operation of the device is not guaranteed if, by this time, V is still below V (min). No
CC
CC
Write, Program or Erase instructions should be sent until the later of:
■
■
t
t
after V passed the V threshold
CC WI
PUW
VSL
after V passed the V (min) level
CC
CC
These values are specified in Table 13.
If the delay, t
, has elapsed, after V has risen above V (min), the device can be
VSL
CC
CC
selected for READ instructions even if the t
delay is not yet fully elapsed.
PUW
As an extra protection, the Reset (Reset) signal could be driven Low for the whole duration
of the Power-up and Power-down phases.
At Power-up, the device is in the following state:
■
■
■
■
The device is in the Standby Power mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset
The Lock Registers are reset (Write Lock bit, Lock Down bit) = (0, 0)
Normal precautions must be taken for supply rail decoupling, to stabilize the VCC supply.
Each device in a system should have the VCC rail decoupled by a suitable capacitor close to
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when VCC drops from the operating voltage, to below the Power On Reset
(POR) threshold voltage, VWI, all operations are disabled and the device does not respond
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
44/60
M25PE20, M25PE10
Power-up and power-down
Figure 25. Power-up timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
Table 13. Power-up timing and V threshold
WI
Symbol
Parameter
Min.
Max.
Unit
(1)
tVSL
VCC(min) to S low
30
1
µs
ms
V
(1)
tPUW
Time delay before the first Write, Program or Erase instruction
Write Inhibit Voltage
10
(1)
VWI
1.5
2.5
1. These parameters are characterized only, over the temperature range –40°C to +85°C.
45/60
Reset
M25PE20, M25PE10
8
Reset
Driving Reset (Reset) Low while an internal operation is in progress will affect this operation
(write, program or erase cycle) and data may be lost.
All the Lock bits are reset to 0 after a Reset Low pulse.
Table 14 shows the status of the device after a Reset Low pulse.
Table 14. Device status after a Reset Low pulse
Conditions:
Reset pulse occurred
Internal logic
status
Lock bits status
Addressed data
While decoding an instruction(1): WREN,
WRDI, RDID, RDSR, READ, RDLR,
Fast_Read, WRLR, PW, PP, PE, SE, BE,
SSE, DP, RDP
Reset to 0
Same as POR
Not significant
Under completion of an Erase or Program
cycle of a PW, PP, PE, SSE, SE, BE
operation
Equivalent to
POR
Addressed data
could be modified
Reset to 0
Equivalent to Write is correctly
Under completion of a WRSR operation
Reset to 0
Reset to 0
POR (after tW)
completed
Device deselected (S High) and in Standby
mode
Same as POR
Not significant
1. S remains Low while Reset is Low.
46/60
M25PE20, M25PE10
Initial delivery state
9
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each Byte
contains FFh). All usable Status Register bits are 0.
10
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 15. Absolute maximum ratings
Symbol
Parameter
Min.
Max.
Unit
TSTG
TLEAD
VIO
Storage Temperature
–65
150
°C
°C
V
Lead Temperature during Soldering
Input and Output Voltage (with respect to Ground)
Supply Voltage
See note (1)
–0.6
–0.6
VCC + 0.6
4.0
VCC
V
VESD
Electrostatic Discharge Voltage (Human Body model)(2) –2000
2000
V
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST ECOPACK®
7191395 specification, and the European directive on Restrictions on Hazardous Substances (RoHS)
2002/95/EU.
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω)
47/60
DC and AC parameters
M25PE20, M25PE10
11
DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the devices. The parameters in the DC and AC Characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 16. Operating conditions
Symbol
Parameter
Min.
Max.
Unit
VCC
TA
Supply Voltage
Ambient Operating Temperature
2.7
3.6
85
V
–40
°C
Table 17. AC measurement conditions
Symbol
Parameter
Load Capacitance
Min.
Max.
Unit
CL
30
pF
ns
V
Input Rise and Fall Times
5
Input Pulse Voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
Input and Output Timing Reference Voltages
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 26. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
0.3V
CC
CC
0.2V
CC
AI00825B
(1)
Table 18. Capacitance
Symbol
Parameter
Test condition
Min.
Max.
Unit
COUT
CIN
Output Capacitance (Q)
VOUT = 0V
VIN = 0V
8
6
pF
pF
Input Capacitance (other pins)
1. Sampled only, not 100% tested, at TA=25°C and a frequency of 20MHz.
48/60
M25PE20, M25PE10
DC and AC parameters
Table 19. DC characteristics
Test condition (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 16)
ILI
Input Leakage Current
Output Leakage Current
± 2
± 2
µA
µA
ILO
Standby Current
(Standby and Reset
modes)
ICC1
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
50
µA
µA
Deep Power-down
Current
ICC2
10
6
C = 0.1VCC / 0.9.VCC at 25 MHz,
Q = open
Operating Current
(FAST_READ)
ICC3
mA
C = 0.1VCC / 0.9.VCC at 33 MHz,
Q = open
8
ICC4
ICC5
VIL
Operating Current (PW)
Operating Current (SE)
Input Low Voltage
S = VCC
S = VCC
15
15
mA
mA
V
– 0.5
0.3VCC
VIH
Input High Voltage
0.7VCC VCC+0.4
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 1.6 mA
0.4
V
IOH = –100 µA
VCC–0.2
V
49/60
DC and AC parameters
M25PE20, M25PE10
Table 20. AC characteristics (25 MHz operation)
Test conditions specified in Table 16 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following
instructions: FAST_READ, PW, PP, PE,
SE, DP, RDP, WREN, WRDI, RDSR
fC
fR
fC
D.C.
25
20
MHz
Clock Frequency for READ instructions
Clock High Time
D.C.
18
18
0.1
10
10
5
MHz
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
(1)
tCH
tCLH
tCLL
(1)
tCL
Clock Low Time
Clock Slew Rate (2)(peak to peak)
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tCSS
tDSU
tDH
Data In Hold Time
5
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
10
10
200
tCSH
tDIS
tV
(2)
tSHQZ
Output Disable Time
15
15
tCLQV
tCLQX
tTHSL
tSHTL
Clock Low to Output Valid
Output Hold Time
tHO
0
Top Sector Lock Setup Time
Top Sector Lock Hold Time
S to Deep Power-down
50
100
(2)
tDP
3
(2)
tRDP
S High to Standby Power Mode
Page Write Cycle Time (256 Bytes)
30
µs
11
(3)
tPW
25
5
ms
ms
10.2 +
n*0.8/256
Page Write Cycle Time (n Bytes)
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
1.2
(3)
tPP
0.4 +
n*0.8/256
tPE
tSE
Page Erase Cycle Time
Sector Erase Cycle Time
10
1
20
5
ms
s
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one
sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
50/60
M25PE20, M25PE10
DC and AC parameters
Table 21. AC characteristics (33 MHz operation)
33MHz only available for products marked since week 40 of 2005(1)Test conditions specified
in Table 16 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following
instructions: FAST_READ, PW, PP, PE,
SE, DP, RDP, WREN, WRDI, RDSR
fC
fR
fC
D.C.
33
20
MHz
Clock Frequency for READ instructions
Clock High Time
D.C.
13
13
0.1
10
10
3
MHz
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
(2)
tCH
tCLH
tCLL
(2)
tCL
Clock Low Time
Clock Slew Rate (3) (peak to peak)
S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
Data In Setup Time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tCSS
tDSU
tDH
Data In Hold Time
5
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
S Deselect Time
5
5
tCSH
tDIS
tV
200
(3)
tSHQZ
Output Disable Time
12
12
tCLQV
tCLQX
tTHSL
tSHTL
Clock Low to Output Valid
Output Hold Time
tHO
0
Top Sector Lock Setup Time
Top Sector Lock Hold Time
S to Deep Power-down
50
100
(3)
tDP
3
(3)
tRDP
S High to Standby Power mode
Page Write Cycle Time (256 Bytes)
30
µs
11
(4)
tPW
25
5
ms
ms
10.2+
n*0.8/256
Page Write Cycle Time (n Bytes)
Page Program Cycle Time (256 Bytes)
Page Program Cycle Time (n Bytes)
1.2
(4)
tPP
0.4+
n*0.8/256
tPE
tSE
Page Erase Cycle Time
Sector Erase Cycle Time
10
1
20
5
ms
s
1. Details of how to find the date of marking are given in Application Note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC
3. Value guaranteed by characterization, not 100% tested in production.
4. When using PP and PW instructions to update consecutive Bytes, optimized timings are obtained with one
sequence including all the Bytes versus several sequences of only a few Bytes. (1 ≤n ≤256)
51/60
DC and AC parameters
M25PE20, M25PE10
(1) (2) (3)
Table 22.
AC characteristics (50 MHz operation, T9HX (0.11µm) process
Test conditions specified in Table 16 and Table 17
)
Symbol Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock Frequency for the following instructions:
FAST_READ, RDLR, PW, PP, WRLR, PE, SE,
SSE, DP, RDP, WREN, WRDI, RDSR, WRSR
fC
fR
fC
D.C.
50
33
MHz
Clock Frequency for READ instructions
D.C.
9
MHz
ns
(4)
tCH
tCLH Clock High Time
tCLL Clock Low Time
(4)
tCL
9
ns
Clock Slew Rate 2 (peak to peak)
0.1
5
V/ns
ns
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tCSS S Active Setup Time (relative to C)
S Not Active Hold Time (relative to C)
tDSU Data In Setup Time
5
ns
2
ns
tDH Data In Hold Time
5
ns
S Active Hold Time (relative to C)
S Not Active Setup Time (relative to C)
tCSH S Deselect Time
5
ns
5
ns
100
ns
(5)
tSHQZ
tCLQV
tCLQX
tDIS Output Disable Time
8
8
ns
tV
tHO Output Hold Time
Write Protect Setup Time
Clock Low to Output Valid
ns
0
ns
(6)
tWHSL
50
ns
(6)
tSHWL
Write Protect Hold Time
100
ns
(5)
tDP
tRDP
tW
S to Deep Power-down
3
µs
(5)
S High to Standby Mode
30
15
23
µs
Write Status Register Cycle Time
Page Write Cycle Time (256 bytes)
Page Program Cycle Time (256 bytes)
Page Program Cycle Time (n bytes)
Page Erase Cycle Time
3
ms
ms
(7)
tPW
11
0.8
(7)
tPP
3
ms
int(n/8) × 0.025(8)
tPE
10
1
20
5
ms
s
tSE
tSSE
tBE
Sector Erase Cycle Time
SubSector Erase Cycle Time
Bulk Erase Cycle Time
40
4.5
150
10
ms
s
1. See Important note on page 6.
2. Preliminary data.
3. Details of how to find the Technology Process in the marking are given in AN1995, see also Section 13: Part numbering.
4. tCH + tCL must be greater than or equal to 1/ fC
5. Value guaranteed by characterization, not 100% tested in production.
6. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
7. When using PP and PW instructions to update consecutive bytes, optimized timings are obtained with one sequence
including all the bytes versus several sequences of only a few bytes (1 ≤n ≤256).
8. int(A) corresponds to the upper integer part of A. E.g. int(12/8) = 2, int(32/8) = 4 int(15.3) =16.
52/60
M25PE20, M25PE10
DC and AC parameters
Figure 27. Serial input timing
tSHSL
tSHCH
tCHCL
S
tCHSL
tSLCH
tCHSH
C
tDVCH
tCHDX
tCLCH
MSB IN
LSB IN
D
High Impedance
Q
AI01447C
Figure 28. Top Sector Lock (T7X process) or Write Protect (T9HX process) setup and hold
timing
TSL or
W
tTHSL
tSHTL
tWHSL
tSHWL
S
C
D
Q
High Impedance
AI3559
1. For the differences between devices produced in the two processes, see Important note on page 6.
53/60
DC and AC parameters
M25PE20, M25PE10
Figure 29. Output timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB OUT
Q
D
tQLQH
tQHQL
ADDR.LSB IN
AI01449e
54/60
M25PE20, M25PE10
DC and AC parameters
Table 23. Reset conditions
Test conditions specified in Table 16 and Table 17
Symbol
Alt.
tRST Reset Pulse Width
Chip Select High to Reset Chip should have been deselected
Parameter
Conditions
Min. Typ. Max. Unit
(1)
tRLRH
10
10
µs
ns
tSHRH
High before Reset is de-asserted
1. Value guaranteed by characterization, not 100% tested in production.
(1)(2)
Table 24. Timings after a Reset Low pulse
Test conditions specified in Table 16 and Table 17
Conditions:
Reset pulse occurred
Symbol Alt.
Parameter
Max.
Unit
While decoding an instruction(3): WREN, WRDI, RDID,
RDSR, READ, RDLR, Fast_Read, WRLR, PW, PP, PE,
SE, BE, SSE, DP, RDP
30
µs
Under completion of an Erase or Program cycle of a
PW, PP, PE, SE, BE operation
300
3
µs
Reset Recovery
Time
tRHSL tREC
Under completion of an Erase cycle of an SSE
operation
ms
tW (see
Table 22)
Under completion of a WRSR operation
ms
µs
Device deselected (S High) and in Standby mode
0
1. All the values are guaranteed by characterization, and not 100% tested in production.
2. See Table 14 for a description of the device status after a Reset Low pulse.
3. S remains Low while Reset is Low.
Figure 30. Reset AC waveforms
S
tSHRH
tRHSL
tRLRH
Reset
AI06808
55/60
Package mechanical
M25PE20, M25PE10
12
Package mechanical
Figure 31. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
Table 25. SO8N – 8 lead Plastic Small Outline, 150 mils body width, package
mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.75
0.25
0.069
0.010
0.10
1.25
0.28
0.17
0.004
0.049
0.011
0.007
0.48
0.23
0.10
5.00
6.20
4.00
–
0.019
0.009
0.004
0.197
0.244
0.157
–
c
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.193
0.236
0.154
0.050
0.189
0.228
0.150
–
E
E1
e
h
0.25
0°
0.50
8°
0.010
0°
0.020
8°
k
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
56/60
M25PE20, M25PE10
Package mechanical
Figure 32. VFQFPN8 (MLP8), 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package outline
A
D
aaa C A
R1
D1
B
E
E1
E2
A2
e
b
2x
0.10 C
B
D2
0.10 C
A
θ
L
ddd
C
A
A1 A3
70-ME
1. Drawing is not to scale.
Table 26. VFQFPN8 (MLP8), 8-lead Very thin Fine Pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
A3
b
0.85
0.80
0.00
1.00
0.05
0.0335
0.0315
0.0000
0.0394
0.0020
0.65
0.20
0.40
6.00
5.75
3.40
5.00
4.75
4.00
1.27
0.10
0.60
0.0256
0.0079
0.0157
0.2362
0.2264
0.1339
0.1969
0.1870
0.1575
0.0500
0.0039
0.0236
0.35
3.20
0.48
3.60
0.0138
0.1260
0.0189
0.1417
D
D1
D2
E
E1
E2
e
3.80
–
4.30
–
0.1496
–
0.1693
–
R1
L
0.00
0.50
0.0000
0.0197
0.75
12°
0.0295
12°
Θ
aaa
bbb
ddd
0.15
0.10
0.05
0.0059
0.0039
0.0020
57/60
Part numbering
M25PE20, M25PE10
13
Part numbering
Table 27. Ordering information scheme
Example:
M25PE20
–
V MN 6 T G
Device Type
M25PE = Page-Erasable Serial Flash memory
Device Function
10 = 1 Mbit (128K x 8)
20 = 2 Mbit (256K x 8)
Operating Voltage
V = VCC = 2.7 V to 3.6 V
Package
MN = SO8N (150 mil width)
MP = VFQFPN8 6 × 5 mm (MLP8)(1)
Device Grade
6 = Industrial: device tested with standard test flow over –40 to 85 °C
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
P or G = ECOPACK® (RoHS compliant)
1. Package only available for products in the T9HX process.
Note:
For a list of available options (speed, package, etc.), for further information on any aspect of
this device or when ordering parts operating at 50 MHz (0.11 µm, process digit ‘4’), please
contact your nearest ST Sales Office.
The category of second Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
58/60
M25PE20, M25PE10
Revision history
14
Revision history
Table 28. Document revision history
Date
Version
Changes
07-Dec-2004
0.1
Document written
Notes 1 and 2 removed from Table 27: Ordering information scheme.
S08N silhouette corrected on page 1.
21-Dec-2004
6-Oct-2005
0.2
1.0
Added <Blue>Table 21., AC characteristics (33 MHz operation).
Document status promoted to full Datasheet. An easy way to modify
data, A fast way to modify data, Page Write (PW) and Page Program
(PP) sections updated to explain optimal use of Page Write and Page
Program instructions. Clock slew rate changed from 0.03 to 0.1 V/ns.
Updated <Blue>Table 27., Ordering information scheme. Added
Ecopack® information.
Document converted to the new ST template.
MLP package removed, SO8N package specifications updated (see
10-Jul-2006
2
Section 12: Package mechanical).
Figure 5: SPI modes supported updated and Note 2 added. Timing line
of tSHQZ moved in Figure 29.
50 MHz frequency added. VFQFPN package added (see Section 12:
Package mechanical).
The sectors are further divided up into subsectors (see Table 5:
M25PE20 memory organization and Table 6: M25PE10 memory
organization). Important note on page 6 added. Figure 4: Bus master
and memory devices on the SPI bus updated and explanatory paragraph
added. VCC supply voltage and VSS ground added. Section 4.8:
Protection modes modified. Section 8: Reset added, Reset timings table
split into Table 23: Reset conditions and Table 24: Timings after a Reset
Low pulse.
At Power-up the WIP bit is reset and the Lock Registers are reset (see
Section 7: Power-up and power-down).
VIO max changed in Table 15: Absolute maximum ratings.
25-Jan-2007
3
M25PE20 and M25PE10 products processed in T9HX process added to
datasheet:
– WP pin replaces TSL (T7X technology), see Section 2.7: Write Protect
(W) or Top Sector Lock (TSL)
– Read Lock Register (RDLR), Write to Lock Register (WRLR), Write
Status Register (WRSR), SubSector Erase (SSE) and Bulk Erase
(BE) instructions added for T9HX process
– subsector protection granularity removed in T9HX process, still exists
in T7X process
– Table 5: M25PE20 memory organization and Table 6: M25PE10
memory organization updated to show subsectors
– Status Register BP1, BP0 bits and SRWD bit added.
Small text changes.
59/60
M25PE20, M25PE10
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60/60
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