LNBK20D2_技术文档

LNBK20D2

LNB SUPPLY AND CONTROL VOLTAGE

REGULATOR (PARALLEL INTERFACE)

■

COMPLETE INTERFACE FOR TWO LNBs

REMOTE SUPPLY AND CONTROL

■

GUARANTEED 400mA OUTPUT CURRENT

LNB SELECTION AND STAND-BY

FUNCTION

■

BUILT-IN TONE OSCILLATOR FACTORY

TRIMMED AT 22KHz

FAST OSCILLATOR START-UP FACILITATES

DiSEqC ENCODING

TWO SUPPLY INPUTS FOR LOWEST

DISSIPATION

BYPASS FUNCTION FOR SLAVE

OPERATION

LNB SHORT CIRCUIT PROTECTION AND

DIAGNOSTIC

AUXILIARY MODULATION INPUT EXTENDS

FLEXIBILITY

SO-20

(MI) and the LNBA pin, thus leaving all LNB

powering and control functions to the Master

Receiver. This electronic switch is closed when

the device is powered and EN pin is LOW.

The regulator outputs can be logic controlled to be

13 or 18 V (typ.) by mean of the VSEL pin for

remote controlling of LNBs. Additionally, it is

possible to increment by 1V (typ.) the selected

voltage value to compensate the excess voltage

drop along the coaxial cable (LLC pin HIGH).

In order to reduce the power dissipation of the

device when the lowest output voltage is selected,

■

CABLE LENGTH COMPENSATION

INTERNAL OVER TEMPERATURE

PROTECTION

BACKWARD CURRENT PROTECTION

COST-EFFECTIVE VERSION OF LNBP

SERIES

■

DESCRIPTION

the regulator has two Supply Input pins V

and

CC1

Intended for analog and digital satellite receivers,

the LNBK20D2 is a monolithic linear voltage

regulator, assembled in SO-20, specifically

designed to provide the powering voltages and the

interfacing signals to the LNB downconverter

situated in the antenna via the coaxial cable. It has

the same functionality of the LNBP1X and

LNBP20 series, at a reduced output current

capability. Since most satellite receivers have two

antenna ports, the output voltage of the regulator

is available at one of two logic-selectable output

pins (LNBA, LNBB). When the IC is powered and

put in Stand-by (EN pin LOW), both regulator

outputs are disabled to allow the antenna

downconverters to be supplied/controlled by

others satellite receivers sharing the same coaxial

lines. In this occurrence the device will limit at 3

mA (max) the backward current that could flow

from LNBA and LNBB output pins to GND.

V

. They must be powered respectively at 16V

CC2

(min) and 23V (min), and an internal switch

automatically will select the suitable supply pin

according to the selected output voltage. If

adequate heatsink is provided and higher power

losses are acceptable, both supply pins can be

powered by the same 23V source without

affecting any other circuit performance.

The ENT (Tone Enable) pin activates the internal

oscillator so that the DC output is modulated by a

±0.3 V, 22KHz (typ.) square wave. This internal

oscillator is factory trimmed within a tolerance of

±2KHz, thus no further adjustments neither

external components are required.

A burst coding of the 22KHz tone can be

accomplished thanks to the fast response of the

ENT input and the prompt oscillator start-up. This

helps designers who want to implement the

DiSEqC protocols (*).

For slave operation in single dish, dual receiver

systems, the bypass function is implemented by

an electronic switch between the Master Input pin

In order to improve design flexibility and to allow

implementation of newcoming LNB remote control

standards, an analogic modulation input pin is

July 2003

1/14

LNBK20D2

available (EXTM). An appropriate DC blocking

capacitor must be used to couple the modulating

signal source to the EXTM pin. When external

modulation is not used, the relevant pin can be left

open.

IMPEDANCE. If the overload is still present, the

protection circuit will cycle again through t and

off

ton until the overload is removed. Typical t +t

on off

value is 1200ms when a 4.7µF external capacitor

is used.

Two pins are dedicated to the overcurrent

protection/monitoring: CEXT and OLF. The

overcurrent protection circuit works dynamically:

as soon as an overload is detected in either LNB

output, the output is shut-down for a time Toff

determined by the capacitor connected between

CEXT and GND. Simultaneously the OLF pin, that

is an open collector diagnostic output flag, from

HIGH IMPEDANCE state goes LOW.

This dynamic operation can greatly reduce the

power dissipation in short circuit condition, still

ensuring excellent power-on start up even with

highly capacitive loads on LNB outputs.

The device is packaged in Multiwatt15 for

thru-holes mounting and in PowerSO-20 for

surface mounting. When a limited functionality in a

smaller package matches design needs, a range

of cost-effective PowerSO-10 solutions is also

offered. All versions have built-in thermal

protection against overheating damage.

After the time has elapsed, the output is resumed

for a time t =1/15t (typ.) and OLF goes in HIGH

on

off

(*): External components are needed to comply to level 2.x and above (bidirectiona) DiSEqC bus hardware requirements. DiSEqC is a

trademark or EUTELSAT.

PIN CONFIGURATION (top view)

2/14

LNBK20D2

TABLE A: PIN CONFIGURATIONS

PIN N°

SYMBOL

NAME

FUNCTION

1

LLC

Line Length Compens.

(1V typ)

Logic control input: see truth table

2

OLF

MI

Over Load Flag

Logic output (open collector). Normally in HIGH

IMPEDANCE, goes LOW when current or thermal overload

occurs

3

4

Master Input

In stand-by mode, the voltage on MI is routed to LNBA pin.

Can be left open if bypass function is not needed

LNBB

GND

Output Port

Ground

See truth tables for voltage and port selection

5, 6, 15,

16

Circuit Ground. It is internally connected to the die frame

7, 13

8

N.C.

Not Connected

Supply Input 1

V

15V to 27V supply. It is automatically selected when

CC1

V

= 13 or 14V

OUT

9

V

Supply Input 2

Output Port

22V to 27V supply. It is automatically selected when

= 18 or 19V

CC2

V

OUT

10

LNBA

See truth table voltage and port selection. In stand-by mode

this port is powered by the MI pin via the internal Bypass

Switch

11

V

Output Voltage Selection: Logic control input: see truth table

13 or 18V (typ)

SEL

12

14

18

19

EN

Port Enable

Port Selection

Logic control input: see truth table

OSEL

ENT

22KHz Tone Enable

External Capacitor

CEXT

Timing Capacitor used by the Dynamic Overload protection.

Typical application is 4.7µF for a 1200ms cycle

20

EXTM

External Modulator

External Modulation Input. Needs DC decoupling to the AC

source. if not used, can be left open.

NOTE: the limited pin availability of the PowerSO-10 package leads to drop some functions.

ABSOLUTE MAXIMUM RATINGS

Symbol

Parameter²

Value

Unit

V

DC Input Voltage (V

, V

, MI)

28

Internally Limited

-0.5 to 7

900

V

mA

V

I

CC1

CC2

I

Output Current (LNBA, LNBB)

O

V

Logic Input Voltage (ENT, EN OSEL, VSEL, LLC)

Bypass Switch Current

I

mA

W

SW

P

Power Dissipation at T

< 85°C

3

D

case

T

Storage Temperature Range

-40 to +150

-40 to +125

°C

stg

T

Operating Junction Temperature Range

op

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is

not implied.

THERMAL DATA

Symbol

Parameter

Thermal Resistance Junction-case

Value

Unit

R

15

°C/W

thj-case

3/14

LNBK20D2

LOGIC CONTROLS TRUTH TABLE

CONTROL I/O

PIN NAME

L

H

OUT

OLF

I

> I

or T > 150°C

I

< I

OMAX

OUT

OMAX

j

OUT

IN

ENT

EN

22KHz tone OFF

See Table Below

22KHz tone ON

See Table Below

OSEL

VSEL

LLC

V

EN

OSEL

VSEL

LLCO

LNBA

LNBB

L

X

V

- 0.4V (typ.)

Disabled

MI

H

L

H

L

13V (typ.)

18V (typ.)

14V (typ.)

19V (typ.)

Disabled

13V (typ.)

18V (typ.)

14V (typ.)

19V (typ.)

L

H

L

H

L

H

L

H

NOTE: All logic input pins have internal pull-down resistor (typ. = 250KΩ)

BLOCK DIAGRAM

4/14

LNBK20D2

ELECTRICAL CHARACTERISTICS FOR LNBK SERIES (T = 0 to 85°C, C = 0.22µF, C =0.1µF,

J

I

O

EN=H, ENT=L, LLC=L, V =16V, V =23V I

=50mA, unless otherwise specified.)

IN1

IN2

OUT

Symbol

Parameter

Test Conditions

Min.

15

Typ.

Max.

Unit

V

Supply Voltage

I

= 400 mA ENT=H, VSEL=L, LLC=L

= 400 mA ENT=H, VSEL=L, LLC=H

= 400 mA ENT=H, VSEL=L, LLC=L

= 400 mA VSEL=L, LLC=H

27

IN1

IN2

CC1

CC2

O

16

V

22

27

V

23

27

V

Output Voltage

Line Regulation

Load Regulation

= 400 mA VSEL=L, LLC=L

17.3

18

19

13

14

5

18.7

V

O1

O2

= 400 mA ENT=H, VSEL=L, LLC=H

= 400 mA VSEL=L, LLC=L

V

12.5

13.5

V

= 400 mA ENT=H, VSEL=L, LLC=H

V

∆V

V

=15 to 18V

=22 to 25V

V

=13V

50

mV

O

IN1

IN2

IN1

OUT

=18V

5

=V =22V

=13 or 18V

65

150

IN2

I

= 0 to 3A

O

SVR Supply Voltage Rejection

V

= V

= 23 ± 0.5V f = 120 Hz,

ac ac

45

dB

mA

ms

IN1

IN2

I

Output Current Limiting

500

650

1100

800

MAX

t

Dynamic Overload

Output Shorted

C

=4.7µF

OFF

EXT

protection OFF Time

t

Dynamic Overload

protection ON Time

=4.7µF

t

/15

ms

ON

EXT

OFF

f

Tone Frequency

ENT=H

20

0.55

40

22

24

0.9

60

15

KHz

Vpp

%

TONE

A

Tone Amplitude

0.72

50

10

5

TONE

D

Tone Duty Cycle

TONE

t , t

Tone Rise and Fall Time

External Modulation Gain

5

µs

r

f

G

V

∆V

/∆V ,

EXTM

f = 10Hz to 40KHz

EXTM

OUT

External Modulation Input

Voltage

AC Coupling

f = 10Hz to 40KHz

EN=L, =300mA,

=8mA

400

mVpp

Ω

Z

External Modulation

Impedance

400

0.35

0.28

EXTM

V

Bypass Switch Voltage

Drop (MI to LNBA)

I

V

-V =4V

0.6

0.5

10

V

SW

CC2 MI

V

Overload Flag Pin Logic

LOW

I

V

OL

OZ

OL

I

Overload Flag Pin OFF

State Leakage Current

V

= 6V

µA

V

OH

V

Control Input Pin Logic

LOW

0.8

IL

IH

V

Control Input Pin Logic

HIGH

2.5

V

I

Control Pins Input Current

Supply Current

V

= 5V

20

µA

IH

I

Output Disabled (EN=L)

0.3

3.1

1

6

mA

CC

ENT=H,

I

=500mA

OUT

I

Output Backward Current

EN=L

V

= V

= 18V

0.2

3

mA

OBK

LNBA

LNBB

V

= V

= 22V or floating

IN1

IN2

T

Temperature Shutdown

Threshold

150

°C

SHDN

5/14

LNBK20D2

TYPICAL CHARACTERISTICS (unless otherwise specified T = 25°C)

j

Figure 1 : Output Voltage vs Output Current

Figure 2 : Tone Duty Cycle vs Temperature

Figure 3 : Tone Fall Time vs Temperature

Figure 4 : Tone Frequency vs Temperature

Figure 5 : Tone Rise Time vs Temperature

Figure 6 : Tone Amplitude vs Temperature

6/14

LNBK20D2

Figure 7 : S.V.R. vs Frequency

Figure 10 : LNBA External Modulation gain vs

Frequency

Figure 8 : External Modulation vs Temperature

Figure 11 : Bypass switch Drop vs Output

Current

Figure 9 : Bypass Switch Drop vs Output Current

Figure 12 : overload Flag pin Logic LOW vs Flag

Current

7/14

LNBK20D2

Figure 13 : Supply Voltage vs Temperature

Figure 16 : Tone Enable

Figure 17 : Tone Disable

Figure 18 : 22KHz Tone

Figure 14 : Supply Current vs Temperature

Figure 15 : Dynamic Overload protection (I vs

SC

Time)

8/14

LNBK20D2

Figure 19 : Enable Time

Figure 21 : 18V to 13V Change

Figure 20 : Disable Time

Figure 22 : 18V to 13V Change

TYPICAL APPLICATION SCHEMATICS

TWO ANTENNA PORTS RECEIVER

MCU+V

10uF

17V

24V

ANT CONNECTORS

C2

11

1

2

AUX DATA

EXTM

OLF

VCC1

VCC2

R1

JA

JB

3

15

14

LNBA

LNBB

MI

47K

13

TUNER

4

9

5

7

12

10

VSEL

ENT

EN

OSEL

LLC

CEXT

C1

4.7µF

C3 C4 C5 C6

+

8

GND

2x 47nF

2x 0.1µF

LNBK20

Vcc

I/Os

MCU

9/14

LNBK20D2

SINGLE ANTENNA RECEIVER WITH MASTER RECEIVER PORT

17V

24V

MCU+V

10uF

C2

1

2

11

13

AUX DATA

EXTM

OLF

VCC1

VCC2

R1

ANT

3

15

14

LNBA

LNBB

MI

47K

MASTER

10

4

9

5

7

12

TUNER

VSEL

ENT

EN

OSEL

LLC

CEXT

4.7µF

C1

C3 C4 C5

+

47nF

8

GND

2x 0.1µF

LNBK20

Vcc

I/Os

MCU

USING SERIAL BUS TO SAVE MPU I/Os

17V

24V

MCU+V

ANT

CONNECTORS

C2

R1

11

13

1

2

AUX DATA

EXTM

VCC1

VCC2

47K

JA

10uF

3

15

14

LNBA

LNBB

MI

OLF

JB

TUNER

1

2

3

15

4

5

6

4

9

5

7

12

10

VSEL

STR

D

CLK

OE

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

CEXT

ENT

EN

OSEL

LLC

4.7µF

C1

C3 C4 C5 C6

2x 0.1µF 2x 47nF

+

7

14

13

12

11

8

GND

LNBK20

9

10

QS

4094

SERIAL

BUS

MCU+V

I/Os

Vcc

MCU

10/14

LNBK20D2

THERMAL DESIGN NOTE

During normal operation, this device dissipates some power. At maximum rated output current (400mA),

the voltage drop on the linear regulator lead to a total dissipated power that is of about 2W. The heat

generated requires a suitable heatsink to keep the junction temperature below the over temperature

protection threshold. Assuming a 40°C temperature inside the Set-Top-Box case, the total Rthj-amb has

to be less than 43°C/W.

While this can be easily achieved using a through-hole power package that can be attached to a small

heatsink or to the metallic frame of the receiver, a surface mount power package must rely on PCB

solutions whose thermal efficiency is often limited. The simplest solution is to use a large, continuous

copper area of the GND layer to dissipate the heat coming from the IC body.

The SO-20 package of this IC has 4 GND pins that are not just intended for electrical GND connection, but

also to provide a low thermal resistance path between the silicon chip and the PCB heatsink. Given an

Rthj-c equal to 15°C/W, a maximum of 28°C/W are left to the PCB heatsink. This figure is achieved if a

2

minimum of 25cm copper area is placed just below the IC body. This area can be the inner GND layer of

a multi-layer PCB, or, in a dual layer PCB, an unbroken GND area even on the opposite side where the

IC is placed. In both cases, the thermal path between the IC GND pins and the dissipating copper area

must exhibit a low thermal resistance.

In figure 4, it is shown a suggested layout for the SO-20 package with a dual layer PCB, where the IC

Ground pins and the square dissipating area are thermally connected through 32 vias holes, filled by

solder. This arrangement, when L=50mm, achieves an Rthc-a of about 28°C/W.

Different layouts are possible, too. Basic principles, however, suggest to keep the IC and its ground pins

approximately in the middle of the dissipating area; to provide as many vias as possible; to design a

dissipating area having a shape as square as possible and not interrupted by other copper traces.

SO-20 SUGGESTED PCB HEATSINK LAYOUT

11/14

LNBK20D2

SO-20 MECHANICAL DATA

mm.

inch

TYP.

DIM.

MIN.

TYP

MAX.

2.65

0.2

MIN.

MAX.

0.104

0.008

0.096

0.019

0.012

A

a1

a2

b

0.1

0.004

2.45

0.49

0.32

0.35

0.23

0.014

0.009

b1

C

0.5

0.020

c1

D

45˚ (typ.)

12.60

10.00

13.00

10.65

0.496

0.393

0.512

0.419

E

e

1.27

0.050

0.450

e3

F

11.43

7.40

0.50

7.60

1.27

0.75

0.291

0.020

0.300

0.050

0.029

L

M

S

˚ (max.)

8

PO13L

12/14

LNBK20D2

Tape & Reel SO-20 MECHANICAL DATA

mm.

TYP

inch

TYP.

DIM.

MIN.

MAX.

330

MIN.

MAX.

12.992

0.519

A

C

12.8

20.2

60

13.2

0.504

0.795

2.362

D

N

T

30.4

11

1.197

0.433

0.528

0.130

0.161

0.476

Ao

Bo

Ko

Po

P

10.8

13.2

3.1

0.425

0.520

0.122

0.153

0.468

13.4

3.3

3.9

4.1

11.9

12.1

13/14

LNBK20D2

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the

consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from

its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications

mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information

previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or

systems without express written approval of STMicroelectronics.

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco

Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.

14/14


型号：	LNBK20D2
厂家：	ST
描述：	LNB SUPPLY AND CONTROL VOLTAGE REGULATOR (PARALLEL INTERFACE) LNB电源和控制稳压器（并行接口）稳压器模拟IC 信号电路光电二极管
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LNBK20D2 [STMICROELECTRONICS]

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