L6935 [STMICROELECTRONICS]
High performance 3 A ULDO linear regulator; 高性能3一ULDO线性稳压器
| 型号： | L6935 |
| 厂家： | 
ST |
| 描述： | High performance 3 A ULDO linear regulator |
| 文件： | 总20页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6935
High performance 3 A ULDO linear regulator
Features
■ Up to 5 V input voltage range
■ 60 mΩ max R
DS(on)
■ 35 µA shut-down current
■ 3 A maximum output current
■ Split bias and power supplies
VFQFPN20
(4.0 x 4.0 x 1.0 mm)
■ Adjustable output voltage: 0.5 V to 3.0 V
■ Excellent load and line regulation: 1 %
Description
accuracy (over temperature)
L6935 is an ultra low drop output linear regulator
operating up to 5 V input and is able to support
output current up to 3 A. Designed with an
■ MLCC supported
■ Programmable soft-start
■ Short-circuit protection
■ 3.5 A overcurrent protection
■ Thermal shut-down
internal low-R
N-channel MOSFET, it can
DS(on)
be used for on-board DC-DC conversions saving
in real estate, list of components and power
dissipation.
■ VFQFPN20 4 x 4 x 1.0 mm package
Bias input and power input are split to allow linear
conversion from buses lower than 1.2 V
minimizing power losses.
L6935 provides the application with an adjustable
voltage from 0.5 V to 3.0 V with a voltage
regulation accuracy of 1 %. soft-start is available
to program the output voltage rise-time according
to the external capacitor connected.
Applications
■ Motherboard
■ Mobile PC
■ Hand-held instruments
■ PCMCIA cards
Enable and Power Good functions make L6935
suitable for complex systems and programmable
start-up sequencing.
■ Processors I/O
The current limit at 3 A protects the system during
a short circuit. The current is sensed in the power
DMOS in order to limit the power dissipation.
Thermal shut down limits the internal temperature
at 150 °C with a hysteresis of 20 °C.
■ Chipset and RAM supply
Table 1.
Device summary
Order codes
Package
Packing
Tube
L6935
VFQFPN20
Rev 1
L6935TR
Tape and reel
May 2008
1/20
www.st.com
20
Contents
L6935
Contents
1
Typical application circuit and block diagram . . . . . . . . . . . . . . . . . . . . 3
1.1
1.2
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
3
Pins description and connection diagrams . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1
3.2
3.3
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4
5
Typical performances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Device description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.1
5.2
5.3
5.4
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
VIN vs VBIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4.1
5.4.2
Over-current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
Components selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1.1
6.1.2
Input capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.2
VIN, VBIAS and sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7
8
9
Demonstration board description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
VFQFPN20 mechanical data and package dimensions . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2/20
Typical application circuit and block diagram
L6935
1
Typical application circuit and block diagram
1.1
Application circuit
Figure 1.
Typical application circuit - VIN = VBIAS
V
IN
V
OUT = 0.5V to 3.0V
VBIAS
VIN
EN
VOUT
ADJ
R1
R2
EN
CIN
L6935
COUT
SS GND PAD PGOOD
CSS
PGOOD
L6935 Reference Schematic
Figure 2.
Typical application circuit - VIN ≠ VBIAS
VBIAS
V
IN = 0.75V to VBIAS
V
OUT > 0.5V (*)
VBIAS
VIN
EN
VOUT
ADJ
R1
R2
EN
L6935
COUT
CIN
SS GND PAD PGOOD
CSS
PGOOD
L6935 Reference Schematic
(*) Vin may decrease until the minimum drop is reached. Conversely, Vout can rise untile the minimum drop is reached.
3/20
Typical application circuit and block diagram
L6935
1.2
Block diagram
Figure 3.
Block diagram
VIN
CHARGE
PUMP
VBIAS
CURRENT
LIMIT
VREF
+
-
REFERENCE
0.500V
SS
ERROR
AMPLIFIER
DRIVER
VOUT
ADJ
THERMAL
SENSOR
EN
ENABLE
PGOOD
+
0.9 VREF
-
GND
4/20
Pins description and connection diagrams
L6935
2
Pins description and connection diagrams
Figure 4. Pins connection (top view)
10
11
9
8
7
6
5
4
3
2
1
N.C.
N.C.
N.C.
N.C.
N.C.
PGOOD
N.C.
12
13
14
15
N.C.
L6935
GND
N.C.
16 17 18 19 20
2.1
Pin descriptions
Table 2.
Pin #
Pins descriptions
Name
Function
1
2
N.C.
GND
N.C.
Not internally connected.
Ground connection. Connect to PCB ground plane.
Not internally connected.
3, 4
Power Good output flag: the pin is open drain and it is forced low if the
output voltage is lower than 90 % of the programmed voltage. If not used, it
can be left floating.
5
6
PGOOD
VBIAS
Input bias supply. This pin supplies the internal logic to drive the power
N-channel MOSFET that realize the voltage conversion. Connect directly to
VIN or to a different supply ranging from VIN to 5 V.
The voltage connected to this pin MUST always be higher or equal that VIN.
Enables the device if a voltage higher than 1 V is applied.
When pulled low, the device is in low-power consumption: everything inside
the controller is kept OFF.
7
EN
See Section 6.2 for details about EN signal and power sequencing.
Power supply voltage. This pin is connected to the drain of the internal
N-channel MOSFET.
8 to 10
11 to15
16 to 18
VIN
N.C.
Filter to GND with capacitor larger than the one used for VOUT
.
Not internally connected.
Regulated output voltage. This pin is connected to the source of the
internal N-mos. MLCC capacitor are supported. Filter to GND with
capacitor smaller than the one used for VIN.
VOUT
5/20
Pins description and connection diagrams
L6935
Table 2.
Pin #
Pins descriptions (continued)
Name
Function
Feedback for the IC regulation.
19
ADJ
Connecting this pin through a voltage divider to VOUT, it is possible to
program the output voltage between 0.5 V and 3.0 V.
Soft-start pin. The soft-start time is programmed connecting an external
capacitor CSS from this pin to GND.
20
SS
In steady state regulation, the voltage at this pin is 3.3 V.
Ground connection. Connect to PCB GND Plane with enough VIAs to
improve thermal conductivity.
PAD
GND
6/20
Electrical specifications
L6935
3
Electrical specifications
3.1
Absolute maximum ratings
Table 3.
Symbol
VIN
VBIAS, EN, PGOOD to GND
Absolute maximum ratings
Parameter
Value
Unit
to GND
5.5
6
V
V
V
V
SS, VOUT
ADJ
to GND
to GND
-0.3 to 3.3
-0.3 to 1
Maximum withstanding voltage range test condition:
1000
V
CDF-AEC-Q100-002 “human body model”
acceptance criteria: “normal performance”
3.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Value
Unit
RthJA
TMAX
TSTG
TJ
Thermal resistance junction to ambient(1)
Maximum junction temperature
Storage temperature range
55
°C/W
°C
150
-50 to 150
-25 to 150
°C
Junction temperature range
°C
1. Measured with the component mounted on demonstration board in free air (22 x 28.5 mm - 2 layer 70 µm
copper).
7/20
Electrical specifications
L6935
3.3
Electrical characteristics
Table 5.
Electrical characteristics
(V = 5 V, V = 5 V; T = 25 °C unless otherwise specified).
IN
BIAS
A
Symbol
Parameter
Test conditions
Min
Typ
Max
Unit
Recommended operating conditions
V
IN = VBIAS
5.0
VIN
Operating supply voltage
V
VBIAS < 5 V
VBIAS rising
Iout = 0 A
VBIAS
VBIAS UVLO
Quiescent current
1.275
3
V
2.3
mA
IIN
VIN = VBIAS = 3.3 V
VIN = VBIAS = 5.0 V
25
40
Shut-down current
Voltage regulation
µA
VOUT
Output voltage
Io = 0.1 A; VIN = 3.3 V; ADJ = OUT
0.496
0.500
0.504
V
Vin = 3.30 V +/- 10 %; Io = 10 mA
Vin = 4.50 V +/- 10 %; Io = 10 mA
2.5
2.5
Line regulation
Load regulation
Ripple rejection (1)
mV
mV
dB
ADJ
Vin = 3.3 V; Io = 100 mA to 3 A
7
F = 100...120 Hz; Io = 10 mA
45
30
Vin = 3 V; ∆Vin = 2 Vpp; Vout = 1 V
RDS(on) Drain-to-source resistance Io = 3 A
60
mΩ
Enable, SS and protections
IOCP
Current limiting
Vo = 1.8 V
VADJ falling, wrt Ref.
3.15
77
3.50
10
3.85
85
A
%
%
V
Power Good threshold
PGOOD Hysteresis
Voltage low
I = -1 mA
0.4
EN
SS
Enable threshold
EN rising
1.05
V
Soft start current
Vss = 0 V
1.0
150
20
µA
°C
°C
Temperature rising (1)
Hysteresis (1)
OT
Thermal shut-down
1. Parameter guaranteed by design, not tested in production
8/20
Typical performances
L6935
4
Typical performances
Figure 5.
Output voltage and OC threshold vs junction temperature
1.0
0.8
4.0
0.6
3.8
3.6
3.4
3.2
3.0
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature [°C]
Temperature [°C]
Figure 6.
Quiescent and shutdown current vs junction temperature
4.0
40
35
3.8
3.6
3.4
3.2
5 VIN
30
25
20
15
3 VIN
10
5
0
3.0
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature [°C]
Temperature [°C]
Figure 7.
Line regulation
0.2%
0.1%
0.0%
-0.1%
-0.2%
0.2%
VBIAS = 1.4V, VOUT = 2V
VBIAS = VIN, VOUT = 0.5V
0.1%
0.0%
-0.1%
-0.2%
1.0
1.5
2.0
2.5
3.0
IN [V]
3.5
4.0
4.5
5.0
2.0
2.5
3.0
3.5
IN [V]
4.0
4.5
5.0
V
V
9/20
Typical performances
Figure 8.
L6935
Load regulation
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
-0.3%
0.3%
0.2%
0.1%
0.0%
-0.1%
-0.2%
VBIAS = VIN = 1.4V, VOUT = 0.5V
VBIAS = 1.4V, VIN = 2.6V, VOUT = 2V
-0.3%
0.0
0.0
0.5
1.0
1.5
2.0
2.5
0.5
1.0
1.5
2.0
2.5
Output Current [A]
Output Current [A]
10/20
Device description
L6935
5
Device description
5.1
Soft-start
L6935 implements a soft-start feature to smoothly charge the output filter avoiding high in-
rush currents to be required to the input power supply.
The soft-start process begins as soon as V
reaches UVLO and ENABLE is asserted.
BIAS
A constant current I = 1.0 µA is sourced through the SS pin: connecting an external
SS
capacitor (C ) to this pin a voltage ramp is implemented; the voltage ramp internally
SS
clamps the E.A. reference, resulting in a controlled slope for the output voltage. As the
voltage on C reaches the V
value the internal clamp is released.
SS
REF
In this way, the soft-start process lasts for:
VREF
= 5 ⋅ 105 ⋅ CSS[F]
-------------
TSS = CSS
⋅
ISS
where C is the external capacitor [F] and T is the soft-start time [sec.].
SS
SS
If the device is disabled (ENABLE low) and the VBIAS is still present, the SS pin is clamped
to GND for a fixed time of about 50 µs. in order to discharge the residual charge present on
C
: in this way, the device will be ready for a new SS process as ENABLE is asserted
SS
again.
Figure 9 describes a typical soft-start process.
Figure 9.
Soft start process diagram (left) and measured (right)
Vbias
>1.1V
ENABLE
>0.7V
ADJ
0.5V
Vout
Programmed Vout
Programmed Tss
~50µsec
11/20
Device description
L6935
5.2
Power Good
L6935 presents a PGOOD flag, an open drain output that is grounded during all the soft
start procedure, and is left free when V reaches 90 % of the programmed value.
OUT
An hysteresis of 10 % is also provided in order to avoid false triggering due to the noise
generated by the application. Figure 10 shows the PGOOD commutations.
Figure 10. Power good window
5.3
VIN vs VBIAS
L6935 provides the flexibility to supply the internal logic (VBIAS) with a supply different than
the power input (VIN). The aim of this feature is to provide low-drop regulation still having
the supply voltage to correctly drive the internal power mosfet so optimizing the conversion.
VIN drives only the drain of the power DMOS and it can be kept as low as possible
(V > V
+ V
), while V
drives the control section. V
must be typically
IN
OUT
DROPmin
BIAS
BIAS
higher than V .
IN
5.4
Protections
L6935 is equipped with a set of protections in order to protect both the load and the device
from electrical overstress. Each protection does not latch the device, that returns to work
properly as the perturbation disappear.
5.4.1
Over-current protection
An over current protection is provided: if the current that flows through the power DMOS is
greater than 3.5 A, the device adjust the power DMOS driving voltage in order to keep
constant the delivered current (I
PGOOD to be set low.
). Anyhow the output may drop also causing the
OUT
Figure 11 show the way the OCP intervention: as the threshold value is reached by I
, the
OUT
device forces a lower output current (~3.5 A).
12/20
Device description
Figure 11. Over-current protection
L6935
5.4.2
Thermal protection
The device constantly monitors its internal temperature. As the silicon reaches a 150 °C, the
control circuit turns off the power DMOS, and stays off until a safe temperature of
150° - 20° = 130 °C. Figure 12 shows how the over-temperature protection intervention.
Figure 12. Over-temperature protection
13/20
Application information
L6935
6
Application information
L6935 is the best choice in smart linear regulator applications, due to its own small size,
high power delivered and high regulation accuracy. Furthermore thermal shut-down and
OCP guarantee the highest reliability for each application.
V
V
V
can be separated by V
: in this way the device can regulate the output voltage even if
IN
IN
IN
BIAS
< V
, resulting in a better performance. In fact, the power dissipated decreases as
BIAS
get lower, according to the relationship P
= (V - V
) x I
.
DISS
IN
OUT
OUT
6.1
Components selection
6.1.1
Input capacitor
The choice of the input capacitor value depends on the several factor such as load transient
requirements, input source (battery or DC/DC converter) and its distance from the input
capacitor. Generally speaking, a capacitor with the lowest ESR possible should be chosen:
a value within the range [10 µF; 100 µF] can be sufficient in many cases.
6.1.2
Output capacitor
The choice of the output capacitor value basically depends on the load transient
requirement. Output capacitor must be sized according to the dynamic requests of the load.
A too small capacitor may exhibit huge voltage drop after a load transient is applied: a value
greater than 10 µF should be used.
In order to guarantee a good reliability, at least X5R type should be used as I/O capacitors.
Different kinds of input/output capacitors can be used: Table 6. shows a few tested
examples.
Table 6.
Input/output capacitor selection guide
Manufacturer
Type
I/O cap. value Rated voltage
Murata - GRM31CR61ExxxK(1)
Panasonic - ECJ3YB1AxxxM
MLCC, SMD1206, X5R
MLCC, SMD1206, X5R
10...100 µF
10...100 µF
6.3 - 25 V
10 - 25 V
SPCap - SMD7343
Panasonic - EEFFD0HxxxR
10...100 µF
4 - 8 V
28 mΩ ESR
POSCAP, SMD6032
Sanyo - 8TPE100MPC2
10...100 µF
10...100 µF
6.3 - 25 V
6.3 V
25 mΩ ESR
TDK - C3216X5R0JxxxMT
MLCC, SMD1210, X5R
1. xxx in the part numbers stands for 106 (10 µF), 226 (22 µF)... 105 (100 µF)
14/20
Application information
L6935
6.2
VIN, VBIAS and sequencing
Different configurations for VIN and VBIAS are possibleand the power sequencing must
consider the different timings in which the power suppliesbecomes available. In order to
properly drive the device internal logic, it is reccomendedto control the sequence between
EN signal and the VIN / VBIAS application: the device need to result being disabled when
VBIAS crosses the UVLO threshols. Furthermore, in case of VIN <> VBIAS, the EN signal
needs to be driven by the last-coming between the two supplies.
It is reccomended to drive the EN pin with a resistor divider connected as reported into
Figure 13 and Figure 14.
Figure 13. Recommended circuit for VBIAS = VIN
VIN
VOUT = 0.5V to 3.0V
VBIAS
VIN
VOUT
REH
R1
RPG
CIN
L6935
COUT
PGOOD
EN
SS
GND PAD ADJ
PGOOD
EN
REL
R2
(OpenDrain Toggle **)
CSS
** Drive EN with external Open-Drain Signal.
Figure 14. Reccomended circuit for VBIAS ≠ VIN
VBIAS
VIN (< VBIAS)
VBIAS
VOUT = 0.5V to 3.0V
VIN
VOUT
R1
RPG
CIN
L6935
COUT
PGOOD
GND PAD ADJ
EN
SS
PGOOD
EN
REL
R2
(OpenDrain Toggle **)
CSS
* EN Divider (REH) needs to be connected to the Last-Coming rail between VCC and VIN.
** Drive EN with external Open-Drain Signal.
15/20
Demonstration board description
L6935
7
Demonstration board description
Figure 15 and Figure 16 show the schematic and the layout of the demonstration board
designed for L6935. V and V may be different and, in this case, R4 must not be
IN
BIAS
mounted. C3 defines the Soft-Start timer, according to the relationship described in the
Section 5.1.
The value of the output divider R / R have to be designed in order to program the desired
1
2
V
value, according to the following equation:
OUT
R1
⎛
⎞
⎠
VOUT = 0.5 ⋅ 1 + ------
⎝
R2
Figure 15. Demonstration board schematic
V
BIAS
PGOOD
R
4
C
2
R5
6
16,17,18
VOUT
VBIAS
V
IN
8, 9, 10
7
VIN
EN
VOUT
R3
5
EN
L6935 PGOOD
C
6
R1
R2
19
ADJ
SS GND PAD
20
C
4
C
1
C5
2
C
3
ADJ
GND
Figure 16. Demonstration board layout
16/20
Demonstration board description
Different values for R are available in order to program the value of V
L6935
(R = 10 kΩ)
1
OUT
2
V
= 0.50 V @ R = 0 Ω
DC 1
OUT
V
= 0.75 V @ R = 5 kΩ
DC 1
OUT
V
= 1.00 V @ R = 10 kΩ
DC 1
OUT
V
= 1.25 V @ R = 15 kΩ
DC 1
OUT
V
= 1.50 V @ R = 20 kΩ
DC 1
OUT
V
= 3.00 V @ R = 50 kΩ
DC 1
OUT
Table 7.
Reference
C1, C2, c3
L6935 demonstration board bill of material
Description
Chip capacitor 100 nF - 6.3 V - X5R
C4
C5
Murata chip capacitor (GRM31CR60J226K) 1206, X5R, 6.3-25V, 22 µF
Murata chip capacitor (GRM31CR61E106K) 1206, X5R, 6.3-25V, 10 µF
Not mounted
C6
R1
Chip resistor 15 kΩ +/-0.1% - 1/16 W
Chip resistor 10 kΩ +/-0.1% - 1/16 W
Chip resistor 10 kΩ +/-5% - 1/16 W
R2
R3, R5
R4
Chip resistor 0 Ω
17/20
VFQFPN20 mechanical data and package dimensions
L6935
8
VFQFPN20 mechanical data and package dimensions
®
In order to meet environmental requirements, ST offers these devices in ECOPACK
packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 17. VFQFPN20 mechanical data and package dimensions
DIMENSIONS
mm
mils
REF.
PACKAGE AND
MIN. TYP. MAX. MIN. TYP. MAX.
PACKING INFORMATION
A
A1
A2
A3
b
0.80
0.90
0.02
0.65
0.25
0.23
4.00
2.80
1.00 31.496 35.433 39.370
0.05
1.00
0.787 1.969
25.591 39.370
Very Fine Quad Flat
Package No lead
9.843
7.087 9.055 11.811
151.57 157.48 163.39
106.30 110.24 114.17
151.57 157.48 163.39
106.30 110.24 114.17
17.717 19.685 21.654
11.811 15.748 19.685
3.150
0.18
3.85
2.70
0.30
4.15
2.90
Weight: not available
D
D2
E
4.00
2.80
0.50
0.4
3.85
2.70
4.15
2.90
0.55
0.5
E2
e
0.45
0.3
L
VFQFPN20 (4x4x1.00mm)
0.08
ddd
18/20
Revision history
L6935
9
Revision history
Table 8.
Date
20-May-2008
Document revision history
Revision
Changes
1
Initial release
19/20
L6935
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