L6983CQTR [STMICROELECTRONICS]
38 V, 3 A synchronous step-down converter with 17 μA quiescent current;
| 型号： | L6983CQTR |
| 厂家： | 
ST |
| 描述： | 38 V, 3 A synchronous step-down converter with 17 μA quiescent current |
| 文件： | 总63页 (文件大小：4968K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6983
Datasheet
38 V, 3 A synchronous step-down converter with 17 µA quiescent current
Features
•
•
•
•
•
•
•
3.5 V to 38 V operating input voltage
Output voltage from 0.85 V to VIN
3.3 V and 5 V fixed output voltage versions
3 A DC output current
17 μA operating quiescent current
Internal compensation network
QFN16 (3 x 3 mm)
Two different versions: LCM for high efficiency at light loads and LNM for noise
sensitive applications
•
•
•
•
•
•
•
2 μA shutdown current
Internal soft-start
Enable
Overvoltage protection
Output voltage sequencing
Thermal protection
200 kHz to 2.3 MHz programmable switching frequency. Stable with low ESR
capacitor
•
•
•
•
Optional spread spectrum for improved EMC
Power Good
Synchronization to external clock for LNM devices
QFN16 package
Maturity status link
Applications
L6983
•
•
•
•
•
Designed for 24 V buses industrial power systems
24 V battery powered equipment
Decentralized intelligent nodes
Sensors and always-on applications
Low noise applications
Description
The L6983 is an easy to use synchronous monolithic step-down regulator capable of
delivering up to 3 A DC to the load. The wide input voltage range makes the device
suitable for a broad range of applications. The L6983 is based on a peak current
mode architecture and is packaged in a QFN16 3x3 with internal compensation thus
minimizing design complexity and size.
The L6983 is available both in low consumption mode (LCM) and low noise mode
(LNM) versions. LCM maximizes the efficiency at light-load with controlled output
voltage ripple so the device is suitable for battery-powered applications. LNM makes
the switching frequency constant and minimizes the output voltage ripple for light
load operations, meeting the specification for low noise sensitive applications. The
L6983 allows the switching frequency to be selected in the 200 kHz - 2.3 MHz range
with optional spread spectrum for improved EMC.
DS13116 - Rev 2 - April 2020
For further information contact your local STMicroelectronics sales office.
www.st.com
L6983
The EN pin provides enable/disable function. The typical shutdown current is 2 µA
when disabled. As soon as the EN pin is pulled up, the device is enabled and the
internal 1.3 ms soft-start takes place. The L6983 features Power Good open collector
that monitors the FB voltage. Pulse-by-pulse current sensing on both power elements
implements an effective constant current protection and thermal shutdown prevents
thermal run-away.
DS13116 - Rev 2
page 2/63
L6983
Diagram
1
Diagram
Figure 1. Block diagram
DS13116 - Rev 2
page 3/63
L6983
Pin configuration
2
Pin configuration
Figure 2. Pin connection (top through view)
16
15
14
13
VIN
1
2
3
4
12
11
10
9
VIN
BOOT
AGND
VCC
VINLDO
E.P.
AGND
EN/CLKIN
5
6
7
8
Table 1. Pin description
Pin
1
Symbol
VIN
Function
DC input voltage.
2
VINLDO
AGND
DC input voltage connected to the supply rail with a simple RC filter.
Analog ground.
3
Enable pin with internal voltage divider. Pull-down/up to disable/
enable the device.
4
EN / CLKIN
In LNM versions, this pin is also used to provide an external clock
signal, which synchronizes the device.
The PGOOD open collector output is driven to low impedance when
the output voltage is out of regulation and released once the output
voltage becomes valid.
5
6
PGOOD
VBIAS
Typically connected to the regulated output voltage, an external
voltage source can be used to supply part of the analog circuitry to
reduce current consumptions at light load. Connect it to AGND if not
used.
This pin operates as VOUT or FB according to the selected part
number. In fixed output voltage versions, VOUT is the output voltage
sensing with selected internal voltage divider.
7
8
FB/VOUT
FSW
In adjustable versions, FB is output voltage sensing with eternal
voltage divider.
Connect an external resistor to program the oscillator frequency and
enable the optional dithering.
This pin supplies the embedded analog circuitry. Connect a ceramic
capacitor (≥ 1 µF) to filter internal voltage reference.
9
VCC
10
AGND
Analog ground.
Connect an external capacitor (100 nF typ.) between BOOT and SW
pins. The gate charge required to drive the internal NMOS is
refreshed during the low-side switch conduction time.
11
BOOT
DS13116 - Rev 2
page 4/63
L6983
Pin configuration
Pin
12
13
14
15
16
-
Symbol
VIN
Function
DC input voltage.
Power ground.
Switching node.
Switching node.
Power ground.
PGND
SW
SW
PGND
Exposed PAD
Exposed pad must be connected to AGND and PGND.
DS13116 - Rev 2
page 5/63
L6983
Typical application circuit
3
Typical application circuit
Figure 3. Basic application (adjustable version)
L6983
RPGOOD
CBOOT
VIN
PGOOD
BOOT
SW
VIN
RFILT
VIN
L
VINLDO
EN/CLKIN
FSW
VOUT
SW
RFBH
R FSW
C VCC
VBIAS
VOUT/FB
PGND
PGND
CIN
VCC
COUT
CFILT
AGND
AGND
RFBL
E.P.
GND
GND
Table 2. Typical application component
Symbol
Value
Description
C
IN
10 µF
Input capacitor
R
0.1 kΩ
1 µF
VINLDO filter resistor
VINLDO filter capacitor
VCC bypass capacitor
Bootstrap capacitor
Output capacitor
FILT
C
FILT
C
VCC
1 µF
C
BOOT
100 nF
40 µF
400 kΩ
82 kΩ
C
OUT
R
FBH
VOUT divider upper resistor
VOUT divider lower resistor
Output inductor
R
FBL
4.7 µH (F
= 1 MHz)
L
SW
R
1 MΩ
10 kΩ
PGOOD resistor
PGOOD
R
FSW setting resistor
FSW
DS13116 - Rev 2
page 6/63
L6983
Absolute maximum ratings
4
Absolute maximum ratings
Stressing the device above the rating listed in Section 4 Absolute maximum ratings may cause permanent
damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect device reliability.
Table 3. Absolute maximum ratings
Symbol
VIN
Parameter
Maximum pin voltage
Min.
- 0.3
Max.
Unit
V
42
0
AGND
PGND
BOOT
VCC
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
Maximum pin voltage
0
V
- 0.3
0.3
V
SW - 0.3
- 0.3
SW + 4
V
Min. (VIN + 0.3 V; 4 V)
8
V
VOUT/FB
FSW
- 0.3
V
- 0.3
VCC + 0.3
VIN + 0.3
VIN + 0.3
VIN + 0.3
VIN + 0.3
V
VBIAS
EN
- 0.3
V
- 0.3
V
PGOOD
- 0.3
V
- 0.85
- 3.8 for 0.5 ns (1)
V
SW
Maximum pin voltage
V
IHS, ILS
High-side / Low-side RMS switch current
Operating temperature range
3
A
T
J
- 40
- 65
150
150
260
°C
°C
°C
TSTG
Storage temperature range
TLEAD
Lead temperature (soldering 10 sec.)
1. Negative peak voltage during switching activities caused by parasitic layout elements.
4.1
4.2
ESD protection
Table 4. ESD performance
Symbol
Parameter
Test conditions
Value
2
Unit
kV
V
HBM
CDM
ESD
ESD protection voltage
500
Thermal characteristics
Table 5. Thermal data
Parameter
Symbol
Package Value Unit
Thermal resistance junction ambient (device soldered on the STMicroelectronics
demonstration board, please refer to Section 9 Application board)
R
th_JA
QFN16
30
°C/W
DS13116 - Rev 2
page 7/63
L6983
Electrical characteristics
5
Electrical characteristics
TJ = 25 °C, VIN = 24 V unless otherwise specified.
Table 6. Electrical characteristics
Symbol
Parameter
Test conditions
Min.
3.5
Typ.
Max.
38
Unit
V
Operating input voltage
range
V
IN
V
V
rising threshold
CC
2.3
3.3
V
IN_H
V
falling
CC UVLO
V
2.15
3.15
V
IN_L
threshold
No slope contribution
Full slope contribution
4.1
3.1
3.3
4.6
3.6
3.9
A
A
A
(1)
I
Peak current limit
PK
I
Valley current limit
Skip current limit
Reverse current limit
High-side RDSON
Low-side RDSON
Minimum off-time
Minimum on-time
4.5
VY
(1) (2)
SKIP
I
0.6
1.5
A
A
(1)
I
LNM or VOUT overvoltage
1.25
1.75
VY_SINK
R
0.130
0.085
200
Ω
DSON_HS
R
Ω
DSON_LS
T
ns
ns
OFF_MIN
T
75
ON_MIN
Enable
Rising
0.7
V
V
V
V
V
Wake-up threshold
Enable threshold
WAKE_UP
Falling
0.2
Rising
1.08
1.2
0.2
1.32
V
EN
Hysteresis
VCC regulator
V
LDO output voltage
3.0
3.3
2
3.6
3
V
CC
Power consumption
Shutdown current from
I
I
I
VEN = GND
μA
SHTDWN
V
IN
LCM device
VBIAS = GND
VBIAS = 5 V
20
1
35
60
6
μA
μA
Quiescent current from
I
Q_VIN
V
IN
3.5
Quiescent current from
VBIAS = 5 V
20
35
60
μA
Q_VBIAS
V
BIAS
LNM device
VBIAS = GND
VBIAS = 5 V
1.6
2.3
3
mA
μA
Quiescent current from
I
Q_VIN
V
IN
300
550
800
Quiescent current from
VBIAS = 5 V
1.3
1.8
2.3
mA
Q_VBIAS
V
BIAS
Soft-start
DS13116 - Rev 2
page 8/63
L6983
Electrical characteristics
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
T
Internal soft-start
1
1.3
1.6
ms
SS
Error amplifier
Adjustable version
0.845
0.842
3.27
0.85
0.85
3.3
3.3
5.0
5
0.855
0.858
3.33
V
V
V
V
V
V
T = 25 °C
J
Adjustable version
T = - 40 °C ≤ T ≤ 125 ° (4)
J
J
Fixed 3.3 V version
T = 25 °C
J
V
Voltage feedback
FB
Fixed 3.3 V version
3.284
4.955
4.93
3.346
5.045
5.07
T = -40 °C ≤ T ≤ 125 °C (4)
J
J
Fixed 5.0 V version
T = 25 °C
J
Fixed 5.0 V version
T = -40 °C ≤ T ≤ 125 °C (4)
J
J
Overvoltage protection
Overvoltage trip (VOVP/
VREF)
V
115
1
120
2
125
6
%
%
OVP
V
Overvoltage hysteresis
OVP_HYST
Synchronization (LNM versions only)
200
(3)
f
Synchronization range
2200
kHz
V
CLKIN
Amplitude of
synchronization clock
(3)
V
2.3
60
CLKIN_TH
Synchronization pulse
ON and OFF time 2.3 V
V
= 2.3 V
ns
ns
CLKIN_TH
≤ V
≤ 2.5 V
CLKIN_TH
(3)
V
CLKIN_T
Synchronization pulse
ON and OFF time
20
V
> 2.5 V
CLKIN_TH
Power Good
Adjustable output version
87
87
87
90
90
93
93
93
%
%
%
T = -40 °C ≤ T ≤ 125 °C (4)
J
J
Fixed 3.3 output version
V
PGOOD threshold
PGOOD hysteresis
THR
T = -40 °C ≤ T ≤ 125 °C (4)
J
J
Fixed 5.0 output version
90
3
T = -40 °C ≤ T ≤ 125 °C (4)
J
J
(4)
V
THR_HYST
VIN > VIN_H AND
VFB < VTH
0.4
0.8
V
V
PGOOD open collector
output
V
4 mA sinking load
PGOOD
2 < VIN < VIN_H
4 mA sinking load
DS13116 - Rev 2
page 9/63
L6983
Frequency selection table
Symbol
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Thermal shutdown
temperature
(5)
T
165
°C
SHDWN
Thermal shutdown
hysteresis
(5)
T
30
°C
HYS
1. Parameter tested in the static condition during testing phase. The parameter value may change over a dynamic application
condition.
2. LCM version.
3. LNM version.
4. Specifications in the - 40 to 125 °C temperature range are assured by characterization and statistical correlation.
5. Not tested in production.
5.1
Frequency selection table
Specification referred to - 40 ≤ TJ ≤ 125 °C and VIN = 24 V, assured by testing at TJ = 25 °C, design,
characterization and statistical correlation.
Table 7. FSW selection
Symbol
Option
RVCC (kΩ)
1.8
RGND (kΩ)
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
1.8
Min.
Typ.
200
Max.
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
0
400
3.3
500
5.6
700
Dithering (5 % F
typ.)
SW
10
1000
1500
2000
2300
200
18
33
56
FSW
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
0
360
400
440
3.3
500
5.6
630
900
700
770
No dithering
10
1000
1500
2000
2300
1100
18
33
56
2000
2600
DS13116 - Rev 2
page 10/63
L6983
Functional description
6
Functional description
The L6983 device is based on a “peak current mode" architecture with constant frequency control. Therefore, the
intersection between the error amplifier output and the sensed inductor current generates the PWM control signal
to drive the power switch.
The device features LNM (low noise mode) that is forced PWM control, or LCM (low consumption mode) to
increase the efficiency at light-load on the selected part number.
The main internal blocks shown in the block diagram in Figure 1. Block diagram and Figure 2. Pin connection (top
through view) are:
•
•
Embedded power elements
A fully integrated adjustable oscillator which is able to set eight different switching frequencies from 200 to
2300 kHz
•
•
•
•
•
The ramp for the slope compensation avoiding subharmonic instability
A transconductance error amplifier with integrated compensation network
The high-side current sense amplifier to sense the inductor current
A “Pulse Width Modulator” (PWM) comparator and the driving circuitry of the embedded power elements
The soft-start block ramps up the reference voltage on error amplifier thus decreasing the inrush current at
power-up. The EN pin inhibits the device when driven low
•
The EN/CLK pin section, which, for LNM versions, allows synchronizing the device to an external clock
generator
•
•
•
•
The pulse-by-pulse high-side / low-side switch current sensing to implement the constant current protection
A circuit to implement the thermal protection function
The OVP circuitry to discharge the output capacitor in case of overvoltage event
The switchover capability of the internal regulator to supply a portion of the quiescent current when the
VBIAS pin is connected to an external output voltage
•
Enable/ disable dithering operation
6.1
Enable
The EN pin is a digital input that turns the device on or off.
In order to maximize both the EN threshold accuracy and the current consumption, the device implements two
different thresholds:
1.
2.
The wake-up threshold, VWAKE_UP = 0.5 V (see Table 6. Electrical characteristics)
The start-up threshold, VEN = 1.2 V (see Table 6. Electrical characteristics)
The following picture shows the device behavior.
DS13116 - Rev 2
page 11/63
L6983
Soft-start
Figure 4. Power-up/down behavior
When the voltage applied on the EN pin rises over VWAKEUP, RISING, the device powers up the internal circuit thus
increasing the current consumption.
As soon as the voltage rises over the VEN, RISING, the device starts the switching activities as described on
Section 6.2 Soft-start.
Once the voltage becomes lower than VEN, FALLING, the device interrupts the switching activities.
As soon as the voltage becomes lower than VWAKEUP.FALLING, the device powers down the internal circuit
reducing the current consumption.
The pin is VIN compatible.
Please refer to Table 6. Electrical characteristics for the reported thresholds.
6.2
Soft-start
The soft-start (SS) limits the inrush current surge and makes the output voltage increase monotonically.
The device implements the soft-start phase ramping the internal reference with very small steps. Once the SS
ends the error amplifier reference is switched to the internal value of 0.85 V coming directly from the band gap
cell.
DS13116 - Rev 2
page 12/63
L6983
Undervoltage lockout
Figure 5. Soft-start procedure
During the normal operation, a new soft-start cycle takes place in case of:
1.
2.
3.
Thermal shutdown event
UVLO event
EN pin rising over VEN threshold. Please refer to Table 6. Electrical characteristics
Figure 6. Soft-start phase with IOUT = 2.5 A
6.3
Undervoltage lockout
The device implements the undervoltage lockout (UVLO) continuously sensing the voltage on the VCC pin, if the
UVLO lasts more than 10 μs, the internal logic resets the device by turning off both LS and HS.
After the reset, if the EN pin is still high, the device repeats the soft-start procedure.
DS13116 - Rev 2
page 13/63
L6983
Light-load operation
6.4
Light-load operation
The L6983 implements two different light load strategies:
1.
2.
Low consumption mode (LCM)
Low noise mode (LNM)
Please refer to Table 12. Order codes to select the part number with the preferred light load strategy.
6.4.1
Low consumption mode (LCM)
The LCM maximizes the efficiency at light load.
When the switch peak current request is lower than the ISKIP threshold (see Table 6. Electrical characteristics),
the device regulates VOUT by the skip threshold. The minimum voltage is given by:
R
+ R
PL
PH
V
= V
FB, LCM
∙
(1)
OUT, LCM
R
PL
Where VFB, LCM is 1.8% (typ.) higher than VFB
.
The device interrupts the switching activities when two conditions happen together:
1.
2.
The peak inductor current required is lower than ISKIP
The voltage on the FB pin is higher than VFB, LCM
Figure 7. Light load operation
VCOMP
VCOMP,MIN
VFB
t
VFB, LCM
VFB
t
t
VSW
IL
ISKIP
t
A new switching cycle takes place once the voltage on the FB pin becomes lower than VFB,LCM
.
The HS switch is kept on until the inductor current reaches ISKIP
.
Once the current on the HS reaches the defined value, the device turns the HS off and turns the LS on. The LS is
kept enabled until one of the following conditions occurs:
1) The inductor current sensed by the LS becomes equal to zero
2) The switching period ends up
If, at the end of the switching cycle, the voltage on the FB pin rises over the VFB,LCM threshold, the LS is kept
enabled until the inductor current becomes equal to zero. Otherwise, the device turns on again the HS and starts
a new switching pulse.
During the burst pulse, if the energy transferred to COUT increases the VFB level over the threshold defined on
Eq. (1), the device interrupts the switching activities. The new cycle takes place only when VFB becomes lower
than the defined threshold. Otherwise, as soon as the LS is turned off the HS is turned on.
Given the energy stored in the inductor during a burst, the voltage ripple depends on the capacitor value:
T
0
BURST
∫
I t dt
L
∆ Q
C
IL
V
=
=
(2)
OUT RIPPLE
C
OUT
OUT
DS13116 - Rev 2
page 14/63
L6983
Light-load operation
Figure 8. LCM operation with ISKIP = 600 mA typ. at zero load. L = 15 µH; COUT = 40 µF
Figure 9. LCM operation over loading condition (part 1-pulse skipping)
DS13116 - Rev 2
page 15/63
L6983
Light-load operation
Figure 10. LCM operation over loading condition (part 2-pulse skipping)
Figure 11. LCM operation over loading condition (part 3-pulse skipping)
DS13116 - Rev 2
page 16/63
L6983
Light-load operation
Figure 12. LCM operation over loading condition (part 4-CCM)
DS13116 - Rev 2
page 17/63
L6983
Light-load operation
6.4.2
Low noise mode (LNM)
The low noise mode implements a forced PWM operation over the different loading conditions. The LNM features
a constant switching frequency to minimize the noise in the final application and a constant voltage ripple at fixed
VIN.
The regulator in steady loading condition operates in continuous conduction mode (CCM) over the different
loading conditions.
The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output
voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). Consequently,
the output capacitor has to be selected in order to have a voltage ripple compliant with the application
requirements.
∆ I
LMAX
V
= ESR ∙ ∆ I
LMAX
+
(3)
OUT RIPPLE
8 ∙ C
∙ f
OUT SW
Usually the resistive component of the ripple can be neglected if the selected output capacitor is a multi-layer
ceramic capacitor (MLCC).
Figure 13. Low noise mode operation at zero load
DS13116 - Rev 2
page 18/63
L6983
Light-load operation
6.4.3
Efficiency for low consumption mode and low noise mode part number
Figure 14. Light-load efficiency for low consumption mode and low noise mode - linear scale, and
Figure 15. Light-load efficiency for low consumption mode and low noise mode - log scale report the efficiency
measurements to highlight the gap at the light-load between LNM and LCM part numbers. The graph reports also
exactly the same efficiency at the medium / high load.
Figure 14. Light-load efficiency for low consumption mode and low noise mode - linear scale
VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz
100
90
80
70
60
50
40
LCM
30
LNM
20
10
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 15. Light-load efficiency for low consumption mode and low noise mode - log scale
VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz
100
90
80
70
60
50
40
LCM
30
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 19/63
L6983
Light-load operation
6.4.4
Load regulation for low consumption mode and Low noise mode part number
Figure 16. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale and
Figure 17. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale report the load
regulation to highlight the gap, given by the different regulation strategy, at the light-load between LNM and LCM
part numbers. When the required IOUT is higher than the threshold defined on the Section 6.4.1 Low
consumption mode (LCM) the behavior of the different part number is exactly the same.
Figure 16. Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale
VIN = 24 V ; VOUT = 5 V; FSW = 0.4 MHz
2
LCM
1.5
LNM
1
0.5
0
-0.5
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 17. Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale
VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz
2
1.5
1
LCM
0.5
LNM
0
-0.5
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 20/63
L6983
Switch-over feature
6.5
Switch-over feature
The switch-over maximizes the efficiency at light load that is crucial for low consumption application.
Figure 18. Switch-over
No Switch-Over
Switch -Over
L6983
L6983
RPGOOD
RPGOOD
PGOOD
BOOT
SW
PGOOD
BOOT
SW
L
L
CBOOT
CBOOT
VOUT
GND
VOUT
GND
SW
SW
RFBH
RFBL
RFBH
RFBL
VBIAS
VOUT/FB
PGND
PGND
VBIAS
VOUT/FB
PGND
PGND
COUT
COUT
E.P.
E.P.
In order to minimize the regulator quiescent current sink from the input voltage, the VBIAS pin can be connected
to an external voltage source in the range of 3.0 V < VBIAS < VIN.
In case the VBIAS pin is connected to the regulated output voltage (VOUT), the total current drawn from the input
voltage is given by the following equation:
V
1
BIAS
I
= I
QOPVIN
+
∙
∙ I
QOPVBIAS
(4)
QVIN
η
V
L6983
IN
6.6
Spread spectrum
The spread spectrum is selectable by connecting the RFSW resistor to VCC (please refer to Table 7. FSW
selection). The internal dithering circuit changes the switching frequency in a range of ± 5%.
∆ F
SW
= 5% ∙ F
sw
(5)
The device updates the frequency every clock period by fixed steps:
•
•
Ramps up in 63 steps from minimum to maximum FSW
Ramps down in 63 steps from maximum to minimum FSW
The modulation shape is almost triangular with a frequency of:
F
sw
F
=
(6)
Ditℎering
126
6.7
Overvoltage protection
The overvoltage protection monitors the FB pin and enables the low-side MOSFET to discharge the output
capacitor if the output voltage is 20% (typ.) over the nominal value.
This is a second level protection and it should never be triggered in normal operating conditions if the system is
properly dimensioned. In other words, the selection of the external power components and the dynamic
performance determined by the compensation network should guarantee an output voltage regulation within the
overvoltage threshold even during the worst-case scenario in term of load transitions.
The protection is reliable and able to operate even during normal load transitions for a system whose dynamic
performance is not in line with the load dynamic request. Consequently, the output voltage regulation would be
affected.
The L6983 device implements a 1.5 A (IVY_SINK refer to Table 6. Electrical characteristics) negative current
limitation to limit the maximum reversed switch current during the overvoltage operation.
DS13116 - Rev 2
page 21/63
L6983
Overcurrent protection
6.8
Overcurrent protection
The current protection circuitry features a constant current protection, so the device limits the maximum peak
current (please refer to Table 6. Electrical characteristics) in overcurrent condition.
The L6983 device implements a pulse-by-pulse current sensing on both power elements (high-side and low-side
switches) for effective current protection over the duty cycle range. The high-side current sensing is called “peak”
the low-side sensing “valley”.
The internal noise generated during the switching activity makes the current sensing circuitry ineffective for a
minimum conduction time of the power element. This time is called “masking time” because the information from
the analog circuitry is masked by the logic to prevent an erroneous detection of the overcurrent event. Therefore,
the peak current protection is disabled for a masking time after the high-side switch is turned on. The masking
time for the valley sensing is activated after the low-side switch is turned on. In other words, the peak current
protection can be ineffective at extremely low duty cycles, the valley current protection at extremely high duty
cycles.
The L6983 device assures an effective overcurrent protection sensing the current flowing in both power elements.
In case one of the two current sensing circuitry is ineffective because of the masking time, the device is protected
sensing the current on the opposite switch. Thus, the combination of the “peak” and “valley” current limits assure
the effectiveness of the overcurrent protection even in extreme duty cycle conditions.
In case the current diverges because of the high-side masking time, the low-side power element is turned on until
the switch current level drops below the valley current sense threshold. The low-side operation is able to prevent
the high-side turn on, so the device can skip pulses decreasing the switching frequency.
Figure 19. Over current protection behavior
In worst case scenario, reported in Figure 19. Over current protection behavior of the overcurrent protection the
switch current is limited to:
V
− V
L
IN
OUT
I
= I
VY
+
∙ T
MASKHS
(7)
MAX
Where IVY is the current threshold of the valley sensing circuitry (please refer to Table 6. Electrical
characteristics) and TMASKHS is the masking time of the high-side switch (75 ns typ.).
DS13116 - Rev 2
page 22/63
L6983
Overcurrent protection
In most of the overcurrent conditions, the conduction time of the high-side switch is higher than the masking time
and so the peak current protection limits the switch current.
I
= I
PK
(8)
MAX
The DC current flowing in the load in overcurrent condition is:
I
V
V
− V
OUT
2 ∙ L
RIPPLE OUT
IN
I
= I
MAX
−
= I
MAX
−
∙ T
ON
(9)
DCOUT
2
The Figure 20. Soft-start procedure with VOUT shorted to GND shows the L6983 soft-start procedure with VOUT
shorted to GND.
Figure 20. Soft-start procedure with VOUT shorted to GND
The Figure 21. Over current procedure with persistent short circuit between VOUT and GND shows the L6983 over
current protection with a persistent short circuit between VOUT and GND.
DS13116 - Rev 2
page 23/63
L6983
Thermal shutdown
Figure 21. Over current procedure with persistent short circuit between VOUT and GND
6.9
Thermal shutdown
The shutdown block disables the switching activity if the junction temperature is higher than a fixed internal
threshold (TSHDWN refer to Table 6. Electrical characteristics). The thermal sensing element is close to the power
elements, assuring fast and accurate temperature detection. A hysteresis of approximately 30 °C prevents the
device from turning ON and OFF too fast. After a thermal protection event is expired, the L6983 restarts with a
new soft-start.
6.10
Power Good
The PGOOD pin indicates whether the output voltage is within its regulation level. The pin output is an open drain
MOSFET. The PG is pulled low when:
1.
2.
The FB pin voltage is lower than 90% (typ.) of the nominal internal reference for more than 10 µs
The FB pin voltage is higher than 120% (typ.) of the nominal internal reference for more than 10 µs (see
Section 6.7 Overvoltage protection)
3.
4.
5.
During the soft-start procedure also with pre-charged VOUT
If a thermal shutdown event occurs
If a UVLO event occurs
The PG pin is VIN compatible.
DS13116 - Rev 2
page 24/63
L6983
Power Good
Figure 22. PGOOD thresholds
VFB
120%
87%
118%
90%
t
t
VPGOOD
VHIGH
VLOW
DS13116 - Rev 2
page 25/63
L6983
Closing the loop
7
Closing the loop
The following picture shows the typical compensation network required to stabilize the system.
Figure 23. Block diagram of the loop
VIN
PWM control
Current sense
LC
filter
Resistor divider
HS
switch
L
LS
switch
IHS/gCS
R1
COUT
FB
Compensation
network
RLOAD
VREF
R2
PWM comparator
RC
CC
Error amplifier
7.1
GCO(s) control to output transfer function
The accurate control to output transfer function for a buck peak current mode converter can be written as follows:
s
1 +
ω
1
Z
G
s = R
∙ g
∙
∙
∙ F
s
(10)
CO
LOAD CS
H
R
∙ T
s
ω
LOAD SW
L
1 +
1 +
∙ m ∙ 1 − D − 0.5
C
P
Where RLOAD represents the load resistance, the gCS equivalent sensing trans-conductance of the current sense
circuitry, ωP the single pole introduced by the power stage and the ωZ zero given by the ESR of the output
capacitor. FH(s) accounts the sampling effect performed by the PWM comparator on the output of the error
amplifier that introduces a double pole at one half of the switching frequency.
1
ω
=
(11)
Z
ESR ∙ C
OUT
m
∙ 1 − D − 0.5
1
C
ω
=
+
(12)
P
R
∙ C
L ∙ C
∙ f
LOAD OUT
OUT SW
where:
S
e
S
n
m
= 1 +
C
S
= I
∙ f
(13)
e
SLOPE SW
V
− V
L
IN
OUT
S
=
n
Where ISLOPE is equal to 1 A.
Sn represents the on-time slope of the sensed inductor current, Se the on-time slope of the external ramp that
implements the slope compensation to avoid sub-harmonic oscillations at duty cycle over 50%.
The sampling effect contribution FH (s) is:
DS13116 - Rev 2
page 26/63
L6983
Error amplifier compensation network
1
F
s =
(14)
(15)
H
2
2
s
∙ Q
P
s
1 +
+
ω
n
ω
n
where:
1
Q
=
P
π ∙ m ∙ 1 − D − 0.5
C
7.2
Error amplifier compensation network
The following figure shows the typical compensation network required to stabilize the system.
Figure 24. Trans-conductance embedded error amplifier
VREF
E/A
FB
RC
CC
VREF
RC
dV
RO
CO
CC
Gm dV
VFB
RC and CC introduce a pole and a zero in the open loop gain. The transfer function of the error amplifier and its
compensation network is:
A
∙ 1 + s ∙ R ∙ C
C C
VO
∙ R ∙ C ∙ R ∙ C + s ∙ R ∙ C + R ∙ C + R ∙ C + 1
A
s =
(16)
O
2
s
O
O
C
C
O
C
O
O
C
C
where:
A
= G ∙ R
m O
(17)
VO
The poles of this transfer function are (if CC >> CO):
1
f
=
=
(18)
(19)
PLF
2 ∙ π ∙ R ∙ C
O
C
1
f
PHF
2 ∙ π ∙ R ∙ C
O
O
Whereas the zero is defined as:
DS13116 - Rev 2
page 27/63
L6983
Voltage divider
1
f
=
(20)
Z
2 ∙ π ∙ R ∙ C
C
C
7.3
Voltage divider
The contribution of a simple voltage divider is:
R
2
G
s =
(21)
DIV
R
+ R
2
1
A small signal capacitor in parallel to the upper resistor (only for the adjustable part number) of the voltage divider
implements a leading network (fZERO < fPOLE), sometimes necessary to improve the system phase margin:
Figure 25. Leading network example
L6983
R
PGOOD
VIN
PGOOD
BOOT
SW
VIN
R
VIN
FILT
L
C
BOOT
VINLDO
EN/CLKIN
FSW
VOUT
GND
SW
R
R
1
FSW
VBIAS
VOUT/FB
PGND
PGND
C
R1
C
IN
VCC
COUT
C
FILT
C
VCC
A GND
A GND
R
2
E.P.
GND
Laplace transformer of the leading network:
R
1 + s ∙ R ∙ C
1 R1
2
G
s =
∙
(22)
DIV
R
+ R
R ∙ R
1 2
1
2
1 + s ∙
∙ C
R1
R
+ R
2
1
where:
1
f
=
(23)
(24)
Z
2 ∙ π ∙ R ∙ C
1
R1
1
∙ R
2
+ R
2
f
=
P
R
1
2 ∙ π ∙
∙ C
R1
R
1
f
< f
(25)
(26)
Z
P
So closing the loop, the loop gain is:
G s = G
DIV
s ∙ G
CO
s ∙ A
s
O
DS13116 - Rev 2
page 28/63
L6983
Application notes
8
Application notes
8.1
Programmable power up threshold
The enable rising threshold is equal to 1.2 V typical (refer to Table 6. Electrical characteristics). The power-up
threshold is adjusted according to the following equation:
R
EN H
V
= 1.2V ∙ 1 +
(27)
Power Up
R
EN L
Figure 26. Leading network example
VIN
VIN
VIN
R
EN H
R
FILT
VINLDO
EN/CLKIN
FSW
R
C
FSW
C
IN
VCC
R
EN L
VCC
C
AGND
AGND
FILT
GND
The enable falling threshold is equal to 1.0 V typical (refer to Table 6. Electrical characteristics). The turn
threshold is obtained according to the following equation:
R
EN H
V
= 1.0V ∙ 1 +
(28)
Power Up
R
EN L
8.2
External synchronization (available for low noise mode only)
The device allows a direct connection between a clock source and the EN/CLKIN pin.
Figure 27. External synchronization. Direct connection.
VIN
VIN
EXT. Clock(t)
VPP
VIN
RFILT
CFILT
VINLDO
EN/CLKIN
FSW
RFSW
CVCC
CIN
VCC
Clock
Source
AGND
AGND
GND
The device internally implements a low-pass filter connected to EN/CLKIN pin that is able to acquire the average
value of the applied signal.
DS13116 - Rev 2
page 29/63
L6983
Output voltage adjustment
The device turns on when the average of the signal applied is higher than VEN rising (refer to Table 6. Electrical
characteristics). The device turns off when the average of the signal should be lower than VEN falling (refer to
Table 6. Electrical characteristics).
Considering, for example, a clock source with VPP = 5.0 V, the minimum duty cycle to guarantee the power-up is
given by:
V
EN, Rising
Duty
min
=
= 0.24
(29)
(30)
V
PP
The maximum duty cycle to guarantee the turn-off is given by:
V
EN, Falling
Duty
MAX,
=
= 0.2
V
PP
The device allows also the AC coupling.
Figure 28. External synchronization. AC coupling
VIN
VIN
VIN
REN H
RFILT
VINLDO
EN/CLKIN(*)
FSW
CEN
RFSW
CIN
EXT. Clock(t)
CFILT
VCC
REN L
CVCC
VPP
Clock
AGND
AGND
Source
GND
The AC-coupling allows the device to keep the power-up and down thresholds defined by the partition connected
to EN/CLKIN pin and described on Section 8.1 Programmable power up threshold.
The following table resumes the minimum pulse duration for the external signal and maximum duty cycle that
allows the synchronization by keeping the selected power-up and down thresholds.
Table 8. External synchronization AC coupling suggested operation range
V
[V]
TON, MIN, EXT
[ns]
DMAX, EXT
[%]
Clock
PP
Clock
2.3
60
20
20
45
30
20
3.3
5
The minimum amplitude for the external clock signal is, for both the configurations, equal to 2.3 V.
The network given by CEN and RENL sets a high-pass filter. Considering a resistor in the order of 220 kΩ, a
capacitor equal to 1 nF is a correct choice.
8.3
Output voltage adjustment
The error amplifier reference voltage is 0.85 V typical (refer to Table 6. Electrical characteristics). The output
voltage is adjustable as per the following equation:
R
1
V
= 0.85V ∙ 1 +
(31)
OUT
R
2
DS13116 - Rev 2
page 30/63
L6983
Switching frequency
CR1 capacitor is sometimes useful to increase the small signal phase margin (please refer to the Section
7 Closing the loop).
Figure 29. Application circuit
L6983
RPGOOD
CBOOT
VIN
PGOOD
BOOT
SW
VIN
RFILT
VIN
L
VINLDO
EN/CLKIN
FSW
VOUT
GND
SW
R1
R FSW
C VCC
CR1
VBIAS
VOUT/FB
PGND
PGND
CIN
VCC
COUT
CFILT
AGND
AGND
R2
E.P.
GND
8.4
Switching frequency
A resistor connected to the FSW pin features the selection of the switching frequency (refer to the Table 7. FSW
selection).
Connecting the resistor between the pins RFSW and VCC, the internal dithering circuit is turned on. (refer to the
Section 6.6 Spread spectrum).
8.5
Design of the power components
8.5.1
Input capacitor selection
The input capacitor voltage rating must be higher than the maximum input operating voltage of the application.
During the switching activity a pulsed current flows into the input capacitor and so, its RMS current capability must
be selected according to the application conditions. Internal losses of the input filter depends on the ESR value so
usually low ESR capacitors (such as multilayer ceramic capacitors) have higher RMS current capability. On the
other hand, given the RMS current value, lower ESR input filter has lower losses and so contributes to higher
conversion efficiency.
The maximum RMS input current, flowing through the capacitor, can be calculated as follows:
D
η
D
η
I
= I
OUT
∙
1 −
∙
(32)
RMS
Where IOUT is the maximum DC output current, D is the duty cycles, η is the efficiency. This function has a
maximum at D = 0.5 and, considering η = 1, it is equal to IOUT/2. In a specific application, the range of possible
duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and
minimum duty cycles can be calculated as:
V
+ ∆ V
OUT
LOWSIDE
− ∆ V
HIGHSIDE
D
=
(33)
(34)
MAX
V
+ ∆ V
INmin
LOWSIDE
V
+ ∆ V
OUT
LOWSIDE
− ∆ V
HIGHSIDE
D
=
min
V
+ ∆ V
INMAX
LOWSIDE
Where ΔVHIGHSIDE and ΔVLOWSIDE are the voltage drops across the embedded switches. The peak-to-peak
voltage across the input filter can be calculated as the equation below:
I
OUT
∙ F
D
η
D
η
V
=
∙ 1 −
∙
+ ESR ∙ I
OUT
+ ∆ I
(35)
PP
L
C
IN SW
In case of negligible ESR (MLCC capacitor), the equation of CIN as a function of the target VPP can be written as
follows:
DS13116 - Rev 2
page 31/63
L6983
Design of the power components
I
OUT
∙ F
D
η
D
η
C
=
∙ 1 −
∙
(36)
(37)
IN
V
PP SW
Considering η = 1 this function has its maximum in D = 0.5:
I
OUT
C
=
INmin
4 ∙ V
∙ F
PPMAX SW
Typically, CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 5%
VINMAX
.
In the following table, some suitable capacitor part numbers are listed.
Table 9. Capacitor part numbers
Manufacturer
Series
Size
1206
1206
1206
Cap value (µF)
Rated voltage (V)
TDK
CGA5L3X5R1H106K160AB
C3216X5R1H106K160AB
GRT31CR61H106KE01
10
10
10
50
50
50
Murata
8.5.2
Inductor selection
The inductor current ripple flowing into the output capacitor determines the output voltage ripple. Usually the
inductor value is selected in order to keep the current ripple lower than 20% - 40% of the output current over the
input voltage range. The inductance value can be calculated by the following equation:
V
− V
L
V
OUT
L
IN
OUT
∆ I
=
∙ T
ON
=
∙ T
OFF
(38)
L
Where TON and TOFF are the on and off time of the internal power switch. The maximum current ripple, at fixed
VOUT, is obtained at maximum TOFF that is at minimum duty cycle. So fixing ΔIL = 20% to 40% of the maximum
output current, the minimum inductance value can be calculated:
V
1 − D
OUT
min
L
=
∙
(39)
min
∆ IL
MAX
F
SW
For those applications requiring higher inductor value for minimized current ripple, pay attention the maximum
value must prevent the sub-harmonic instability given the designed internal slope compensation. As a
consequence the inductor value must satisfy the quality factor range:
0.4 ≤ Q ≤ 1.33
(40)
(41)
P
Where QP has been defined in Section 7.1 GCO(s) control to output transfer function.
The peak current through the inductor is given by:
∆ I
L
2
I
= I +
OUT
L, PK
So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device)
increases. The higher is the inductor value, the higher is the average output current that can be delivered, without
reaching the current limit.
8.5.3
Output capacitor selection
The triangular shape current ripple (with zero average value) flowing into the output capacitor gives the output
voltage ripple, that depends on the capacitor value and the equivalent resistive component (ESR). Therefore, the
output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements.
The voltage ripple equation can be calculated as:
∆ I
L, MAX
∆ V
OUT
= ESR ∙ ∆ I
L, MAX
+
(42)
8 ∙ C
∙ F
OUT SW
For a ceramic (MLCC) capacitor, the capacitive component of the ripple dominates the resistive one. While for an
electrolytic capacitor the opposite is true. Neglecting the ESR contribution the minimum value of the output
capacitor is given by:
DS13116 - Rev 2
page 32/63
L6983
Design of the power components
∆ I
L, MAX
C
=
(43)
OUT, min, RIPPLE
8 ∙ ∆ V
∙ F
OUT SW
As the compensation network is internal, the output capacitor should be selected in order to have a proper phase
margin and then a stable control loop. A good rule to obtain a proper dimensioning for the minimum amount of the
output capacitor is set the target system bandwidth equal to FSW/8. The following equation keep into account the
precedent consideration:
8.04
C
=
(44)
OUT, BW, min
Fsw
∙ V
OUT
8
The maximum amount of the output capacitor is given by:
−3
0.960 ∙ 10
C
=
(45)
OUT, BW, MAX
V
OUT
DS13116 - Rev 2
page 33/63
L6983
Application board
9
Application board
The figure below shows the reference evaluation board schematic:
Figure 30. Evaluation board schematic
V
1 6 = p e T y
5 C
F
2 2 µ
0
1 2 e 1 i z s
V
1 6 = p e T y 4 C
F
1 0 µ
6
1 2 e 0 i z s
V
1 6 = p e T y
3 C
F
1 0 µ
6
1 2 e 0 i z s
5
0 8 e 0 i z s
N D G P
W F S
F B
1
3 1
4 1
5 1
6 1
8
7
6
5
1
2
2
W S
W S
N D G P
S A V B I
O O D G P
5
0 8 e 0 i z s
F
V
1 µ
6
C 1
5
0 8 e 0 i z s
5 0 = p e T y
F
1 0 µ
5
1 0 0 u
C 1
V
5 0 F
V
5 0 = p e T y 1 C
1 2 e 0 i z s
0
1 0 P x 1 1 0 H 1 1 Z A H E E
c i o s n n a P
6
F
7 . µ 4
2
C 1
V
5 0 = p e T y
6
1 2 e 0 i z s
F
7 . µ 4
V
5 0 = p e T y
3
C 1
6
1 2 e 0 i z s
6
1 2 e 0 i z s
F
7 . µ 4
4
C 1
V
5 0 = p e T y
The additional input filter (C14, L3, C13, L2, C12, and C15) limits the conducted emission on the power supply.
DS13116 - Rev 2
page 34/63
L6983
Application board
Table 10. Bill of material
Reference
Part number
Description
10 µF 50 V
1 µF 50 V
Manufacturer
TDK
C1
CGA5L3X5R1H106K160AB
CGA4J3X7R1H105K125AB
GCM31CR71C106KA64L
CGA6P1X7R1C226M250AC
CGA3E2X7R1H104K080AA
C2012X8R1C105K125AB
C2A, C2B, C16
TDK
C3-C4
10 µF 16 V
22 µF 16 V
100 nF 50 V
1 µF 16V
MURATA
TDK
C5
C6
TDK
C7
TDK
C8, C9, C11, C17
NOT MOUNTED
4.7 µF 50 V
100 µF, 50 V
NOT MOUNTED
4.7 µH
C12-C13-C14
C15
L1B
L1A
L2
GRM31CR71H475KA12L
EEHZA1H101P
Murata
Panasonic
XAL6060-472ME
XAL4030-472ME
MPZ2012S221A
Coilcraft
Coilcraft
TDK
4.7 µH
L3
220 Ω 100 MHz
10 k 1%
R1
any
R2
NOT MOUNTED
400 k 1%
R3
any
any
any
R4
82 k 1%
R5
0
R6
NOT MOUNTED
1 M 1%
R7
any
any
R8
10 k 1%
R9
NOT MOUNTED
NOT MOUNTED
0
R11
R12
R13
J2
any
any
0.1 k 1%
U1
L6983CQTR
ST Microelectronics
DS13116 - Rev 2
page 35/63
L6983
Application board
Figure 31. Top layer
Figure 32. Bottom layer
DS13116 - Rev 2
page 36/63
L6983
Efficiency curves
10
Efficiency curves
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
2 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
XAL6060-153ME (Coilcraft)
–
Figure 33. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ
V = 24 V; VOUT = 5 V; FSW = 0.4 MHz
IN
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 34. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale)
VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHz
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 37/63
L6983
Efficiency curves
Figure 35. Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ
V
IN
= 24 V ; VOUT = 5 V; FSW = 0.4 MHz
2.5
2
16
14
12
10
8
1.5
1
6
4
LCM
LNM
0.5
0
2
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
2 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
XAL6060-153ME (Coilcraft).
–
Figure 36. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ
V = 12 V; VOUT = 5 V; FSW = 0.4 MHz
IN
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
DS13116 - Rev 2
page 38/63
L6983
Efficiency curves
Figure 37. Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale)
VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHz
100
90
80
70
60
50
40
30
LCM
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
Figure 38. Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ
VIN = 12 V ; VOUT = 5 V; FSW = 0.4 MHz
2
16
14
12
10
8
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
6
LCM
4
LNM
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
2 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
2 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
XAL6060-822ME (Coilcraft).
–
DS13116 - Rev 2
page 39/63
L6983
Efficiency curves
Figure 39. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ
V = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz
IN
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 40. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale)
VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHz
100
90
80
70
60
50
40
30
LCM
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 40/63
L6983
Efficiency curves
Figure 41. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ
Vin = 24 V ; Vout = 3.3 V ; Fsw = 0.4 MHz
1.8
12
10
8
1.6
1.4
1.2
1
6
0.8
0.6
0.4
0.2
0
4
LCM
LNM
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
2 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
2 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
–
XAL6060-822ME (Coilcraft)
DS13116 - Rev 2
page 41/63
L6983
Efficiency curves
Figure 42. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ
VIN = 12 V ; VOUT = 3.3 V ; FSW = 0.4 MHz
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 43. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale)
VIN = 12 V ; VOUT = 3.3 V ; FSW = 0.4 MHz
100
90
80
70
60
50
40
30
LCM
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 42/63
L6983
Efficiency curves
Figure 44. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ
VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHz
1.8
12
10
8
1.6
1.4
1.2
1
6
0.8
0.6
0.4
0.2
0
4
LCM
LNM
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
1 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
XAL6060-472ME (Coilcraft).
–
DS13116 - Rev 2
page 43/63
L6983
Efficiency curves
Figure 45. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ
VIN = 24 V ; VOUT = 3.3 V ; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 46. Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale)
VIN = 24 V ; VOUT = 3.3 V ; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
LCM
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 44/63
L6983
Efficiency curves
Figure 47. Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ
VIN = 24 V ; VOUT = 3.3 V ; FSW = 1.0 MHz
2.5
2
12
10
8
1.5
1
6
LCM
4
LNM
0.5
0
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
1 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
XAL6060-472ME (Coilcraft).
–
DS13116 - Rev 2
page 45/63
L6983
Efficiency curves
Figure 48. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ
VIN = 12 V ; VOUT = 3.3 V ; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 49. Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale)
VIN = 12 V ; VOUT = 3.3 V ; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
LCM
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
DS13116 - Rev 2
page 46/63
L6983
Efficiency curves
Figure 50. Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ
Vin = 12 V ; Vout = 3.3 V ; Fsw = 1.0 MHz
2
1.8
1.6
1.4
1.2
1
12
10
8
6
0.8
0.6
0.4
0.2
0
LCM
4
LNM
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
1 x CGA6P1X7R1C226M250AC 22 µF 16V (TDK);
2 x CGA5L3X5R1H106K160AB 10 µF 50V (TDK).
•
Inductor:
XAL6060-472ME (Coilcraft).
–
DS13116 - Rev 2
page 47/63
L6983
Efficiency curves
Figure 51. . Efficiency VIN = 24 V; VOUT = 5 V; FSW = 1.0 MHZ
V = 24 V ; VOUT = 5.0 V ; FSW = 1.0 MHz
IN
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
Figure 52. Efficiency VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale)
V
IN
= 24 V ; VOUT = 5.0 V ; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0.001
0.01
0.1
1
IOUT [A]
Figure 53. Power losses VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ
DS13116 - Rev 2
page 48/63
L6983
Efficiency curves
VIN = 24 V ; VOUT = 5.0 V ; FSW = 1.0 MHz
3
2.5
2
16
14
12
10
8
1.5
1
6
LCM
4
LNM
0.5
0
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
The following three figures show the efficiency and power losses acquired on the standard evaluation board of the
device, STEVAL-ISA208V1, selecting the following output filter:
•
COUT
:
–
–
1 x CGA6P1X7R1C226M250AC 22 µF 16 V (TDK);
1 x CGA5L3X5R1H106K160AB 10 µF 50 V (TDK).
•
Inductor:
XAL6060-472ME (Coilcraft).
–
Figure 54. Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ
V
IN
= 12 V ; VOUT = 5.0 V ; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
20
10
0
LCM
LNM
0
0.5
1
1.5
2
2.5
3
IOUT [A]
DS13116 - Rev 2
page 49/63
L6983
Efficiency curves
Figure 55. Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale)
VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHz
100
90
80
70
60
50
40
30
LCM
LNM
20
10
0
0.001
0.01
0.1
1
IOUT [A]
Figure 56. Power losses VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ
Vin = 12 V ; Vout = 5.0 V ; Fsw = 1.0 MHz
2.5
2
16
14
12
10
8
1.5
1
6
LCM
LNM
4
0.5
0
2
POUT
0
0
0.5
1
1.5
2
2.5
3
IOUT [A]
DS13116 - Rev 2
page 50/63
L6983
Thermal dissipation
11
Thermal dissipation
The thermal design is important in order to prevents thermal shutdown of the device if junction temperature goes
above 165 °C. The three different sources of losses within the device are:
1.
Conduction losses due to the on-resistance of high-side switch (RDSON_HS) and low-side switch (RDSON_LS);
these are equal to:
2
2
P
= R
∙ I
∙ D + R
∙ I
∙ 1 − D
(46)
(47)
COND
DSON_HS OUT
DSON_LS OUT
where D is the duty cycle of the selected application and is given by the following formula:
V
+ R
+ DCRl ∙ I
OUT
OUT
− R
DSON_LS
D =
V
− R
∙ I
IN
DSON
HS
DSON_LS OUT
In order to obtain a more accurate extimation it is necessary to keep into account that the amount of resistance of
the internal power MOSFET increases together with the temperature. For this reason, the value of RDSONHS and
RDSONLS, should be increased from the typical of a factor equal to 15%.
1.
Switching losses due to high-side power MOSFET turn-ON and OFF; these can be calculated as per below:
T
+ T
RISE
FALL
P
= V ∙ I
IN OUT
∙
F
= V ∙ I
∙ T
∙ F
(48)
SW
SW IN OUT SW SW
2
where TRISE and TFALL are the overlap times of the voltage across the high side power switch (VDS) and the
current flowing into it during turn-ON and turn-OFF phases, as shown in Figure 57. Switching losses.
TSW is the equivalent switching time. For this device the typical value for the equivalent switching time is 20 ns.
1. Quiescent current losses, calculated as the equation below:
P
= V ∙ I
IN Q, MAX
(49)
Q
where IQ is the quiescent current and depends on the VBIAS connections. If VBIAS is connected to GND, the
maximum is equal to 3 mA. Otherwise if VBIAS is connected to VOUT the quiescent current is given by:
V
1
BIAS
I
= 0.8 mA +
∙
∙ 2.3 mA
(50)
Q, MAX
η
V
L6983
IN
The power losses are given by:
P
= P
COND
+ P
+ P
Q
(51)
(52)
LOSS
SW
The junction temperature TJ can be calculated as:
T
= T + R
∙ P
J
A
tℎJA LOSS
where TA is the ambient temperature. RthJA is the equivalent thermal resistance junction to ambient of the device;
it can be calculated as the parallel of many paths of heat conduction from the junctions to the ambient. For this
device the path through the exposed pad is the one conducting the largest amount of heat. The RthJA measured
on the demonstration board described in the following section is about 30 °C/W.
DS13116 - Rev 2
page 51/63
L6983
Thermal dissipation
Figure 57. Switching losses
VIN
VSW(t)
ISW,HS (t)
VDS,HS(t)
t
PSW
PCOND,LS
PCOND,HS
t
TFALL
TRISE
It is also possible to estimate the junction temperature directly from the efficiency measures acquired on a
stationary application condition.
Considering that the power losses are given by:
P
= P − P
IN OUT
(53)
LOSS
Neglecting the AC losses of the selected inductor, the power losses related to the L6983 are given by:
2
OUT
P
= V ∙ I − V
∙ I
− DCRl ∙ I
(54)
(55)
LOSS L6983
IN IN OUT OUT
Therefore, the junction temperature TJ can be calculated as:
T
= T + R
∙ P
J
A
tℎJA LOSS, L6983
DS13116 - Rev 2
page 52/63
L6983
Package information
12
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.
DS13116 - Rev 2
page 53/63
L6983
QFN16 (3x3 mm) package information
12.1
QFN16 (3x3 mm) package information
Figure 58. QFN16 (3x3 mm) package outline
DS13116 - Rev 2
page 54/63
L6983
QFN16 (3x3 mm) package information
Table 11. QFN16 (3x3 mm) mechanical data
mm
Dim.
Min.
0.7
Typ.
0.75
0.02
Max.
0.8
A
A1
A3
b
0
0.05
0.203 Ref.
0.18
0.25
0.3
D
3.00 BSC
3.00 BSC
0.50 BSC
0.43
E
e
D2
E2
L
0.48
0.86
0.4
0.53
0.91
0.45
0.81
0.35
K
0.84
K1
K2
N
0.5
0.86
16
4
ND
NE
aaa
bbb
ccc
ddd
eee
4
0.05
0.1
0.05
0.05
0.05
Figure 59. QFN16 (3x3 mm) recommended footprint
0.85
0.43
0.30
0.50
0.90
0.77
0.80
0.50
DS13116 - Rev 2
page 55/63
L6983
Ordering information
13
Ordering information
Table 12. Order codes
Light load behavior
Part numbers
L6983CQTR
Output voltage
Package
Packaging
Adj.
5 V
LCM
L6983C50QTR
L6983C33QTR
L6983NQTR
(Low Consumption Mode)
3.3 V
Adj.
QFN16
Tape and reel
LNM
L6983N50QTR
L6983N33QTR
5 V
(Low Noise Mode)
3.3 V
DS13116 - Rev 2
page 56/63
L6983
Revision history
Table 13. Document revision history
Date
Revision
Changes
29-Oct-2019
1
Initial release.
Updated: Feature on the cover page, R
value in
DSON_LS
20-Apr-2020
2
Table 6. Electrical characteristics, Section 8.5.2 Inductor selection,
Figure 30. Evaluation board schematic and Table 10. Bill of material.
DS13116 - Rev 2
page 57/63
L6983
Contents
Contents
1
2
3
4
Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Typical application circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.1
4.2
ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5
6
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
5.1
Frequency selection table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
6.1
6.2
6.3
6.4
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Light-load operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
6.4.1
6.4.2
6.4.3
6.4.4
Low consumption mode (LCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Low noise mode (LNM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Efficiency for low consumption mode and low noise mode part number . . . . . . . . . . . . . . 19
Load regulation for low consumption mode and Low noise mode part number . . . . . . . . . 20
6.5
6.6
6.7
6.8
6.9
Switch-over feature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Spread spectrum. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Thermal shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
6.10 Power Good. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
7
8
Closing the loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7.1
7.2
7.3
GCO(s) control to output transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Error amplifier compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Voltage divider. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Application notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
8.1
Programmable power up threshold. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
DS13116 - Rev 2
page 58/63
L6983
Contents
8.2
8.3
8.4
8.5
External synchronization (available for low noise mode only) . . . . . . . . . . . . . . . . . . . . . . . . .29
Output voltage adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Switching frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Design of the power components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8.5.1
8.5.2
8.5.3
Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Output capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
9
Application board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
10 Efficiency curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
11 Thermal dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
12 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
12.1 DFN6 (3x3) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
13 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
DS13116 - Rev 2
page 59/63
L6983
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Typical application component. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
FSW selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
External synchronization AC coupling suggested operation range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Capacitor part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10. Bill of material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 11. QFN16 (3x3 mm) mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 12. Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 13. Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
DS13116 - Rev 2
page 60/63
L6983
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin connection (top through view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Basic application (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Power-up/down behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Soft-start procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Soft-start phase with IOUT = 2.5 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Light load operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
LCM operation with ISKIP = 600 mA typ. at zero load. L = 15 µH; COUT = 40 µF. . . . . . . . . . . . . . . . . . . . . . . 15
LCM operation over loading condition (part 1-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LCM operation over loading condition (part 2-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LCM operation over loading condition (part 3-pulse skipping) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LCM operation over loading condition (part 4-CCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Low noise mode operation at zero load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Light-load efficiency for low consumption mode and low noise mode - linear scale. . . . . . . . . . . . . . . . . . . . . 19
Light-load efficiency for low consumption mode and low noise mode - log scale . . . . . . . . . . . . . . . . . . . . . . 19
Load regulation for LCM and LNM. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - linear scale. . . . . . . . . . . . . . . . 20
Load regulation for low noise mode. VIN = 24 V; VOUT = 5 V; FSW = 400 kHz - log scale. . . . . . . . . . . . . . . . . 20
Switch-over . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Over current protection behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Soft-start procedure with VOUT shorted to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Over current procedure with persistent short circuit between VOUT and GND . . . . . . . . . . . . . . . . . . . . . . . . 24
PGOOD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Block diagram of the loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trans-conductance embedded error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Leading network example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External synchronization. Direct connection.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
External synchronization. AC coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Evaluation board schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Bottom layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Efficiency VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Power losses VIN = 24 V; VOUT = 5 V; FSW = 0.4 MHZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Efficiency VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ (log scale). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Power losses VIN = 12 V; VOUT = 5 V; FSW = 0.4 MHZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 0.4 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Efficiency VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Power losses VIN = 24 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Efficiency VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
DS13116 - Rev 2
page 61/63
L6983
List of figures
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
Figure 57.
Figure 58.
Figure 59.
Power losses VIN = 12 V; VOUT = 3.3 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. Efficiency VIN = 24 V; VOUT = 5 V; FSW = 1.0 MHZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Efficiency VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Power losses VIN = 24 V; VOUT = 5.0 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Efficiency VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ (log scale) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Power losses VIN = 12 V; VOUT = 5.0 V; FSW = 1.0 MHZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
QFN16 (3x3 mm) package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
QFN16 (3x3 mm) recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
DS13116 - Rev 2
page 62/63
L6983
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DS13116 - Rev 2
page 63/63
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