L6599ADTR [STMICROELECTRONICS]
Improved high-voltage resonant controller; 改进的高压谐振控制器
| 型号： | L6599ADTR |
| 厂家： | 
ST |
| 描述： | Improved high-voltage resonant controller |
| 文件： | 总35页 (文件大小：2006K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6599A
Improved high-voltage resonant controller
Datasheet − production data
Features
■ 50% duty cycle, variable frequency control of
resonant half bridge
■ High-accuracy oscillator
■ Up to 500 kHz operating frequency
■ Two-level OCP: frequency-shift and latched
shutdown
DIP16
SO16N
■ Interface with PFC controller
■ Latched disable input
■ Burst mode operation at light load
■ Input for power-ON/OFF sequencing or
brownout protection
■ Non-linear soft-start for monotonic output
voltage rise
■ 600 V-rail compatible high-side gate driver with
integrated bootstrap diode and high dv/dt
immunity
■ -300/800 mA high-side and low-side gate
drivers with UVLO pull-down
■ DIP16, SO16N package
Applications
■ LCD and PDP TV
■ Desktop PC, entry-level server
■ Telecom SMPS
■ High efficiency industrial SMPS
■ AC-DC adapter, open frame SMPS
Table 1.
Device summary
Order code
Package
Packaging
L6599AN
L6599AD
DIP16
SO16N
SO16N
Tube
Tube
L6599ADTR
Tape and reel
January 2013
Doc ID 15308 Rev 7
1/35
This is information on a product in full production.
www.st.com
35
Contents
L6599A
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
6
7
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8
9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2/35
Doc ID 15308 Rev 7
L6599A
Description
1
Description
The L6599A is an improved revision of the previous L6599. It is a double-ended controller
specific to series-resonant half bridge topology. It provides 50% complementary duty cycle:
the high-side switch and the low-side switch are driven ON/OFF 180° out-of-phase for
exactly the same time. Output voltage regulation is obtained by modulating the operating
frequency. A fixed deadtime inserted between the turn-off of one switch and the turn-on of
the other guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high-voltage
floating structure able to withstand more than 600 V with a synchronous-driven high-voltage
DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the designer to set the operating frequency range of the converter by means
of an externally programmable oscillator.
At startup, to prevent uncontrolled inrush current, the switching frequency starts from a
programmable maximum value and progressively decays until it reaches the steady-state
value determined by the control loop. This frequency shift is non-linear to minimize output
voltage overshoots; its duration is programmable as well.
At light load the IC may enter a controlled burst mode operation that keeps the converter
input consumption to a minimum.
IC functions include a not-latched active-low disable input with current hysteresis useful for
power sequencing or for brownout protection, a current sense input for OCP with frequency
shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if
the first-level protection is not sufficient to control the primary current. Their combination
offers complete protection against overload and short-circuits. An additional latched disable
input (DIS) allows easy implementation of OTP and/or OVP.
An interface with the PFC controller is provided that enables the pre-regulator to be
switched off during fault conditions, such as OCP shutdown and DIS high, or during burst
mode operation.
Doc ID 15308 Rev 7
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Block diagram
L6599A
2
Block diagram
Figure 1.
Block diagram
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4/35
Doc ID 15308 Rev 7
L6599A
Pin connection
3
Pin connection
Figure 2.
Pin connection (top view)
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Table 2.
Pin N#
Pin description
Type
Function
Soft-start. This pin connects an external capacitor to GND and a resistor to
RFmin (pin 4) that set both the maximum oscillator frequency and the time
constant for the frequency shift that occurs as the chip starts up (soft-
start). An internal switch discharges this capacitor every time the chip turns
off (Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5 V,
DELAY > 2 V) to make sure it is soft-started next, and when the voltage on
the current sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75
V.
1
Css
Delayed shutdown upon overcurrent. A capacitor and a resistor are
connected from this pin to GND to set the maximum duration of an
overcurrent condition before the IC stops switching and the delay after
which the IC restarts switching. Every time the voltage on the ISEN pin
exceeds 0.8 V, the capacitor is charged by an internal 150 µA current
generator and is slowly discharged by the external resistor. If the voltage
on the pin reaches 2 V, the soft-start capacitor is completely discharged so
that the switching frequency is pushed to its maximum value and the 150
µA is kept always on. As the voltage on the pin exceeds 3.5 V the IC stops
switching and the internal generator is turned off, so that the voltage on the
pin decays because of the external resistor. The IC is soft-restarted as the
voltage drops below 0.3 V. In this way, under short-circuit conditions, the
converter works intermittently with very low input average power.
2
DELAY
Timing capacitor. A capacitor connected from this pin to GND is charged
and discharged by internal current generators programmed by the external
network connected to pin 4 (RFmin) and determines the switching
frequency of the converter.
3
CF
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Pin connection
Table 2.
L6599A
Pin description (continued)
Type
Pin N#
Function
Minimum oscillator frequency setting. This pin provides a precise 2 V
reference and a resistor connected from this pin to GND defines a current
that is used to set the minimum oscillator frequency. To close the feedback
loop that regulates the converter output voltage by modulating the
oscillator frequency, the phototransistor of an optocoupler is connected to
this pin through a resistor. The value of this resistor sets the maximum
operating frequency. An R-C series connected from this pin to GND sets
frequency shift at startup to prevent excessive energy inrush (soft-start).
4
RFmin
Burst mode operation threshold. The pin senses some voltage related to
the feedback control, which is compared to an internal reference (1.24 V).
If the voltage on the pin is lower than the reference, the IC enters an idle
state and its quiescent current is reduced. The chip restarts switching as
the voltage exceeds the reference by 50 mV. Soft-start is not invoked. This
function realizes burst mode operation when the load falls below a level
that can be programmed by properly choosing the resistor connecting the
optocoupler to pin RFmin (see block diagram). Tie the pin to RFmin if burst
mode is not used.
5
STBY
Current sense input. The pin senses the primary current though a sense
resistor or a capacitive divider for lossless sensing. This input is not
intended for a cycle-by-cycle control; therefore the voltage signal must be
filtered to get average current information. As the voltage exceeds a 0.8 V
threshold (with 50 mV hysteresis), the soft-start capacitor connected to pin
1 is internally discharged: the frequency increases, so limiting the power
throughput. Under output short-circuit, this normally results in a nearly
constant peak primary current. This condition is allowed for a maximum
time set at pin 2. If the current keeps on building up despite this frequency
increase, a second comparator referenced at 1.5 V latches the device off
and brings its consumption almost to a “before startup” level. The
information is latched and it is necessary to recycle the supply voltage of
the IC to enable it to restart: the latch is removed as the voltage on the Vcc
pin goes below the UVLO threshold. Tie the pin to GND if the function is
not used.
6
ISEN
Line sensing input. The pin is to be connected to the high-voltage input bus
with a resistor divider to perform either AC or DC (in systems with PFC)
brownout protection. A voltage below 1.24 V shuts down (not latched) the
IC, lowers its consumption and discharges the soft-start capacitor. IC
operation is re-enabled (soft-started) as the voltage exceeds 1.24 V. The
comparator is provided with current hysteresis: an internal 13 µA current
generator is ON as long as the voltage applied at the pin is below 1.24 V
and is OFF if this value is exceeded. Bypass the pin with a capacitor to
GND to reduce noise pick-up. The voltage on the pin is top-limited by an
internal Zener. Activating the Zener causes the IC to shut down (not
latched). Bias the pin between 1.24 and 6 V if the function is not used.
7
LINE
Latched device shutdown. Internally, the pin connects a comparator that,
when the voltage on the pin exceeds 1.85 V, shuts the IC down and brings
its consumption almost to a “before startup” level. The information is
latched and it is necessary to recycle the supply voltage of the IC to enable
it to restart: the latch is removed as the voltage on the VCC pin goes below
the UVLO threshold. Tie the pin to GND if the function is not used.
8
DIS
6/35
Doc ID 15308 Rev 7
L6599A
Pin connection
Table 2.
Pin N#
Pin description (continued)
Type
Function
Open-drain ON/OFF control of PFC controller. This pin, normally open, is
intended for stopping the PFC controller, for protection purposes or during
burst mode operation. It goes low when the IC is shut down by DIS>1.85 V,
PFC_STOP ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V. The pin is pulled low also
when the voltage on the DELAY exceeds 2 V and goes back open as the
voltage falls below 0.3 V. During UVLO, it is open. Leave the pin
unconnected if not used.
9
Chip ground. Current return for both the low-side gate-drive current and
the bias current of the IC. All of the ground connections of the bias
components should be tied to a track going to this pin and kept separate
10
GND
from any pulsed current return.
Low-side gate-drive output. The driver is capable of 0.3 A min. source and
11
12
13
14
LVG
Vcc
0.8 A min. sink peak current to drive the lower MOSFET of the half bridge
leg. The pin is actively pulled to GND during UVLO.
Supply voltage of both the signal part of the IC and the low-side gate
driver. Sometimes a small bypass capacitor (0.1 µF typ.) to GND may be
useful to get a clean bias voltage for the signal part of the IC.
High-voltage spacer. The pin is not internally connected to isolate the high-
voltage pin and ease compliance with safety regulations (creepage
distance) on the PCB.
N.C.
OUT
High-side gate-drive floating ground. Current return for the high-side gate-
drive current. Layout carefully the connection of this pin to avoid too large
spikes below ground.
High-side floating gate-drive output. The driver is capable of 0.3 A min.
source and 0.8 A min. sink peak current to drive the upper MOSFET of the
half bridge leg. A resistor internally connected to pin 14 (OUT) ensures
that the pin is not floating during UVLO.
15
16
HVG
High-side gate-drive floating supply voltage. The bootstrap capacitor
connected between this pin and pin 14 (OUT) is fed by an internal
synchronous bootstrap diode driven in-phase with the low-side gate drive.
This patented structure replaces the normally used external diode.
VBOOT
Doc ID 15308 Rev 7
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Electrical data
L6599A
4
Electrical data
4.1
Absolute maximum ratings
Table 3.
Symbol
Absolute maximum rating
Pin
Parameter
Value
Unit
VBOOT
HVG
16
15
Floating supply voltage
HVG voltage
-1 to 618
V
V
VOUT -0.3 to VBOOT +0.3
-3 up to a value included
in the range VBOOT -18
and VBOOT
VOUT
14
Floating ground voltage
V
dVOUT /dt
Vcc
14
12
11
9
Floating ground max. slew rate
IC supply voltage (Icc = 25 mA)
LVG voltage
50
Self-limited
-0.3 to VCC +0.3
-0.3 to Vcc
Self-limited
Self-limited
2
V/ns
V
LVG
V
VPFC_STOP
IPFC_STOP
VLINEmax
IRFmin
Maximum voltage (pin open)
Maximum sink current (pin low)
Maximum pin voltage (Ipin ≤1 mA)
Maximum source current
V
9
A
7
V
4
mA
V
---
1 to 6, 8 Analog inputs and outputs
Power dissipation @TA = 70 °C (DIP16)
-0.3 to 5
1
Ptot
W
Power dissipation @TA = 50 °C (SO16)
Junction temperature operating range
Storage temperature
0.83
Tj
-40 to 150
-55 to 150
°C
°C
Tstg
Note:
ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V.
4.2
Thermal data
Table 4.
Symbol
Thermal data
Parameter
Value
Unit
Max. thermal resistance junction-to-ambient (DIP16)
Max. thermal resistance junction-to-ambient (SO16)
80
°C/W
°C/W
Rth(JA)
120
8/35
Doc ID 15308 Rev 7
L6599A
Electrical characteristics
5
Electrical characteristics
TJ = 0 to 105 °C, Vcc = 15 V, VBOOT = 15 V, CHVG = CLVG = 1 nF; CF = 470 pF;
RRFmin = 12 kΩ; unless otherwise specified.
Table 5.
Symbol
Electrical characteristics
Parameter
Test condition
Min. Typ. Max. Unit
IC supply voltage
Vcc
VccOn
VccOff
Hys
Operating range
After device turn-on
Voltage rising
8.85
10
16
V
V
V
V
V
Turn-on threshold
Turn-off threshold
Hysteresis
10.7
8.15
2.55
17
11.4
8.85
Voltage falling
7.45
VZ
Vcc clamp voltage
Iclamp = 15 mA
16
17.9
Supply current
Before device turn-on
Vcc = VccOn- 0.2 V
Istart-up Startup current
200
250
µA
Iq
Quiescent current
Operating current
Device on, VSTBY = 1 V
Device on, VSTBY = VRFmin
VDIS > 1.85 V or
1.5
3.5
2
5
mA
mA
Iop
Iq
Residual consumption
300
400
µA
VDELAY > 3.5 V or VLINE
1.24 V or VLINE = Vclamp
<
High-side floating gate-drive supply
ILKBOOT VBOOT pin leakage current VBOOT = 580 V
5
5
µA
µA
ILKOUT OUT pin leakage current
VOUT = 562 V
VLVG = HIGH
Synchronous bootstrap
RDS(on)
150
250
Ω
diode on-resistance
Overcurrent comparator
IISEN
tLEB
Input bias current
VISEN = 0 to VISENdis
-1
µA
ns
After VHVG and VLVG low-
to-high transition
Leading edge blanking
VISENx Frequency shift threshold
Hysteresis
Voltage rising (1)
0.77
1.45
0.8
50
0.83
V
mV
V
Voltage falling
VISENdis Latch-off threshold
Voltage rising (1)
1.5
300
1.55
400
td(H-L)
Delay to output
ns
Line sensing
Vth
IHys
Threshold voltage
Voltage rising or falling (1)
VLINE = 1.1 V
1.2
10
6
1.24
13
1.28
16
8
V
µA
V
Current hysteresis
Clamp level
Vclamp
ILINE = 1 mA
Doc ID 15308 Rev 7
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Electrical characteristics
L6599A
Table 5.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Min. Typ. Max. Unit
DIS function
IDIS
Vth
Input bias current
Disable threshold
VDIS = 0 to Vth
-1
µA
V
Voltage rising (1)
1.78
1.85
1.92
Oscillator
D
Output duty cycle
Both HVG and LVG
48
58.2
240
0.2
50
60
250
0.3
3.9
0.9
2
52
61.8
260
0.4
%
fosc
Oscillation frequency
kHz
RRFmin = 2.7 kΩ
TD
Deadtime
Between HVG and LVG
µs
V
VCFp
VCFv
Peak value
Valley value
V
(1)
1.93
1.93
2.07
2.07
VREF
KM
Voltage reference at pin 4
Current mirroring ratio
V
IREF = -2 mA (1)
2
1
A/A
PFC_STOP function
VPFC_STOP = Vcc,
Ileak
High level leakage current
1
µA
Ω
VDIS = 0 V
IPFC_STOP = 1 mA,
VDIS = 1.5 V
RPFC_STOP ON-state resistance
130
120
200
0.2
IPFC_STOP = 1 mA,
VL
Low saturation level
V
VDIS = 1.5 V
Soft-start function
Ileak
R
Open-state current
Discharge resistance
V(Css) = 2 V
ISEN > VISENx
0.5
µA
V
Ω
Standby function
IDIS
Vth
Hys
Input bias current
VDIS = 0 to Vth
Voltage falling (1)
Voltage rising
-1
µA
V
Disable threshold
Hysteresis
1.2
1.24
50
1.28
mV
Delayed shutdown function
Ileak Open-state current
V(DELAY) = 0
VDELAY = 1 V,
0.5
µA
µA
ICHARGE Charge current
100
150
200
VISEN = 0.85 V
Threshold for forced
operation at max.
frequency
Vth1
Voltage rising (1)
1.98
2.05
2.12
V
Vth2
Vth3
Shutdown threshold
Restart threshold
Voltage rising (1)
Voltage falling (1)
3.35
0.3
3.5
3.65
0.36
V
V
0.33
10/35
Doc ID 15308 Rev 7
L6599A
Electrical characteristics
Min. Typ. Max. Unit
Table 5.
Symbol
Electrical characteristics (continued)
Parameter Test condition
Low-side gate driver (voltages referred to GND)
VLVGL
VLVGH
Output low voltage
Output high voltage
Isink = 200 mA
Isource = 5 mA
1.5
V
V
12.8
-0.3
0.8
13.3
Isourcepk Peak source current
A
Isinkpk
Peak sink current
Fall time
A
tf
tr
30
60
ns
ns
Rise time
Vcc = 0 to VccOn
Isink = 2 mA
,
UVLO saturation
1.1
1.5
V
High-side gate driver (voltages referred to OUT)
VLVGL
VLVGH
Output low voltage
Output high voltage
Isink = 200 mA
Isource = 5 mA
V
V
12.8
-0.3
0.8
13.3
Isourcepk Peak source current
A
Isinkpk
Peak sink current
Fall time
A
tf
tr
30
60
25
ns
ns
kΩ
Rise time
HVG-OUT pull-down
1. Values tracking each other.
Doc ID 15308 Rev 7
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Typical electrical performance
L6599A
6
Typical electrical performance
Figure 3.
Device consumption vs. supply
voltage
Figure 4.
Figure 6.
Figure 8.
IC consumption vs. junction
temperature
AM13167v1
AM13168v1
Figure 5.
VCC clamp voltage vs. junction
temperature
UVLO thresholds vs. junction
temperature
AM13169v1
AM13170v1
Figure 7.
Oscillator frequency vs. junction
temperature
Deadtime vs. junction temperature
AM13172v1
AM13171v1
12/35
Doc ID 15308 Rev 7
L6599A
Typical electrical performance
Figure 9.
Oscillator frequency vs. timing
components
Figure 10. Oscillator ramp vs. junction
temperature
Pin 3 fsw [kHz]
1000
100
10
Vcc = 15V
CF:
220 pF
330 pF
470 pF
680 pF
1.0 nF
2.2 nF
0
5
10
15
20
RFmin [kΩ ]
AM13173v1
AM13174v
Figure 11. Reference voltage vs. junction
temperature
Figure 12. Current mirroring ratio vs. junction
temperature
AM13176v1
AM13175v1
Figure 13. OCP delay source current vs.
junction temperature
Figure 14. OCP delay thresholds vs. junction
temperature
AM13178v1
AM13177v1
Doc ID 15308 Rev 7
13/35
Typical electrical performance
L6599A
Figure 15. Standby thresholds vs. junction
temperature
Figure 16. Current sense thresholds vs.
junction temperature
AM13180v1
AM13179v1
Figure 17. Line thresholds vs. junction
temperature
Figure 18. Line source current vs. junction
temperature
Pin 7 (uA)
13.5
13
Vcc= 15V
12.5
12
11.5
-20
0
20
40
60
80
100
120
Tj (°C)
AM13182v1
AM13181v1
Figure 19. Latched disable threshold vs.
junction temperature
AM13183v1
14/35
Doc ID 15308 Rev 7
L6599A
Application information
7
Application information
The L6599A is an advanced double-ended controller specific for resonant half bridge
topology (see Figure 21). In these converters the switches (MOSFETs) of the half bridge leg
are alternately switched on and off (180° out-of-phase) for exactly the same time. This is
commonly referred to as operation at “50% duty cycle”, although the real duty cycle, that is
the ratio of the ON-time of either switch to the switching period, is actually less than 50%.
The reason is that there is an internally fixed deadtime TD inserted between the turn-off of
either MOSFET and the turn-on of the other one, where both MOSFETs are off. This
deadtime is essential in order for the converter to work correctly: it ensures soft-switching
and enables high-frequency operation with high efficiency and low EMI emissions.
To perform converter output voltage regulation the device is able to operate in different
modes (Figure 20), depending on the load conditions:
1. Variable frequency at heavy and medium/light load. A relaxation oscillator (see
Section 7.1: Oscillator for more details) generates a symmetrical triangular waveform,
which the MOSFET switching is locked to. The frequency of this waveform is related to
a current that is modulated by the feedback circuitry. As a result, the tank circuit driven
by the half bridge is stimulated at a frequency dictated by the feedback loop to keep the
output voltage regulated, therefore exploiting its frequency-dependent transfer
characteristics.
2. Burst mode control with no or very light load. When the load falls below a value, the
converter enters a controlled intermittent operation, where a series of a few switching
cycles at a nearly fixed frequency are spaced out by long idle periods where both
MOSFETs are in OFF-state. A further load decrease is translated into longer idle
periods and then in a reduction of the average switching frequency. When the converter
is completely unloaded, the average switching frequency can go down even to few
hundred hertz, therefore minimizing magnetizing current losses as well as all
frequency-related losses and making it easier to comply with energy saving
recommendations.
Figure 20. Multi-mode operation of the L6599A
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Application information
Figure 21. Typical system block diagram
L6599A
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7.1
Oscillator
The oscillator is programmed externally by means of a capacitor (CF), connected from pin 3
(CF) to ground, that is alternately charged and discharged by the current defined with the
network connected to pin 4 (RFmin). The pin provides an accurate 2 V reference with about
2 mA source capability and the higher the current sourced by the pin is, the higher the
oscillator frequency is. The block diagram of Figure 22 shows a simplified internal circuit that
explains the operation.
The network that loads the RFmin pin is generally made up of three branches:
1. A resistor RFmin connected between the pin and ground that determines the minimum
operating frequency.
2. A resistor RFmax connected between the pin and the collector of the (emitter-
grounded) phototransistor that transfers the feedback signal from the secondary side
back to the primary side; while in operation, the phototransistor modulates the current
through this branch - therefore modulating the oscillator frequency - to perform output
voltage regulation; the value of RFmax determines the maximum frequency the half
bridge is operated at when the phototransistor is fully saturated.
3. An R-C series circuit (CSS+RSS) connected between the pin and ground that enables
a frequency shift to be set up at startup (see Section 7.3: Soft-start). Note that the
contribution of this branch is zero during steady-state operation.
16/35
Doc ID 15308 Rev 7
L6599A
Application information
Figure 22. Oscillator internal block diagram
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The following approximate relationships hold for the minimum and the maximum oscillator
frequency respectively:
Equation 1
1
1
fmin
=
;
fmax =
3 ⋅CF ⋅RFmin
3 ⋅CF ⋅
(
RFmin //RFmax
)
After fixing CF in the hundred pF or in the nF (consistently with the maximum source
capability of the RFmin pin and trading this off against the total consumption of the device),
the value of RFmin and RFmax is selected so that the oscillator frequency is able to cover
the entire range needed for regulation, from the minimum value fmin (at minimum input
voltage and maximum load) to the maximum value fmax (at maximum input voltage and
minimum load):
Equation 2
1
RFmin
fmax
fmin
RFmin
=
; RFmax =
3⋅CF⋅fmin
−1
A different selection criterion is given for RFmax in case burst mode operation at no load is
used (see Section 7.2: Operation at no load or very light load).
Doc ID 15308 Rev 7
17/35
Application information
L6599A
Figure 23. Oscillator waveforms and their relationship with gate-driving signals
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In Figure 23 the timing relationship between the oscillator waveform and the gate-drive
signal, as well as the swinging node of the half bridge leg (HB), is shown. Note that the low-
side gate drive is turned on while the oscillator triangle is ramping up and the high-side gate
drive is turned on while the triangle is ramping down. In this way, at startup, or as the IC
resumes switching during burst mode operation, the low-side MOSFET is switched on first
to charge the bootstrap capacitor. As a result, the bootstrap capacitor is always charged and
ready to supply the high-side floating driver.
7.2
Operation at no load or very light load
When the resonant half bridge is lightly loaded or not loaded at all, its switching frequency is
at its maximum value. To keep the output voltage under control in these conditions and to
avoid losing soft-switching, there must be some significant residual current flowing through
the transformer’s magnetizing inductance. This current, however, produces some
associated losses that prevent converter no load consumption from achieving very low
values.
To overcome this issue, the L6599A enables the designer to make the converter operate
intermittently (burst mode operation), with a series of a few switching cycles spaced out by
long idle periods where both MOSFETs are in OFF-state, so that the average switching
frequency can be substantially reduced. As a result, the average value of the residual
magnetizing current and the associated losses are considerably cut down, therefore
facilitating the converter to comply with energy saving recommendations.
The L6599A can be operated in burst mode by using pin 5 (STBY): if the voltage applied to
this pin falls below 1.24 V, the IC enters an idle state where both gate-drive outputs are low,
the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V
reference at the RFmin pin stays alive to minimize IC consumption and Vcc capacitor
discharge. The IC resumes normal operation as the voltage on the pin exceeds 1.24 V by 50
mV.
To implement burst mode operation the voltage applied to the STBY pin needs to be related
to the feedback loop. Figure 24 (a) shows the simplest implementation, suitable with a
narrow input voltage range (e.g. when there is a PFC front-end).
18/35
Doc ID 15308 Rev 7
L6599A
Application information
Figure 24. Burst mode implementation: a) narrow input voltage range; b) wide input
voltage range
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Essentially, RFmax defines the switching frequency fmax above which the L6599A enters
burst mode operation. Once fmax is fixed, RFmax is found from the relationship:
Equation 3
3 RFmin
RFmax
=
fmax
8
−1
fmin
Note that, unlike the fmax considered in the previous section (“Section 7.1: Oscillator“), here
max is associated to some load PoutB greater than the minimum one. PoutB is such that the
f
transformer peak currents are low enough not to cause audible noise.
Resonant converter switching frequency, however, depends also on the input voltage;
therefore, in the case of quite a large input voltage range with the circuit of Figure 24a, the
value of PoutB would change considerably. In this case it is recommended to use the
arrangement shown in Figure 24b, where the information on the converter input voltage is
added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship
between switching frequency and input voltage, it is more practical to find empirically the
right amount of correction RA / (RA + RB) needed to minimize the change of PoutB. Make
sure to choose the total value RA + RB much greater than RC to minimize the effect on the
LINE pin voltage (see Section 7.6: Line sensing function).
Whichever circuit is in use, its operation can be described as follows. As the load falls below
the value PoutB the frequency tries to exceed the maximum programmed value fmax and
the voltage on the STBY pin (VSTBY) goes below 1.24 V. The IC then stops with both gate-
drive outputs low, so that both MOSFETs of the half bridge leg are in OFF-state. The voltage
V
STBY now increases as a result of the feedback reaction to the energy delivery stop and, as
it exceeds 1.29 V, the IC restarts switching. After a while, VSTBY goes down again in
response to the energy burst and stops the IC. In this way, the converter works in a burst
mode fashion with a nearly constant switching frequency. A further load decrease then
causes a frequency reduction, which can go down even to few hundred hertz. The timing
diagram of Figure 25 illustrates this kind of operation, showing the most significant signals.
A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close
to the IC as possible to reduce switching noise pick-up, helps obtain clean operation.
To help the designer meet energy saving requirements even in power-factor-corrected
systems, where a PFC pre-regulator precedes the DC-DC converter, the L6599A allows that
the PFC pre-regulator can be turned off during burst mode operation, therefore eliminating
Doc ID 15308 Rev 7
19/35
Application information
L6599A
the no load consumption of this stage (0.5 1 W). There is no compliance issue in that,
because EMC regulations on low-frequency harmonic emissions refer to nominal load, no
limit is envisaged when the converter operates with light or no load.
To do so, the L6599A provides pin 9 (PFC_STOP): it is an open collector output, normally
open, that is asserted low when the IC is idle during burst mode operation. This signal is
externally used for switching off the PFC controller and the pre-regulator, as shown in
Figure 26. When the L6599A is in UVLO, the pin is kept open to let the PFC controller start
first.
Figure 25. Load-dependent operating modes: timing diagram
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Figure 26. How the L6599A can switch off a PFC controller at light load
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20/35
Doc ID 15308 Rev 7
L6599A
Application information
7.3
Soft-start
Generally speaking, the purpose of soft-start is to progressively increase converter power
capability when it is started up, so as to avoid excessive inrush current. In resonant
converters the deliverable power depends inversely on frequency, soft-start is then done by
sweeping the operating frequency from an initial high value until the control loop takes over.
With the L6599A converter, soft-startup is simply realized with the addition of an R-C series
circuit from pin 4 (RFmin) to ground (see Figure 27, left).
Initially, the capacitor CSS is totally discharged, so that the series resistor RSS is effectively
in parallel to RFmin and the resulting initial frequency is determined by RSS and RFmin
only, since the optocoupler phototransistor is cut off (as long as the output voltage is not too
far away from the regulated value):
Equation 4
1
fstart
=
3 ⋅CF ⋅
(
RFmin //RSS
)
The CSS capacitor is progressively charged until its voltage reaches the reference voltage
(2 V) and, consequently, the current through RSS goes to zero. This conventionally is
imposed 5 times by selecting the constants RSS·CSS. Before reaching 2 V on Css, the
output voltage should be already close to the regulated value and the feedback loop already
taken over, so that it is the optocoupler phototransistor to determine the operating frequency
from that moment onwards.
During this frequency sweep phase the operating frequency decays following the
exponential charge of CSS, that is, initially it changes relatively quickly but the rate of change
gets slower and slower. This counteracts the non-linear frequency dependence of the tank
circuit that makes the converter power capability change little as frequency is away from
resonance and change very quickly as frequency approaches resonance frequency (see
Figure 27, right).
Figure 27. Soft-start circuit (left) and power vs. frequency curve in a resonant
half bridge (right)
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As a result, the average input current smoothly increases, without the peaking that occurs
with linear frequency sweep, and the output voltage reaches the regulated value with almost
no overshoot.
Doc ID 15308 Rev 7
21/35
Application information
Typically, RSS and CSS are selected based on the following relationships:
Equation 5
L6599A
RFmin
fstart
3⋅10−3
RSS
RSS
=
; CSS =
−1
fmin
where fstart is recommended to be at least 4 times fmin. The proposed criterion for CSS is
quite empirical and is a compromise between an effective soft-start action and an effective
OCP (see next section). Please refer to the timing diagram of Figure 27 to see some
significant signals during the soft-start phase.
7.4
Current sense, OCP and OLP
The resonant half bridge is essentially voltage-mode controlled; therefore a current sense
input only serves as an overcurrent protection (OCP).
Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the
primary switch (or switches), in a resonant half bridge the duty cycle is fixed and energy flow
is controlled by its switching frequency. This impacts on the way current limitation can be
realized. While in PWM-controlled converters energy flow can be limited simply by
terminating switch conduction beforehand when the sensed current exceeds a preset
threshold (this is commonly known as cycle-by-cycle limitation), in a resonant half bridge the
switching frequency, that is, its oscillator frequency must be increased and this cannot be
done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the
frequency change. This implies that, to have an effective increase able to change the energy
flow significantly, the rate of change of the frequency must be slower than the frequency
itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that, therefore,
the information on the primary current fed to the current sensing input must be somehow
averaged. Of course, the averaging time must not be too long to prevent the primary current
from reaching too high values.
In Figure 28 a couple of current sensing methods are illustrated and are described in the
following. The circuit of Figure 28a is simpler but the dissipation on the sense resistor Rs
might not be negligible, damaging efficiency; the circuit of Figure 28b is more complex but
virtually lossless and recommended when the efficiency target is very high.
22/35
Doc ID 15308 Rev 7
L6599A
Application information
Figure 28. Current sensing techniques: a) with sense resistor, b) “lossless”,
with capacitive shunt
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The L6599A is equipped with a current sensing input (pin 6, ISEN) and a sophisticated
overcurrent management system. The ISEN pin is internally connected to the input of a first
comparator, referenced to 0.8 V, and to that of a second comparator referenced to 1.5 V. If
the voltage externally applied to the pin by either circuit in Figure 28 exceeds 0.8 V, the first
comparator is tripped and this causes an internal switch to be turned on and discharge the
soft-start capacitor CSS (see Section 7.3: Soft-start). This quickly increases the oscillator
frequency and thereby limits energy transfer. The discharge goes on until the voltage on the
ISEN pin has dropped by 50 mV; this, with an averaging time in the range of 10/fmin, ensures
an effective frequency rise. Under output short-circuit, this operation results in a nearly
constant peak primary current.
It is normal that the voltage on the ISEN pin may overshoot above 0.8 V; however, if the
voltage on the ISEN pin reaches 1.5 V, the second comparator is triggered, the L6599A
shuts down and latches off with both the gate drive outputs and the PFC_STOP pin low,
therefore turning off the entire unit. The supply voltage of the IC must be pulled below the
UVLO threshold and then again above the startup level in order to restart. Such an event
may occur if the soft-start capacitor CSS is too large, so that its discharge is not fast enough
or in the case of transformer magnetizing inductance saturation or a shorted secondary
rectifier.
In the circuit shown in Figure 28a, where a sense resistor Rs in series to the source of the
low-side MOSFET is used, note the particular connection of the resonant capacitor. In this
way the voltage across Rs is related to the current flowing through the high-side MOSFET
and is positive most of the switching period, except for the time needed for the resonant
current to reverse after the low-side MOSFET has been switched off. Assuming that the time
constant of the RC filter is at least ten times the minimum switching frequency fmin, the
approximate value of Rs can be found using the empirical equation:
Equation 6
Vspkx
ICrpkx
5⋅0.8
ICrpkx
4
Rs =
≈
≈
ICrpkx
where ICrpkx is the maximum desired peak current flowing through the resonant capacitor
and the primary winding of the transformer, which is related to the maximum load and the
minimum input voltage.
Doc ID 15308 Rev 7
23/35
Application information
L6599A
The circuit shown in Figure 28b can be operated in two different ways. If the resistor RA in
series to CA is small (not above some hundred Ω, just to limit current spiking), the circuit
operates like a capacitive current divider; CA is typically selected equal to Cr/100 or less and
is a low-loss type, the sense resistor RB is selected as:
Equation 7
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
0.8π
ICrpkx
Cr
RB
=
1+
CA
and CB is such that RB·CB is in the range of 10 /fmin
.
If the resistor RA in series to CA is not small (in this case it is typically selected in the ten kΩ),
the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr,
which, in turn, is related to its current through the reactance of Cr. Again, CA is typically
selected equal to Cr/100 or less, not necessarily a low-loss type this time, while RB
(provided it is << RA) according to:
Equation 8
R2A + XC2
0.8π
ICrpkx
A
RB =
XCr
where the reactance of CA (XCA) and Cr (XCr) should be calculated at the frequency where
Crpk = ICrpkx. Again, CB is such that RB·CB is in the range of 10 /fmin
I
.
Whichever circuit is used, the calculated values of Rs or RB should be considered just a first
cut value that needs to be adjusted after experimental verification.
OCP is effective in limiting primary-to-secondary energy flow in case of an overload or an
output short-circuit, but the output current through the secondary winding and rectifiers
under these conditions might be so high as to endanger converter safety if continuously
flowing. To prevent any damage during these conditions, it is customary to force the
converter’s intermittent operation, in order to bring the average output current to values such
that the thermal stress for the transformer and the rectifiers can be easily handled.
With the L6599A the designer can externally program the maximum time TSH that the
converter is allowed to run overloaded or under short-circuit conditions. Overloads or short-
circuits lasting less than TSH do not cause any other action, therefore providing the system
with immunity to short duration phenomena. If, instead, TSH is exceeded, an overload
protection (OLP) procedure is activated that shuts down the L6599A and, in the case of
continuous overload/short-circuit, results in continuous intermittent operation with a user-
defined duty cycle.
24/35
Doc ID 15308 Rev 7
L6599A
Application information
Figure 29. Soft-start and delayed shutdown upon overcurrent timing diagram
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This function is realized with pin 2 (DELAY), by means of a capacitor CDelay and a parallel
resistor RDelay connected to ground. As the voltage on the ISEN pin exceeds 0.8 V the first
OCP comparator, in addition to discharging CSS, turns on an internal current generator that
sources 150 µA from the DELAY pin and charges CDelay. During an overload/short-circuit,
the OCP comparator and the internal current source is repeatedly activated and CDelay is
charged with an average current that depends essentially on the time constant of the current
sense filtering circuit on CSS and the characteristics of the resonant circuit; the discharge
due to RDelay can be neglected, considering that the associated time constant is typically
much longer.
This operation continues until the voltage on CDelay reaches 2 V, which defines the time TSH
There is no simple relationship that links TSH to CDelay, therefore it is more practical to
determine CDelay experimentally. As a rough indication, with CDelay = 1 µF, TSH is in the
order of 100 ms.
.
Once CDelay is charged at 2 V the internal switch that discharges CSS is forced low
continuously regardless of the OCP comparator output, and the 150 µA current source is
continuously on, until the voltage on CDelay reaches 3.5 V. This phase lasts:
Equation 9
TMP = 10 ⋅ CDelay
with TMP expressed in ms and CDelay in µF. During this time the L6599A runs at a frequency
close to fstart (see Section 7.3: Soft-start) to minimize the energy inside the resonant circuit.
As the voltage on CDelay is 3.5 V, the L6599A stops switching and the PFC_STOP pin is
pulled low. Also the internal generator is turned off, so that CDelay is now slowly discharged
by RDelay. The IC restarts when the voltage on CDelay is less than 0.3 V, which takes:
Equation 10
TSTOP = RDelay CDelay ln 3.5 ≈ 2.5RDelay CDelay
0.3
Doc ID 15308 Rev 7
25/35
Application information
L6599A
The timing diagram of Figure 29 shows this operation. Note that, if, during TSTOP, the supply
voltage of the L6599A (Vcc) falls below the UVLO threshold, the IC records the event and
does not restart immediately after Vcc exceeds the startup threshold if V(DELAY) is still
higher than 0.3 V. Also the PFC_STOP pin stays low as long as V(DELAY) is greater than
0.3 V. Note also that, in the case of an overload lasting less than TSH, the value of TSH for
the next overload is lower if they are close to one another.
7.5
Latched shutdown
The L6599A is equipped with a comparator having the non-inverting input externally
available at pin 8 (DIS) and with the inverting input internally referenced to 1.85 V. As the
voltage on the pin exceeds the internal threshold, the IC is immediately shut down and its
consumption reduced to a low value. The information is latched and it is necessary to let the
voltage on the VCC pin go below the UVLO threshold to reset the latch and restart the IC.
This function is useful to implement a latched overtemperature protection very easily by
biasing the pin with a divider from an external reference voltage (e.g. pin 4, RFmin), where
the upper resistor is an NTC physically located close to a heating element like the MOSFET,
or the secondary diode or transformer.
An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an
overvoltage condition via an optocoupler.
7.6
Line sensing function
This function basically stops the IC as the input voltage to the converter falls below the
specified range and lets it restart as the voltage goes back within the range. The sensed
voltage can be either the rectified and filtered mains voltage, in which case the function acts
as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output
voltage of the PFC stage, in which case the function serves as a power-on and power-off
sequencing.
L6599A shutdown upon input undervoltage is accomplished by means of an internal
comparator, as shown in the block diagram of Figure 30, whose non-inverting input is
available at pin 7 (LINE). The comparator is internally referenced to 1.24 V and disables the
IC if the voltage applied at the LINE pin is below the internal reference. Under these
conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of
the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the
reference. The comparator is provided with current hysteresis instead of a more usual
voltage hysteresis: an internal 13 µA current sink is ON as long as the voltage applied at the
LINE pin is below the reference and is OFF if the voltage is above the reference.
This approach provides an additional degree of freedom: it is possible to set the ON
threshold and the OFF threshold separately by properly choosing the resistors of the
external divider (see below). With voltage hysteresis, instead, fixing one threshold
automatically fixes the other, depending on the built-in hysteresis of the comparator.
26/35
Doc ID 15308 Rev 7
L6599A
Application information
Figure 30. Line sensing function: internal block diagram and timing diagram
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With reference to Figure 28, the following relationships can be established for the ON
(VinON) and OFF (VinOFF) thresholds of the input voltage:
Equation 11
VinON −1.24
VinOFF −1.24
1.24
RL
1.24
RL
= 13 ⋅10−6
+
=
RH
RH
which, solved for RH and RL, yields:
Equation 12
VinON − VinOFF
13 ⋅10−6
1.24
RH
=
;
RL = R
H VinOFF −1.24
While the line undervoltage is active, the startup generator keeps on working but there is no
PWM activity, therefore the Vcc voltage (if not supplied by another source) continuously
oscillates between the startup and the UVLO thresholds, as shown in the timing diagram of
Figure 30.
As an additional safety measure (e.g. in case the low-side resistor is open or missing, or in
non-power factor corrected systems in case of abnormally high input voltage), if the voltage
on the pin exceeds 7 V, the L6599A is shut down. If its supply voltage is always above the
UVLO threshold, the IC restarts as the voltage falls below 7 V.
The LINE pin, while the device is operating, is a high impedance input connected to high
value resistors, therefore it is prone to pick-up noise, which might alter the OFF threshold or
give origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin
to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this kind.
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Application information
L6599A
If the function is not used, the pin must be connected to a voltage greater than 1.24 V but
lower than 6 V (worst-case value of the 7 V threshold).
7.7
Bootstrap section
The supply of the floating high-side section is obtained by means of a bootstrap circuitry.
This solution normally requires a high-voltage fast recovery diode (DBOOT, Figure 31a) to
charge the bootstrap capacitor CBOOT. In the L6599A a patented integrated structure,
replaces this external diode. It is realized by means of a high-voltage DMOS, working in the
third quadrant and driven synchronously with the low-side driver (LVG), with a diode in
series to the source, as shown in Figure 31b.
Figure 31. Bootstrap supply: a) standard circuit; b) internal bootstrap synchronous
diode
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The diode prevents any current being able to flow from the VBOOT pin back to Vcc, in case
the supply is quickly turned off when the internal capacitor of the pump is not fully
discharged. To drive the synchronous DMOS a voltage higher than the supply voltage Vcc is
necessary. This voltage is obtained by means of an internal charge pump (Figure 31b).
The bootstrap structure introduces a voltage drop while recharging CBOOT (i.e. when the
low-side driver is on), which increases with the operating frequency and with the size of the
external Power MOSFET. It is the sum of the drop across the R(DS)ON and the forward drop
across the series diode. At low frequency this drop is very small and can be neglected but,
as the operating frequency increases, it must be taken into account. In fact, the drop
reduces the amplitude of the driving signal and can significantly increase the R(DS)ON of the
external high-side MOSFET and then its conductive loss.
This concern applies to converters designed with a high resonance frequency (indicatively,
> 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter runs
at high frequency at light load, where the current flowing in the MOSFETs of the half bridge
leg is low, so that, generally, an R(DS)ON rise is not an issue. However, it is wise to check this
point anyway and the following equation is useful to compute the drop on the bootstrap
driver:
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Doc ID 15308 Rev 7
L6599A
Application information
Equation 13
Qg
VDrop = IchargeR(DS)on + VF =
R(DS)on + VF
Tcharge
where Qg is the gate charge of the external Power MOSFET, R(DS)ON is the on-resistance of
the bootstrap DMOS (150 W, typ.) and Tcharge is the ON-time of the bootstrap driver, which
equals about half the switching period minus the deadtime TD. For example, using a
MOSFET with a total gate charge of 30 nC, the drop on the bootstrap driver is about 3 V at a
switching frequency of 200 kHz:
Equation 14
30⋅10−9
2.5⋅10−6 − 0.27⋅10−6
VDrop
=
150 + 0.6 = 2.7 V
If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be
used, therefore saving the drop on the R(DS)ON of the internal DMOS.
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Application information
L6599A
Figure 32. Application example: 90 W AC/DC adapter using L6563H, L6599A and
SRK2000
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Doc ID 15308 Rev 7
L6599A
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com.
ECOPACK is an ST trademark.
Table 6.
DIP16 mechanical data
mm
Dim.
Min.
0.51
0.77
Typ.
Max.
a1
B
b
1.65
0.5
b1
D
E
e
0.25
20
8.5
2.54
17.78
e3
F
7.1
5.1
I
L
3.3
Z
1.27
Figure 33. DIP16 drawing
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Package mechanical data
L6599A
Table 7.
Dim.
SO16N mechanical data
mm
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.25
0.10
1.25
0.31
0.17
9.80
5.80
3.80
0.51
0.25
10.00
6.20
4.00
c
D
9.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0
0.50
1.27
8°
L
k
ccc
0.10
Figure 34. SO16N drawing
0016020_F
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L6599A
Package mechanical data
Figure 35. SO16N recommended footprint (dimensions are in mm)
Doc ID 15308 Rev 7
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Revision history
L6599A
9
Revision history
Table 8.
Date
Document revision history
Revision
Changes
19-Jan-2009
25-Feb-2009
13-Mar-2009
30-Oct-2009
28-Sep-2010
1
2
3
4
5
Initial release
Updated Table 5 on page 9
Updated data on Table 5 on page 9 under oscillator section
Updated Table 5 on page 9
Added: Section 6 on page 12
Updated Figure 9: Oscillator frequency vs. timing components and
Section 8: Package mechanical data
10-Sep-2012
14-Jan-2013
6
7
Updated Table 3: Absolute maximum rating on page 8
34/35
Doc ID 15308 Rev 7
L6599A
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