L6599AF [STMICROELECTRONICS]
Very low temperature improved high voltage resonant controller;
| 型号： | L6599AF |
| 厂家： | 
ST |
| 描述： | Very low temperature improved high voltage resonant controller |
| 文件： | 总32页 (文件大小：959K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
L6599AF
Very low temperature
improved high voltage resonant controller
Datasheet - production data
Applications
Outdoor LED drivers
Street lighting
AC-DC adapters, open frame SMPS
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Table 1. Device summary
Order code
Package
Packaging
Features
L6599AFD
Tube
SO16N
50% duty cycle, variable frequency control of
L6599AFDTR
Tape and reel
resonant half bridge
High accuracy oscillator
Up to 500 kHz operating frequency
Two-level OCP: frequency-shift and latched
shutdown
Interface with PFC controller
Latched disable input
Burst mode operation at light load
Input for power-ON/OFF sequencing or
brownout protection
Non-linear soft-start for monotonic output
voltage rise
600 V - rail compatible high-side gate driver
with integrated bootstrap diode and high dv/dt
immunity
-300/700 mA high-side and low-side gate
drivers with UVLO pull-down
Guaranteed for temperatures as low as -50 °C
August 2015
DocID028175 Rev 3
1/32
This is information on a product in full production.
www.st.com
Contents
L6599AF
Contents
1
2
3
4
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
4.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Operation at no load or very light load . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Current sense, OCP and OLP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Latched shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Line sensing function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Bootstrap section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7
8
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1
SO16N package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
DocID028175 Rev 3
L6599AF
Description
1
Description
The L6599AF is an improved revision of the previous L6599A. It is a double-ended
controller specific to series-resonant half bridge topology. It provides 50% complementary
duty cycle: the high-side switch and the low-side switch are driven ON/OFF 180° out-of-
phase for exactly the same time. Output voltage regulation is obtained by modulating the
operating frequency. A fixed deadtime inserted between the turn-off of one switch and the
turn-on of the other guarantees soft-switching and enables high-frequency operation.
To drive the high-side switch with the bootstrap approach, the IC incorporates a high voltage
floating structure able to withstand more than 600 V with a synchronous-driven high voltage
DMOS that replaces the external fast-recovery bootstrap diode.
The IC enables the designer to set the operating frequency range of the converter by means
of an externally programmable oscillator.
At startup, to prevent uncontrolled inrush current, the switching frequency starts from a
programmable maximum value and progressively decays until it reaches the steady-state
value determined by the control loop. This frequency shift is non-linear to minimize output
voltage overshoots; its duration is programmable as well.
At light load the IC may enter a controlled burst mode operation that keeps the converter
input consumption to a minimum.
IC functions include a not-latched active-low disable input with current hysteresis useful for
power sequencing or for brownout protection, a current sense input for OCP with frequency
shift and delayed shutdown with automatic restart. A higher level OCP latches off the IC if
the first-level protection is not sufficient to control the primary current. Their combination
offers complete protection against overload and short-circuits. An additional latched disable
input (DIS) allows easy implementation of OTP and/or OVP.
An interface with the PFC controller is provided that enables the pre-regulator to be
switched off during fault conditions, such as OCP shutdown and DIS high, or during burst
mode operation.
DocID028175 Rev 3
3/32
32
Block diagram
L6599AF
2
Block diagram
Figure 1. Block diagram
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4/32
DocID028175 Rev 3
L6599AF
Pin connection
3
Pin connection
Figure 2. Pin connection (top view)
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Table 2. Pin description
Function
Pin no.
Type
Soft-start. This pin connects an external capacitor to GND and a resistor to RFmin (pin 4)
that set both the maximum oscillator frequency and the time constant for the frequency shift
that occurs as the chip starts up (soft-start). An internal switch discharges this capacitor
every time the chip turns off (Vcc < UVLO, LINE < 1.24 V or > 6 V, DIS > 1.85 V, ISEN > 1.5
V, DELAY > 2 V) to make sure it is soft-started next, and when the voltage on the current
sense pin (ISEN) exceeds 0.8 V, as long as it stays above 0.75 V.
1
Css
Delayed shutdown upon overcurrent. A capacitor and a resistor are connected from this pin
to GND to set the maximum duration of an overcurrent condition before the IC stops
switching and the delay after which the IC restarts switching. Every time the voltage on the
ISEN pin exceeds 0.8 V, the capacitor is charged by an internal 150 µA current generator
and is slowly discharged by the external resistor. If the voltage on the pin reaches 2 V, the
soft-start capacitor is completely discharged so that the switching frequency is pushed to its
maximum value and the 150 µA is kept always on. As the voltage on the pin exceeds 3.5 V
the IC stops switching and the internal generator is turned off, so that the voltage on the pin
decays because of the external resistor. The IC is soft-restarted as the voltage drops below
0.3 V. In this way, under short-circuit conditions, the converter works intermittently with very
low input average power.
2
DELAY
Timing capacitor. A capacitor connected from this pin to GND is charged and discharged by
internal current generators programmed by the external network connected to pin 4 (RFmin)
and determines the switching frequency of the converter.
3
4
CF
Minimum oscillator frequency setting. This pin provides a precise 2 V reference and a
resistor connected from this pin to GND defines a current that is used to set the minimum
oscillator frequency. To close the feedback loop that regulates the converter output voltage
by modulating the oscillator frequency, the phototransistor of an optocoupler is connected to
this pin through a resistor. The value of this resistor sets the maximum operating frequency.
An R-C series connected from this pin to GND sets frequency shift at startup to prevent
excessive energy inrush (soft-start).
RFmin
DocID028175 Rev 3
5/32
32
Pin connection
L6599AF
Table 2. Pin description (continued)
Function
Pin no.
Type
Burst mode operation threshold. The pin senses some voltage related to the feedback
control, which is compared to an internal reference (1.24 V). If the voltage on the pin is lower
than the reference, the IC enters an idle state and its quiescent current is reduced. The chip
restarts switching as the voltage exceeds the reference by 50 mV. Soft-start is not invoked.
This function realizes burst mode operation when the load falls below a level that can be
programmed by properly choosing the resistor connecting the optocoupler to pin RFmin
(see block diagram). Tie the pin to RFmin if burst mode is not used.
5
STBY
Current sense input. The pin senses the primary current though a sense resistor or a
capacitive divider for lossless sensing. This input is not intended for a cycle-by-cycle control;
therefore the voltage signal must be filtered to get average current information. As the
voltage exceeds a 0.8 V threshold (with 50 mV hysteresis), the soft-start capacitor
connected to pin 1 is internally discharged: the frequency increases, so limiting the power
throughput. Under output short-circuit, this normally results in a nearly constant peak
primary current. This condition is allowed for a maximum time set at pin 2. If the current
keeps on building up despite this frequency increase, a second comparator referenced at
1.5 V latches the device off and brings its consumption almost to a “before startup” level.
The information is latched and it is necessary to recycle the supply voltage of the IC to
enable it to restart: the latch is removed as the voltage on the Vcc pin goes below the UVLO
threshold. Tie the pin to GND if the function is not used.
6
ISEN
Line sensing input. The pin is to be connected to the high voltage input bus with a resistor
divider to perform either AC or DC (in systems with PFC) brownout protection. A voltage
below 1.24 V shuts down (not latched) the IC, lowers its consumption and discharges the
soft-start capacitor. IC operation is re-enabled (soft-started) as the voltage exceeds 1.24 V.
The comparator is provided with current hysteresis: an internal 13 µA current generator is
ON as long as the voltage applied at the pin is below 1.24 V and is OFF if this value is
exceeded. Bypass the pin with a capacitor to GND to reduce noise pick-up. The voltage on
the pin is top-limited by an internal Zener diode. Activating the Zener diode causes the IC to
shut down (not latched). Bias the pin between 1.24 and 6 V if the function is not used.
7
LINE
Latched device shutdown. Internally, the pin connects a comparator that, when the voltage
on the pin exceeds 1.85 V, shuts the IC down and brings its consumption almost to a “before
startup” level. The information is latched and it is necessary to recycle the supply voltage of
the IC to enable it to restart: the latch is removed as the voltage on the VCC pin goes below
the UVLO threshold. Tie the pin to GND if the function is not used.
8
9
DIS
Open-drain ON/OFF control of PFC controller. This pin, normally open, is intended for
stopping the PFC controller, for protection purposes or during burst mode operation. It goes
low when the IC is shut down by DIS>1.85 V, ISEN > 1.5 V, LINE > 6 V and STBY < 1.24 V.
The pin is pulled low also when the voltage on the DELAY exceeds 2 V and goes back open
as the voltage falls below 0.3 V. During UVLO, it is open. Leave the pin unconnected if not
used.
PFC_STOP
Chip ground. Current return for both the low-side gate-drive current and the bias current of
the IC. All of the ground connections of the bias components should be tied to a track going
to this pin and kept separate from any pulsed current return.
10
11
12
GND
LVG
Vcc
Low-side gate-drive output. The driver is capable of 0.3 A min. source and 0.7 A min. sink
peak current to drive the lower MOSFET of the half bridge leg. The pin is actively pulled to
GND during UVLO.
Supply voltage of both the signal part of the IC and the low-side gate driver. Sometimes
a small bypass capacitor (0.1 µF typ.) to GND may be useful to get a clean bias voltage for
the signal part of the IC.
6/32
DocID028175 Rev 3
L6599AF
Pin connection
Table 2. Pin description (continued)
Function
Pin no.
Type
high voltage spacer. The pin is not internally connected to isolate the high voltage pin and
ease compliance with safety regulations (creepage distance) on the PCB.
13
N.C.
High-side gate-drive floating ground. Current return for the high-side gate-drive current.
Layout carefully the connection of this pin to avoid too large spikes below ground.
14
15
OUT
HVG
High-side floating gate-drive output. The driver is capable of 0.3 A min. source and 0.7 A
min. sink peak current to drive the upper MOSFET of the half bridge leg. A resistor internally
connected to pin 14 (OUT) ensures that the pin is not floating during UVLO.
High-side gate-drive floating supply voltage. The bootstrap capacitor connected between
this pin and pin 14 (OUT) is fed by an internal synchronous bootstrap diode driven in-phase
with the low-side gate drive. This patented structure replaces the normally used external
diode.
16
VBOOT
DocID028175 Rev 3
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32
Electrical data
L6599AF
4
Electrical data
4.1
Absolute maximum ratings
Table 3. Absolute maximum rating
Symbol
Pin
Parameter
Value
Unit
VBOOT
HVG
16
15
Floating supply voltage
HVG voltage
-1 to 618
V
V
OUT -0.3 to VBOOT +0.3
V
-3 up to a value included
in the range VBOOT -18
and VBOOT
VOUT
14
Floating ground voltage
V
dVOUT /dt
Vcc
14
12
11
9
Floating ground max. slew rate
IC supply voltage (Icc = 25 mA)
LVG voltage
50
Self-limited
-0.3 to VCC +0.3
-0.3 to Vcc
Self-limited
Self-limited
2
V/ns
V
LVG
V
VPFC_STOP
IPFC_STOP
VLINEmax
IRFmin
Maximum voltage (pin open)
Maximum sink current (pin low)
Maximum pin voltage (Ipin 1 mA)
Maximum source current
V
9
A
7
V
4
mA
V
---
1 to 6, 8 Analog inputs and outputs
Power dissipation at TA = 70 °C (DIP16)
-0.3 to 5
1
Ptot
W
Power dissipation at TA = 50 °C (SO16)
Junction temperature operating range
Storage temperature
0.83
Tj
-50 to 150
-55 to 150
°C
°C
Tstg
Note:
ESD immunity for pins 14, 15 and 16 is guaranteed up to 900 V.
4.2
Thermal data
Table 4. Thermal data
Symbol
Rth(JA)
Parameter
Value
Unit
Max. thermal resistance junction to ambient (SO16)
120
°C/W
8/32
DocID028175 Rev 3
L6599AF
Electrical characteristics
5
Electrical characteristics
T = - 50 to 125 °C, V = 15 V, VBOOT = 15 V, C
= C
= 1 nF; C = 470 pF;
J
CC
HVG
LVG
F
R
= 12 k; unless otherwise specified.
RFmin
Table 5. Electrical characteristics
Test condition
Symbol
Parameter
Min. Typ. Max. Unit
IC supply voltage
Vcc
VccOn
VccOff
Hys
Operating range
After device turn-on
Voltage rising
8.85
10
16
V
V
V
V
V
Turn-on threshold
Turn-off threshold
Hysteresis
10.7
8.15
2.55
17
11.4
8.85
Voltage falling
7.45
VZ
Vcc clamp voltage
Iclamp = 15 mA
16
Supply current
Before device turn-on
Vcc = VccOn- 0.2 V
Istart-up
Startup current
200
250
µA
Iq
Quiescent current
Operating current
Device on, VSTBY = 1 V
1.5
3.5
2
5
mA
mA
Iop
Device on, VSTBY = VRFmin
VDIS > 1.85 V or VDELAY > 3.5 V
or VLINE < 1.24 V or VLINE = Vclamp
Iq
Residual consumption
300
400
µA
High-side floating gate-drive supply
ILKBOOT VBOOT pin leakage current VBOOT = 580 V
5
5
µA
µA
ILKOUT
OUT pin leakage current
VOUT = 562 V
VLVG = HIGH
Synchronous bootstrap
diode on-resistance
RDS(on)
150
250
Overcurrent comparator
IISEN Input bias current
VISEN = 0 to VISENdis
-1
µA
ns
After VHVG and VLVG low-to-high
transition
tLEB
Leading edge blanking
VISENx
Frequency shift threshold
Hysteresis
Voltage rising(1)
Voltage falling
Voltage rising(1)
0.76
1.44
0.8
50
0.84
V
mV
V
VISENdis Latch-off threshold
td(H-L) Delay to output
Line sensing
1.5
300
1.56
400
ns
Vth
IHys
Threshold voltage
Voltage rising or falling(1)
VLINE = 1.1 V
1.2
10
6
1.24
13
1.28
16
8
V
µA
V
Current hysteresis
Clamp level
Vclamp
ILINE = 1 mA
DocID028175 Rev 3
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32
Electrical characteristics
L6599AF
Table 5. Electrical characteristics (continued)
Test condition
Symbol
Parameter
Min. Typ. Max. Unit
DIS function
IDIS
Vth
Input bias current
Disable threshold
VDIS = 0 to Vth
Voltage rising (1)
-1
µA
V
1.78
1.85
1.92
Oscillator
D
Output duty cycle
Both HVG and LVG
48
58.2
240
0.2
50
62
250
0.3
3.9
0.9
2
52
65.8
260
0.4
%
fosc
Oscillation frequency
kHz
RRFmin = 2.7 k
TD
Deadtime
Between HVG and LVG
µs
V
VCFp
VCFv
Peak value
Valley value
V
(1)
1.93
1.8
2.07
2.2
VREF
KM
Voltage reference at pin 4
Current mirroring ratio
V
IREF = -2 mA(1)
2
1
A/A
PFC_STOP function
Ileak
High level leakage current VPFC_STOP = Vcc, VDIS = 0 V
1
µA
I
V
PFC_STOP = 1 mA,
DIS = 1.5 V
RPFC_STOP ON-state resistance
130
200
IPFC_STOP = 1 mA,
VDIS = 1.5 V
VL
Low saturation level
0.2
0.5
V
Soft-start function
Ileak
R
Open-state current
Discharge resistance
V(Css) = 2 V
µA
VISEN > VISENx
120
Standby function
IDIS
Vth
Hys
Input bias current
VDIS = 0 to Vth
Voltage falling(1)
Voltage rising
-1
µA
V
Disable threshold
Hysteresis
1.2
1.24
50
1.28
mV
Delayed shutdown function
Ileak Open-state current
V(DELAY) = 0
0.5
µA
µA
VDELAY = 1 V,
ICHARGE Charge current
100
150
200
VISEN = 0.85 V
Threshold for forced
operation at max.
Vth1
Voltage rising(1)
1.98
2.05
2.12
V
frequency
Vth2
Vth3
Shutdown threshold
Restart threshold
Voltage rising(1)
Voltage falling(1)
3.35
0.3
3.5
3.65
0.36
V
V
0.33
10/32
DocID028175 Rev 3
L6599AF
Electrical characteristics
Min. Typ. Max. Unit
Table 5. Electrical characteristics (continued)
Parameter Test condition
Symbol
Low-side gate driver (voltages referred to GND)
VLVGL
VLVGH
Output low voltage
Output high voltage
Isink = 200 mA
1.8
V
V
Isource = 5 mA
12.8
-0.3
0.7
13.3
Isourcepk Peak source current
A
Isinkpk
Peak sink current
Fall time
A
tf
30
60
ns
ns
tr
Rise time
Vcc = 0 to VccOn
Isink = 2 mA
,
UVLO saturation
1.1
1.8
V
High-side gate driver (voltages referred to OUT)
VLVGL
VLVGH
Output low voltage
Output high voltage
Isink = 200 mA
Isource = 5 mA
V
V
12.8
-0.3
0.7
13.3
Isourcepk Peak source current
A
Isinkpk
Peak sink current
Fall time
A
tf
30
60
25
ns
ns
k
tr
Rise time
HVG-OUT pull-down
1. Values tracking each other.
DocID028175 Rev 3
11/32
32
Application information
L6599AF
6
Application information
The L6599AF is an advanced double-ended controller specific for resonant half bridge
topology (see Figure 4). In these converters the switches (MOSFETs) of the half bridge leg
are alternately switched on and off (180° out-of-phase) for exactly the same time. This is
commonly referred to as operation at “50% duty cycle”, although the real duty cycle, that is
the ratio of the ON-time of either switch to the switching period, is actually less than 50%.
The reason is that there is an internally fixed deadtime T inserted between the turn-off of
D
either MOSFET and the turn-on of the other one, where both MOSFETs are off. This
deadtime is essential in order for the converter to work correctly: it ensures soft-switching
and enables high-frequency operation with high efficiency and low EMI emissions.
To perform converter output voltage regulation the device is able to operate in different
modes (Figure 3), depending on the load conditions:
1. Variable frequency at heavy and medium/light load. A relaxation oscillator (see
Section 6.1: Oscillator for more details) generates a symmetrical triangular waveform,
which the MOSFET switching is locked to. The frequency of this waveform is related to
a current that is modulated by the feedback circuitry. As a result, the tank circuit driven
by the half bridge is stimulated at a frequency dictated by the feedback loop to keep the
output voltage regulated, therefore exploiting its frequency-dependent transfer
characteristics.
2. Burst mode control with no or very light load. When the load falls below a value, the
converter enters a controlled intermittent operation, where a series of a few switching
cycles at a nearly fixed frequency are spaced out by long idle periods where both
MOSFETs are in OFF-state. A further load decrease is translated into longer idle
periods and then in a reduction of the average switching frequency. When the
converter is completely unloaded, the average switching frequency can go down even
to few hundred hertz, therefore minimizing magnetizing current losses as well as all
frequency-related losses and making it easier to comply with energy saving
recommendations.
Figure 3. Multi-mode operation of the L6599AF
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DocID028175 Rev 3
L6599AF
Application information
Figure 4. Typical system block diagram
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6.1
Oscillator
The oscillator is programmed externally by means of a capacitor (CF), connected from the
pin 3 (CF) to ground, that is alternately charged and discharged by the current defined with
the network connected to pin 4 (RF ). The pin provides an accurate 2 V reference with
min
about 2 mA source capability and the higher the current sourced by the pin is, the higher the
oscillator frequency is. The block diagram of Figure 5 shows a simplified internal circuit that
explains the operation.
The network that loads the R
pin is generally made up of three branches:
Fmin
1. A resistor RF
connected between the pin and ground that determines the minimum
min
operating frequency.
2. A resistor RF
connected between the pin and the collector of the (emitter-grounded)
max
phototransistor that transfers the feedback signal from the secondary side back to the
primary side; while in operation, the phototransistor modulates the current through this
branch - therefore modulating the oscillator frequency - to perform output voltage
regulation; the value of RF
determines the maximum frequency the half bridge is
max
operated at when the phototransistor is fully saturated.
3. An R-C series circuit (CSS+RSS) connected between the pin and ground that enables
a frequency shift to be set up at startup (see Section 6.3: Soft-start on page 18). Note
that the contribution of this branch is zero during steady-state operation.
DocID028175 Rev 3
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32
Application information
L6599AF
Figure 5. Oscillator internal block diagram
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The following approximate relationships hold for the minimum and the maximum oscillator
frequency respectively:
Equation 1
1
1
fmin
;
fmax
3 CF RFmin
3 CF
RFmin //RFmax
After fixing CF in the hundred pF or in the nF (consistently with the maximum source
capability of the RF pin and trading this off against the total consumption of the device),
min
the value of RF
and RF
is selected so that the oscillator frequency is able to cover the
min
max
entire range needed for regulation, from the minimum value f
(at minimum input voltage
min
and maximum load) to the maximum value f
load):
(at maximum input voltage and minimum
max
Equation 2
1
RFmin
RFmin
;
RFmax
fmax
3 CF fmin
1
fmin
A different selection criterion is given for R
in case burst mode operation at no load is
Fmax
used (see Section 6.2: Operation at no load or very light load).
14/32
DocID028175 Rev 3
L6599AF
Application information
Figure 6. Oscillator waveforms and their relationship with gate-driving signals
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In Figure 6 the timing relationship between the oscillator waveform and the gate-drive
signal, as well as the swinging node of the half bridge leg (HB), is shown. Note that the low-
side gate drive is turned on while the oscillator triangle is ramping up and the high-side gate
drive is turned on while the triangle is ramping down. In this way, at startup, or as the IC
resumes switching during burst mode operation, the low-side MOSFET is switched on first
to charge the bootstrap capacitor. As a result, the bootstrap capacitor is always charged and
ready to supply the high-side floating driver.
6.2
Operation at no load or very light load
When the resonant half bridge is lightly loaded or not loaded at all, its switching frequency is
at its maximum value. To keep the output voltage under control in these conditions and to
avoid losing soft-switching, there must be some significant residual current flowing through
the transformer’s magnetizing inductance. This current, however, produces some
associated losses that prevent converter no load consumption from achieving very low
values.
To overcome this issue, the L6599AF enables the designer to make the converter operate
intermittently (burst mode operation), with a series of a few switching cycles spaced out by
long idle periods where both MOSFETs are in OFF-state, so that the average switching
frequency can be substantially reduced. As a result, the average value of the residual
magnetizing current and the associated losses are considerably cut down, therefore
facilitating the converter to comply with energy saving recommendations.
The L6599AF can be operated in burst mode by using pin 5 (STBY): if the voltage applied to
this pin falls below 1.24 V, the IC enters an idle state where both gate-drive outputs are low,
the oscillator is stopped, the soft-start capacitor CSS keeps its charge and only the 2 V
reference at the RF
pin stays alive to minimize IC consumption and Vcc capacitor
min
discharge. The IC resumes normal operation as the voltage on the pin exceeds 1.24 V by
50 mV.
To implement burst mode operation the voltage applied to the STBY pin needs to be related
to the feedback loop. Figure 7 (a) shows the simplest implementation, suitable with a narrow
input voltage range (e.g. when there is a PFC front-end).
DocID028175 Rev 3
15/32
32
Application information
L6599AF
Figure 7. Burst mode implementation: a) narrow input voltage range; b) wide input voltage range
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Essentially, RF
defines the switching frequency f
above which the L6599AF enters
max
max
burst mode operation. Once f
is fixed, RF
is found from the relationship:
max
max
Equation 3
3 RFmin
RFmax
fmax
8
1
fmin
Note that, unlike the f
considered in the previous section (Section 6.1: Oscillator), here
max
f
is associated to some load Pout greater than the minimum one. Pout is such that the
max
B B
transformer peak currents are low enough not to cause audible noise.
Resonant converter switching frequency, however, depends also on the input voltage;
therefore, in the case of quite a large input voltage range with the circuit of Figure 7a, the
value of Pout would change considerably. In this case it is recommended to use the
B
arrangement shown in Figure 7b, where the information on the converter input voltage is
added to the voltage applied to the STBY pin. Due to the strongly non-linear relationship
between switching frequency and input voltage, it is more practical to find empirically the
right amount of correction R / (R + R ) needed to minimize the change of Pout . Make
A
A
B
B
sure to choose the total value R + R much greater than R to minimize the effect on the
A
B
C
LINE pin voltage (see Section 6.6: Line sensing function on page 23).
Whichever circuit is in use, its operation can be described as follows. As the load falls below
the value Pout the frequency tries to exceed the maximum programmed value f
and the
B
max
voltage on the STBY pin (V
) goes below 1.24 V. The IC then stops with both gate-drive
STBY
outputs low, so that both MOSFETs of the half bridge leg are in OFF-state. The voltage
now increases as a result of the feedback reaction to the energy delivery stop and, as
V
STBY
it exceeds 1.29 V, the IC restarts switching. After a while, V
goes down again in
STBY
response to the energy burst and stops the IC. In this way, the converter works in a burst
mode fashion with a nearly constant switching frequency. A further load decrease then
causes a frequency reduction, which can go down even to few hundred hertz. The timing
diagram of Figure 8 illustrates this kind of operation, showing the most significant signals.
A small capacitor (typically in the hundred pF) from the STBY pin to ground, placed as close
to the IC as possible to reduce switching noise pick-up, helps obtain clean operation.
To help the designer meet energy saving requirements even in power-factor-corrected
systems, where a PFC pre-regulator precedes the DC-DC converter, the L6599AF allows
that the PFC pre-regulator can be turned off during burst mode operation, therefore
16/32
DocID028175 Rev 3
L6599AF
Application information
eliminating the no load consumption of this stage (0.51 W). There is no compliance issue in
that, because EMC regulations on low-frequency harmonic emissions refer to nominal load,
no limit is envisaged when the converter operates with light or no load.
To do so, the L6599AF provides pin 9 (PFC_STOP): it is an open collector output, normally
open, that is asserted low when the IC is idle during burst mode operation. This signal is
externally used for switching off the PFC controller and the pre-regulator, as shown in
Figure 9. When the L6599AF is in UVLO, the pin is kept open to let the PFC controller start
first.
Figure 8. Load-dependent operating modes: timing diagram
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Figure 9. How the L6599AF can switch off a PFC controller at light load
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DocID028175 Rev 3
17/32
32
Application information
L6599AF
6.3
Soft-start
Generally speaking, the purpose of soft-start is to progressively increase converter power
capability when it is started up, so as to avoid excessive inrush current. In resonant
converters the deliverable power depends inversely on frequency, soft-start is then done by
sweeping the operating frequency from an initial high value until the control loop takes over.
With the L6599AF converter, soft-startup is simply realized with the addition of an R-C
series circuit from pin 4 (RF ) to ground (see Figure 10, left).
min
Initially, the capacitor C is totally discharged, so that the series resistor R is effectively
SS
SS
in parallel to RF
and the resulting initial frequency is determined by R and RF
only,
min
SS
min
since the optocoupler phototransistor is cut off (as long as the output voltage is not too far
away from the regulated value):
Equation 4
1
fstart
3 CF
RFmin //RSS
The C capacitor is progressively charged until its voltage reaches the reference voltage
SS
(2 V) and, consequently, the current through R goes to zero. This conventionally is
SS
imposed 5 times by selecting the constants R ·C . Before reaching 2 V on C , the output
SS SS
ss
voltage should be already close to the regulated value and the feedback loop already taken
over, so that it is the optocoupler phototransistor to determine the operating frequency from
that moment onwards.
During this frequency sweep phase the operating frequency decays following the
exponential charge of C , that is, initially it changes relatively quickly but the rate of change
SS
gets slower and slower. This counteracts the non-linear frequency dependence of the tank
circuit that makes the converter power capability change little as frequency is away from
resonance and change very quickly as frequency approaches resonance frequency (see
Figure 10, right).
Figure 10. Soft-start circuit (left) and power vs. frequency curve in a resonant half bridge (right)
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As a result, the average input current smoothly increases, without the peaking that occurs
with linear frequency sweep, and the output voltage reaches the regulated value with almost
no overshoot.
18/32
DocID028175 Rev 3
L6599AF
Application information
Typically, R and C are selected based on the following relationships:
SS
SS
Equation 5
RFmin
fstart
fmin
3 103
RSS
RSS
; CSS
1
where f
is recommended to be at least 4 times f . The proposed criterion for C is
start
min
SS
quite empirical and is a compromise between an effective soft-start action and an effective
OCP (see next section). Please refer to the timing diagram of Figure 10 to see some
significant signals during the soft-start phase.
6.4
Current sense, OCP and OLP
The resonant half bridge is essentially voltage-mode controlled; therefore a current sense
input only serves as an overcurrent protection (OCP).
Unlike PWM-controlled converters, where energy flow is controlled by the duty cycle of the
primary switch (or switches), in a resonant half bridge the duty cycle is fixed and energy flow
is controlled by its switching frequency. This impacts on the way current limitation can be
realized. While in PWM-controlled converters energy flow can be limited simply by
terminating switch conduction beforehand when the sensed current exceeds a preset
threshold (this is commonly known as cycle-by-cycle limitation), in a resonant half bridge the
switching frequency, that is, its oscillator frequency must be increased and this cannot be
done as quickly as turning off a switch: it takes at least the next oscillator cycle to see the
frequency change. This implies that, to have an effective increase able to change the
energy flow significantly, the rate of change of the frequency must be slower than the
frequency itself. This, in turn, implies that cycle-by-cycle limitation is not feasible and that,
therefore, the information on the primary current fed to the current sensing input must be
somehow averaged. Of course, the averaging time must not be too long to prevent the
primary current from reaching too high values.
In Figure 11 a couple of current sensing methods are illustrated and are described in the
following. The circuit of Figure 11 a is simpler but the dissipation on the sense resistor Rs
might not be negligible, damaging efficiency; the circuit of Figure 11 b is more complex but
virtually lossless and recommended when the efficiency target is very high.
DocID028175 Rev 3
19/32
32
Application information
L6599AF
Figure 11. Current sensing techniques: a) with sense resistor, b) “lossless”, with capacitive shunt
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The L6599AF is equipped with a current sensing input (pin 6, ISEN) and a sophisticated
overcurrent management system. The ISEN pin is internally connected to the input of a first
comparator, referenced to 0.8 V, and to that of a second comparator referenced to 1.5 V. If
the voltage externally applied to the pin by either circuit in Figure 11 exceeds 0.8 V, the first
comparator is tripped and this causes an internal switch to be turned on and discharge the
soft-start capacitor C (see Section 6.3: Soft-start). This quickly increases the oscillator
SS
frequency and thereby limits energy transfer. The discharge goes on until the voltage on the
ISEN pin has dropped by 50 mV; this, with an averaging time in the range of 10/f
,
min
ensures an effective frequency rise. Under output short-circuit, this operation results in
a nearly constant peak primary current.
It is normal that the voltage on the ISEN pin may overshoot above 0.8 V; however, if the
voltage on the ISEN pin reaches 1.5 V, the second comparator is triggered, the L6599AF
shuts down and latches off with both the gate drive outputs and the PFC_STOP pin low,
therefore turning off the entire unit. The supply voltage of the IC must be pulled below the
UVLO threshold and then again above the startup level in order to restart. Such an event
may occur if the soft-start capacitor C is too large, so that its discharge is not fast enough
SS
or in the case of transformer magnetizing inductance saturation or a shorted secondary
rectifier.
In the circuit shown in Figure 11a, where a sense resistor Rs in series to the source of the
low-side MOSFET is used, note the particular connection of the resonant capacitor. In this
way the voltage across Rs is related to the current flowing through the high-side MOSFET
and is positive most of the switching period, except for the time needed for the resonant
current to reverse after the low-side MOSFET has been switched off. Assuming that the
time constant of the RC filter is at least ten times the minimum switching frequency f , the
min
approximate value of Rs can be found using the empirical equation:
Equation 6
Vspkx
ICrpkx
5 0.8
ICrpkx
4
ICrpkx
Rs
where I
is the maximum desired peak current flowing through the resonant capacitor
Crpkx
and the primary winding of the transformer, which is related to the maximum load and the
minimum input voltage.
20/32
DocID028175 Rev 3
L6599AF
Application information
The circuit shown in Figure 11 b can be operated in two different ways. If the resistor R in
A
series to C is small (not above some hundred , just to limit current spiking), the circuit
A
operates like a capacitive current divider; C is typically selected equal to Cr/100 or less and
A
is a low-loss type, the sense resistor R is selected as:
B
Equation 7
0.8
ICrpkx
Cr
CA
RB
1
and C is such that R ·C is in the range of 10 /f .
min
B
B
B
If the resistor R in series to C is not small (in this case it is typically selected in the ten
A
A
k), the circuit operates like a divider of the ripple voltage across the resonant capacitor Cr,
which, in turn, is related to its current through the reactance of Cr. Again, C is typically
A
selected equal to Cr/100 or less, not necessarily a low-loss type this time, while R
B
(provided it is << R ) according to:
A
Equation 8
R2A XC2
0.8
ICrpkx
A
RB
XCr
where the reactance of C (X ) and Cr (X ) should be calculated at the frequency where
A
CA
Cr
I
= I
. Again, C is such that R ·C is in the range of 10 /f
.
Crpk
Crpkx
B
B
B
min
Whichever circuit is used, the calculated values of Rs or R should be considered just a first
B
cut value that needs to be adjusted after experimental verification.
OCP is effective in limiting primary-to-secondary energy flow in case of an overload or an
output short-circuit, but the output current through the secondary winding and rectifiers
under these conditions might be so high as to endanger converter safety if continuously
flowing. To prevent any damage during these conditions, it is customary to force the
converter’s intermittent operation, in order to bring the average output current to values
such that the thermal stress for the transformer and the rectifiers can be easily handled.
With the L6599AF the designer can externally program the maximum time T that the
SH
converter is allowed to run overloaded or under short-circuit conditions. Overloads or short-
circuits lasting less than T do not cause any other action, therefore providing the system
SH
with immunity to short duration phenomena. If, instead, T is exceeded, an overload
SH
protection (OLP) procedure is activated that shuts down the L6599AF and, in the case of
continuous overload/short-circuit, results in continuous intermittent operation with a user-
defined duty cycle.
DocID028175 Rev 3
21/32
32
Application information
L6599AF
Figure 12. Soft-start and delayed shutdown upon overcurrent timing diagram
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This function is realized with pin 2 (DELAY), by means of a capacitor C
and a parallel
Delay
resistor R
connected to ground. As the voltage on the ISEN pin exceeds 0.8 V the first
Delay
OCP comparator, in addition to discharging C , turns on an internal current generator that
SS
sources 150 µA from the DELAY pin and charges C
. During an overload/short-circuit,
Delay
the OCP comparator and the internal current source is repeatedly activated and C
is
Delay
charged with an average current that depends essentially on the time constant of the current
sense filtering circuit on C and the characteristics of the resonant circuit; the discharge
SS
due to R
can be neglected, considering that the associated time constant is typically
Delay
much longer.
This operation continues until the voltage on C
reaches 2 V, which defines the time
Delay
T
. There is no simple relationship that links T to C
, therefore it is more practical to
SH
SH
Delay
determine C
experimentally. As a rough indication, with C
= 1 µF, T is in the
Delay SH
Delay
order of 100 ms.
Once C is charged at 2 V the internal switch that discharges C is forced low
Delay
SS
continuously regardless of the OCP comparator output, and the 150 µA current source is
continuously on, until the voltage on C
reaches 3.5 V. This phase lasts:
Delay
Equation 9
TMP 10 CDelay
with T expressed in ms and C
in µF. During this time the L6599AF runs at
Delay
MP
a frequency close to f
(see Section 6.3: Soft-start) to minimize the energy inside the
start
resonant circuit. As the voltage on C
is 3.5 V, the L6599AF stops switching and the
Delay
PFC_STOP pin is pulled low. Also the internal generator is turned off, so that C
is now
Delay
slowly discharged by R
which takes:
. The IC restarts when the voltage on C
is less than 0.3 V,
Delay
Delay
Equation 10
TSTOP RDelay CDelay ln 3.5 2.5RDelay CDelay
0.3
22/32
DocID028175 Rev 3
L6599AF
Application information
The timing diagram of Figure 12 shows this operation. Note that, if, during T
, the supply
STOP
voltage of the L6599AF (V ) falls below the UVLO threshold, the IC records the event and
CC
does not restart immediately after V exceeds the startup threshold if V(DELAY) is still
CC
higher than 0.3 V. Also the PFC_STOP pin stays low as long as V(DELAY) is greater than
0.3 V. Note also that, in the case of an overload lasting less than T , the value of T for
SH
SH
the next overload is lower if they are close to one another.
6.5
Latched shutdown
The L6599AF is equipped with a comparator having the non-inverting input externally
available at pin 8 (DIS) and with the inverting input internally referenced to 1.85 V. As the
voltage on the pin exceeds the internal threshold, the IC is immediately shut down and its
consumption reduced to a low value. The information is latched and it is necessary to let the
voltage on the V pin go below the UVLO threshold to reset the latch and restart the IC.
CC
This function is useful to implement a latched overtemperature protection very easily by
biasing the pin with a divider from an external reference voltage (e.g. pin 4, RF ), where
min
the upper resistor is an NTC physically located close to a heating element like the MOSFET,
or the secondary diode or transformer.
An OVP can be implemented as well, e.g. by sensing the output voltage and transferring an
overvoltage condition via an optocoupler.
6.6
Line sensing function
This function basically stops the IC as the input voltage to the converter falls below the
specified range and lets it restart as the voltage goes back within the range. The sensed
voltage can be either the rectified and filtered mains voltage, in which case the function acts
as a brownout protection, or, in systems with a PFC pre-regulator front-end, the output
voltage of the PFC stage, in which case the function serves as a power-on and power-off
sequencing.
L6599AF shutdown upon input undervoltage is accomplished by means of an internal
comparator, as shown in the block diagram of Figure 13, whose non-inverting input is
available at pin 7 (LINE). The comparator is internally referenced to 1.24 V and disables the
IC if the voltage applied at the LINE pin is below the internal reference. Under these
conditions the soft-start is discharged, the PFC_STOP pin is open and the consumption of
the IC is reduced. PWM operation is re-enabled as the voltage on the pin is above the
reference. The comparator is provided with current hysteresis instead of a more usual
voltage hysteresis: an internal 13 µA current sink is ON as long as the voltage applied at the
LINE pin is below the reference and is OFF if the voltage is above the reference.
This approach provides an additional degree of freedom: it is possible to set the ON
threshold and the OFF threshold separately by properly choosing the resistors of the
external divider (see below). With voltage hysteresis, instead, fixing one threshold
automatically fixes the other, depending on the built-in hysteresis of the comparator.
DocID028175 Rev 3
23/32
32
Application information
L6599AF
Figure 13. Line sensing function: internal block diagram and timing diagram
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With reference to Figure 11, the following relationships can be established for the ON
(Vin ) and OFF (Vin
) thresholds of the input voltage:
ON
OFF
Equation 11
VinON 1.24
VinOFF 1.24
1.24
RL
1.24
RL
13 106
RH
RH
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H
L
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VinON VinOFF
13 106
1.24
VinOFF 1.24
RH
;
RL RH
While the line undervoltage is active, the startup generator keeps on working but there is no
PWM activity, therefore the V voltage (if not supplied by another source) continuously
CC
oscillates between the startup and the UVLO thresholds, as shown in the timing diagram of
Figure 13.
As an additional safety measure (e.g. in case the low-side resistor is open or missing, or in
non-power factor corrected systems in case of abnormally high input voltage), if the voltage
on the pin exceeds 7 V, the L6599AF is shut down. If its supply voltage is always above the
UVLO threshold, the IC restarts as the voltage falls below 7 V.
The LINE pin, while the device is operating, is a high impedance input connected to high
value resistors, therefore it is prone to pick-up noise, which might alter the OFF threshold or
give origin to undesired switch-off of the IC during ESD tests. It is possible to bypass the pin
to ground with a small film capacitor (e.g. 1-10 nF) to prevent any malfunctioning of this
24/32
DocID028175 Rev 3
L6599AF
Application information
kind. If the function is not used, the pin must be connected to a voltage greater than 1.24 V
but lower than 6 V (worst-case value of the 7 V threshold).
6.7
Bootstrap section
The supply of the floating high-side section is obtained by means of a bootstrap circuitry.
This solution normally requires a high voltage fast recovery diode (D
, Figure 14 a) to
BOOT
charge the bootstrap capacitor C
. In the L6599AF a patented integrated structure,
BOOT
replaces this external diode. It is realized by means of a high voltage DMOS, working in the
third quadrant and driven synchronously with the low-side driver (LVG), with a diode in
series to the source, as shown in Figure 14 b.
Figure 14. Bootstrap supply: a) standard circuit; b) internal bootstrap synchronous diode
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The diode prevents any current being able to flow from the VBOOT pin back to V , in case
CC
the supply is quickly turned off when the internal capacitor of the pump is not fully
discharged. To drive the synchronous DMOS a voltage higher than the supply voltage V
CC
is necessary. This voltage is obtained by means of an internal charge pump (Figure 14 b).
The bootstrap structure introduces a voltage drop while recharging CBOOT (i.e. when the
low-side driver is on), which increases with the operating frequency and with the size of the
external power MOSFET. It is the sum of the drop across the R
and the forward drop
(DS)ON
across the series diode. At low frequency this drop is very small and can be neglected but,
as the operating frequency increases, it must be taken into account. In fact, the drop
reduces the amplitude of the driving signal and can significantly increase the R
external high-side MOSFET and then its conductive loss.
of the
(DS)ON
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Application information
L6599AF
This concern applies to converters designed with a high resonance frequency (indicatively,
> 150 kHz), so that they run at high frequency also at full load. Otherwise, the converter runs
at high frequency at light load, where the current flowing in the MOSFETs of the half bridge
leg is low, so that, generally, an R
rise is not an issue. However, it is wise to check this
(DS)ON
point anyway and the following equation is useful to compute the drop on the bootstrap
driver:
Equation 13
Qg
VDrop IchargeR(DS)on VF
R(DS)on VF
Tcharge
where Q is the gate charge of the external power MOSFET, R
is the on-resistance of
(DS)ON
g
the bootstrap DMOS (150 W, typ.) and T
is the ON-time of the bootstrap driver, which
charge
equals about half the switching period minus the deadtime T . For example, using
D
a MOSFET with a total gate charge of 30 nC, the drop on the bootstrap driver is about 3 V at
a switching frequency of 200 kHz:
Equation 14
30 109
2.5 106 0.27 106
VDrop
150 0.6 2.7 V
If a significant drop on the bootstrap driver is an issue, an external ultra-fast diode can be
used, therefore saving the drop on the R of the internal DMOS.
(DS)ON
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Application information
Figure 15. Application example: 90 W AC/DC adapter using L6563H, L6599AF and SRK2000
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Package information
L6599AF
7
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
®
ECOPACK packages, depending on their level of environmental compliance. ECOPACK
specifications, grade definitions and product status are available at www.st.com.
ECOPACK is an ST trademark.
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L6599AF
Package information
7.1
SO16N package information
Figure 16. SO16N package outline
ꢀꢀꢁꢉꢀꢂꢀB)
Table 6. SO16N package mechanical data
Dimensions (mm)
Symbol
Min.
Typ.
Max.
A
A1
A2
b
1.75
0.25
0.10
1.25
0.31
0.17
9.80
5.80
3.80
0.51
0.25
10.00
6.20
4.00
c
D
9.90
6.00
3.90
1.27
E
E1
e
h
0.25
0.40
0
0.50
1.27
8°
L
k
ccc
0.10
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Package information
L6599AF
Figure 17. SO16N recommended footprint (dimensions are in mm)
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Revision history
8
Revision history
Table 7. Document revision history
Changes
Date
Revision
29-Jul-2015
1
Initial release.
Document status promoted from Target specification to Production
data.
26-Aug-2015
27-Aug-2015
2
3
Updated document title and product features.
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L6599AF
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© 2015 STMicroelectronics – All rights reserved
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