EMIF01-10018W5 [STMICROELECTRONICS]
EMI FILTER INCLUDING ESD PROTECTION; EMI滤波器，它包括ESD保护
| 型号： | EMIF01-10018W5 |
| 厂家： | 
ST |
| 描述： | EMI FILTER INCLUDING ESD PROTECTION |
| 文件： | 总10页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EMIF01-10018W5
®
EMI FILTER
INCLUDING ESD PROTECTION
Application Specific Discretes
A.S.D.TM
MAIN APPLICATIONS
Where EMI filtering in ESD sensitive equipment is required :
Computers and printers
Communication systems
Mobile phones
MCU Boards
DESCRIPTION
The EMIF01-10018W5 is a highly integrated array
designed to suppress EMI / RFI noise in all systems
subjected to electromagnetic interferences.
SOT323-5L
Additionally, this filter includes an ESD protection circuitry
which prevents the protected device from destruction when
subjected to ESD surges up to 15 kV.
FUNCTIONAL DIAGRAM
BENEFITS
I1
O1
O2
Cost-effectiveness compared to discrete solution
EMI bi-directional low-pass filter
High efficiency in ESD suppression.
High flexibility in the design of high density boards
Very low PCB space consuming : 4.2 mm2 typically
High reliability offered by monolithic integration
GND
I2
COMPLIES WITH THE FOLLOWING STANDARD:
IEC 1000-4-2
15kV
level 4 8 kV
(air discharge)
(contact discharge)
RI/O = 100Ω
CIN = 180pF
MIL STD 883C - Methode 3015-6 Class 3
Filtering behavior
ESD response to IEC1000-4-2 (16 kV air discharge)
dB
0
-10
-20
-30
-40
Vin
Vout
1
10
100
1,000 2,000
f(MHz)
TM : ASD is trademark of STMicroelectronics.
September 1999 - Ed: 1
1/10
EMIF01-10018W5
ABSOLUTE MAXIMUM RATINGS (Tamb = 25 °C)
Symbol
Parameter and test conditions
Value
Unit
VPP
ESD discharge IEC1000-4-2, air discharge
ESD discharge IEC1000-4-2, contact discharge
ESD discharge MIL STD 883 Method 3015-6
16
9
25
kV
Tj
Junction temperature
150
°C
°C
°C
°C
Top
Tstg
TL
Operating temperature range
Storage temperature range
-40 to + 85
-55 to +150
260
Lead solder temperature (10 seconds duration)
ELECTRICAL CHARACTERISTICS (Tamb = 25 °C)
Symbol
VBR
IRM
Parameter
Breakdown voltage
I
Leakage current @ VRM
Stand-off voltage
VRM
VCL
VCL VBR VRM
Clamping voltage
V
IRM
IR
Rd
Dynamic resistance
Peak pulse current
IPP
slope : 1 / R
d
IPP
RI/O
Series resistance between Input
and Output
CIN
Input capacitance per line
Symbol
VBR
IRM
Test conditions
IR = 1 mA
Min.
Typ.
Max.
8
Unit
V
6
7
VRM = 3V
100
120
nA
Ω
RI/O
Rd
80
100
1
µ
Ω
Ipp = 10 A, tp = 2.5 s (see note 1)
CIN
at 0V bias
180
pF
Note 1 : to calculate the ESD residual voltage, please refer to the paragraph "ESD PROTECTION" on pages 4 & 5
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EMIF01-10018W5
TECHNICAL INFORMATION
FREQUENCY BEHAVIOR
The EMIF01-10018W5 is firstly designed as an EMI/RFI filter. This low-pass filter is characterized by the following
parameters:
- Cut-off frequency
- Insertion loss
- High frequency rejection
Fig A1: EMIF01-10018W5 frequency response curve.
dB
0
-10
-20
-30
-40
1
10
100
1,000 2,000
f(MHz)
Figure A1 gives these parameters, in particular the signal rejection at the GSM frequency is about
-24dB @ 900MHz
-20dB @ 1800MHz
Fig. A2: Measurement conditions
TRACKING GENERATOR
SPECTRUM ANALYSER
RF IN
TEST BOARD
SMA
SMA
50Ω
TG OUT
50Ω
Vg
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EMIF01-10018W5
ESD PROTECTION
In addition to its filtering function, the EMIF01-10018W5 is particularly optimized to perform ESD protection.
ESD protection is based on the use of device which clamps at :
VCL = VBR + Rd.IPP
This protection function is splitted in 2 stages. As shown in figure A3, the ESD strikes are clamped by the first stage S1 and
then its remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output
voltage very low at the Vout level.
Fig. A3: ESD clamping behavior.
Rg
R
Rd
Rd
ESD
Surge
Vg
Rload
Vout
Vin
Vbr
Vbr
S2
S1
Device to be protected
EMIF01-10018W5
To have a good approximation of the remaining voltages at both Vin and Vout stages, we provide the typical dynamical
resistance value Rd. By taking into account these following hypothesis : R>>Rd, R >>Rd and Rload>>Rd, it gives these
G
formulas:
Rg Vbr+Rd Vg
.
.
Vin =
Rg
R Vbr+Rd Vin
.
.
Vout =
R
The results of the calculation done for an IEC 1000-4-2 Level 4 Contact Discharge surge (Vg=8kV, Rg=330Ω) and V =7V
BR
(typ.) give:
Vin = 31.2 V
Vout = 7.3 V
This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this
approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at
the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R.
LATCH-UP PHENOMENA
The early ageing and destruction of IC’s is often due to latch-up phenomena which mainly induced by dV/dt. Thanks to
its RC structure, the EMIF01-10018W5 provides a high immunity to latch-up by integration of fast edges. (Please see the
response of EMIF01-10018W5 to a 3 ns edge on Fig. A9)
The measurements done here after show very clearly (Fig. A5a & A5b) the high efficiency of the ESD protection :
- almost no influence of the parasitic inductances on Vout stage
- Vout clamping voltage very close to Vbr
Fig. A4: Measurement conditions
ESD
SURGE
TEST BOARD
16kV
Air
Vin
Vout
Discharge
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EMIF01-10018W5
Fig. A5: Remaining voltage at both stages S1 (Vin) and S2 (Vout) during ESD surge
Vin
Vin
Vout
Vout
a) Positive surge
b) Negative surge
Please note that the EMIF01-10018W5 is not only acting for positive ESD surges but also for negative ones. For negatives
surges, it clamps close to ground voltage as shown in Fig. A5b.
NOTE: DYNAMIC RESISTANCE MEASUREMENT
Fig. A6: Rd measurement current wave
I
I
PP
t
2 µs
2.5 µs
2.5 µs duration measurement wave
As the value of the dynamic resistance remains stable for
a surge duration lower than 20µs, the 2.5µs rectangular
surge is well adapted. In addition both rise and fall times
are optimized to avoid any parasitic phenomenon during
the measurement of Rd.
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EMIF01-10018W5
CROSSTALK BEHAVIOR
1- Crosstalk phenomena
Fig. A7: Crosstalk phenomena
RG1
line 1
line 2
β
α
1VG1 12VG2
+
VG1
RL1
RG2
VG2
RL2
α 2
VG2
β
+
21VG1
DRIVERS
RECEIVERS
The crosstalk phenomena are due to the coupling between 2 lines. The coupling factor ( β or β ) increases when the
12
21
gap across lines decreases, particularly in silicon dice. In the example above the expected signal on load R is α2V , in
L2
G2
fact the real voltage at this point has got an extra value β21V . This part of the V signal represents the effect of the
G1
G1
crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose
fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works
with low voltage signal or high load impedance (few kΩ). The following chapters give the value of both digital and analog
crosstalk.
2- Digital Crosstalk
Fig. A8: Digital crosstalk measurement
+5V
+5V
74HC04
74HC04
Line 1
EMIF01
10018W5
VG1
+5V
Square
Pulse
Line 2
Generator
5KHz
β
21 VG1
Figure A8 shows the measurement circuit used to quantify the crosstalk effect in a classical digital application.
Figure A9 shows that in such a condition signal from 0 to 5V and rise time of few ns, the impact on the disturbed line is less
than 50mV peak to peak. No data disturbance was noted on the concerned line.The measurements performed with falling
edges gives an impact within the same range.
Fig. A9: Digital crosstalk results
V
G1
β
V
21 G1
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EMIF01-10018W5
3- Analog Crosstalk
Fig. A10: Analog crosstalk measurement
TRACKING GENERATOR
SPECTRUM ANALYSER
RF IN
TEST BOARD
SMA
SMA
50Ω
TG OUT
EMIF01
50Ω
Vg
Fig. A11: Typical analog crosstalk result
dB
0
-20
-40
-60
-80
-100
1
10
100
1,000 2,000
f(MHz)
Figure A10 gives the measurement circuit for the analog application. In figure A11, the curve shows the effect of cell I/O1
on cell I/O2. In usual frequency range of analog signals (up to 100MHz) the effect on disturbed line is less than -42 dB.
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EMIF01-10018W5
4 - PSpice model
Fig. A13: PSpice parameters
Fig. A12: PSpice model of one EMIF01 cell
1.2nH
100
Ω
1.2nH
Dz
Df
1000
85p
Dr
1000
1p
IN
OUT
BV
Cjo
IBV
IKF
IS
ISR
N
M
7
85p
1u
1000
10E-15
100p
1
0.3333
1
0.6
Dz
Dr
Df
Df
Dz
Dr
1u
1u
1000
1.016E-15
100p
1.0755
0.3333
1
1000
10E-15
100p
0.6
0.3333
1m
0.38nH
RS
VJ
TT
0.6
50n
0.6
1n
50n
GND
Note: This model is available for an ambient temperature of 27°C
Fig. A14: PSpice simulation : IEC 1000-4-2 Contact Discharge response
a) Positive surge b) Negative surge
(V)
(V)
0
60
Vin
Vin
50
40
30
20
10
0
-10
-20
-30
-40
-50
-60
Vout
Vout
0
20
40
60
80
100
0
20
40
60
80
100
t(ns)
t(ns)
Fig. A15: Comparison between PSpice
simulation and measured frequency response
dB
0
Measure
PSpice
-10
-20
-30
-40
1
10
100
1,000 2,000
f(MHz)
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EMIF01-10018W5
ORDER CODE
EMIF
01 - 100
18
W5
SOT323-5L package
Input capacitance value /10
EMI FILTER
TYPE
Series resistance value
Delivery
mode
Order code
Marking
Package
Weight
Base qty
EMIF01-10018W5
N12
SOT323-5L
5.4 mg
3000
Tape & reel
9/10
EMIF01-10018W5
PACKAGE MECHANICAL DATA
SOT323-5L
DIMENSIONS
Millimeters Inches
Min. Max. Min.
0.8 1.1
REF.
A
A2
Max.
0.043
0.004
0.039
0.012
0.007
0.086
0.053
A
A1
A2
b
0.031
0
A1
0
0.1
1
0.8
0.031
0.006
0.004
0.071
0.045
D
0.15
0.1
0.3
0.18
2.2
1.35
e
e
c
D
1.8
E
1.15
H
E
e
0.65 Typ.
H
1.8
0.1
2.4
0.4
0.071
0.004
0.094
0.016
Q1
Q1
c
b
RECOMMENDED FOOTPRINT
0.3mm
Mechanical specifications
Lead plating Tin-lead
1mm
µ
Lead plating thickness 5 m min.
µ
25 m max.
Lead material
Sn / Pb
(70% to 90% Sn)
29mm
µ
Lead coplanarity
Body material
Flammability
100 m max.
Molded epoxy
UL94V-0
1mm
0.35mm
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of
use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied.
STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written ap-
proval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 1999 STMicroelectronics - Printed in Italy - All rights reserved.
STMicroelectronics GROUP OF COMPANIES
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