74VHCT273 [STMICROELECTRONICS]
OCTAL D-TYPE FLIP FLOP WITH CLEAR; 八路D型触发器与Clear FLOP
| 型号： | 74VHCT273 |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE FLIP FLOP WITH CLEAR |
| 文件： | 总9页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHCT273A
OCTAL D-TYPE FLIP FLOP WITH CLEAR
■
■
■
■
■
■
■
■
HIGH SPEED:
MAX =170MHz(TYP.) at VCC =5V
f
LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25 oC
COMPATIBLEWITH TTL OUTPUTS:
VIH =2V (MIN), VIL = 0.8V(MAX)
POWERDOWN PROTECTIONON INPUTS&
OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
M
T
(Micro Package)
(TSSOPPackage)
ORDER CODES :
74VHCT273AM
74VHCT273AT
technology.
Information signals applied to D inputs are
transfered to the Q outputs on the positive going
edge of the clock pulse.
When the CLEAR input is held low, the Q outputs
are held low independentlyof the other inputs .
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used to interface 5V to 3V.
OPERATING VOLTAGERANGE:
VCC (OPR)= 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES273
IMPROVED LATCH-UP IMMUNITY
LOWNOISE:VOLP = 0.9V(Max.)
■
■
DESCRIPTION
The 74VHCT273A is an advanced high-speed
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
CMOS OCTAL
CLEAR fabricated with sub-micron silicon gate
and double-layer metal wiring
C2MOS
D-TYPE FLIP FLOP WITH
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/9
November 1999
74VHCT273A
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
CLEAR
Asyncronous Master
Reset (Active LOW)
2, 5, 6, 9,
12, 15, 16,
19
Q0 to Q7 Flip-Flop Outputs
3, 4, 7, 8,
13, 14, 17,
18
D0 to D7 Data Inputs
11
CLOCK
Clock Input
(LOW-to-HIGH, Edge-
Triggered)
10
20
GND
VCC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
FUNCTION
CLEAR
D
X
L
CLOCK
Q
L
L
H
H
H
X
CLEAR
L
H
X
H
Qn
NO CHANGE
X:Don’t Care
LOGIC DIAGRAM
Thislogic diagram has notbe used to esimate propagation delays
2/9
74VHCT273A
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to VCC + 0.5
- 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage (see note 1)
DC Output Voltage (see note 2)
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
VO
V
IIK
mA
mA
mA
mA
oC
oC
IOK
20
25
±
±
IO
ICC or IGND DC VCC or Ground Current
± 50
-65 to +150
300
Tstg
Storage Temperature
TL
Lead Temperature (10 sec)
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
1)VCC=0
2)High or Low State
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
4.5 to 5.5
0 to 5.5
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage (see note 1)
Output Voltage (see note 2)
Operating Temperature
0 to 5.5
V
VO
0 to VCC
-40 to +85
0 to 20
V
oC
Top
dt/dv
ns/V
Input Rise and Fall Time (see note 3) (VCC = 5.0 0.5V)
±
1)VCC=0
2)High or Low State
3)VIN from0.8Vto2 V
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
VCC
Value
TA = 25 oC
Unit
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
VIH
VIL
High Level Input
Voltage
4.5 to 5.5
2
2
V
V
Low Level Input
Voltage
4.5 to 5.5
0.8
0.8
VOH
High Level Output
Voltage
4.5
4.5
IO=-50 µA
IO=-8 mA
4.4
4.5
0.0
4.4
3.8
V
3.94
VOL
Low Level Output
Voltage
4.5
IO=50 µA
0.1
0.36
±0.1
4
0.1
0.44
±1.0
40
V
4.5
IO=8 mA
II
Input Leakage Current
0 to 5.5
5.5
VI = 5.5V or GND
VI = VCC or GND
µA
ICC
Quiescent Supply
Current
A
µ
∆ICC
Additional Worst Case
Supply Current
5.5
0
One Input at 3.4V,
other input at VCC or
GND
1.35
0.5
1.5
5.0
mA
IOPD
Output Leakage
Current
VOUT = 5.5V
µA
3/9
74VHCT273A
AC ELECTRICAL CHARACTERISTICS
(Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
CL
(pF)
-40 to 85 oC
tPLH
tPHL
Propagation Delay
Time CK to Q
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0(*)
15
50
15
50
5.6
6.3
6.9
7.7
8.2
9.2
1.0
1.0
1.0
1.0
5.0
10.0
11.0
11.6
12.6
ns
tPHL
Propagation Delay
Time CLR to Q
10.0
11.0
ns
ns
tw
tw
CLR pulse Width
LOW
5.0
5.0
2.0
2.0
1.0
CK pulse Width
HIGH or LOW
5.0(*)
5.0(*)
5.0(*)
5.0(*)
5.0
2.0
2.0
1.0
ns
ns
ns
ns
ts
Setup Time D to CK
HIGH or LOW
th
Hold Time D to CK
HIGH or LOW
tREM
fMAX
Removal Time
CLR to CK
Maximum Clock
Frequency
5.0(*)
5.0(*)
5.0(*)
15
50
75
50
170
160
65
45
MHz
ns
tOSLH Output to Output Skew
tOSHL
1.0
1.0
50
Time (note 1)
(*) Voltagerangeis5V ± 0.5V
Note1:Parameter guaranteed bydesign. tsoLH =|tpLHm-tpLHn|,tsoHL =|tpHLm -tpHLn
|
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
-40 to 85 oC
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
4
10
10
pF
pF
CPD
Power Dissipation
15
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operating current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/8(per Flip-Flop)
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
VCC
(V)
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
-40 to 85 oC
VOLP Dynamic Low Voltage
5.0
0.6
0.9
Quiet Output (note 1, 2)
VOLV
-0.9
2.0
-0.6
VIHD
VILD
Dynamic High Voltage
Input (note 1, 3)
5.0
5.0
CL = 50 pF
V
Dynamic Low Voltage
Input (note 1, 3)
0.8
1)Worstcase package.
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto3.0V, (n -1)outputs switching andone outputatGND.
3)Max number ofdatainputs (n)switching.(n-1)switching 0Vto3.0V. Inputsunder testswitching: 3.0Vtothreshold (VILD),0V tothreshold (VIHD),f=1MHz.
4/9
74VHCT273A
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RT = ZOUT ofpulse generator (typically50Ω)
WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES
(f=1MHz; 50% duty cycle)
5/9
74VHCT273A
WAVEFORM 2: PROPAGATION DELAYS
(f=1MHz; 50% duty cycle)
WAVEFORM 3: REMOVAL TIME (f=1MHz; 50% duty cycle)
6/9
74VHCT273A
SO-20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45 (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8 (max.)
P013L
7/9
74VHCT273A
TSSOP20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.260
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
6.4
0.10
0.9
0.15
0.95
0.30
0.2
0.002
0.335
0.0075
0.0035
0.252
0.246
0.169
0.004
0.354
c
D
6.5
6.4
6.6
0.256
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
8/9
74VHCT273A
Information furnished isbelieved to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. Thispublication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in lifesupport devices or systems withoutexpress written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
1999 STMicroelectronics – Printed in Italy – All Rights Reserved
STMicroelectronics GROUP OF COMPANIES
Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan- Malaysia - Malta - Morocco
Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A.
http://www.st.com
.
9/9
相关型号：
©2020 ICPDF网 联系我们和版权申明