74VHC373 [STMICROELECTRONICS]
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING; 八D型具有三态输出的非反相锁存
| 型号： | 74VHC373 |
| 厂家： | 
ST |
| 描述： | OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING |
| 文件： | 总10页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74VHC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUT NON INVERTING
■
■
HIGH SPEED:tPD =5.0ns (TYP.) atVCC = 5V
LOW POWER DISSIPATION:
ICC =4 µA (MAX.) at TA =25 oC
HIGH NOISEIMMUNITY:
■
M
T
VNIH = VNIL =28% VCC (MIN.)
POWERDOWN PROTECTIONON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 8 mA (MIN)
(Micro Package)
(TSSOPPackage)
■
■
ORDER CODES :
74VHC373M
74VHC373T
■
■
■
BALANCEDPROPAGATIONDELAYS:
tPLH tPHL
OPERATING VOLTAGERANGE:
While the LE input is held at a high level, the Q
outputswill follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
VCC (OPR)= 2V to 5.5V
PIN AND FUNCTION COMPATIBLEWITH
74 SERIES373
IMPROVED LATCH-UP IMMUNITY
LOWNOISE:VOLP = 0.9V(Max.)
■
■
DESCRIPTION
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
The 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C2MOS technology.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
PIN CONNECTION AND IEC LOGIC SYMBOLS
1/10
June 1999
74VHC373
INPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
PIN No
SYMBOL NAME AND FUNCTION
1
OE
3 State Output Enable
Input (Active LOW)
2, 5, 6,
9, 12, 15,
16, 19
D0 to D7 Data Inputs
3, 4, 7,
8, 13, 14,
17, 18
Q0 to Q7 3 State Outputs
11
LE
Latch Enable
Input
10
20
GND
VCC
Ground (0V)
Positive Supply Voltage
TRUTH TABLE
INPUTS
OUTPUTS
OE
H
LE
X
D
Q
X
X
L
Z
L
L
NO CHANGE *
L
H
L
L
X:DON’TCARE
H
H
H
Z:HIGHIMPEDANCE
*:Q OUTPUTSARELATCHEDATTHETIMEWHENTHELEINPUT ISTAKENLOWLOGIC LEVEL.
LOGIC DIAGRAM
2/10
74VHC373
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VI
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to VCC + 0.5
- 20
Unit
V
Supply Voltage
DC Input Voltage
V
VO
DC Output Voltage
DC Input Diode Current
DC Output Diode Current
DC Output Current
V
IIK
mA
mA
mA
mA
oC
IOK
± 20
IO
25
75
±
±
ICC or IGND DC VCC or Ground Current
Tstg
TL
Storage Temperature
-65 to +150
300
Lead Temperature (10 sec)
oC
AbsoluteMaximum Ratingsarethose values beyond whichdamage tothe device may occur. Functional operation under these condition isnot implied.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VI
Parameter
Value
2.0 to 5.5
0 to 5.5
Unit
V
Supply Voltage
Input Voltage
V
VO
Output Voltage
0 to VCC
-40 to +85
V
oC
Top
Operating Temperature
dt/dv
0 to 100
0 to 20
ns/V
ns/V
Input Rise and Fall Time (see note 1) (VCC = 3.3 0.3V)
±
(V CC = 5.0 ± 0.5V)
1)VIN from30% to70%of VCC
DC SPECIFICATIONS
Symbol
Parameter
Test Conditions
VCC
Value
TA = 25 oC
Unit
-40 to 85 oC
(V)
Min. Typ. Max. Min. Max.
VIH
VIL
High Level Input
Voltage
2.0
3.0 to 5.5
2.0
1.5
1.5
V
V
0.7VCC
0.7VCC
Low Level Input
Voltage
0.5
0.5
3.0 to 5.5
2.0
0.3VCC
0.3VCC
VOH
High Level Output
Voltage
IO=-50
A
1.9
2.9
2.0
3.0
4.5
1.9
2.9
µ
3.0
I =-50
O
A
µ
V
4.5
IO=-50 µA
IO=-4 mA
IO=-8 mA
IO=50 µA
4.4
4.4
3.0
2.58
3.94
2.48
3.8
4.5
VOL
Low Level Output
Voltage
2.0
0.0
0.0
0.0
0.1
0.1
0.1
0.1
3.0
I =50 A
µ
O
V
4.5
IO=50 µA
IO=4 mA
IO=8 mA
0.1
0.1
3.0
0.36
0.36
±0.25
0.44
0.44
±2.5
4.5
IOZ
High Impedance
Output Leakage
Current
VI = VIH or VIL
VO = VCC or GND
µA
5.5
II
Input Leakage Current
0 to 5.5
5.5
VI = 5.5V or GND
VI = VCC or GND
0.1
±
4
1.0
A
A
±
µ
µ
ICC
Quiescent Supply
Current
40
3/10
74VHC373
AC ELECTRICAL CHARACTERISTICS
(Input tr = tf =3 ns)
Symbol
Parameter
Test Condition
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
VCC
(V)
CL
(pF)
-40 to 85 oC
tPLH
tPHL
Propagation Delay
Time
LE to Q
3.3(*)
3.3(*)
15
50
7.0
9.5
4.9
6.4
7.3
9.8
5.0
6.5
7.3
9.8
5.5
7.0
9.5
6.5
11.0
14.5
7.2
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
13.0
16.5
8.5
ns
ns
ns
5.0(**)
5.0(**)
3.3(*)
3.3(*)
5.0(**)
5.0(**)
3.3(*)
3.3(*)
5.0(**)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
3.3(*)
5.0(**)
15
50
15
50
15
50
15
50
15
50
50
50
9.2
10.5
13.5
17.0
8.5
tPLH
tPHL
Propagation Delay
Time
D to Q
11.4
14.9
7.2
9.2
10.5
13.5
17.0
9.5
tPZL
tPZH
Output EnableTime
RL = 1KΩ
RL = 1KΩ
RL = 1KΩ
RL = 1KΩ
11.4
14.9
8.1
10.1
13.2
9.2
11.5
15.0
10.5
5.0
tPLZ
tPHZ
Output Disable Time
R = 1K
Ω
L
ns
ns
ns
RL = 1KΩ
tw
ts
th
Pulse Width (LE)
HIGH
5.0
5.0
5.0
Setup Time D to LE
HIGH or LOW
4.0
4.0
4.0
4.0
Hold Time D toLE
HIGH or LOW
3.3(*)
5.0(**)
3.3(*)
5.0(**)
1.0
1.0
1.0
1.0
ns
ns
tOSLH Output to Output Skew
tOSHL
50
50
1.5
1.0
1.5
1.0
Time (note 1)
(*) Voltagerangeis3.3V ± 0.3V
(**) Voltagerange is 5V± 0.5V
Note1:Parameter guaranteed bydesign. tsoLH =|tpLHm-tpLHn|,tsoHL =|tpHLm -tpHLn
|
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Test Conditions
Value
TA = 25 oC
Unit
-40 to 85 oC
Min. Typ. Max. Min. Max.
CIN
Input Capacitance
4
6
10
10
pF
pF
pF
COUT Output Capacitance
CPD
Power Dissipation
27
Capacitance (note 1)
1)CPD isdefined as thevalue ofthe IC’sinternal equivalent capacitance whichiscalculated fromthe operating current consumption without load. (Referto
TestCircuit).Average operating current can beobtained bythe followingequation. ICC(opr)= CPD • VCC • fIN + ICC/8(per Latch)
4/10
74VHC373
DYNAMIC SWITCHING CHARACTERISTICS
Symbol
Parameter
Test Conditions
VCC
(V)
Value
TA = 25 oC
Min. Typ. Max. Min. Max.
Unit
-40 to 85 oC
VOLP Dynamic Low Voltage
5.0
0.6
0.9
Quiet Output (note 1, 2)
VOLV
-0.9
3.5
-0.6
VIHD
VILD
Dynamic High Voltage
Input (note 1, 3)
5.0
5.0
CL = 50 pF
V
Dynamic Low Voltage
Input (note 1, 3)
1.5
1)Worstcase package.
2)Max number ofoutputs defined as (n). Datainputs aredriven 0Vto5.0V, (n -1)outputs switching andone outputatGND.
3)Max number ofdatainputs (n)switching.(n-1)switching 0Vto5.0V. Inputsunder testswitching: 5.0Vtothreshold (VILD),0V tothreshold (VIHD),f=1MHz.
TEST CIRCUIT
TEST
SWITCH
Open
VCC
tPLH, tPHL
tPZL, tPLZ
tPZH, tPHZ
GND
CL = 15/50 pF or equivalent (includes jig and probe capacitance)
RL =R1 =1KΩ orequivalent
RT = ZOUT ofpulse generator (typically50Ω)
5/10
74VHC373
WAVEFORM 1: LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH,
Dn TO LE SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
6/10
74VHC373
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES
(f=1MHz; 50% duty cycle)
WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
7/10
74VHC373
SO-20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
2.65
0.20
2.45
0.49
0.32
MIN.
MAX.
0.104
0.007
0.096
0.019
0.012
A
a1
a2
b
0.10
0.004
0.35
0.23
0.013
0.009
b1
C
0.50
0.020
c1
D
45 (typ.)
12.60
10.00
13.00
10.65
0.496
0.393
0.512
0.419
E
e
1.27
0.050
0.450
e3
F
11.43
7.40
0.50
7.60
1.27
0.75
0.291
0.19
0.299
0.050
0.029
L
M
S
8 (max.)
P013L
8/10
74VHC373
TSSOP20 MECHANICAL DATA
mm
inch
TYP.
DIM.
MIN.
TYP.
MAX.
1.1
MIN.
MAX.
0.433
0.006
0.374
0.0118
0.0079
0.260
0.256
0.176
A
A1
A2
b
0.05
0.85
0.19
0.09
6.4
0.10
0.9
0.15
0.95
0.30
0.2
0.002
0.335
0.0075
0.0035
0.252
0.246
0.169
0.004
0.354
c
D
6.5
6.4
6.6
0.256
0.252
E
6.25
4.3
6.5
E1
e
4.4
4.48
0.173
0.65 BSC
4o
0.0256 BSC
4o
K
0o
8o
0o
8o
L
0.50
0.60
0.70
0.020
0.024
0.028
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
9/10
74VHC373
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subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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