74VHC373M [FAIRCHILD]
Octal D-Type Latch with 3-STATE Outputs; 八D型锁存器带3态输出
| 型号： | 74VHC373M |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Octal D-Type Latch with 3-STATE Outputs |
| 文件： | 总8页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1993
Revised April 2005
74VHC373
Octal D-Type Latch with 3-STATE Outputs
General Description
Features
The VHC373 is an advanced high speed CMOS octal D-
type latch with 3-STATE output fabricated with silicon gate
CMOS technology. It achieves the high speed operation
similar to equivalent Bipolar Schottky TTL while maintain-
ing the CMOS low power dissipation. This 8-bit D-type
latch is controlled by a latch enable input (LE) and an out-
put enable input (OE). The latches appear transparent to
data when latch enable (LE) is HIGH. When LE is LOW, the
data that meets the setup time is LATCHED. When the OE
input is HIGH, the eight outputs are in a high impedance
state.
■ High Speed: tPD 5.0 ns (typ) @ VCC 5V
■ High Noise Immunity: VNIH VNIL 28% VCC (Min)
■ Power Down Protection is provided on all inputs
■ Low Noise: VOLP 0.6V (typ)
■ Low Power Dissipation: ICC
4 A (Max) @ TA 25 C
■ Pin and Function Compatible with 74HC373
An input protection circuit ensures that 0V to 7V can be
applied to the input pins without regard to the supply volt-
age. This device can be used to interface 5V to 3V systems
and two supply systems such as battery back up. This cir-
cuit prevents device destruction due to mismatched supply
and input voltages.
Ordering Code:
Order Number Package Number
Package Description
74VHC373M
74VHC373SJ
74VHC373MTC
74VHC373N
M20B
M20D
MTC20
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Logic Symbol
Connection Diagram
IEEE/IEC
© 2005 Fairchild Semiconductor Corporation
DS011555
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Pin Descriptions
Truth Table
Pin Names
Description
Data Inputs
Inputs
Outputs
On
D0–D7
LE
OE
Dn
LE
Latch Enable Input
X
H
H
L
H
L
L
L
X
L
Z
L
OE
Output Enable Input
3-STATE Outputs
O0–O7
H
X
H
O0
H
L
Z
X
O
HIGH Voltage Level
LOW Voltage Level
High Impedance
Immaterial
Previous O before HIGH-to-LOW transition of Latch Enable
0
0
Functional Description
The VHC373 contains eight D-type latches with 3-STATE
standard outputs. When the Latch Enable (LE) input is
HIGH, data on the Dn inputs enters the latches. In this con-
sition of LE. The 3-STATE standard outputs are controlled
by the Output Enable (OE) input. When OE is LOW, the
standard outputs are in the 2-state mode. When OE is
HIGH, the standard outputs are in the high impedance
mode but this does not interfere with entering new data into
the latches.
dition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions (Note 2)
Supply Voltage (VCC
DC Input Voltage (VIN
DC Output Voltage (VOUT
)
0.5V to 7.0V
0.5V to 7.0V
0.5V to VCC 0.5V
20 mA
)
Supply Voltage (VCC
Input Voltage (VIN
Output Voltage (VOUT
Operating Temperature (TOPR
)
2.0V to 5.5V
0V to 5.5V
0V to VCC
)
)
Input Diode Current (IIK
Output Diode Current
)
)
20 mA
)
40 C to 85 C
DC Output Current (IOUT
)
25 mA
Input Rise and Fall Time (tr, tf)
VCC 3.3V 0.3V
DC VCC/GND Current (ICC
)
75 mA
0
100 ns/V
Storage Temperature (TSTG
Lead Temperature (TL)
(Soldering, 10 seconds)
)
65 C to 150 C
VCC 5.0 0.5V
0 20 ns/V
Note 1: Absolute Maximum Ratings are values beyond which the device
may be damaged or have its useful life impaired. The databook specifica-
tions should be met, without exception, to ensure that the system design is
reliable over its power supply, temperature, and output/input loading vari-
ables. Fairchild does not recommend operation outside databook specifica-
tions.
260 C
Note 2: Unused inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
V
T
25 C
Typ
T
A
40 C to 85 C
Max
CC
A
Symbol
Parameter
Units
Conditions
(V)
Min
Max
Min
1.50
0.7 V
V
V
V
HIGH Level
2.0
1.50
IH
V
V
Input Voltage
LOW Level
3.0 5.5 0.7 V
2.0
CC
CC
0.50
0.50
0.3 V
IL
Input Voltage
HIGH Level
Output Voltage
3.0 5.5
0.3 V
CC
CC
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
1.9
2.0
3.0
4.5
1.9
2.9
V
V
V
I
50 A
OH
IN
IH
OH
2.9
4.4
V
V
V
or V
IL
4.4
2.58
3.94
2.48
3.80
I
I
I
4 mA
8 mA
OH
OH
OL
V
LOW Level
0.0
0.0
0.0
0.1
0.1
0.1
0.1
V
IH
50 A
OL
IN
Output Voltage
or V
IL
0.1
0.1
0.36
0.36
0.25
0.44
0.44
2.5
I
I
4 mA
8 mA
OL
OL
V
A
I
3-STATE Output
V
V
V
V
V
or V
IL
OZ
IN
IH
Off-State Current
V or GND
CC
OUT
IN
I
I
Input Leakage Current
Quiescent Supply Current
0
5.5
5.5
0.1
4.0
1.0
A
A
5.5 or GND
V or GND
CC
IN
40.0
CC
IN
Noise Characteristics
V
T
25 C
CC
(V)
5.0
A
Symbol
Parameter
Quiet Output Maximum Dynamic V
Units
Conditions
Typ
Limits
V
0.6
0.9
0.9
3.5
1.5
V
V
V
V
C
C
C
C
50 pF
50 pF
50 pF
50 pF
OLP
(Note 3)
OL
L
L
L
L
V
Quiet Output Minimum Dynamic V
5.0
5.0
5.0
0.6
OLV
(Note 3)
OL
V
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
IHD
(Note 3)
V
ILD
(Note 3)
Note 3: Parameter guaranteed by design.
3
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AC Electrical Characteristics
V
T
25 C
Typ
T
A
40 C to 85 C
CC
A
Symbol
Parameter
Units
ns
Conditions
(V)
Min
Max
11.0
14.5
7.2
Min
Max
13.0
16.5
8.5
t
t
Propagation Delay
3.3 0.3
7.0
9.5
4.9
6.4
7.3
9.8
5.0
6.5
7.3
9.8
5.5
7.0
9.5
6.5
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
15 pF
50 pF
50 pF
50 pF
50 pF
50 pF
PLH
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Time (LE to O )
n
PHL
5.0 0.5
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
ns
9.2
10.5
13.5
17.0
8.5
t
t
Propagation Delay
11.4
14.9
7.2
PLH
PHL
Time (D to O )
n
ns
9.2
10.5
13.5
17.0
9.5
t
t
3-STATE
Output
11.4
14.9
8.1
R
R
1 k
1 k
PZL
PZH
L
ns
ns
ns
ns
Enable Time
10.1
13.2
9.2
11.5
15.0
10.5
1.5
t
t
t
t
3-STATE Output
Disable Time
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
PLZ
L
PHZ
Output to
1.5
(Note 4)
OSLH
OSHL
Output Skew
1.0
1.0
C
C
C
Input Capacitance
Output Capacitance
Power Dissipation
Capacitance
4
6
10
10
pF
pF
pF
V
V
Open
5.0V
IN
CC
OUT
PD
CC
27
(Note 5)
Note 4: Parameter guaranteed by design. t
|t
t
|; t
|t
t min|
PHL
OSLH
PLH max
PLH min
OSHL
PHL max
Note 5: C is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load. Average
PD
operating current can be obtained by the equation: I
(opr.)
C
• V • f
I
/8 (per Latch). The total C when n pcs. of the Latch operates can be
CC PD
CC
PD
CC
IN
calculated by the equation: C (total) 14 13n.
PD
AC Operating Requirements
V
T
25 C
Typ
T
40 C to 85 C
Min Max
CC
A
A
Symbol
(H)
Parameter
Minimum Pulse Width (LE)
Units
ns
(V)
Min
5.0
5.0
4.0
4.0
1.0
1.0
Max
t
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
3.3 0.3
5.0 0.5
5.0
5.0
4.0
4.0
1.0
1.0
W
t
Minimum Set-Up Time
Minimum Hold Time
S
ns
t
H
ns
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4
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
5
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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8
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