74ALVCH16373 [STMICROELECTRONICS]
LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS; 低压CMOS 16 BITD类锁存器（ 3 -STATE ） ，在3.6V容错输入和输出
| 型号： | 74ALVCH16373 |
| 厂家： | 
ST |
| 描述： | LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE) WITH 3.6V TOLERANT INPUTS AND OUTPUTS |
| 文件： | 总11页 (文件大小：279K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVCH16373
LOW VOLTAGE CMOS 16-BITD-TYPE LATCH (3-STATE)
WITH 3.6V TOLERANT INPUTS AND OUTPUTS
■
■
3.6V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
t
t
= 3.6 ns (MAX.) at V = 3.0 to 3.6V
PD
PD
PD
CC
= 4.5 ns (MAX.) at V = 2.3 to 2.7V
CC
=
6.5 ns (MAX.) at V = 1.65V
CC
■
■
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
TSSOP
TUBE
|I | = I = 24mA (MIN) at V = 3.0V
OH
OL
CC
|I | = I = 18mA (MIN) at V = 2.3V
OH
OL
CC
ORDER CODES
PACKAGE
|I | = I = 4mA (MIN) at V = 1.65V
OH
OL
CC
T & R
■
■
OPERATING VOLTAGE RANGE:
(OPR) = 1.65V to 3.6V
TSSOP
74ALVCH16373TTR
V
CC
BUS HOLD PROVIDED ON DATA INPUTS
PIN CONNECTION
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 16373
■
■
LATCH-UP PERFORMANCE EXCEEDS
300mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
DESCRIPTION
The 74ALVCH16373 is a low voltage CMOS 16
BIT D-TYPE LATCH with 3 STATE OUTPUTS
NON INVERTING fabricated with sub-micron
2
silicon gate and five-layer metal wiring C MOS
technology. It is ideal for low power and very high
speed 1.65 to 3.6V applications; it can be
interfaced to 3.6V signal environment for both
inputs and outputs.
These 16 bit D-TYPE latches are bite controlled
by two latch enable inputs (nLE) and two output
enable inputs (OE).
While the nLE input is held at a high level, the nQ
outputs will follow the data input precisely.
When the nLE is taken low, the nQ outputs will be
in a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.This device is designed to be
used with 3 state memory address drivers, etc.
Active bus-hold circuitry holds unused or undriven
inputs at a valid logic state.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
February 2003
1/11
74ALVCH16373
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN DESCRIPTION
IEC LOGIC SYMBOLS
PIN No
SYMBOL
NAME AND FUNCTION
1
1OE
3 State Output Enable
Input (Active LOW)
2, 3, 5, 6, 8, 9, 1Q0 to 1Q7 3-State Outputs
11, 12
13, 14, 16, 17, 2Q0 to 2Q7 3-State Outputs
19, 20, 22, 23
24
2OE
3 State Output Enable
Input (Active LOW)
25
2LE
Latch Enable Input
36, 35, 33, 32, 2D0 to 2D7 Data Inputs
30, 29, 27, 26
47, 46, 44, 43, 1D0 to 1D7 Data Inputs
41, 40, 38, 37
48
1LE
Latch Enable Input
Ground (0V)
4, 10, 15, 21,
28, 34, 39, 45
GND
7, 18, 31, 42
V
Positive Supply Voltage
CC
TRUTH TABLE
INPUTS
LE
OUTPUT
OE
D
Q
H
L
L
X
L
X
X
L
Z
NO CHANGE *
H
H
L
L
H
H
X : Don‘t Care
Z : High Impedance
* : Q outputs are latched at the time when the LE input is taken low
logic level.
2/11
74ALVCH16373
LOGIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
Supply Voltage
-0.5 to +4.6
-0.5 to +4.6
-0.5 to +4.6
V
V
CC
V
DC Input Voltage
I
V
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
V
O
O
V
I
-0.5 to V + 0.5
V
CC
- 50
- 50
mA
mA
mA
mA
mW
°C
°C
IK
I
DC Output Diode Current (note 2)
DC Output Current
OK
I
± 50
O
I
or I
DC V or Ground Current per Supply Pin
± 100
400
CC
GND
CC
P
Power Dissipation
D
T
Storage Temperature
Lead Temperature (10 sec)
-65 to +150
300
stg
T
L
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I absolute maximum rating must be observed
O
2) V < GND, V > V
CC
O
O
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Value
Unit
V
Supply Voltage
1.65 to 3.6
-0.3 to 3.6
0 to 3.6
V
V
CC
V
Input Voltage
I
V
Output Voltage (OFF State)
V
O
V
Output Voltage (High or Low State)
0 to V
V
O
CC
I
I
I
, I
High or Low Level Output Current (V = 3.0 to 3.6V)
± 24
± 12
mA
mA
mA
°C
ns/V
OH OL
CC
, I
High or Low Level Output Current (V = 2.3 to 2.7V)
OH OL
CC
, I
High or Low Level Output Current (V = 1.8V)
± 4
OH OL
CC
T
Operating Temperature
-55 to 125
0 to 10
op
dt/dv
Input Rise and Fall Time (note 1)
1) V from 0.8V to 2V at V = 3.0V
IN
CC
3/11
74ALVCH16373
DC SPECIFICATIONS
Test Condition
Value
Symbol
Parameter
-40 to 85 °C
-55 to 125 °C
Unit
V
CC
(V)
Min.
Max.
Min.
Max.
V
High Level Input
Voltage
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
1.65 to 3.6
0.65 Vcc
1.7
0.65 Vcc
1.7
IH
2.0
2.0
V
V
Low Level Input
Voltage
0.35 Vcc
0.7
0.35 Vcc
0.7
IL
0.8
0.8
V
High Level Output
Voltage
I =-100 µA
V
-0.2
V
-0.2
CC
OH
O
CC
I =-4 mA
1.65
2.3
1.2
1.2
O
I =-6 mA
2.0
1.7
2.2
2.4
2.0
2.0
1.7
2.2
2.4
2.0
O
I =-12 mA
2.3
V
V
O
I =-12 mA
2.7
O
I =-12 mA
3.0
O
I =-24 mA
3.0
O
V
Low Level Output
Voltage
I =100 µA
1.65 to 3.6
1.65
2.3
0.2
0.45
0.4
0.2
0.45
0.4
OL
O
I =4 mA
O
I =6 mA
O
I =12 mA
2.3
0.7
0.7
O
I =12 mA
2.7
0.4
0.4
O
I =24 mA
3.0
0.55
0.55
O
I
Input Leakage
Current
I
V = 0 or 3.6V
3.6
± 5
± 5
µA
µA
I
I
Bus Hold Input
Leakage Current
V =0.58 V
1.65
1.65
2.3
2.3
3.0
3.0
3.6
0
+ 25
- 25
+ 45
- 45
+ 75
- 75
+ 25
- 25
+ 45
- 45
+ 75
- 75
IHOLD
I
V =1.07 V
I
V =0.7 V
I
V =1.7 V
I
V =0.8 V
I
V =2 V
I
V = 0 to 3.6V
± 500
± 500
I
I
Power Off Leakage
Current
V or V = 3.6V
10
20
µA
µA
off
I
O
I
High Impedance
Output Leakage
Current
3.6
V = V or V
± 5
± 10
OZ
I
IH
IL
V
= 0 to V
O
CC
I
Quiescent Supply
Current
3.6
V = V or GND
20
40
µA
µA
CC
I
CC
I = 0
O
∆I
I
incr. per Input
3.0 to 3.6
V
= V - 0.6V
500
750
CC
CC
IH
CC
4/11
74ALVCH16373
AC ELECTRICAL CHARACTERISTICS
Test Condition
Value
Symbol
Parameter
-40 to 85 °C
-55 to 125 °C
Unit
ns
V
(V)
C
(pF)
R
(Ω)
t = t
(ns)
CC
L
L
s
r
Min.
Max.
Min.
Max.
t
t
t
Propagation Delay
Time Dn to Qn
1.65 to 1.95
2.3 to 2.7
2.7
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
30
30
50
50
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
1000
500
500
500
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
2.0
2.0
2.5
2.5
1
1
6.5
4.5
4.3
3.6
7.0
4.9
4.6
3.9
8.5
6
1
1
6.5
4.5
4.3
3.6
7.0
4.9
4.6
3.9
8.5
6
PLH PHL
1
1
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
1
1
t
Propagation Delay
Time LE to Qn
1
1
PLH PHL
1
1
ns
1
1
3.0 to 3.6
1
1
t
t
t
Output Enable Time 1.65 to 1.95
1
1
PZL PZH
2.3 to 2.7
1
1
ns
2.7
1
5.7
4.7
7
1
5.7
4.7
7
3.0 to 3.6
1
1
t
Output Disable Time 1.65 to 1.95
1
1
PLZ PHZ
2.3 to 2.7
1
5.1
4.5
4.1
1
5.1
4.5
4.1
ns
2.7
3.0 to 3.6
1
1
1
1
t
Setup TIme, HIGH or 1.65 to 1.95
LOW level Dn to LE
1
1
s
2.3 to 2.7
2.7
1
1
ns
1
1
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
1.1
1.5
1.5
1.7
1.4
4
1.1
1.5
1.5
1.7
1.4
4
t
Hold Time High or
LOW level Dn to LE
h
ns
3.0 to 3.6
1.65 to 1.95
2.3 to 2.7
2.7
t
LE Pulse Width,
HIGH
w
3.3
3.3
3.3
3.3
3.3
3.3
ns
3.0 to 3.6
5/11
74ALVCH16373
CAPACITIVE CHARACTERISTICS
Test Condition
Value
T
= 25 °C
Symbol
Parameter
Unit
A
V
CC
(V)
Min.
Typ.
Max.
C
C
Input Capacitance Control
Inputs
IN
IN
V
V
=V or GND
CC
3.3
3.3
3
6
pF
IN
Input Capacitance Data Inputs
Output Capacitance
=V or GND
pF
pF
IN
CC
C
V
= 0 to V
CC
3.3
3.3
2.5
3.3
2.5
7
19
16
5
OUT
IN
C
Power Dissipation Capacitance
Output enabled (note 1)
f
= 10MHz
PD
IN
C =50pF
L
pF
V
= 0 or V
C
Power Dissipation Capacitance
Output disabled (note 1)
IN
CC
PD
4
1) C is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
PD
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
circuit)
= C x V x f + I /16 (per
CC(opr)
PD CC IN CC
TEST CIRCUIT
TEST
SWITCH
t
t
t
t
, t
Open
6V
PLH PHL
, t
(V = 3.0 to 3.6V)
CC
PZL PLZ
, t
(V = 2.3 to 2.7V)
2V
CC
PZL PLZ
CC
, t
GND
PZH PHZ
= Z
R
of pulse generator (typically 50Ω)
OUT
T
TEST CIRCUIT AND WAVEFORM SYMBOL VALUE
V
CC
Symbol
3.0 to 3.6V
2.7V
2.7V
2.7V
1.5V
2.3 to 2.7V
1.65 to 1.95V
V
V
V
CC
IH
CC
V
1.5V
V
/2
V
/2
M
CC
CC
V
V
V
+0.3V
-0.3V
V
+0.3V
V
+0.15V
-0.15V
V
V
+0.15V
-0.15V
X
Y
OL
OL
OL
OL
OH
V
V
-0.3V
V
OH
OH
OH
C
50pF
50pF
30pF
500Ω
30pF
1000Ω
<2.0ns
L
R =R
500Ω
500Ω
L
1
t = t
<2.5ns
<2.5ns
<2.0ns
r
r
6/11
74ALVCH16373
WAVEFORM 1 : LE TO Qn PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f=1MHz; 50% duty cycle)
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cycle)
7/11
74ALVCH16373
WAVEFORM 3 : PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
8/11
74ALVCH16373
TSSOP48 MECHANICAL DATA
mm.
inch
TYP.
DIM.
MIN.
TYP
MAX.
1.2
MIN.
MAX.
0.047
0.006
A
A1
A2
b
0.05
0.15
0.002
0.9
0.035
0.17
0.09
12.4
0.27
0.20
12.6
0.0067
0.0035
0.488
0.011
0.0079
0.496
c
D
E
8.1 BSC
0.5 BSC
0.318 BSC
E1
e
6.0
6.2
0.236
0.244
0.0197 BSC
K
0˚
8˚
0˚
8˚
L
0.50
0.75
0.020
0.030
A2
A
K
L
b
e
A1
E
c
D
E1
PIN 1 IDENTIFICATION
1
7065588C
9/11
74ALVCH16373
Tape & Reel TSSOP48 MECHANICAL DATA
mm.
TYP
inch
TYP.
DIM.
MIN.
MAX.
330
MIN.
MAX.
12.992
0.519
A
C
12.8
20.2
60
13.2
0.504
0.795
2.362
D
N
T
30.4
8.9
1.197
0.350
0.524
0.067
0.161
0.476
Ao
Bo
Ko
Po
P
8.7
13.1
1.5
0.343
0.516
0.059
0.153
0.468
13.3
1.7
3.9
4.1
11.9
12.1
10/11
74ALVCH16373
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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11/11
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