74ALVCH16373/D [ETC]
Low-Voltage 16-Bit Transparent Latch with Bus Hold 1.8/2.5/3.3 V ; 低电压16位透明锁存器与总线保持1.8 / 2.5 / 3.3 V
| 型号： | 74ALVCH16373/D |
| 厂家： | 
ETC |
| 描述： | Low-Voltage 16-Bit Transparent Latch with Bus Hold 1.8/2.5/3.3 V
|
| 文件： | 总12页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ALVCH16373
Low-Voltage 16-Bit
Transparent Latch with Bus
Hold 1.8/2.5/3.3 V
(3–State, Non–Inverting)
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MARKING DIAGRAM
The 74ALVCH16373 is an advanced performance, non–inverting
16–bit transparent latch. It is designed for very high–speed, very
low–power operation in 1.8 V, 2.5 V or 3.3 V systems. The
VCXH16373 is byte controlled, with each byte functioning
identically, but independently. Each byte has separate Output Enable
and Latch Enable inputs. These control pins can be tied together for
full 16–bit operation.
48
48
74ALVCH16373DT
AWLYYWW
1
The 74ALVCH16373 contains 16 D–type latches with 3–state
3.6 V–tolerant outputs. When the Latch Enable (LEn) inputs are
HIGH, data on the Dn inputs enters the latches. In this condition, the
latches are transparent, (a latch output will change state each time its D
input changes). When LE is LOW, the latch stores the information that
was present on the D inputs a setup time preceding the
HIGH–to–LOW transition of LE. The 3–state outputs are controlled
by the Output Enable (OEn) inputs. When OE is LOW, the outputs are
enabled. When OE is HIGH, the standard outputs are in the high
impedance state, but this does not interfere with new data entering into
the latches. The data inputs include active bushold circuitry,
eliminating the need for external pull–up resistors to hold unused or
floating inputs at a valid logic state.
TSSOP–48
DT SUFFIX
CASE 1201
1
= Assembly Location
A
WL = Wafer Lot
YY = Year
WW = Work Week
PIN NAMES
Pins
Function
OEn
LEn
D0–D15
O0–O15
Output Enable Inputs
Latch Enable Inputs
Inputs
• Designed for Low Voltage Operation: V = 1.65 – 3.6 V
CC
Outputs
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.6 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
6.8 ns max for 1.65 to 1.95 V
ORDERING INFORMATION
• Static Drive: ±24 mA Drive at 3.0 V
±12 mA Drive at 2.3 V
Device
Package
Shipping
74ALVCH16373DTR TSSOP 2500/Tape & Reel
±4 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• Includes Active Bushold to Hold Unused or Floating Inputs at a Valid
Logic State
†
• I
Specification Guarantees High Impedance When V = 0 V
CC
OFF
• Near Zero Static Supply Current in All Three Logic States (40 mA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±250 mA @ 125°C
• ESD Performance: Human Body Model >2000V; Machine Model >200V
• Second Source to Industry Standard 74ALVCH16373
†To ensure the outputs activate in the 3–state condition, the output enable pins
should be connected to V through a pull–up resistor. The value of the resistor is
CC
determined by the current sinking capability of the output connected to the OE pin.
Semiconductor Components Industries, LLC, 2002
1
Publication Order Number:
September, 2002 – Rev. 1
74ALVCH16373/D
74ALVCH16373
1
24
25
OE1
LE1
OE2
LE2
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE1
O0
LE1
D0
48
3
O1
D1
2
13
14
16
17
19
20
22
23
nLE
D
nLE
D
O0
O1
O2
O3
O4
O5
O6
O7
O8
47
Q
Q
Q
Q
Q
Q
Q
Q
36
Q
Q
Q
Q
Q
Q
Q
Q
4
GND
O2
GND
D2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
5
3
6
nLE
D
nLE
D
O3
D3
O9
46
44
43
41
40
38
37
35
33
32
30
29
27
26
7
V
CC
V
CC
8
O4
O5
D4
5
nLE
D
nLE
D
9
D5
O10
O11
O12
O13
O14
O15
D10
D11
D12
D13
D14
D15
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
O6
GND
D6
6
nLE
D
nLE
D
O7
D7
O8
D8
O9
D9
8
nLE
D
nLE
D
GND
O10
O11
GND
D10
D11
9
nLE
D
nLE
D
V
CC
V
CC
O12
O13
GND
O14
O15
OE2
D12
D13
GND
D14
D15
LE2
11
12
nLE
D
nLE
D
nLE
D
nLE
D
Figure 1. 48–Lead Pinout
Figure 2. Logic Diagram
(Top View)
1
48
25
24
EN1
OE1
LE1
LE2
OE2
EN2
EN3
EN4
2
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1
1
1
2
O0
O1
D0
D1
D2
D3
D4
D5
D6
D7
3
5
O2
O3
8
6
O4
O5
9
11
O6
O7
13
12
1
1
3
4
O8
O9
D8
D9
14
16
O10
O11
19
D10
D11
D12
D13
D14
D15
17
O12
O13
O14
O15
20
22
23
Figure 3. IEC Logic Diagram
Inputs
Outputs
Inputs
Outputs
LE1
X
OE1
H
D0:7
X
O0:7
Z
LE2
X
OE2
H
D8:15
O8:15
X
L
Z
L
H
L
L
L
H
L
H
L
H
H
H
L
H
X
H
L
L
X
O0
L
L
O0
H = High Voltage Level; L = Low Voltage Level; Z = High Impedance State; X = High or Low Voltage Level and Transitions Are Acceptable, for
reasons, DO NOT FLOAT Inputs. O0 = No Change.
I
CC
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2
74ALVCH16373
MAXIMUM RATINGS (Note 1)
Symbol
Parameter
Value
*0.5 to )4.6
*0.5 to )4.6
*0.5 to )4.6
*50
Unit
V
V
V
V
DC Supply Voltage
CC
I
DC Input Voltage
V
DC Output Voltage
V
O
I
I
I
I
I
DC Input Diode Current
DC Output Diode Current
DC Output Sink Current
DC Supply Current per Supply Pin
DC Ground Current per Ground Pin
Storage Temperature Range
V < GND
mA
mA
mA
mA
mA
°C
IK
I
V
< GND
O
*50
OK
O
$50
$
1
0
0
CC
GND
$
1
0
0
T
T
T
*65 to )150
260
STG
Lead Temperature, 1 mm from Case for 10 Seconds
Junction Temperature Under Bias
Thermal Resistance (Note 2)
Moisture Sensitivity
°C
L
)
1
5
0
°C
J
q
90
°C/W
JA
MSL
Level 1
F
R
Flammability Rating
Oxygen Index: 30 to 35
UL 94 V–O @ 0.125 in
V
ESD
ESD Withstand Voltage
Human Body Model (Note 3)
Machine Model (Note 4)
Charged Device Model (Note 5)
u2000
u200
N/A
V
I
Latch–Up Performance
Above V and Below GND at 125°C (Note 6)
$
2
5
0
mA
LATCH–UP
CC
Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those
indicated may adversely affect device reliability. Functional operation under absolute maximum–rated conditions is not implied. Functional
operation should be restricted to the Recommended Operating Conditions.
1. I absolute maximum rating must be observed.
O
2. Measured with minimum pad spacing on an FR4 board, using 10 mm–by–1 inch, 2–ounce copper trace with no air flow.
3. Tested to EIA/JESD22–A114–A.
4. Tested to EIA/JESD22–A115–A.
5. Tested to JESD22–C101–A.
6. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
V
CC
Supply Voltage
Operating
Data Retention Only
2.3
1.5
3.6
3.6
V
V
V
Input Voltage
(Note 7)
–0.5
3.6
V
V
I
Output Voltage
(Active State)
(3–State)
0
0
3.6
3.6
O
T
Operating Free–Air Temperature
Input Transition Rise or Fall Rate
*
4
0
)
8
5
°C
A
Dt/DV
V
CC
V
CC
= 2.5 V $ 0.2 V
= 3.0 V $ 0.3 V
0
0
20
10
ns/V
7. Unused inputs may not be left open. All inputs must be tied to a high–logic voltage level or a low–logic input voltage level.
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3
74ALVCH16373
DC ELECTRICAL CHARACTERISTICS
T
= *405C to )855C
A
Min
Max
Symbol
Parameter
Condition
Unit
V
V
V
HIGH Level Input Voltage
(Note 8)
1.65 V v V t 2.3 V
0.65 ꢀ V
1.7
V
IH
CC
CC
2.3 V v V v 2.7 V
CC
2.7 V t V v 3.6 V
2.0
CC
LOW Level Input Voltage
(Note 8)
1.65 V v V t 2.3 V
0.35 ꢀ V
0.7
V
V
IL
CC
CC
2.3 V v V v 2.7 V
CC
2.7 V t V v 3.6 V
0.8
CC
HIGH Level Output Voltage
1.65 V v V v 3.6 V; I = *100 mA
V
CC
* 0.2
OH
CC
OH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V; I = *4 mA
1.2
OH
= 2.3 V; I = *6 mA
2.0
1.7
2.2
2.4
2.0
OH
= 2.3 V; I = *12 mA
OH
= 2.7 V; I = *12 mA
OH
= 3.0 V; I = *12 mA
OH
= 3.0 V; I = *24 mA
OH
V
LOW Level Output Voltage
1.65 V v V v 3.6 V; I = 100 mA
0.2
0.45
0.4
V
OL
CC
OL
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V; I = 4 mA
OL
= 2.3 V; I = 6 mA
OL
= 2.3 V; I = 12 mA
0.7
OL
= 2.7 V; I = 12 mA
0.4
OL
= 3.0 V; I = 24 mA
0.55
$5.0
$500
OL
I
I
Input Leakage Current
1.65 V v V v 3.6 V; 0 V v V v 3.6 V
mA
mA
I
CC
I
Minimum Bus–hold Input
Current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 3.6 V; V = 0 to 3.6 V
IN
I(HOLD)
= 3.0 V, V = 0.8 V
75
*75
45
IN
= 3.0 V, V = 2.0 V
IN
= 2.3 V, V = 0.7 V
IN
= 2.3 V, V = 1.7 V
*45
25
IN
= 1.65 V, V = 0.58 V
IN
= 1.65 V, V = 1.07 V
*
2
5
IN
I
I
I
3–State Output Current
1.65 V v V v 3.6 V; 0 V v V v 3.6 V; V = V or V
IL
$10
10
mA
mA
mA
OZ
CC
O
I
IH
Power–Off Leakage Current
V = 0 V; V or V = 3.6 V
CC I O
OFF
CC
Quiescent Supply Current
(Note 9)
1.65 V v V v 3.6 V; V = GND or V
CC
40
CC
I
1.65 V v V v 3.6 V; 3.6 V v V, V v 3.6 V
$40
750
CC
I
O
DI
Increase in I per Input
2.7 V t V ≤ 3.6 V; V = V * 0.6 V
mA
CC
CC
CC
IH
CC
8. These values of V are used to test DC electrical characteristics only.
I
9. Outputs disabled or 3–state only.
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4
74ALVCH16373
AC CHARACTERISTICS (Note 10; tR = tF = 2.0 ns; CL = 30 pF; RL = 500 W)
Limits
T
= –40°C to +85°C
= 2.3 V to 2.7 V
A
V
CC
= 3.0 V t o 3.6 V
V
CC
V
CC
= 1.65 V to 1.95 V
Min
1.0
Max
Min
1.0
Max
Min
1.0
Max
Symbol
Parameter
Propagation Delay
Waveform
Unit
t
t
1
3.6
3.6
4.5
4.5
6.8
6.8
ns
PLH
Dn to On
1.0
1.0
1.0
PHL
t
t
Propagation Delay
LE to On
1
2
2
1.0
1.0
3.9
3.9
1.0
1.0
4.9
4.9
1.0
1.0
7.8
7.8
ns
ns
ns
PLH
PHL
t
t
Output Enable Time to
High and Low Level
1.0
1.0
4.7
4.7
1.0
1.0
6.0
6.0
1.0
1.0
9.2
9.2
PZH
PZL
t
t
Output Disable Time From
High and Low Level
1.0
1.0
4.1
4.1
1.0
1.0
5.1
5.1
1.0
1.0
6.8
6.8
PHZ
PLZ
t
t
t
Setup Time, High or Low Dn to LE
Hold Time, High or Low Dn to LE
LE Pulse Width, High
3
3
3
1.5
1.0
1.5
1.5
1.0
1.5
2.5
1.0
4.0
ns
ns
ns
ns
s
h
w
t
t
Output–to–Output Skew
(Note 11)
0.5
0.5
0.5
0.5
0.75
0.75
OSHL
OSLH
10.For C = 50 pF, add approximately 300 ps to the AC maximum specification.
L
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.
The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t
) or LOW–to–HIGH (t
); parameter
OSHL
OSLH
guaranteed by design.
CAPACITIVE CHARACTERISTICS
Symbol
Parameter
Input Capacitance
Condition
Note 12
Typical
Unit
pF
C
C
C
6
7
IN
Output Capacitance
Note 12
pF
OUT
Power Dissipation Capacitance
Note 12, 10 MHz
20
pF
PD
12.V = 1.8, 2.5 or 3.3 V; V = 0V or V .
CC
CC
I
V
IH
Vm
Vm
Dn
On
0 V
t
t
PHL
PLH
V
OH
OL
Vm
Vm
V
WAVEFORM 1 - PROPAGATION DELAYS
= t = 2.0 ns, 10% to 90%; f = 1MHz; t = 500 ns
t
R
F
W
Figure 4. AC Waveforms
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5
74ALVCH16373
V
IH
V
IH
Dn
Vm
Vm
Vm
Vm
OEn
0 V
V
0 V
t
s
t
h
t
t
PHZ
PZH
V
IH
OH
Vy
LEn
t
w
Vm
Vm
Vm
Vm
On
0 V
≈ 0 V
t
, t
PLH PHL
t
t
PLZ
PZL
V
OH
OL
≈ V
CC
On
Vm
On
V
Vx
V
OL
WAVEFORM 3 - LE to On PROPAGATION DELAYS, LE MINIMUM
PULSE WIDTH, Dn to LE SETUP AND HOLD TIMES
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns except when noted
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
= t = 2.0 ns, 10% to 90%; f = 1 MHz; t = 500 ns
t
R
t
R
F
W
F
W
Figure 5. AC Waveforms
V
CC
3.3 V ±0.3 V
2.7 V
2.5 V ±0.2 V
1.8 V ±0.15 V
Symbol
V
IH
V
CC
V
CC
V
m
1.5 V
V
CC
/2
V
CC
/2
V
V
+ 0.3 V
– 0.3 V
V
+ 0.15 V
– 0.15 V
V
+ 0.15 V
– 0.15 V
x
OL
OL
OL
V
y
V
OH
V
OH
V
OH
V
CC
6 V or V × 2
CC
OPEN
GND
R
L
PULSE
GENERATOR
DUT
R
T
C
L
R
L
TEST
SWITCH
t
t
, t
Open
PLH PHL
, t
6 V at V = 3.3 ±0.3 V;
CC
× 2 at V = 2.5 ±0.2 V; 1.8 V ±0.15 V
PZL PLZ
V
CC
CC
t
, t
GND
PZH PHZ
C = 50 pF for V = 3.0 ± 0.3 V
L
CC
R = 500 W or equivalent
L
R = Z
T
of pulse generator (typically 50 W)
OUT
Figure 6. Test Circuit
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6
74ALVCH16373
10 PITCHES
CUMULATIVE
TOLERANCE ON
TAPE
±0.2 mm
(±0.008")
P
0
K
t
P
2
D
TOP
COVER
TAPE
E
A
B
SEE NOTE 2
+
0
F
W
+
+
K
0
B
1
0
SEE
NOTE 2
D
1
P
FOR COMPONENTS
2.0 mm × 1.2 mm
AND LARGER
EMBOSSMENT
USER DIRECTION OF FEED
CENTER LINES
OF CAVITY
FOR MACHINE REFERENCE
ONLY
INCLUDING DRAFT AND RADII
CONCENTRIC AROUND B
0
*TOP COVER
TAPE THICKNESS (t )
1
0.10 mm
(0.004") MAX
R MIN
TAPE AND COMPONENTS
SHALL PASS AROUND RADIUS R"
WITHOUT DAMAGE
EMBOSSED
CARRIER
BENDING RADIUS
EMBOSSMENT
100 mm
(3.937")
MAXIMUM COMPONENT ROTATION
10°
1 mm MAX
TYPICAL
COMPONENT CAVITY
CENTER LINE
TAPE
1 mm
(0.039") MAX
250 mm
(9.843")
TYPICAL
COMPONENT
CENTER LINE
CAMBER (TOP VIEW)
ALLOWABLE CAMBER TO BE 1 mm/100 mm NONACCUMULATIVE OVER 250 mm
Figure 7. Carrier Tape Specifications
EMBOSSED CARRIER DIMENSIONS (See Notes 13 and 14)
Tape
Size
B
1
Max
D
D
E
F
K
P
P
0
P
2
R
T
W
1
24mm
20.1mm 1.5 + 0.1mm
(0.791")
1.5mm
Min
(0.060")
1.75
11.5
11.9 mm
Max
(0.468")
16.0
±0.1 mm
(0.63
4.0
±0.1 mm
(0.157
2.0
±0.1 mm
(0.079
30 mm
(1.18")
0.6 mm
(0.024")
24.3 mm
(0.957")
-0.0
(0.059
+0.004" -0.0)
±0.1 mm ±0.10 mm
(0.069
±0.004")
(0.453
±0.004")
±0.004")
±0.004")
±0.004")
13.Metric Dimensions Govern–English are in parentheses for reference only.
14.A , B , and K are determined by component size. The clearance between the components and the cavity must be within 0.05 mm min to
0
0
0
0.50 mm max. The component cannot rotate more than 10° within the determined cavity.
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7
74ALVCH16373
t MAX
13.0 mm ±0.2 mm
(0.512" ±0.008")
1.5 mm MIN
(0.06")
20.2 mm MIN
(0.795")
50 mm MIN
(1.969")
A
FULL RADIUS
G
Figure 8. Reel Dimensions
REEL DIMENSIONS
Tape Size
A Max
G
t Max
24 mm
360 mm
(14.173")
24.4 mm + 2.0 mm, -0.0
(0.961" + 0.078", -0.00)
30.4 mm
(1.197")
DIRECTION OF FEED
BARCODE LABEL
POCKET
HOLE
Figure 9. Reel Winding Direction
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8
74ALVCH16373
TAPE TRAILER
(Connected to Reel Hub)
NO COMPONENTS
160 mm MIN
TAPE LEADER
NO COMPONENTS
400 mm MIN
COMPONENTS
CAVITY TOP TAPE
TAPE
DIRECTION OF FEED
Figure 10. Tape Ends for Finished Goods
User Direction of Feed
Figure 11. Reel Configuration
F
K
G
L
48 Leads
Figure 12. Package Footprint
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9
74ALVCH16373
PACKAGE DIMENSIONS
TSSOP
DT SUFFIX
CASE 1201–01
ISSUE A
48X K REF
K
K1
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
M
S
S
V
0.12 (0.005)
T
U
J
J1
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION K DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN
EXCESS OF THE K DIMENSION AT MAXIMUM
MATERIAL CONDITION.
48
25
SECTION N–N
B
–U–
L
N
5. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
1
24
6. DIMENSIONS A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
MILLIMETERS
INCHES
A
–V–
PIN 1
DIM MIN
MAX
12.60
6.20 0.236
1.10 ---
MIN
0.488
MAX
0.496
0.244
0.043
0.006
0.030
IDENT.
A
B
12.40
6.00
---
N
C
M
F
D
0.05
0.50
0.15 0.002
0.75 0.020
F
0.25 (0.010)
DETAIL E
G
H
0.50 BSC
0.0197 BSC
0.37
0.09
0.09
0.17
0.17
7.95
0
--- 0.015
0.20 0.004
0.16 0.004
0.27 0.007
0.23 0.007
8.25 0.313
---
0.008
0.006
0.011
0.009
0.325
8
J
J1
K
D
C
K1
L
–W–
0.076 (0.003)
M
8
0
_
_
_
_
DETAIL E
–T–
SEATING
PLANE
H
G
http://onsemi.com
10
74ALVCH16373
Notes
http://onsemi.com
11
74ALVCH16373
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