SST36VF1602G-70-4I-B3KE [SST]
16 Mbit (x8/x16) Concurrent SuperFlash; 16兆位（ X8 / X16 ）并行的SuperFlash
| 型号： | SST36VF1602G-70-4I-B3KE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 16 Mbit (x8/x16) Concurrent SuperFlash |
| 文件： | 总36页 (文件大小：935K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit (x8/x16) Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
SST36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash
Data Sheet
FEATURES:
•
•
Organized as 1M x16 or 2M x8
Dual Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit Bottom Sector Protection
- SST36VF1601G: 4 Mbit + 12 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602G: 12 Mbit + 4 Mbit
Single 2.7-3.6V for Read and Write Operations
Superior Reliability
•
Block-Erase Capability
– Uniform 32 KWord blocks
Erase-Suspend / Erase-Resume Capabilities
Security ID Feature
– SST: 128 bits
– User: 256 Byte
•
•
•
Fast Read Access Time
– 70 ns
Latched Address and Data
Fast Erase and Program (typical):
•
•
•
•
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
CMOS I/O Compatibility
Conforms to Common Flash Memory Interface (CFI)
JEDEC Standards
•
•
•
Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
•
•
Hardware Sector Protection/WP# Input Pin
– Protects the 4 outermost sectors (8 KWord)
in the smaller bank by driving WP# low and
unprotects by driving WP# high
Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
•
•
•
•
•
•
Byte# Pin
– Selects 8-bit or 16-bit mode
Sector-Erase Capability
– Uniform 2 KWord sectors
Chip-Erase Capability
– Flash EEPROM Pinouts and command sets
Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
– 56-ball LFBGA (8mm x 10mm)
•
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF1601G and SST36VF1602G are 1M x16 or
2M x8 CMOS Concurrent Read/Write Flash Memory man-
ufactured with SST proprietary, high performance CMOS
SuperFlash memory technology. The split-gate cell design
and thick oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The devices write (Program or Erase) with a 2.7-3.6V
power supply and conform to JEDEC standard pinouts for
x8/x16 memories.
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
SST36VF160xG significantly improve performance and
reliability, while lowering power consumption. These
devices inherently use less energy during Erase and Pro-
gram than alternative flash technologies, because the total
energy consumed is a function of the applied voltage, cur-
rent, and time of application. For any given voltage range,
the SuperFlash technology uses less current to program
and has a shorter erase time; therefore, the total energy
consumed during any Erase or Program operation is less
than alternative flash technologies.
Featuring high performance Program, the SST36VF160xG
provide a typical Program time of 7 µsec and use Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
©2006 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF is a trademark of Silicon Storage Technology, Inc.
S71342-00-000
1
12/06
These specifications are subject to change without notice.
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
The Read operation of the SST36VF160xG is controlled
by CE# and OE#, both of which have to be low for the
system to obtain data from the outputs. CE# is used for
device selection. When CE# is high, the chip is deselected
and only standby power is consumed. OE# is the output
control and is used to gate data from the output pins. The
data bus is in a high impedance state when either CE# or
OE# is high. Refer to Figure 9, the Read cycle timing dia-
gram, for further details.
To meet high-density, surface-mount requirements, the
SST36VF1601G and SST36VF1602G devices are offered
in 48-ball TFBGA, 48-lead TSOP, and 56-ball LFBGA
packages. See Figures 6, 7, and 8 for pin assignments.
Program Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, ensure that the sector which is
being programmed is fully erased.
Device Operation
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
The Program operation is accomplished in three steps:
1. Initiate Software Data Protection using the three-
byte load sequence.
2. Load address and data.
Auto Low Power Mode
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
These devices also have the Auto Lower Power mode
which puts them in a near-standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the typical IDD active Read current to 4 µA.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
3. Initiate the internal Program operation after the
rising edge of the fourth WE# or CE#, whichever
occurs first. The Program operation, once initi-
ated, will be completed typically within 7 µs.
Concurrent Read/Write Operation
See Figures 10 and 11 for WE# and CE# controlled Pro-
gram operation timing diagrams and Figure 25 for flow-
charts. During the Program operation, the only valid reads
are Data# Polling and Toggle Bit. During the internal Pro-
gram operation, the host is free to perform additional tasks.
Any commands issued during an internal Program opera-
tion are ignored.
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank. See Table 1 below
for more information.
TABLE 1: Concurrent Read/Write State
Bank 1
Read
Bank 2
No Operation
Write
Read
Write
Read
Write
No Operation
Read
No Operation
No Operation
Write
Note: For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
2
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Sector-Erase/Block-Erase Operation
Erase-Suspend/Erase-Resume Operations
The Sector- or Block- Erase operation allows the system to
erase the device on a sector-by-sector (or block-by-block)
basis. The SST36VF160xG offer both Sector-Erase and
Block-Erase operations.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read or programmed into any sector or block that is not
engaged in an Erase operation. The operation is executed
by issuing a one-byte command sequence with Erase-Sus-
pend command (B0H). The device automatically enters
read mode no more than 10 µs after the Erase-Suspend
command had been issued. (TES maximum latency equals
10 µs.) Valid data can be read from any sector or block that
is not suspended from an Erase operation. Reading at
address location within erase-suspended sectors/blocks
will output DQ2 toggling and DQ6 at ‘1’. While in Erase-Sus-
pend mode, a Program operation is allowed except for the
sector or block selected for Erase-Suspend.
The sector architecture is based on a uniform sector size of
2 KWord. The Sector-Erase operation is initiated by execut-
ing a six-byte command sequence with a Sector-Erase
command (50H) and sector address (SA) in the last bus
cycle.
The Block-Erase mode is based on a uniform block size of
32 KWord. Block-Erase is initiated by executing a six-byte
command sequence with Block-Erase command (30H) and
block address (BA) in the last bus cycle. The sector or block
address is latched on the falling edge of the sixth WE#
pulse, while the command (50H or 30H) is latched on the
rising edge of the sixth WE# pulse. The internal Erase oper-
ation begins after the sixth WE# pulse.
To resume a suspended Sector-Erase or Block-Erase
operation, the system must issue an Erase-Resume com-
mand. The operation is executed by issuing a one-byte
command sequence with Erase Resume command (30H)
at any address in the one-byte sequence.
Any commands issued during the Sector- or Block-Erase
operation are ignored except Erase-Suspend and Erase-
Resume. See Figures 15 and 16 for timing waveforms.
Write Operation Status Detection
To optimize the system Write cycle time, the
SST36VF160xG provide two software means to detect the
completion of a Write (Program or Erase) cycle The soft-
ware detection includes two status bits: Data# Polling
(DQ7) and Toggle Bit (DQ6). The End-of-Write detection
mode is enabled after the rising edge of WE#, which ini-
tiates the internal Program or Erase operation.
Chip-Erase Operation
The SST36VF1601G and SST36VF1602G provide a
Chip-Erase operation, which erases the entire memory
array to the ‘1’ state. This operation is useful when the
entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 6 for the command sequence, Figure
14 for timing diagram, and Figure 29 for the flowchart.
When WP# is low, any attempt to Chip-Erase will be
ignored.
The actual completion of the nonvolatile write is asyn-
chronous with the system. Therefore, Data# Polling or
Toggle Bit maybe be read concurrent with the completion
of the write cycle. If this occurs, the system may possibly
get an incorrect result from the status detection process.
For example, valid data may appear to conflict with either
DQ7 or DQ6. To prevent false results, upon detection of
failures, the software routine should loop to read the
accessed location an additional two times. If both reads
are valid, then the device has completed the Write cycle,
otherwise the failure is valid.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
3
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Ready/Busy# (RY/BY#)
Toggle Bits (DQ6 and DQ2)
The SST36VF160xG include a Ready/Busy# (RY/BY#)
output signal. RY/BY# is an open drain output pin that indi-
cates whether an Erase or Program operation is in
progress. Since RY/BY# is an open drain output, it allows
several devices to be tied in parallel to VDD via an external
pull-up resistor. After the rising edge of the final WE# pulse
in the command sequence, the RY/BY# status is valid.
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating ‘1’s
and ‘0’s, i.e., toggling between ‘1’ and ‘0’. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling, and the device is then ready for the next
operation. For Sector-, Block-, or Chip-Erase, the toggle bit
(DQ6) is valid after the rising edge of sixth WE# (or CE#)
pulse. DQ6 will be set to ‘1’ if a Read operation is attempted
on an Erase-Suspended Sector or Block. If Program oper-
ation is initiated in a sector/block not selected in Erase-Sus-
pend mode, DQ6 will toggle.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector or block is being actively erased or erase-sus-
pended. Table 2 shows detailed bit status information. The
Toggle Bit (DQ2) is valid after the rising edge of the last
WE# (or CE#) pulse of Write operation. See Figure 13 for
Toggle Bit timing diagram and Figure 26 for a flowchart.
Byte/Word (BYTE#)
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pins DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic ‘0’, the device is in x8 data con-
figuration -- only data I/O pins DQ0-DQ7 are active and con-
trolled by CE# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
TABLE 2: Write Operation Status
Status
DQ7
DQ6
DQ2
RY/BY#
Normal
Standard
DQ7# Toggle No Toggle
0
Operation Program
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
0
1
Erase-
Suspend Erase
Mode Suspended
Read From
Data# Polling (DQ7)
When the SST36VF160xG are in an internal Program
operation, any attempt to read DQ7 will produce the com-
plement of true data. Once the Program operation is com-
pleted, DQ7 will produce valid data.
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
N/A
1
During internal Erase operation, any attempt to read DQ7
will produce a ‘0’. Once the internal Erase operation is com-
pleted, DQ7 will produce a ‘1’. The Data# Polling is valid
after the rising edge of fourth WE# (or CE#) pulse for Pro-
gram operation. For Sector-, Block-, or Chip-Erase, the
Data# Polling is valid after the rising edge of sixth WE# (or
CE#) pulse. See Figure 12 for Data# Polling (DQ7) timing
diagram and Figure 26 for a flowchart.
Program
DQ7# Toggle
0
T2.1 1342
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
4
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
All Program operations require the inclusion of the three-
byte sequence. The three-byte load sequence is used to
initiate the Program operation, providing optimal protection
from inadvertent Write operations. SDP for Erase opera-
tions is similar to Program, but a six-byte load sequence is
required for Erase operations.
Data Protection
The SST36VF160xG provide both hardware and software
features to protect nonvolatile data from inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
During SDP command sequence, invalid commands will
abort the device to read mode within TRC. The contents of
DQ15-DQ8 can be VIL or VIH, but no other value, during any
SDP command sequence.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Common Flash Memory Interface (CFI)
These devices contain Common Flash Memory Interface
(CFI) information that describes the characteristics of the
device. In order to enter the CFI Query mode, the system
must write a three-byte sequence, using the CFI Query
command, to address BKx555H in the last byte sequence.
The system can also use the one-byte sequence with
address BKx55H and Data Bus 98H to enter this mode.
See Figure 18 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 7
through 9.
Hardware Block Protection
The SST36VF1601G and SST36VF1602G provide hard-
ware block protection which protects the outermost 8
KWord in the smaller bank. The block is protected when
WP# is held low. See Figures 2, 3, 4, and 5 for Block-Pro-
tection location.
Block protection is disabled by driving WP# high. This
allows data to be erased or programmed into the protected
sectors. WP# must be held high prior to issuing the Write
command and remain stable until after the entire Write
operation has completed. If WP# is left floating, it is inter-
nally held high via a pull-up resistor, and the Boot Block is
unprotected, enabling Program and Erase operations on
that block.
The system must write the CFI Exit command to return to
Read mode from the CFI Query mode.
Security ID
The SST36VF160xG offer a 136-word Security ID space.
The Secure ID space is divided into two segments — one
128-bit, factory-programmed, segment and one 256-Byte,
user programmed segment. The first segment is pro-
grammed and locked at SST and contains a 128 bit Unique
ID which uniquely identifies the device. The user segment is
left un-programmed for the customer to program as desired.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see). When no internal Program/
Erase operation is in progress, a minimum period of TRHR
is required after RST# is driven high before a valid Read
can take place. See Figures 22 and 21 for more informa-
tion.
The user segment of the Security ID can be programmed
using the Security ID Program command. End-of-Write sta-
tus is checked by reading the toggle bits. Data# Polling is
not used for Security ID End-of-Write detection.
The interrupted Erase or Program operation must be re-ini-
tiated after the device resumes normal operation mode to
ensure data integrity.
Once the programming is complete, lock the Sec ID by
issuing the User Sec ID Program Lock-Out command.
Locking the Sec ID disables any corruption of this space.
Note that regardless of whether or not the Sec ID is locked,
the Sec ID segments can not be erased.
Software Data Protection (SDP)
The SST36VF160xG devices implement the JEDEC
approved Software Data Protection (SDP) scheme for all
data alteration operations, such as Program and Erase.
These devices are shipped with the Software Data Protec-
tion permanently enabled. See Table 6 for the specific soft-
ware command codes.
The Secure ID space can be queried by executing a three-
byte command sequence with Query Sec ID command
(88H) at address 555H in the last byte sequence. See Fig-
ure 20 for timing diagram. To exit this mode, the Exit Sec ID
command should be executed. Refer to Table 6 for more
details.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
5
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Product Identification Mode Exit/CFI Mode Exit
Product Identification
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. The exit is
accomplished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode.
This command may also be used to reset the device to the
Read mode after any inadvertent transient condition that
causes the device to behave abnormally. Please note that
the Software ID Exit/CFI Exit command is ignored during an
internal Program or Erase operation. See Table 6 for the
software command code, Figure 19 for timing waveform
and Figure 28 for a flowchart.
The Product Identification mode identifies the devices as
SST36VF1601G or SST36VF1602G and the manufac-
turer as SST. For details, see Table 3 for software opera-
tion, Figure 17 for the Software ID Entry and Read timing
diagram, and Figure 27 for the Software ID Entry com-
mand sequence flowchart.
The addresses A19 and A18 indicate a bank address. When
the addressed bank is switched to Product Identification
mode, it is possible to read another address from the same
bank without issuing a new Software ID Entry command.
TABLE 3: Product Identification
Address
Data
Manufacturer’s ID
Device ID
BK0000H
00BFH
SST36VF1601G
SST36VF1602G
BK0001H
BK0001H
7343H
7344H
T3.0 1342
Note: BK = Bank Address (A19-A18
)
Address
Buffers
Memory
Address
SuperFlash Memory
12 Mbit Bank
BYTE#
RST#
CE#
SuperFlash Memory
4 Mbit Bank
(8 KWord Sector Protection)
Control
Logic
WP#
DQ /A - DQ
0
I/O Buffers
WE#
15 -1
OE#
RY/BY#
1342 B01.0
FIGURE 1: Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
6
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
FFFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
07FFFH
02000H
01FFFH
00000H
Block 0
8 KWord Sector Protection
(4-2 KWord Sectors)
1342 F01.0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0
FIGURE 2: SST36VF1601G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
7
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
1FFFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
00FFFFH
004000H
003FFFH
000000H
Block 0
16 KByte Sector Protection
(4-4 KByte Sectors)
1342 F02.0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
FIGURE 3: SST36VF1601G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
8
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Top Block Protection; 32 KWord Blocks; 2 KWord Sectors
8 KWord Block Protection
(4 - 2 KWord Sectors)
FFFFFH
FE000H
FDFFFH
F8000H
F7FFFH
F0000H
Block 31
Block 30
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH
00000H
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
1342 F03.0
Note: The address input range in x16 mode (BYTE#=VIH) is
FIGURE 4: SST36VF1602G, 1M x16 Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
9
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Top Block Protection; 64 KByte Blocks; 4 KByte Sectors
16 KByte Block Protection
(4 - 4 KByte Sectors)
1FFFFFH
1FC000H
1FBFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
00FFFFH
000000H
Block 0
1342 F04.0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
FIGURE 5: SST36VF1602G, 2M x8 Concurrent SuperFlash Dual-Bank Memory Organization
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
10
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TOP VIEW (balls facing down)
6
A13 A12 A14 A15 A16 BYTE# NOTE*
V
SS
5
4
3
2
1
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC A19 DQ5 DQ12 V
DQ4
DD
RY/BY#WP# A18 NC DQ2 DQ10 DQ11 DQ3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E
F
G
H
Note* = DQ /A
15 -1
FIGURE 6: Pin Assignments for 48-ball TFBGA (6mm x 8mm)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A
DQ7
-1
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
V
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A6
A5
A4
A3
A2
A1
V
SS
CE#
A0
1342 48-tsop P02.0
FIGURE 7: Pin Assignments for 48-lead TSOP (12mm x 20mm)
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
11
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TOP VIEW (balls facing down)
8
7
6
5
4
3
2
1
A15
NC
NC
A14
A10
A16 BYTE# V
SS
A11 A12 A13
NC DQ15/A DQ7 DQ14
-1
A8
A19
NC
A9
DQ6 DQ13 DQ12 DQ5
WE#
NC
DQ4
DQ3
NC
NC
WP# RST# RY/BY#
V
DD
DQ11
NC
A7
NC
A6
A18
A5
A17
A4
DQ1 DQ9 DQ10 DQ2
V
OE#
DQ0 DQ8
NC
SS
A3
A2
A1
A0
CE#
A
B
C
D
E
F
G
H
FIGURE 8: Pin Assignments for 56-lead LFBGA (8mm x 10mm)
TABLE 4: Pin Description
Symbol
Name
Functions
A19-A0
Address Inputs
To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A19-A11 address lines will select the sector. During Block-Erase A19-A15 address
lines will select the block.
DQ14-DQ0 Data Input/Output
To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.
DQ15/A-1 Data Input/Output
and LBS Address
DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)
A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)
CE#
Chip Enable
To activate the device when CE# is low.
To gate the data output buffers
OE#
Output Enable
Write Enable
Hardware Reset
Ready/Busy#
WE#
To control the Write operations
RST#
RY/BY#
To reset and return the device to Read mode
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
WP#
Write Protect
To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.
BYTE#
VDD
Word/Byte Configuration To select 8-bit or 16-bit mode.
Power Supply
Ground
To provide 2.7-3.6V power supply voltage
VSS
NC
No Connection
Unconnected pins
T4.0 1342
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
12
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TABLE 5: Operation Modes Selection
DQ15-DQ8
BYTE# = VIL
Mode1
Read
CE# OE# WE#
DQ7-DQ0
DOUT
DIN
BYTE# = VIH
Address
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
DOUT
DIN
X
DQ14-DQ8 = High Z
DQ15 = A-1
AIN
AIN
Program
Erase
X2
High Z
Sector or Block
address,
555H for Chip-Erase
Standby
VIHC
X
X
VIL
X
X
X
High Z
High Z
High Z
High Z
High Z
X
X
X
Write Inhibit
High Z / DOUT
High Z / DOUT
High Z / DOUT
High Z / DOUT
X
VIH
Product
Identification
Software
Mode
VIL
VIL
VIH
Manufacturer’s ID
(BFH)
Manufacturer’s ID
(00H)
High Z
High Z
See Table 6
Device ID3
Device ID3
T5.2 1342
1. RST# = VIH for all described operation modes
2. X can be VIL or VIH, but no other value.
3. Device ID =
SST36VF1601G = 7343H,
SST36VF1602G = 7344H
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
13
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TABLE 6: Software Command Sequence
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
555H
555H
AAH
AAH
AAH
AAH
B0H
30H
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Program
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
50H
30H
10H
Sector-Erase
Block-Erase
Chip-Erase
555H
555H
555H
XXXXH
XXXXH
555H
Erase-Suspend
Erase-Resume
Query Sec ID5
2AAH
2AAH
55H
55H
555H
555H
88H
A5H
555H
SIWA6
XXH
Data
User Security ID
Program
555H
AAH
2AAH
55H
555H
85H
0000H
User Security ID
Program Lock-out7
9
Software ID Entry8
CFI Query Entry
CFI Query Entry
555H
555H
AAH
AAH
98H
AAH
2AAH
2AAH
55H
55H
BKX
90H
98H
555H
9
BKX
555H
9
BKX
55H
555H
2AAH
55H
555H
F0H
Software ID Exit/
CFI Exit/
Sec ID Exit10,11
XXH
F0H
Software ID Exit/
CFI Exit/
Sec ID Exit10,11
T6.0 1342
1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.
When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word/byte address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. For SST36VF1601G,
SST ID is read with A3 = 0 (Address range = 00000H to 00007H),
User ID is read with A3 = 1 (Address range = = 00008H to 00087H).
Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
For SST36VF1602G,
SST ID is read with A3 = 0 (Address range = C0000H to C0007H),
User ID is read with A3 = 1 (Address range = = C0008H to C0087H).
Lock Status is read with A7-A0 = C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. SIWA = User Security ID Program word/byte address
For SST36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.
For SST36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH).
8. The device does not remain in Software Product Identification mode if powered down.
9. A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode
With A17-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0 = 0
SST36VF1601G Device ID = 7343H, is read with A0 = 1
SST36VF1602G Device ID = 7344H, is read with A0 = 1
10. Both Software ID Exit operations are equivalent
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the
User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
For SST36VF1601G, valid Word-Addresses for User Sec ID are from 00008H to 00087H.
For SST36VF1602G, valid Word-Addresses for User Sec ID are from C0008H to C0087H.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
14
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TABLE 7: CFI Query Identification String1
Address
x16 Mode x8 Mode
Address
Data2
0051H
0052H
0059H
0002H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Description
Query Unique ASCII string “QRY”
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T7.0 1342
1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.
TABLE 8: System Interface Information
Address
x16 Mode x8 Mode
Address
Data1
Description
VDD Min (Program/Erase)
1BH
1CH
36H
38H
0027H
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
3AH
3CH
3EH
40H
42H
44H
46H
48H
4AH
4CH
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
0001H
VPP min (00H = no VPP pin)
VPP max (00H = no VPP pin)
Typical time out for Program 2N µs (24 = 16 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T8.0 1342
1. In x8 mode, only the lower byte of data is output.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
15
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TABLE 9: Device Geometry Information
Address
x16 Mode x8 Mode
Address
Data1
0015H
0002H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
001FH
0000H
0000H
0001H
Description
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0002H = x8/x16 asynchronous interface
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FFH = 512)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T9.1 1342
1. In x8 mode, only the lower byte of data is output.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
16
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Operating Range:
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC Conditions of Test
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 23 and 24
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
17
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TABLE 10: DC Operating Characteristics VDD = 2.7-3.6V
Limits
Symbol Parameter
Freq
Min
Max
Units
Test Conditions
1
IDD
Active VDD Current
Read
5 MHz
1 MHz
15
4
mA
mA
mA
mA
mA
µA
CE#=VIL, WE#=OE#=VIH
CE#=WE#=VIL, OE#=VIH
CE#=VIL, OE#=VIH
Program and Erase
30
45
35
20
20
Concurrent Read/Write
5 MHz
1 MHz
ISB
Standby VDD Current
CE#, RST#=VDD 0.3V
IALP
Auto Low Power VDD Current
µA
CE#=0.1V, VDD=VDD Max
WE#=VDD-0.1V
Address inputs=0.1V or VDD-0.1V
IRT
ILI
Reset VDD Current
20
1
µA
µA
µA
RST#=GND
Input Leakage Current
VIN =GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST# pin
10
WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
Input Low Voltage
1
µA
V
VOUT =GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
0.8
0.3
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD VDD+0.3
VDD-0.3 VDD+0.3
0.2
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
T10.1 1342
1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 23)
TABLE 11: Recommended System Power-up Timings
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
µs
µs
1
TPU-WRITE
100
T11.0 1342
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: Capacitance (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
10 pF
10 pF
1
CIN
VIN = 0V
T12.0 1342
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: Reliability Characteristics
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T13.0 1342
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
18
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
AC CHARACTERISTICS
TABLE 14: Read Cycle Timing Parameters VDD = 2.7-3.6V
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
35
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
16
16
ns
1
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T14.1 1342
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 15: Program/Erase Cycle Timing Parameters
Symbol
TBP
Parameter
Min
Max
Units
µs
Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
40
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
25
ns
TSE
TBE
TSCE
TES
ms
ms
ms
µs
Block-Erase
Chip-Erase
50
Erase-Suspend Latency
RY/BY# Delay Time
Bus Recovery Time
10
1,2
TBY
90
ns
1
TBR
0
µs
T15.1 1342
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
19
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
T
T
AA
RC
ADDRESSES
T
CE
CE#
OE#
T
OE
T
T
OHZ
OLZ
V
IH
WE#
T
T
T
CHZ
CLZ
OH
HIGH-Z
HIGH-Z
DATA VALID
DATA VALID
DQ
15-0
1342 F05.0
FIGURE 9: Read Cycle Timing Diagram
T
BP
555
2AA
555
ADDR
ADDRESSES
WE#
T
AH
T
WP
T
T
WPH
AS
OE#
CE#
T
CH
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1342 F06.0
Note: X can be VIL or VIH, but no other value.
FIGURE 10: WE# Controlled Program Cycle Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
20
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESSES
WE#
T
AH
T
CP
T
CPH
T
AS
OE#
CE#
T
CH
T
CS
T
T
BR
BY
RY/BY#
T
DS
T
DH
DQ
15-0
XXAA
XX55
XXA0
DATA
VALID
WORD
(ADDR/DATA)
1342 F07.1
Note: X can be VIL or VIH, but no other value.
FIGURE 11: CE# Controlled Program Cycle Timing Diagram
ADDRESS A
19-0
T
CE
CE#
T
T
OES
OEH
OE#
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
1342 F08.1
FIGURE 12: Data# Polling Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
21
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
ADDRESS A
19-0
T
CE
CE#
OE#
WE#
T
OEH
T
OES
T
OE
T
BR
DQ
7
VALID DATA
TWO READ CYCLES
WITH SAME OUTPUTS
1342 F09.1
FIGURE 13: Toggle Bit Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
SCE
555
2AA
555
ADDRESSES
CE#
OE#
WE#
T
OEH
T
T
BR
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX10
XX80
VALID
1342 F10.1
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. See Table 15 on page 19.
X can be VL or VIH, but not other value.
FIGURE 14: WE# Controlled Chip-Erase Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
22
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
T
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
BE
555
2AA
BA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX50
XX80
VALID
1342 F11.1
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE# signals are interchangeable
as long as minimum timings are met. See Table 15 on page 19.
BAx = Block Address
X can be VL or VIH, but not other value.
FIGURE 15: WE# Controlled Block-Erase Timing Diagram
T
SIX-BYTE CODE FOR CHIP-ERASE
SE
555
2AA
555
555
2AA
SA
X
ADDRESSES
CE#
OE#
WE#
T
WP
T
BR
T
BY
RY/BY#
DQ
15-0
XX55
XXAA
XX55
XXAA
XX30
XX80
VALID
1342 F12.1
Note: This device also supports CD# controlled Sector-Erase operation. The WE# and CE# signals are inter-
changeable as long as minimum timings are met. See Table 15 on page 19.
BAx = Block Address
X can be VL or VIH, but no other value.
FIGURE 16: WE# Controlled Sector-Erase Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
23
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESSES
555
2AA
555
0000
0001
CE#
OE#
WE#
T
T
T
IDA
WP
WPH
T
AA
DQ
15-0
XXAA
XX55
XX90
00BF
Device ID
1342 F13.1
Note: Device ID = 7343H for SST36VF1601G, and 7344H for SST36VF1602G
X can be VIL or VIH, but no other value.
FIGURE 17: Software ID Entry and Read
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES
CE#
555
2AA
555
OE#
T
T
T
WP
WPH
IDA
WE#
T
AA
DQ
15-0
XXAA
XX55
XX98
1342 F14.1
Note: X can be VIL or VIH, but no other value.
FIGURE 18: CFI Entry and Read
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
24
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
ADDRESSES
555
2AA
555
DQ
15-0
XXAA
XX55
XXF0
T
IDA
CE#
OE#
WE#
T
T
WPH
WP
1342 F15.1
Note: X can be VIL or VIH, but no other value.
FIGURE 19: Software ID Exit/CFI Exit
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES
CE#
555
2AA
555
OE#
T
T
T
IDA
WP
WPH
WE#
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX88
SW2
1342 F16.1
Note: WP# must be held in proper logic state (VIL or VIH) 1µs prior to and 1 µs after the command
sequence.
X can be VIL or VIH, but no other value.
FIGURE 20: Sec ID Entry
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
25
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
RY/BY#
0V
T
RP
RST#
T
RHR
CE#/OE#
1342 F17.0
FIGURE 21: RST# Timing Diagram (When no internal operation is in progress)
T
RY
RY/BY#
RST#
T
RP
CE#
OE#
T
BR
1342 F18.0
FIGURE 22: RST# Timing Diagram (During Sector- or Block-Erase operation)
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
26
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
V
V
IHT
ILT
V
V
OT
IT
INPUT
REFERENCE POINTS
OUTPUT
1342 F19.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 23: AC Input/Output Reference Waveforms
TO TESTER
TO DUT
C
L
1342 F20.0
FIGURE 24: A Test Load Example
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
27
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load
Address/Data
Wait for end of
Program (T
,
BP
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
1342 F21.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 25: Program Algorithm
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
28
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read
byte/word
Read DQ
7
Wait T
,
BP
T
T
SCE SE
,
or T
BE
Read same
byte/word
Is DQ =
7
true data?
No
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1342 F22.0
FIGURE 26: Wait Options
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
29
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555H
Load data: XX98H
Address: 555H
Load data: XX88H
Address: 555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read Software ID
Read CFI data
Read Sec ID
X can be V or V , but no other value
IL IH
1342 F23.0
FIGURE 27: Software Product ID/CFI/Sec ID Entry Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
30
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V but no other value
IL
IH,
1342 F24.0
FIGURE 28: Software Product ID/CFI/Sec ID Exit Command Flowcharts
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
31
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Load data: XX30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1342F25.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 29: Erase Command Sequence
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
32
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
PRODUCT ORDERING INFORMATION
SST 36 VF 1601G - 70
-
4C
-
B3K
E
XX XX XXXXX - XXX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
B3 = TFBGA (6mm x 8mm)
E =TSOP (type 1, die up, 12mm x 20mm)
L1P = LFBGA (8mm x 10mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Bank Split
1 = 4 Mbit + 12 Mbit
2 = 12 Mbit + 4 Mbit
Device Density
160 = 1 Mbit x16 or
2 Mbit x8
Voltage
V = 2.7-3.6V
Product Series
36 = Concurrent SuperFlash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST36VF1601G
SST36VF1601G-70-4C-B3KE
SST36VF1601G-70-4I-B3KE
SST36VF1601G-70-4C-EKE
SST36VF1601G-70-4I-EKE
SST36VF1601G-70-4C-L1PE
SST36VF1601G-70-4I-L1PE
Valid combinations for SST36VF1602G
SST36VF1602G-70-4C-B3KE
SST36VF1602G-70-4I-B3KE
SST36VF1602G-70-4C-EKE
SST36VF1602G-70-4I-EKE
SST36VF1602G-70-4C-L1PE
SST36VF1602G-70-4I-L1PE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
33
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60
0.45 0.05
0.80
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
FIGURE 30: 48-ball Thin-profile, Fine-pitch Ball Grid Array (TFBGA) 6mm x 8mm
SST Package Code: B3K
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
34
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
FIGURE 31: 48-lead Thin Small Outline Package (TSOP) 12mm x 20mm
SST Package Code: EK
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
35
16 Mbit Concurrent SuperFlash
SST36VF1601G / SST36VF1602G
Data Sheet
TOP VIEW
10.00 0.20
BOTTOM VIEW
5.60
0.80
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
5.60
0.80
8.00 0.20
0.45 0.05
(56X)
H
G F E D C B A
A
B C D E F G H
A1 CORNER
A1 CORNER
1.30 0.10
SIDE VIEW
1mm
0.12
SEATING PLANE
0.35 0.05
Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
56-lfbga-L1P-8x10-450mic-4
FIGURE 32: 56-Ball, Low-Profile, Fine-Pitch Ball Grid Array (LFBGA) 8mm x 10mm
SST Package Code: L1P
TABLE 16: Revision History
Number
Description
Date
00
Dec 2006
•
Initial release of data sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2006 Silicon Storage Technology, Inc.
S71342-00-000
12/06
36
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