SST36VF3203-70-4C-EKE [MICROCHIP]
2M X 16 FLASH 2.7V PROM, 70 ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, MO-142DD, TSOP1-48;
| 型号： | SST36VF3203-70-4C-EKE |
| 厂家： | 
MICROCHIP |
| 描述： | 2M X 16 FLASH 2.7V PROM, 70 ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, MO-142DD, TSOP1-48 可编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总33页 (文件大小：392K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32 Mbit (x8/x16) Concurrent SuperFlash
SST36VF3203 / SST36VF3204
SST36VF3201C / 1602C32Mb (x8/x16) Concurrent SuperFlash
Advance Information
FEATURES:
•
•
Organized as 2M x16 or 4M x8
•
Block-Erase Capability
Dual Bank Architecture for Concurrent
Read/Write Operation
– Uniform 32 KWord blocks
•
•
Erase-Suspend / Erase-Resume Capabilities
Security ID Feature
– 32 Mbit Bottom Sector Protection
(in the smaller bank)
- SST36VF3203: 24 Mbit + 8 Mbit
– 32 Mbit Top Sector Protection
(in the smaller bank)
– SST: 128 bits
– User: 256 Bytes
•
Fast Read Access Time
– 70 ns
- SST36VF3204: 8 Mbit + 24 Mbit
•
•
Single 2.7-3.6V for Read and Write Operations
Superior Reliability
•
•
Latched Address and Data
Fast Erase and Program (typical):
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
•
•
•
Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
•
•
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
Hardware Sector Protection/WP# Input Pin
– Protects 8 KWord in the smaller bank or, top or
bottom bank for 16 Mbit+16 Mbit, by driving WP#
low and unprotects by driving WP# high
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
Hardware Reset Pin (RST#)
•
•
•
CMOS I/O Compatibility
– Resets the internal state machine to reading
array data
Conforms to Common Flash Memory Interface (CFI)
JEDEC Standards
•
•
•
Byte# Pin
– Flash EEPROM Pinouts and command sets
Packages Available
– Selects 8-bit or 16-bit mode
Sector-Erase Capability
– Uniform 2 KWord sectors
Chip-Erase Capability
•
•
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF320x are 2M x16 or 4M x8 CMOS Concur-
rent Read/Write Flash Memory manufactured with SST’s
proprietary, high performance CMOS SuperFlash technol-
ogy. The split-gate cell design and thick-oxide tunneling
injector attain better reliability and manufacturability com-
pared with alternate approaches. The devices write (Pro-
gram or Erase) with a 2.7-3.6V power supply and conform
to JEDEC standard pinouts for x8/x16 memories.
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
Featuring high performance Word-Program, these devices
provide a typical Program time of 7 µsec and use the Tog-
gle Bit, Data# Polling, or RY/BY# to detect the completion
of the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
©2005 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF is a trademark of Silicon Storage Technology, Inc.
S71270-00-000
1
2/05
These specifications are subject to change without notice.
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Read Operation
The Read operation is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out-
puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 3).
To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 1 and 2 for pin assignments.
Program Operation
Device Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
The Program operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
Auto Low Power Mode
2. Address and data are loaded.
These devices also have the Auto Lower Power mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the IDD active Read current to 4 µA typically.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank.
See Figures 4 and 5 for WE# and CE# controlled Program
operation timing diagrams and Figure 19 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.
CONCURRENT READ/WRITE STATE
Bank 1
Read
Bank 2
No Operation
Write
Read
Write
Read
Write
No Operation
Read
No Operation
No Operation
Write
Note: For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
2
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Sector- (Block-) Erase Operation
Erase-Suspend/Erase-Resume Operations
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (50H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (30H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 9 and 10 for timing waveforms.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode within 20 µs after
the Erase-Suspend command had been issued. Valid data
can be read from any sector or block that is not suspended
from an Erase operation. Reading at address location
within erase-suspended sectors/blocks will output DQ2 tog-
gling and DQ6 at “1”. While in Erase-Suspend mode, a Pro-
gram operation is allowed except for the sector or block
selected for Erase-Suspend. The Software ID Entry com-
mand can also be executed. To resume Sector-Erase or
Block-Erase operation which has been suspended, the
system must issue an Erase-Resume command. The
operation is executed by issuing a one-byte command
sequence with Erase Resume command (30H) at any
address in the last byte sequence.
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.
Write Operation Status Detection
These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 7 for the command sequence, Figure 8
for timing diagram, and Figure 22 for the flowchart. When
WP# is low, any attempt to Chip-Erase will be ignored.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ7), or Toggle Bit (DQ6) Read may
be simultaneous with the completion of the Write cycle. If
this occurs, the system may get an erroneous result, i.e.,
valid data may appear to conflict with either DQ7 or DQ6. In
order to prevent spurious rejection if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
Reads are valid, then the Write cycle has completed, other-
wise the rejection is valid.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
3
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Ready/Busy# (RY/BY#)
Toggle Bits (DQ6 and DQ2)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to VDD via an external pull-up
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (BYTE#)
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 7 for Toggle Bit timing dia-
gram and Figure 20 for a flowchart.
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pins DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ0-DQ7 are active and con-
trolled by CE# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
TABLE 1: WRITE OPERATION STATUS
Status
DQ7
DQ6
DQ2
RY/BY#
Normal
Standard
DQ7# Toggle No Toggle
0
Operation Program
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
0
1
Data# Polling (DQ7)
When the devices are in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 6 for Data# Polling
(DQ7) timing diagram and Figure 20 for a flowchart.
Erase-
Suspend Erase
Mode Suspended
Read From
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
N/A
1
Program
DQ7# Toggle
0
T1.1 1270
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
Data Protection
The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
4
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Hardware Data Protection
Software Data Protection (SDP)
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 7 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within TRC. The contents of DQ15-DQ8 can be VIL or
VIH, but no other value during any SDP command
sequence.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The devices provide hardware block protection which pro-
tects the outermost 8 KWord in the smaller bank or, top or
bottom bank for 16 Mbit +16 Mbit. The block is protected
when WP# is held low. When WP# is held low and a Block-
Erase command is issued to the protected black, the data
in the outermost 8 KWord/16 KByte section will be pro-
tected. The rest of the block will be erased. See Tables 3
and 4 for Block-Protection location.
Common Flash Memory Interface (CFI)
These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com-
mand with 98H (CFI Query command) to address
BKX555H in the last byte sequence. In order to enter the
CFI Query mode, the system can also use the one-byte
sequence with BKX55H on Address and 98H on Data Bus.
See Figure 12 for CFI Entry and Read timing diagram.
Once the device enters the CFI Query mode, the system
can read CFI data at the addresses given in Tables 8
through 10. The system must write the CFI Exit command
to return to Read mode from the CFI Query mode.
A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro-
tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 16) and all output pins
are set to High-Z. When no internal Program/Erase opera-
tion is in progress, a minimum period of TRHR is required
after RST# is driven high before a valid Read can take
place (see Figure 15).
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
5
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
address from the same bank without issuing a new Soft-
ware ID Entry command. The Software ID Entry command
may be written to an address within a bank that is in Read
Mode or in Erase-Suspend mode. The Software ID Entry
command may not be written while the device is program-
ming or erasing in the other bank.
Security ID
The SST36VF320x devices offer a 136-word Security ID
space. The Secure ID space is divided into two seg-
ments—one 128-bit factory programmed segment and one
128-word (256-byte) user-programmed segment. The first
segment is programmed and locked at SST with a unique,
128-bit number. The user segment is left un-programmed
for the customer to program as desired. To program the
user segment of the Security ID, the user must use the
Security ID Program command. End-of-Write status is
checked by reading the toggle bits. Data# Polling is not
used for Security ID End-of-Write detection. Once pro-
gramming is complete, the Sec ID should be locked using
the User Sec ID Program Lock-Out. This disables any
future corruption of this space. Note that regardless of
whether or not the Sec ID is locked, neither Sec ID seg-
ment can be erased. The Secure ID space can be queried
by executing a three-byte command sequence with Query
Sec ID command (88H) at address 555H in the last byte
sequence. See Figure 14 for timing diagram. To exit this
mode, the Exit Sec ID command should be executed.
Refer to Table 7 for more details.
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
BKX0000H 00BFH
SST36VF3203
SST36VF3204
BKX0001H 7354H
BKX0001H 7353H
T2.1 1270
Note: BKX = Bank Address (A20-A18
)
Product Identification Mode
Exit/CFI Mode Exit
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode. This
command may also be used to reset the device to the Read
mode after any inadvertent transient condition that appar-
ently causes the device to behave abnormally, e.g., not read
correctly. Please note that the Software ID Exit/CFI Exit
command is ignored during an internal Program or Erase
operation. See Table 7 for the software command code, Fig-
ure 13 for timing waveform and Figure 21 for a flowchart.
Product Identification
The Product Identification mode identifies the devices and
manufacturer. For details, see Table 2 for software opera-
tion, Figure 11 for the Software ID Entry and Read timing
diagram and Figure 21 for the Software ID Entry command
sequence flowchart. The addresses A20 and A18 indicate a
bank address. When the addressed bank is switched to
Product Identification mode, it is possible to read another
FUNCTIONAL BLOCK DIAGRAM
(8 KWord / 16 KByte
Sector Protection)
Address
Buffers
Memory
Address
SuperFlash Memory
Bank 1
BYTE#
RST#
CE#
SuperFlash Memory
Bank 2
Control
Logic
WP#
DQ /A - DQ
15 -1
I/O Buffers
WE#
0
OE#
1270 B01.0
RY/BY#
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
6
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 3: SST36VF3203, 2M X16 CSF BOTTOM DUAL-BANK MEMORY ORGANIZATION (1 OF 2)
SST36VF3203
Block
Block Size
Address Range x8
000000H–003FFFH
004000H–00FFFFH
010000H–01FFFFH
020000H–02FFFFH
030000H–03FFFFH
040000H–04FFFFH
050000H–05FFFFH
060000H—06FFFFH
070000H—07FFFFH
080000H—08FFFFH
090000H—09FFFFH
0A0000H—0AFFFFH
0B0000H—0BFFFFH
0C0000H—0CFFFFH
0D0000H—0DFFFFH
0E0000H—0EFFFFH
0F0000H—0FFFFFH
100000H—10FFFFH
110000H—11FFFFH
120000H—12FFFFH
130000H—13FFFFH
140000H—14FFFFH
150000H—15FFFFH
160000H—16FFFFH
170000H—17FFFFH
180000H—18FFFFH
190000H—19FFFFH
1A0000H—1AFFFFH
1B0000H—1BFFFFH
1C0000H—1CFFFFH
1D0000H—1DFFFFH
1E0000H—1EFFFFH
1F0000H—1FFFFFH
200000H—20FFFFH
210000H—21FFFFH
220000H—22FFFFH
230000H—23FFFFH
240000H—24FFFFH
250000H—25FFFFH
260000H—26FFFFH
270000H—27FFFFH
280000H—28FFFFH
290000H—29FFFFH
Address Range x16
000000H–001FFFH
002000H–007FFFH
008000H–00FFFFH
010000H–017FFFH
018000H–01FFFFH
020000H–027FFFH
028000H–02FFFFH
030000H–037FFFH
038000H–03FFFFH
040000H–047FFFH
048000H–04FFFFH
050000H–057FFFH
058000H–05FFFFH
060000H–067FFFH
068000H–06FFFFH
070000H–077FFFH
078000H–07FFFFH
080000H–087FFFH
088000H–08FFFFH
090000H–097FFFH
098000H–09FFFFH
0A0000H–0A7FFFH
0A8000H–0AFFFFH
0B0000H–0B7FFFH
0B8000H–0BFFFFH
0C0000H–0C7FFFH
0C8000H–0CFFFFH
0D0000H–0D7FFFH
0D8000H–0DFFFFH
0E0000H—0E7FFFH
0E8000H—0EFFFFH
0F0000H—0F7FFFH
0F8000H—0FFFFFH
100000H—107FFFH
108000H—10FFFFH
110000H—117FFFH
118000H—11FFFFH
120000H—127FFFH
128000H—12FFFFH
130000H—137FFFH
138000H—13FFFFH
140000H—147FFFH
148000H—14FFFFH
8 KW / 16 KB
24 KW / 48 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
BA0
BA1
BA2
BA3
BA4
BA5
BA6
BA7
Bank 1
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
BA19
BA20
BA21
BA22
BA23
BA24
BA25
BA26
BA27
BA28
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BA37
BA38
BA39
BA40
BA41
Bank 2
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
7
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 3: SST36VF3203, 2M X16 CSF BOTTOM DUAL-BANK MEMORY ORGANIZATION (CONTINUED) (2 OF 2)
SST36VF3203
Block
BA42
BA43
BA44
BA45
BA46
BA47
BA48
BA49
BA50
BA51
BA52
BA53
BA54
BA55
BA56
BA57
BA58
BA59
BA60
BA61
BA62
BA63
Block Size
Address Range x8
2A0000H—2AFFFFH
2B0000H–2BFFFFH
2C0000H–2CFFFFH
2D0000H–2DFFFFH
2E0000H–2EFFFFH
2F0000H–2FFFFFH
300000H–30FFFFH
310000H–31FFFFH
320000H–32FFFFH
330000H–33FFFFH
340000H–34FFFFH
350000H–35FFFFH
360000H–36FFFFH
370000H–37FFFFH
380000H–38FFFFH
390000H–39FFFFH
3A0000H–3AFFFFH
3B0000H–3BFFFFH
3C0000H–3CFFFFH
3D0000H–3DFFFFH
3E0000H–3EFFFFH
3F0000H–3FFFFFH
Address Range x16
150000H—157FFFH
158000H–15FFFFH
160000H–167FFFH
168000H–16FFFFH
170000H–177FFFH
178000H–17FFFFH
180000H–187FFFH
188000H–18FFFFH
190000H–197FFFH
198000H–19FFFFH
1A0000H–1A7FFFH
1A8000H–1AFFFFH
1B0000H–1B7FFFH
1B8000H–1BFFFFH
1C0000H–1C7FFFH
1C8000H–1CFFFFH
1D0000H–1D7FFFH
1D8000H–1DFFFFH
1E0000H–1E7FFFH
1E8000H–1EFFFFH
1F0000H–1F7FFFH
1F8000H–1FFFFFH
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
Bank 2
T3.0 1270
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
8
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 4: SST36VF3204, 2M X16 CSF TOP DUAL-BANK MEMORY ORGANIZATION (1 OF 2)
SST36VF3204
Block
BA0
Block Size
Address Range x8
000000H–00FFFFH
010000H–01FFFFH
020000H–02FFFFH
030000H–03FFFFH
040000H–04FFFFH
050000H–05FFFFH
060000H—06FFFFH
070000H—07FFFFH
080000H—08FFFFH
090000H—09FFFFH
0A0000H—0AFFFFH
0B0000H—0BFFFFH
0C0000H—0CFFFFH
0D0000H—0DFFFFH
0E0000H—0EFFFFH
0F0000H—0FFFFFH
100000H—10FFFFH
110000H—11FFFFH
120000H—12FFFFH
130000H—13FFFFH
140000H—14FFFFH
150000H—15FFFFH
160000H—16FFFFH
170000H—17FFFFH
180000H—18FFFFH
190000H—19FFFFH
1A0000H—1AFFFFH
1B0000H—1BFFFFH
1C0000H—1CFFFFH
1D0000H—1DFFFFH
1E0000H—1EFFFFH
1F0000H—1FFFFFH
200000H—20FFFFH
210000H—21FFFFH
220000H—22FFFFH
230000H—23FFFFH
240000H—24FFFFH
250000H—25FFFFH
260000H—26FFFFH
270000H—27FFFFH
280000H—28FFFFH
290000H—29FFFFH
2A0000H—2AFFFFH
Address Range x16
000000H–007FFFH
008000H–00FFFFH
010000H–017FFFH
018000H–01FFFFH
020000H–027FFFH
028000H–02FFFFH
030000H–037FFFH
038000H–03FFFFH
040000H–047FFFH
048000H–04FFFFH
050000H–057FFFH
058000H–05FFFFH
060000H–067FFFH
068000H–06FFFFH
070000H–077FFFH
078000H–07FFFFH
080000H–087FFFH
088000H–08FFFFH
090000H–097FFFH
098000H–09FFFFH
0A0000H–0A7FFFH
0A8000H–0AFFFFH
0B0000H–0B7FFFH
0B8000H–0BFFFFH
0C0000H–0C7FFFH
0C8000H–0CFFFFH
0D0000H–0D7FFFH
0D8000H–0DFFFFH
0E0000H–0E7FFFH
0E8000H–0EFFFFH
0F0000H–0F7FFFH
0F8000H–0FFFFFH
100000H–107FFFH
108000H–10FFFFH
110000H–117FFFH
118000H–11FFFFH
120000H–127FFFH
128000H–12FFFFH
130000H–137FFFH
138000H–13FFFFH
140000H–147FFFH
148000H–14FFFFH
150000H–157FFFH
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
BA1
BA2
BA3
BA4
BA5
BA6
BA7
BA8
BA9
BA10
BA11
BA12
BA13
BA14
BA15
BA16
BA17
BA18
BA19
BA20
BA21
BA22
BA23
BA24
BA25
BA26
BA27
BA28
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BA37
BA38
BA39
BA40
BA41
BA42
Bank 2
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
9
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 4: SST36VF3204, 2M X16 CSF TOP DUAL-BANK MEMORY ORGANIZATION (CONTINUED) (2 OF 2)
SST36VF3204
Block
BA43
BA44
BA45
BA46
BA47
BA48
BA49
BA50
BA51
BA52
BA53
BA54
BA55
BA56
BA57
BA58
BA59
BA60
BA61
BA62
Block Size
Address Range x8
2B0000H–2BFFFFH
2C0000H–2CFFFFH
2D0000H–2DFFFFH
2E0000H–2EFFFFH
2F0000H–2FFFFFH
300000H–30FFFFH
310000H–31FFFFH
320000H–32FFFFH
330000H–33FFFFH
340000H–34FFFFH
350000H–35FFFFH
360000H–36FFFFH
370000H–37FFFFH
380000H–38FFFFH
390000H–39FFFFH
3A0000H–3AFFFFH
3B0000H–3BFFFFH
3C0000H–3CFFFFH
3D0000H–3DFFFFH
3E0000H–3EFFFFH
3F0000H–3FBFFFH
3FC000H–3FFFFFH
Address Range x16
158000H–15FFFFH
160000H–167FFFH
168000H–16FFFFH
170000H–177FFFH
178000H–17FFFFH
180000H–187FFFH
188000H–18FFFFH
190000H–197FFFH
198000H–19FFFFH
1A0000H–1A7FFFH
1A8000H–1AFFFFH
1B0000H–1B7FFFH
1B8000H–1BFFFFH
1C0000H–1C7FFFH
1C8000H–1CFFFFH
1D0000H–1D7FFFH
1D8000H–1DFFFFH
1E0000H–1E7FFFH
1E8000H–1EFFFFH
1F0000H–1F7FFFH
1F8000H–1FDFFFH
1FE000H–1FFFFFH
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
32 KW / 64 KB
24 KW / 48 KB
8 KW / 16 KB
Bank 2
Bank 1
BA63
T4.0 1270
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
10
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TOP VIEW (balls facing down)
6
A13 A12 A14 A15 A16 BYTE# NOTE*
V
SS
5
4
3
2
1
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC A19 DQ5 DQ12 V
DQ4
DD
RY/BY#WP# A18 A20 DQ2 DQ10 DQ11 DQ3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E
F
G
H
Note* = DQ /A
15 -1
FIGURE 1: PIN ASSIGNMENTS FOR 48-BALL TFBGA (6MM X 8MM)
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
2
BYTE#
3
V
SS
4
DQ15/A
DQ7
-1
5
6
DQ14
DQ6
7
A8
8
DQ13
DQ5
Standard Pinout
Top View
A19
A20
WE#
RST#
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
V
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
V
SS
A2
CE#
A0
A1
1270 48-tsop P02.0
FIGURE 2: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
11
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 5: PIN DESCRIPTION
Symbol
Name
Functions
A20-A0
Address Inputs
To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A20-A11 address lines will select the sector. During Block-Erase A20-A15 address
lines will select the block.
DQ14-DQ0 Data Input/Output
To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.
DQ15/A-1 Data Input/Output
and LBS Address
DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)
A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)
CE#
Chip Enable
To activate the device when CE# is low.
To gate the data output buffers
OE#
Output Enable
Write Enable
Hardware Reset
Ready/Busy#
WE#
To control the Write operations
RST#
RY/BY#
To reset and return the device to Read mode
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
WP#
Write Protect
To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.
BYTE#
VDD
Word/Byte Configuration To select 8-bit or 16-bit mode.
Power Supply
Ground
To provide 2.7-3.6V power supply voltage
VSS
NC
No Connection
Unconnected pins
T5.0 1270
TABLE 6: OPERATION MODES SELECTION
DQ15-DQ8
Mode
Read
CE# OE# WE#
RST#
VIH
DQ7-DQ0
DOUT
DIN
BYTE# = VIH
BYTE# = VIL
DQ14-DQ8 = High Z
DQ15 = A-1
Address
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
DOUT
DIN
X
AIN
AIN
Program
Erase
VIH
VIH
X1
High Z
Sector or Block
address,
555H for
Chip-Erase
Standby
VIHC
X
X
VIL
X
X
X
VIHC
VIH
High Z
High Z
High Z
High Z
High Z
X
X
X
Write Inhibit
High Z / DOUT
High Z / DOUT
High Z / DOUT
High Z / DOUT
X
VIH
VIH
Product
Identification
Software
Mode
VIL
X
VIL
X
VIH
VIH
Manufacturer’s ID Manufacturer’s ID
High Z
See Table 7
(BFH)
Device ID2
High Z
(00H)
Device ID2
High Z
High Z
High Z
Reset
X
VIL
X
T6.1 1270
1. X can be VIL or VIH, but no other value.
2. Device ID = SST36VF3203 = 7354H, SST36VF3204 = 7353H
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
12
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 7: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
555H
555H
555H
555H
XXXH
XXXH
555H
555H
AAH
AAH
AAH
AAH
B0H
30H
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Word-Program
Sector-Erase
Block-Erase
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
50H
30H
10H
555H
Chip-Erase
Erase-Suspend
Erase-Resume
Query Sec ID5
2AAH
2AAH
55H
55H
555H
555H
88H
A5H
SIWA6
Data
User Security ID
Word-Program
555H
AAH
2AAH
55H
555H
85H
XXXH 0000H
User Security ID
Program Lock-out
4
Software ID Entry7,8
CFI Query Entry8
CFI Query Entry8
555H
555H
AAH
AAH
98H
AAH
2AAH
2AAH
55H
55H
BKX
90H
98H
555H
4
BKX
555H
4
BKX
55H
555H
2AAH
55H
555H
F0H
Software ID Exit/
CFI Exit/
Sec ID Exit9,10
XXH
F0H
Software ID Exit/
CFI Exit/
Sec ID Exit9,10
T7.0 1270
1. Address format A10-A0 (Hex), Addresses A20-A11 can be VIL or VIH, but no other value (unless otherwise stated), for the command
sequence when in x16 mode.
When in x8 mode, Addresses A20-A12, Address A-1, and DQ14-DQ8 can be VIL or VIH, but no other value (unless otherwise stated), for
the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word address
4. SAX for Sector-Erase; uses A20-A11 address lines
BAX for Block-Erase; uses A20-A15 address lines
BKX for Bank Address; uses A20-A18 address lines
5. For SST36VF3203 the Security ID Address Range is: (x16 mode) = 10000H to 100087H,(x8 mode) = 100000H to 10010FH
SST ID is read at Address Range(x16 mode) = 100000H to 100007H (x8 mode) = 100000H to 10000FH
User ID is read at Address Range(x16 mode) = 100008H to 100087H (x8 mode) = 100010H to 10010FH
Lock status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
For SST36VF3204 the Security ID Address Range is:(x16 mode) = 0FF000H to 0FF087H, (x8 mode) = 000000H to 00010FH
SST ID is read at Address Range (x16 mode) = 000000H to 000007H (x8 mode) = 000000H to 0000FFH
User ID is read at Address Range (x16 mode) = 000008H to 000087H (x8 mode) = 000100H to 00010FH
Lock Status is read at Address 0000FFH (x16) or 0001FFH (x8). Unlocked: DQ3 = 1 / Locked: DQ3 = 0
6. SIWA = Valid Word addresses for user Sec ID
For SST36VF3203 User ID valid Address Range is (x16 mode) = 100008H-100087H (x8 mode) = 100010H-10010FH.
For SST36VF3204 User ID valid Address Range is (x16 mode) = 000008H-000087H (x8 mode) = 000010H-00010FH.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The device does not remain in Software Product Identification mode if powered down.
8. A20, A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode
With A17-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0 = 0
SST36VF3203 Device ID = 7354H, is read with A0 = 1
SST36VF3204 Device ID = 7353H, is read with A0 = 1
9. Both Software ID Exit operations are equivalent
10. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the
User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
13
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
1
TABLE 8: CFI QUERY IDENTIFICATION STRING
Address
x16 Mode x8 Mode
Address
Data2
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Description
Query Unique ASCII string “QRY”
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T8.0 1270
1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.
TABLE 9: SYSTEM INTERFACE INFORMATION
Address
x16 Mode x8 Mode
Address
Data1
Description
VDD Min (Program/Erase)
1BH
1CH
36H
38H
0027H
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
0036H
VDD Max (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
3AH
3CH
3EH
40H
42H
44H
46H
48H
4AH
4CH
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
0001H
VPP min (00H = no VPP pin)
VPP max (00H = no VPP pin)
Typical time out for Program 2N µs (24 = 16 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T9.0 1270
1. In x8 mode, only the lower byte of data is output.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
14
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 10: DEVICE GEOMETRY INFORMATION
Address
x16 Mode x8 Mode
Address
Data1
0016H
0002H
0000H
0000H
0000H
0002H
00FFH
0003H
0010H
0000H
003FH
0000H
0000H
0001H
Description
Device size = 2N Bytes (16H = 22; 222 = 4 MByte)
Flash Device Interface description; 0002H = x8/x16 asynchronous interface
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 1023 + 1 = 1024 sectors (03FFH = 1023)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 63 + 1 = 64 blocks (003FH = 63)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T10.1 1270
1. In x8 mode, only the lower byte of data is output.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
15
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Excluding certain with-Pb 32-PLCC units, all packages are 260°C capable in both non-Pb and with-Pb solder versions.
Certain with-Pb 32-PLCC package types are capable of 240°C for 10 seconds; please consult the factory for the latest information.
OPERATING RANGE
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 17 and 18
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
16
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
TABLE 11: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol Parameter
Freq
Min
Max
Units
Test Conditions
1
IDD
Active VDD Current
Read
5 MHz
1 MHz
15
4
mA
mA
mA
mA
mA
µA
CE#=VIL, WE#=OE#=VIH
CE#=WE#=VIL, OE#=VIH
CE#=VIL, OE#=VIH
Program and Erase
30
45
35
20
20
Concurrent Read/Write
5 MHz
1 MHz
ISB
Standby VDD Current
CE#, RST#=VDD±0.3V
IALP
Auto Low Power VDD Current
µA
CE#=0.1V, VDD=VDD Max
WE#=VDD-0.1V
Address inputs=0.1V or VDD-0.1V
IRT
ILI
Reset VDD Current
20
1
µA
µA
µA
RST#=GND
Input Leakage Current
VIN =GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST# pin
10
WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
Input Low Voltage
1
µA
V
VOUT =GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
0.8
0.3
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD VDD+0.3
VDD-0.3 VDD+0.3
0.2
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
T11.1 1270
1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 17)
TABLE 12: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
µs
µs
1
TPU-WRITE
100
T12.0 1270
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
10 pF
10 pF
1
CIN
VIN = 0V
T13.0 1270
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 14: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T14.0 1270
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
17
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
AC CHARACTERISTICS
TABLE 15: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
30
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
16
16
ns
1
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T15.1 1270
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
40
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
25
ns
TSE
TBE
TSCE
TES
ms
ms
ms
µs
Block-Erase
Chip-Erase
50
Erase-Suspend Latency
RY/BY# Delay Time
Bus Recovery Time
20
1,2
TBY
90
ns
1
TBR
0
µs
T16.-0 1270
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
18
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
T
T
AA
RC
ADDRESSES
CE#
T
CE
T
OE
OE#
T
OHZ
T
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1270 F03.0
FIGURE 3: READ CYCLE TIMING DIAGRAM
T
BP
555
2AA
555
ADDR
ADDRESSES
WE#
T
AH
T
WP
T
WPH
T
AS
OE#
CE#
T
CH
T
BY
T
T
BR
CS
RY/BY#
T
DS
T
DH
DQ
VALID
15-0
XXAA
XX55
XXA0
DATA
WORD
(ADDR/DATA)
1270 F04.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 4: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
19
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
T
BP
555
2AA
555
ADDR
ADDRESSES
CE#
T
AH
T
CP
T
CPH
T
AS
OE#
T
CH
WE#
T
BY
T
T
BR
CS
RY/BY#
T
DS
T
DH
VALID
DQ
XXAA
XX55
XXA0
DATA
15-0
WORD
1270 F05.0
(ADDR/DATA)
Note: X can be V or V , but no other value.
IL
IH
FIGURE 5: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS
T
CE
CE#
OE#
T
OES
T
OEH
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
1270 F06.0
FIGURE 6: DATA# POLLING TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
20
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
ADDRESSES
T
CE
CE#
OE#
WE#
T
OE
T
OEH
T
BR
DQ
6
VALID DATA
TWO READ CYCLES
1270 F07.0
WITH SAME OUTPUTS
FIGURE 7: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
555
2AA
555
ADDRESSES
CE#
OE#
T
WP
WE#
T
T
BR
BY
RY/BY#
DQ
XXAA
XX55
XX80
XXAA
XX55
XX10
15-0
VALID
1270 F08.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals
are interchageable as long as minimum timings are met. (See Table 16)
X can be V or V , but no other value.
IL IH
FIGURE 8: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
21
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
555 555 2AA
555
2AA
BA
ADDRESSES
CE#
X
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
VALID
XXAA
XX55
XX80
XXAA
XX55
XX30
DQ
15-0
1270 F09.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE#
signals are interchageable as long as minimum timings are met. (See Table 16)
BA = Block Address
X
X can be V or V , but no other value.
IL IH
FIGURE 9: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
555
2AA
555
555
2AA
SA
ADDRESSES
X
CE#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
XXAA
XX55
XX80
XXAA
XX55
XX50
DQ
VALID
15-0
1270 F10.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE#
signals are interchageable as long as minimum timings are met. (See Table 16)
SA = Sector Address
X
X can be V or V but no other value.
IL IH,
FIGURE 10: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
22
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESSES
555
2AA
555
0000
0001
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
XX55
XX90
00BF
Device ID
1270 F11.0
Device ID = 7354H for SST36VF3203 and 7353H for SST36VF3204
Note: X can be V or V , but no other value.
IL
IH
FIGURE 11: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES
555
2AA
555
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
XXAA
XX55
XX98
15-0
1270 F12.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 12: CFI ENTRY AND READ
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
23
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESSES
DQ
15-0
XXAA
XX55
XXF0
T
IDA
CE#
OE#
T
WP
WE#
T
WPH
1270 F13.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 13: SOFTWARE ID EXIT/CFI EXIT
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
555
2AA
555
MS-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX88
SW2
1270 F14.0
Note:
A
= Most significant address
MS
MS
A
= A for SST39VF3203/3204
20
WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL
IH
X can be V or V but no other value.
IH,
IL
FIGURE 14: SEC ID ENTRY
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
24
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
RY/BY#
0V
T
RP
RST#
CE#/OE#
T
RHR
1270 F15.0
FIGURE 15: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
T
RY
RY/BY#
RST#
T
RP
CE#
OE#
T
BR
1270 F16.0
FIGURE 16: RST# TIMING DIAGRAM (DURING SECTOR- OR BLOCK-ERASE OPERATION)
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
25
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
V
V
IHT
V
V
OT
IT
INPUT
REFERENCE POINTS
OUTPUT
ILT
1270 F17.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 17: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1270 F18.0
FIGURE 18: A TEST LOAD EXAMPLE
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
26
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load
Address/Data
Wait for end of
Program (T
,
BP
Data# Polling
bit, or Toggle bit
operation)
Program
Completed
1270 F19.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 19: WORD-PROGRAM ALGORITHM
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
27
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read
byte/word
Read DQ
7
Wait T
,
BP
T
T
SCE SE
,
or T
BE
Read same
byte/word
Is DQ =
7
true data?
No
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1270 F20.0
FIGURE 20: WAIT OPTIONS
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
28
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Software ID Exit/
Software Product ID Entry
Command Sequence
CFI Query Entry
Command Sequence
CFI Exit/Sec ID
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555H
Load data: XX98H
Address: 555H
Load data: XXF0H
Address: 555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Return to normal
operation
Read Software ID
Read CFI data
X can be V or V but no other value
IL
IH,
1270 F20.0
FIGURE 21: SOFTWARE PRODUCT ID/CFI/SEC ID ENTRY COMMAND FLOWCHARTS
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
29
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX50H
Load data: XX30H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1270 F22.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 22: ERASE COMMAND SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
30
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
PRODUCT ORDERING INFORMATION
SST 36 VF
320x - 70
-
4C
-
B3K
E
XX XX
XXXX - XXX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
B3 = TFBGA (6mm x 8mm)
E =TSOP (type 1, die up, 12mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Bank Split
3 = Bottom 24 Mbit + 8 Mbit
4 = Top 8 Mbit + 24 Mbit
Device Density
320 = 1 Mbit x16 or
2 Mbit x8
Voltage
V = 2.7-3.6V
Product Series
36 = Concurrent SuperFlash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST36VF3203
SST36VF3203-70-4C-B3K
SST36VF3203-70-4C-B3KE
SST36VF3203-70-4C-EK
SST36VF3203-70-4C-EKE
SST36VF3203-70-4I-B3K
SST36VF3203-70-4I-B3KE
SST36VF3203-70-4I-EK
SST36VF3203-70-4I-EKE
Valid combinations for SST36VF3204
SST36VF3204-70-4C-B3K
SST36VF3204-70-4C-B3KE
SST36VF3204-70-4C-EK
SST36VF3204-70-4C-EKE
SST36VF3204-70-4I-B3K
SST36VF3204-70-4I-B3KE
SST36VF3204-70-4I-EK
SST36VF3204-70-4I-EKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
31
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
PACKAGING DIAGRAMS
TOP VIEW
8.00 ± 0.20
BOTTOM VIEW
5.60
0.45 ± 0.05
0.80
(48X)
6
5
4
3
2
1
6
5
4
3
2
1
4.00
0.80
6.00 ± 0.20
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 ± 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 ± 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm (± 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
32
32 Mbit Concurrent SuperFlash
SST36VF3203 / SST36VF3204
Advance Information
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK
TABLE 17: REVISION HISTORY
Number
Description
Date
Feb 2005
00
•
Initial release of data sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2005 Silicon Storage Technology, Inc.
S71270-00-000
2/05
33
相关型号：
SST36VF3204-70-4C-B3KE
Flash, 2MX16, 70ns, PBGA48, 6 X 8 MM, ROHS COMPLIANT, MO-210AB-1, TFBGA-48
SILICON
SST36VF3204-70-4C-B3KE
Flash, 2MX16, 70ns, PBGA48, 6 X 8 MM, ROHS COMPLIANT, MO-210AB-1, TFBGA-48
MICROCHIP
SST36VF3204-70-4C-EKE
Flash, 2MX16, 70ns, PDSO48, 12 X 20 MM, ROHS COMPLIANT, MO-142DD, TSOP1-48
MICROCHIP
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