SST36VF1602E-70-4C-B3KE [SST]
16 Mbit (x8/x16) Concurrent SuperFlash; 16兆位（ X8 / X16 ）并行的SuperFlash
| 型号： | SST36VF1602E-70-4C-B3KE |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 16 Mbit (x8/x16) Concurrent SuperFlash |
| 文件： | 总35页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Mbit (x8/x16) Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
SST36VF1601E / 1602E16Mb (x8/x16) Concurrent SuperFlash
Data Sheet
FEATURES:
•
•
Organized as 1M x16 or 2M x8
Dual Bank Architecture for Concurrent
Read/Write Operation
– 16 Mbit Bottom Sector Protection
- SST36VF1601E: 12 Mbit + 4 Mbit
– 16 Mbit Top Sector Protection
- SST36VF1602E: 4 Mbit + 12 Mbit
Single 2.7-3.6V for Read and Write Operations
Superior Reliability
•
Block-Erase Capability
– Uniform 32 KWord blocks
Erase-Suspend / Erase-Resume Capabilities
Security ID Feature
– SST: 128 bits
– User: 128 bits
•
•
•
Fast Read Access Time
– 70 ns
Latched Address and Data
Fast Erase and Program (typical):
•
•
•
•
– Endurance: 100,000 cycles (typical)
– Greater than 100 years Data Retention
– Sector-Erase Time: 18 ms
– Block-Erase Time: 18 ms
– Chip-Erase Time: 35 ms
– Program Time: 7 µs
Automatic Write Timing
– Internal VPP Generation
End-of-Write Detection
– Toggle Bit
– Data# Polling
– Ready/Busy# pin
CMOS I/O Compatibility
Conforms to Common Flash Memory Interface (CFI)
JEDEC Standards
•
•
•
Low Power Consumption:
– Active Current: 6 mA typical
– Standby Current: 4 µA typical
– Auto Low Power Mode: 4 µA typical
•
•
Hardware Sector Protection/WP# Input Pin
– Protects the 4 outermost sectors (8 KWord)
in the larger bank by driving WP# low and
unprotects by driving WP# high
Hardware Reset Pin (RST#)
– Resets the internal state machine to reading
array data
•
•
•
•
•
•
Byte# Pin
– Selects 8-bit or 16-bit mode
Sector-Erase Capability
– Uniform 2 KWord sectors
Chip-Erase Capability
– Flash EEPROM Pinouts and command sets
Packages Available
– 48-ball TFBGA (6mm x 8mm)
– 48-lead TSOP (12mm x 20mm)
•
•
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST36VF1601E and SST36VF1602E are 1M x16 or
2M x8 CMOS Concurrent Read/Write Flash Memory man-
ufactured with SST’s proprietary, high performance CMOS
SuperFlash memory technology. The split-gate cell design
and thick oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The devices write (Program or Erase) with a 2.7-3.6V
power supply and conform to JEDEC standard pinouts for
x8/x16 memories.
and tested for a wide spectrum of applications, these
devices are offered with a guaranteed endurance of 10,000
cycles. Data retention is rated at greater than 100 years.
These devices are suited for applications that require con-
venient and economical updating of program, configura-
tion, or data memory. For all system applications, the
devices significantly improve performance and reliability,
while lowering power consumption. Since for any given
voltage range, the SuperFlash technology uses less cur-
rent to program and has a shorter erase time, the total
energy consumed during any Erase or Program operation
is less than alternative flash technologies. These devices
also improve flexibility while lowering the cost for program,
data, and configuration storage applications.
Featuring high performance Program, these devices pro-
vide a typical Program time of 7 µsec and use the Toggle
Bit, Data# Polling, or RY/BY# to detect the completion of
the Program or Erase operation. To protect against inad-
vertent write, the devices have on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufactured,
©2005 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
CSF is a trademark of Silicon Storage Technology, Inc.
S71274-03-000
1
11/05
These specifications are subject to change without notice.
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
SuperFlash technology provides fixed Erase and Program
times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose
Erase and Program times increase with accumulated
Erase/Program cycles.
Read Operation
The Read operation is controlled by CE# and OE#; both
have to be low for the system to obtain data from the out-
puts. CE# is used for device selection. When CE# is high,
the chip is deselected and only standby power is con-
sumed. OE# is the output control and is used to gate data
from the output pins. The data bus is in a high impedance
state when either CE# or OE# is high. Refer to the Read
cycle timing diagram for further details (Figure 7).
To meet high-density, surface-mount requirements, these
devices are offered in 48-ball TFBGA and 48-lead TSOP
packages. See Figures 5 and 6 for pin assignments.
Program Operation
Device Operation
These devices are programmed on a word-by-word or
byte-by-byte basis depending on the state of the BYTE#
pin. Before programming, one must ensure that the sector
which is being programmed is fully erased.
Memory operation functions are initiated using standard
microprocessor write sequences. A command is written by
asserting WE# low while keeping CE# low. The address
bus is latched on the falling edge of WE# or CE#, which-
ever occurs last. The data bus is latched on the rising edge
of WE# or CE#, whichever occurs first.
The Program operation is accomplished in three steps:
1. Software Data Protection is initiated using the
three-byte load sequence.
Auto Low Power Mode
2. Address and data are loaded.
These devices also have the Auto Lower Power mode
which puts them in a near standby mode within 500 ns
after data has been accessed with a valid Read operation.
This reduces the IDD active Read current to 4 µA typically.
While CE# is low, the devices exit Auto Low Power mode
with any address transition or control signal transition used
to initiate another Read cycle, with no access time penalty.
During the Program operation, the addresses are
latched on the falling edge of either CE# or WE#,
whichever occurs last. The data is latched on the
rising edge of either CE# or WE#, whichever
occurs first.
3. The internal Program operation is initiated after
the rising edge of the fourth WE# or CE#, which-
ever occurs first. The Program operation, once ini-
tiated, will be completed typically within 7 µs.
Concurrent Read/Write Operation
The dual bank architecture of these devices allows the
Concurrent Read/Write operation whereby the user can
read from one bank while programming or erasing in the
other bank. For example, reading system code in one bank
while updating data in the other bank.
See Figures 8 and 9 for WE# and CE# controlled Program
operation timing diagrams and Figure 23 for flowcharts.
During the Program operation, the only valid reads are
Data# Polling and Toggle Bit. During the internal Program
operation, the host is free to perform additional tasks. Any
commands issued during an internal Program operation
are ignored.
CONCURRENT READ/WRITE STATE
Bank 1
Read
Bank 2
No Operation
Write
Read
Write
Read
Write
No Operation
Read
No Operation
No Operation
Write
Note: For the purposes of this table, write means to perform Block-
or Sector-Erase or Program operations as applicable to the
appropriate bank.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
2
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Sector-Erase/Block-Erase Operation
Erase-Suspend/Erase-Resume Operations
These devices offer both Sector-Erase and Block-Erase
operations. These operations allow the system to erase the
devices on a sector-by-sector (or block-by-block) basis. The
sector architecture is based on a uniform sector size of 2
KWord. The Block-Erase mode is based on a uniform block
size of 32 KWord. The Sector-Erase operation is initiated by
executing a six-byte command sequence with a Sector-
Erase command (30H) and sector address (SA) in the last
bus cycle. The Block-Erase operation is initiated by execut-
ing a six-byte command sequence with Block-Erase com-
mand (50H) and block address (BA) in the last bus cycle.
The sector or block address is latched on the falling edge of
the sixth WE# pulse, while the command (30H or 50H) is
latched on the rising edge of the sixth WE# pulse. The inter-
nal Erase operation begins after the sixth WE# pulse. Any
commands issued during the Sector- or Block-Erase opera-
tion are ignored except Erase-Suspend and Erase-
Resume. See Figures 13 and 14 for timing waveforms.
The Erase-Suspend operation temporarily suspends a
Sector- or Block-Erase operation thus allowing data to be
read from any memory location, or program data into any
sector/block that is not suspended for an Erase operation.
The operation is executed by issuing a one-byte command
sequence with Erase-Suspend command (B0H). The
device automatically enters read mode no more than 10 µs
after the Erase-Suspend command had been issued. (TES
maximum latency equals 10 µs.) Valid data can be read
from any sector or block that is not suspended from an
Erase operation. Reading at address location within erase-
suspended sectors/blocks will output DQ2 toggling and
DQ6 at “1”. While in Erase-Suspend mode, a Program
operation is allowed except for the sector or block selected
for Erase-Suspend. To resume Sector-Erase or Block-
Erase operation which has been suspended, the system
must issue an Erase-Resume command. The operation is
executed by issuing a one-byte command sequence with
Erase Resume command (30H) at any address in the one-
byte sequence.
Chip-Erase Operation
The devices provide a Chip-Erase operation, which allows
the user to erase all sectors/blocks to the “1” state. This is
useful when a device must be quickly erased.
Write Operation Status Detection
These devices provide one hardware and two software
means to detect the completion of a Write (Program or
Erase) cycle in order to optimize the system Write cycle
time. The hardware detection uses the Ready/Busy# (RY/
BY#) output pin. The software detection includes two sta-
tus bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The
End-of-Write detection mode is enabled after the rising
edge of WE#, which initiates the internal Program or Erase
operation.
The Chip-Erase operation is initiated by executing a six-
byte command sequence with Chip-Erase command (10H)
at address 555H in the last byte sequence. The Erase
operation begins with the rising edge of the sixth WE# or
CE#, whichever occurs first. During the Erase operation,
the only valid Read is Toggle Bit or Data# Polling. Any com-
mands issued during the Chip-Erase operation are
ignored. See Table 5 for the command sequence, Figure
12 for timing diagram, and Figure 27 for the flowchart.
When WP# is low, any attempt to Chip-Erase will be
ignored.
The actual completion of the nonvolatile write is asynchro-
nous with the system; therefore, either a Ready/Busy# (RY/
BY#), a Data# Polling (DQ7), or Toggle Bit (DQ6) Read may
be simultaneous with the completion of the Write cycle. If
this occurs, the system may get an erroneous result, i.e.,
valid data may appear to conflict with either DQ7 or DQ6. In
order to prevent spurious rejection if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
Reads are valid, then the Write cycle has completed, other-
wise the rejection is valid.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
3
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Ready/Busy# (RY/BY#)
Toggle Bits (DQ6 and DQ2)
The devices include a Ready/Busy# (RY/BY#) output sig-
nal. RY/BY# is an open drain output pin that indicates
whether an Erase or Program operation is in progress.
Since RY/BY# is an open drain output, it allows several
devices to be tied in parallel to VDD via an external pull-up
resistor. After the rising edge of the final WE# pulse in the
command sequence, the RY/BY# status is valid.
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating “1”s
and “0”s, i.e., toggling between 1 and 0. When the internal
Program or Erase operation is completed, the DQ6 bit will
stop toggling. The device is then ready for the next opera-
tion. The toggle bit is valid after the rising edge of the fourth
WE# (or CE#) pulse for Program operations. For Sector-,
Block-, or Chip-Erase, the toggle bit (DQ6) is valid after the
rising edge of sixth WE# (or CE#) pulse. DQ6 will be set to
“1” if a Read operation is attempted on an Erase-sus-
pended Sector/Block. If Program operation is initiated in a
sector/block not selected in Erase-Suspend mode, DQ6 will
toggle.
When RY/BY# is actively pulled low, it indicates that an
Erase or Program operation is in progress. When RY/BY#
is high (Ready), the devices may be read or left in standby
mode.
Byte/Word (BYTE#)
An additional Toggle Bit is available on DQ2, which can be
used in conjunction with DQ6 to check whether a particular
sector is being actively erased or erase-suspended. Table 1
shows detailed status bit information. The Toggle Bit (DQ2)
is valid after the rising edge of the last WE# (or CE#) pulse
of a Write operation. See Figure 11 for Toggle Bit timing
diagram and Figure 24 for a flowchart.
The device includes a BYTE# pin to control whether the
device data I/O pins operate x8 or x16. If the BYTE# pin is
at logic “1” (VIH) the device is in x16 data configuration: all
data I/0 pins DQ0-DQ15 are active and controlled by CE#
and OE#.
If the BYTE# pin is at logic “0”, the device is in x8 data con-
figuration: only data I/O pins DQ0-DQ7 are active and con-
trolled by CE# and OE#. The remaining data pins DQ8-
DQ14 are at Hi-Z, while pin DQ15 is used as the address
input A-1 for the Least Significant Bit of the address bus.
TABLE 1: WRITE OPERATION STATUS
Status
DQ7
DQ6
DQ2
RY/BY#
Normal
Standard
DQ7# Toggle No Toggle
0
Operation Program
Standard
Erase
0
1
Toggle
1
Toggle
Toggle
0
1
Data# Polling (DQ7)
When the devices are in an internal Program operation, any
attempt to read DQ7 will produce the complement of the
true data. Once the Program operation is completed, DQ7
will produce true data. During internal Erase operation, any
attempt to read DQ7 will produce a ‘0’. Once the internal
Erase operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of fourth WE# (or
CE#) pulse for Program operation. For Sector-, Block-, or
Chip-Erase, the Data# Polling is valid after the rising edge
of sixth WE# (or CE#) pulse. See Figure 10 for Data# Poll-
ing (DQ7) timing diagram and Figure 24 for a flowchart.
Erase-
Suspend Erase
Mode Suspended
Read From
Sector/Block
Read From
Non-Erase
Suspended
Sector/Block
Data
Data
Data
N/A
1
Program
DQ7# Toggle
0
T1.1 1274
Note: DQ7, DQ6, and DQ2 require a valid address when reading
status information. The address must be in the bank where
the operation is in progress in order to read the operation sta-
tus. If the address is pointing to a different bank (not busy),
the device will output array data.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
4
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Data Protection
Software Data Protection (SDP)
The devices provide both hardware and software features
to protect nonvolatile data from inadvertent writes.
These devices provide the JEDEC standard Software Data
Protection scheme for all data alteration operations, i.e.,
Program and Erase. Any Program operation requires the
inclusion of the three-byte sequence. The three-byte load
sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations,
e.g., during the system power-up or power-down. Any
Erase operation requires the inclusion of the six-byte
sequence. The devices are shipped with the Software Data
Protection permanently enabled. See Table 5 for the spe-
cific software command codes. During SDP command
sequence, invalid commands will abort the device to Read
mode within TRC. The contents of DQ15-DQ8 can be VIL or
VIH, but no other value during any SDP command
sequence.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5
ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE#
high will inhibit the Write operation. This prevents inadvert-
ent writes during power-up or power-down.
Hardware Block Protection
The devices provide hardware block protection which pro-
tects the outermost 8 KWord in the larger bank. The block
is protected when WP# is held low. See Figures 1, 2, 3,
and 4 for Block-Protection location.
Common Flash Memory Interface (CFI)
These devices also contain the CFI information to
describe the characteristics of the devices. In order to
enter the CFI Query mode, the system must write the
three-byte sequence, same as the Software ID Entry com-
mand with 98H (CFI Query command) to address 555H in
the last byte sequence. See Figure 16 for CFI Entry and
Read timing diagram. Once the device enters the CFI
Query mode, the system can read CFI data at the
addresses given in Tables 6 through 8. The system must
write the CFI Exit command to return to Read mode from
the CFI Query mode.
A user can disable block protection by driving WP# high.
This allows data to be erased or programmed into the pro-
tected sectors. WP# must be held high prior to issuing the
Write command and remain stable until after the entire
Write operation has completed. If WP# is left floating, it is
internally held high via a pull-up resistor, and the Boot
Block is unprotected, enabling Program and Erase opera-
tions on that block.
Hardware Reset (RST#)
Security ID
The RST# pin provides a hardware method of resetting the
devices to read array data. When the RST# pin is held low
for at least TRP, any in-progress operation will terminate and
return to Read mode (see Figure 20). When no internal
Program/Erase operation is in progress, a minimum period
of TRHR is required after RST# is driven high before a valid
Read can take place (see Figure 19).
The SST36VF160xE devices offer a 256-bit Security ID
space. The Secure ID space is divided into two 128-bit seg-
ments—one factory programmed segment and one user
programmed segment. The first segment is programmed
and locked at SST with a unique, 128-bit number. The user
segment is left un-programmed for the customer to pro-
gram as desired. To program the user segment of the
Security ID, the user must use the Security ID Program
command. End-of-Write status is checked by reading the
toggle bits. Data# Polling is not used for Security ID End-of-
Write detection. Once programming is complete, the Sec
ID should be locked using the User Sec ID Program Lock-
Out. This disables any future corruption of this space. Note
that regardless of whether or not the Sec ID is locked, nei-
ther Sec ID segment can be erased. The Secure ID space
can be queried by executing a three-byte command
sequence with Query Sec ID command (88H) at address
555H in the last byte sequence. See Figure 18 for timing
diagram. To exit this mode, the Exit Sec ID command
should be executed. Refer to Table 5 for more details.
The Erase operation that has been interrupted needs to be
reinitiated after the device resumes normal operation mode
to ensure data integrity.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
5
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Product Identification
Product Identification Mode
Exit/CFI Mode Exit
The Product Identification mode identifies the devices and
manufacturer. For details, see Table 2 for software opera-
tion, Figure 15 for the Software ID Entry and Read timing
diagram and Figure 25 for the Software ID Entry command
sequence flowchart. The addresses A19 and A18 indicate a
bank address. When the addressed bank is switched to
Product Identification mode, it is possible to read another
address from the same bank without issuing a new Soft-
ware ID Entry command.
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exit is accom-
plished by issuing the Software ID Exit command
sequence, which returns the device to the Read mode. This
command may also be used to reset the device to the Read
mode after any inadvertent transient condition that appar-
ently causes the device to behave abnormally, e.g., not read
correctly. Please note that the Software ID Exit/CFI Exit
command is ignored during an internal Program or Erase
operation. See Table 5 for the software command code, Fig-
ure 17 for timing waveform and Figure 26 for a flowchart.
TABLE 2: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
BK0000H
00BFH
SST36VF1601E
SST36VF1602E
BK0001H
BK0001H
734BH
734AH
T2.0 1274
Note: BK = Bank Address (A19-A18
)
FUNCTIONAL BLOCK DIAGRAM
(8 KWord Sector Protection)
Address
Buffers
Memory
Address
SuperFlash Memory
12 Mbit Bank
BYTE#
RST#
CE#
SuperFlash Memory
4 Mbit Bank
Control
Logic
WP#
DQ /A - DQ
15 -1
I/O Buffers
WE#
0
OE#
1274 B01.0
RY/BY#
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
6
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Bottom Sector Protection; 32 KWord Blocks; 2 KWord Sectors
FFFFFH
F8000H
F7FFFH
F0000H
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
D7FFFH
D0000H
CFFFFH
C8000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
07FFFH
02000H
01FFFH
00000H
Block 0
8 KWord Sector Protection
(4-2 KWord Sectors)
1274 F01.0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0
FIGURE 1: SST36VF1601E, 1M X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
7
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Bottom Sector Protection; 64 KByte Blocks; 4 KByte Sectors
1FFFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
00FFFFH
004000H
003FFFH
000000H
Block 0
16 KByte Sector Protection
(4-4 KByte Sectors)
1274 F02.0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
FIGURE 2: SST36VF1601E, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
8
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Top Block Protection; 32 KWord Blocks; 2 KWord Sectors
8 KWord Block Protection
(4 - 2 KWord Sectors)
FFFFFH
FE000H
FDFFFH
F8000H
F7FFFH
F0000H
Block 31
Block 30
EFFFFH
E8000H
E7FFFH
E0000H
DFFFFH
D8000H
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
D7FFFH
D0000H
CFFFFH
C8000H
C7FFFH
C0000H
BFFFFH
B8000H
B7FFFH
B0000H
AFFFFH
A8000H
A7FFFH
A0000H
9FFFFH
98000H
97FFFH
90000H
8FFFFH
88000H
87FFFH
80000H
7FFFFH
78000H
77FFFH
70000H
6FFFFH
68000H
67FFFH
60000H
5FFFFH
58000H
57FFFH
50000H
4FFFFH
48000H
47FFFH
40000H
3FFFFH
38000H
37FFFH
30000H
2FFFFH
28000H
27FFFH
20000H
1FFFFH
18000H
17FFFH
10000H
0FFFFH
08000H
07FFFH
00000H
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
Block 0
1274 F03.0
Note: The address input range in x16 mode (BYTE#=VIH) is A19-A0
FIGURE 3: SST36VF1602E, 1M X16 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
9
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Top Block Protection; 64 KByte Blocks; 4 KByte Sectors
16 KByte Block Protection
(4 - 4 KByte Sectors)
1FFFFFH
1FC000H
1FBFFFH
1F0000H
1EFFFFH
1E0000H
1DFFFFH
1D0000H
1CFFFFH
1C0000H
1BFFFFH
1B0000H
1AFFFFH
1A0000H
19FFFFH
190000H
Block 31
Block 30
Block 29
Block 28
Block 27
Block 26
Block 25
Block 24
Block 23
Block 22
Block 21
Block 20
Block 19
Block 18
Block 17
Block 16
Block 15
Block 14
Block 13
Block 12
Block 11
Block 10
Block 9
18FFFFH
180000H
17FFFFH
170000H
16FFFFH
160000H
15FFFFH
150000H
14FFFFH
140000H
13FFFFH
130000H
12FFFFH
120000H
11FFFFH
110000H
10FFFFH
100000H
0FFFFFH
0F0000H
0EFFFFH
0E0000H
0DFFFFH
0D0000H
0CFFFFH
0C0000H
0BFFFFH
0B0000H
0AFFFFH
0A0000H
09FFFFH
090000H
08FFFFH
080000H
07FFFFH
070000H
06FFFFH
060000H
05FFFFH
050000H
04FFFFH
040000H
03FFFFH
030000H
02FFFFH
020000H
01FFFFH
010000H
Block 8
Block 7
Block 6
Block 5
Block 4
Block 3
Block 2
Block 1
00FFFFH
000000H
Block 0
1274 F04.0
Note: The address input range in x8 mode (BYTE#=VIL) is A19-A-1
FIGURE 4: SST36VF1602E, 2M X8 CONCURRENT SUPERFLASH DUAL-BANK MEMORY ORGANIZATION
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
10
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
TOP VIEW (balls facing down)
6
A13 A12 A14 A15 A16 BYTE# NOTE*
V
SS
5
4
3
2
1
A9
A8 A10 A11 DQ7 DQ14 DQ13 DQ6
WE# RST# NC A19 DQ5 DQ12 V
DQ4
DD
RY/BY#WP# A18 NC DQ2 DQ10 DQ11 DQ3
A7 A17 A6 A5 DQ0 DQ8 DQ9 DQ1
A3
A4
A2
A1
A0 CE# OE# V
SS
A
B
C
D
E
F
G
H
Note* = DQ /A
15 -1
FIGURE 5: PIN ASSIGNMENTS FOR 48-BALL TFBGA (6MM X 8MM)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A
DQ7
-1
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
Standard Pinout
Top View
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE#
RST#
NC
WP#
RY/BY#
A18
A17
A7
V
DD
Die Up
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
A6
A5
A4
A3
A2
A1
V
CE#
SS
A0
1274 48-tsop P02.0
FIGURE 6: PIN ASSIGNMENTS FOR 48-LEAD TSOP (12MM X 20MM)
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
11
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
TABLE 3: PIN DESCRIPTION
Symbol
Name
Functions
A19-A0
Address Inputs
To provide memory addresses. During Sector-Erase and Hardware Sector Protection,
A19-A11 address lines will select the sector. During Block-Erase A19-A15 address
lines will select the block.
DQ14-DQ0 Data Input/Output
To output data during Read cycles and receive input data during Write cycles
Data is internally latched during a Write cycle. The outputs are in tri-state when
OE# or CE# is high.
DQ15/A-1 Data Input/Output
and LBS Address
DQ15 is used as data I/O pin when in x16 mode (BYTE# = “1”)
A-1 is used as the LSB address pin when in x8 mode (BYTE# = “0”)
CE#
Chip Enable
To activate the device when CE# is low.
To gate the data output buffers
OE#
Output Enable
Write Enable
Hardware Reset
Ready/Busy#
WE#
To control the Write operations
RST#
RY/BY#
To reset and return the device to Read mode
To output the status of a Program or Erase operation
RY/BY# is a open drain output, so a 10KΩ - 100KΩ pull-up resistor is required
to allow RY/BY# to transition high indicating the device is ready to read.
WP#
Write Protect
To protect and unprotect top or bottom 8 KWord (4 outermost sectors) from Erase or
Program operation.
BYTE#
VDD
Word/Byte Configuration To select 8-bit or 16-bit mode.
Power Supply
Ground
To provide 2.7-3.6V power supply voltage
VSS
NC
No Connection
Unconnected pins
T3.0 1274
TABLE 4: OPERATION MODES SELECTION
DQ15-DQ8
BYTE# = VIL
Mode1
Read
CE# OE# WE#
DQ7-DQ0
DOUT
DIN
BYTE# = VIH
Address
AIN
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
DOUT
DIN
X
DQ14-DQ8 = High Z
DQ15 = A-1
Program
Erase
AIN
X2
High Z
Sector or Block
address,
555H for Chip-Erase
Standby
VIHC
X
X
VIL
X
X
X
High Z
High Z
High Z
High Z
High Z
X
X
X
Write Inhibit
High Z / DOUT
High Z / DOUT
High Z / DOUT
High Z / DOUT
X
VIH
Product
Identification
Software
Mode
VIL
VIL
VIH
Manufacturer’s ID
(BFH)
Manufacturer’s ID
(00H)
High Z
High Z
See Table 5
Device ID3
Device ID3
T4.2 1274
1. RST# = VIH for all described operation modes
2. X can be VIL or VIH, but no other value.
3. Device ID =
SST36VF1601E = 734BH,
SST36VF1602E = 734AH
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
12
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
TABLE 5: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2 Addr1 Data2
555H
555H
AAH
AAH
AAH
AAH
B0H
30H
AAH
AAH
2AAH
2AAH
2AAH
2AAH
55H
55H
55H
55H
555H
555H
555H
555H
A0H
80H
80H
80H
WA3
555H
555H
555H
Data
AAH
AAH
AAH
Program
4
4
2AAH
2AAH
2AAH
55H
55H
55H
SAX
BAX
30H
50H
10H
Sector-Erase
Block-Erase
Chip-Erase
555H
555H
555H
XXXXH
XXXXH
555H
Erase-Suspend
Erase-Resume
Query Sec ID5
2AAH
2AAH
55H
55H
555H
555H
88H
A5H
555H
SIWA6
XXH
Data
User Security ID
Program
555H
AAH
2AAH
55H
555H
85H
0000H
User Security ID
Program Lock-out7
9
Software ID Entry8
CFI Query Entry
555H
555H
555H
AAH
AAH
AAH
2AAH
2AAH
2AAH
55H
55H
55H
BKX
90H
98H
F0H
555H
9
BKX
555H
555H
Software ID Exit/
CFI Exit/
Sec ID Exit10,11
XXH
F0H
Software ID Exit/
CFI Exit/
Sec ID Exit10,11
T5.1 1274
1. Address format A10-A0 (Hex), Addresses A19-A11 can be VIL or VIH, but no other value, for the command sequence when in x16 mode.
When in x8 mode, Addresses A19-A12, Address A-1 and DQ14-DQ8 can be VIL or VIH, but no other value, for the command sequence.
2. DQ15-DQ8 can be VIL or VIH, but no other value, for the command sequence
3. WA = Program word/byte address
4. SAX for Sector-Erase; uses A19-A11 address lines
BAX for Block-Erase; uses A19-A15 address lines
5. For SST36VF1601E,
SST ID is read with A3 = 0 (Address range = 00000H to 00007H),
User ID is read with A3 = 1 (Address range = 00010H to 00017H).
Lock Status is read with A7-A0 = 000FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
For SST36VF1602E,
SST ID is read with A3 = 0 (Address range = C0000H to C0007H),
User ID is read with A3 = 1 (Address range = C0010H to C0017H).
Lock Status is read with A7-A0 = C00FFH. Unlocked: DQ3 = 1 / Locked: DQ3 = 0.
6. SIWA = User Security ID Program word/byte address
For SST36VF1601E, valid Word-Addresses for User Sec ID are from 00010H-00017H.
For SST36VF1602E, valid Word-Addresses for User Sec ID are from C0010H-C0017H.
All 4 cycles of User Security ID Program and Program Lock-out must be completed before going back to Read-Array mode.
7. The User Security ID Program Lock-out command must be executed in x16 mode (BYTE#=VIH).
8. The device does not remain in Software Product Identification mode if powered down.
9. A19 and A18 = BKX (Bank Address): address of the bank that is switched to Software ID/CFI Mode
With A17-A1 = 0;SST Manufacturer’s ID = 00BFH, is read with A0 = 0
SST36VF1601E Device ID = 734BH, is read with A0 = 1
SST36VF1602E Device ID = 734AH, is read with A0 = 1
10. Both Software ID Exit operations are equivalent
11. If users never lock after programming, User Sec ID can be programmed over the previously unprogrammed bits (data=1) using the
User Sec ID mode again (the programmed “0” bits cannot be reversed to “1”).
For SST36VF1601E, valid Word-Addresses for User Sec ID are from 00010H-00017H.
For SST36VF1602E, valid Word-Addresses for User Sec ID are from C0010H-C0017H.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
13
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
1
TABLE 6: CFI QUERY IDENTIFICATION STRING
Address
x16 Mode x8 Mode
Address
Data2
0051H
0052H
0059H
0001H
0007H
0000H
0000H
0000H
0000H
0000H
0000H
Description
Query Unique ASCII string “QRY”
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
20H
22H
24H
26H
28H
2AH
2CH
2EH
30H
32H
34H
Primary OEM command set
Address for Primary Extended Table
Alternate OEM command set (00H = none exists)
Address for Alternate OEM extended Table (00H = none exits)
T6.0 1274
1. Refer to CFI publication 100 for more details.
2. In x8 mode, only the lower byte of data is output.
TABLE 7: SYSTEM INTERFACE INFORMATION
Address
x16 Mode x8 Mode
Address
Data1
Description
DD Min (Program/Erase)
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
VDD Max (Program/Erase)
1BH
1CH
36H
38H
0027H
V
0036H
DQ7-DQ4: Volts, DQ3-DQ0: 100 millivolts
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
3AH
3CH
3EH
40H
42H
44H
46H
48H
4AH
4CH
0000H
0000H
0004H
0000H
0004H
0006H
0001H
0000H
0001H
0001H
VPP min (00H = no VPP pin)
V
PP max (00H = no VPP pin)
Typical time out for Program 2N µs (24 = 16 µs)
Typical time out for min size buffer program 2N µs (00H = not supported)
Typical time out for individual Sector/Block-Erase 2N ms (24 = 16 ms)
Typical time out for Chip-Erase 2N ms (26 = 64 ms)
Maximum time out for Program 2N times typical (21 x 24 = 32 µs)
Maximum time out for buffer program 2N times typical
Maximum time out for individual Sector-/Block-Erase 2N times typical (21 x 24 = 32 ms)
Maximum time out for Chip-Erase 2N times typical (21 x 26 = 128 ms)
T7.0 1274
1. In x8 mode, only the lower byte of data is output.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
14
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
TABLE 8: DEVICE GEOMETRY INFORMATION
Address
x16 Mode x8 Mode
Address
Data1
0015H
0002H
0000H
0000H
0000H
0002H
00FFH
0001H
0010H
0000H
001FH
0000H
0000H
0001H
Description
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
4EH
50H
52H
54H
56H
58H
5AH
5CH
5EH
60H
62H
64H
66H
68H
Device size = 2N Bytes (15H = 21; 221 = 2 MByte)
Flash Device Interface description; 0002H = x8/x16 asynchronous interface
Maximum number of bytes in multi-byte write = 2N (00H = not supported)
Number of Erase Sector/Block sizes supported by device
Sector Information (y + 1 = Number of sectors; z x 256B = sector size)
y = 511 + 1 = 512 sectors (01FFH = 512)
z = 16 x 256 Bytes = 4 KByte/sector (0010H = 16)
Block Information (y + 1 = Number of blocks; z x 256B = block size)
y = 31 + 1 = 32 blocks (001FH = 31)
z = 256 x 256 Bytes = 64 KByte/block (0100H = 256)
T8.1 1274
1. In x8 mode, only the lower byte of data is output.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
15
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OPERATING RANGE:
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Industrial
2.7-3.6V
2.7-3.6V
-40°C to +85°C
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 21 and 22
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
16
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
TABLE 9: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V
Limits
Symbol Parameter
Freq
Min
Max
Units
Test Conditions
1
IDD
Active VDD Current
Read
5 MHz
1 MHz
15
4
mA
mA
mA
mA
mA
µA
CE#=VIL, WE#=OE#=VIH
CE#=WE#=VIL, OE#=VIH
CE#=VIL, OE#=VIH
Program and Erase
30
45
35
20
20
Concurrent Read/Write
5 MHz
1 MHz
ISB
Standby VDD Current
CE#, RST#=VDD 0.3V
IALP
Auto Low Power VDD Current
µA
CE#=0.1V, VDD=VDD Max
WE#=VDD-0.1V
Address inputs=0.1V or VDD-0.1V
IRT
ILI
Reset VDD Current
20
1
µA
µA
µA
RST#=GND
Input Leakage Current
VIN =GND to VDD, VDD=VDD Max
ILIW
Input Leakage Current
on WP# pin and RST# pin
10
WP#=GND to VDD, VDD=VDD Max
RST#=GND to VDD, VDD=VDD Max
ILO
Output Leakage Current
Input Low Voltage
1
µA
V
VOUT =GND to VDD, VDD=VDD Max
VDD=VDD Min
VIL
0.8
0.3
VILC
VIH
Input Low Voltage (CMOS)
Input High Voltage
V
VDD=VDD Max
0.7 VDD VDD+0.3
VDD-0.3 VDD+0.3
0.2
V
VDD=VDD Max
VIHC
VOL
VOH
Input High Voltage (CMOS)
Output Low Voltage
V
VDD=VDD Max
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
Output High Voltage
VDD-0.2
V
T9.1 1274
1. Address input = VILT/VIHT, VDD=VDD Max (See Figure 21)
TABLE 10: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
µs
µs
1
TPU-WRITE
100
T10.0 1274
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: CAPACITANCE (TA = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
10 pF
10 pF
1
CIN
VIN = 0V
T11.0 1274
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T12.0 1274
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
17
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
AC CHARACTERISTICS
TABLE 13: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.6V
Symbol
TRC
Parameter
Min
Max
Units
ns
Read Cycle Time
70
TCE
Chip Enable Access Time
Address Access Time
70
70
30
ns
TAA
ns
TOE
Output Enable Access Time
CE# Low to Active Output
OE# Low to Active Output
CE# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
RST# Pulse Width
ns
1
TCLZ
0
0
ns
1
TOLZ
ns
1
TCHZ
16
16
ns
1
TOHZ
ns
1
TOH
0
ns
1
TRP
500
50
ns
1
TRHR
RST# High before Read
RST# Pin Low to Read Mode
ns
1,2
TRY
20
µs
T13.1 1274
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS
Symbol
TBP
Parameter
Min
Max
Units
µs
Program Time
10
TAS
Address Setup Time
Address Hold Time
WE# and CE# Setup Time
WE# and CE# Hold Time
OE# High Setup Time
OE# High Hold Time
CE# Pulse Width
0
40
0
ns
TAH
ns
TCS
ns
TCH
0
ns
TOES
TOEH
TCP
0
ns
10
40
40
30
30
30
0
ns
ns
TWP
WE# Pulse Width
ns
1
TWPH
WE# Pulse Width High
CE# Pulse Width High
Data Setup Time
ns
1
TCPH
ns
TDS
ns
1
TDH
Data Hold Time
ns
1
TIDA
Software ID Access and Exit Time
Sector-Erase
150
25
25
ns
TSE
TBE
TSCE
TES
ms
ms
ms
µs
Block-Erase
Chip-Erase
50
Erase-Suspend Latency
RY/BY# Delay Time
Bus Recovery Time
10
1,2
TBY
90
ns
1
TBR
0
µs
T14.1 1274
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
2. This parameter applies to Sector-Erase, Block-Erase, and Program operations.
This parameter does not apply to Chip-Erase operations.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
18
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
T
T
AA
RC
ADDRESSES
CE#
T
CE
T
OE
OE#
T
OHZ
T
OLZ
V
IH
WE#
T
CHZ
T
OH
T
CLZ
HIGH-Z
HIGH-Z
DQ
15-0
DATA VALID
DATA VALID
1274 F05.0
FIGURE 7: READ CYCLE TIMING DIAGRAM
T
BP
555
2AA
555
ADDR
ADDRESSES
WE#
T
AH
T
WP
T
WPH
T
AS
OE#
CE#
T
CH
T
BY
T
CS
T
BR
RY/BY#
T
DS
T
DH
DQ
VALID
15-0
XXAA
XX55
XXA0
DATA
WORD
(ADDR/DATA)
1274 F06.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 8: WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
19
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
T
BP
555
2AA
555
ADDR
ADDRESSES
T
AH
T
CP
CE#
OE#
T
CPH
T
AS
T
CH
WE#
T
BY
T
T
BR
CS
RY/BY#
T
DS
T
DH
VALID
DQ
XXAA
XX55
XXA0
DATA
15-0
WORD
1274 F07.0
(ADDR/DATA)
Note: X can be V or V , but no other value.
IL
IH
FIGURE 9: CE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
19-0
T
CE
CE#
T
OES
T
OEH
OE#
T
OE
WE#
T
BY
RY/BY#
DQ
7
DATA
DATA#
DATA#
DATA
1274 F08.0
FIGURE 10: DATA# POLLING TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
20
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
ADDRESSES
T
CE
CE#
OE#
WE#
T
OE
T
OEH
T
BR
DQ
6
VALID DATA
TWO READ CYCLES
1274 F09.0
WITH SAME OUTPUTS
FIGURE 11: TOGGLE BIT TIMING DIAGRAM
T
SCE
SIX-BYTE CODE FOR CHIP-ERASE
555 555 2AA
555
2AA
555
ADDRESSES
CE#
OE#
T
WP
WE#
T
T
BR
BY
RY/BY#
DQ
XXAA
XX55
XX80
XXAA
XX55
XX10
15-0
VALID
1274 F10.0
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals
are interchageable as long as minimum timings are met. (See Table 14)
X can be V or V , but no other value.
IL IH
FIGURE 12: WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
21
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
T
BE
SIX-BYTE CODE FOR BLOCK-ERASE
555 555 2AA
555
2AA
BA
ADDRESSES
CE#
X
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
VALID
XXAA
XX55
XX80
XXAA
XX55
XX50
DQ
15-0
1274 F11.0
Note: This device also supports CE# controlled Block-Erase operation. The WE# and CE#
signals are interchageable as long as minimum timings are met. (See Table 14)
BA = Block Address
X
X can be V or V , but no other value.
IL IH
FIGURE 13: WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
555
2AA
555
555
2AA
SA
ADDRESSES
X
CE#
OE#
T
WP
WE#
T
BR
T
BY
RY/BY#
XXAA
XX55
XX80
XXAA
XX55
XX30
DQ
VALID
15-0
1274 F12.0
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE#
signals are interchageable as long as minimum timings are met. (See Table 14)
SA = Sector Address
X
X can be V or V but no other value.
IL IH,
FIGURE 14: WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
22
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESSES
555
2AA
555
0000
0001
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
XX55
XX90
00BF
Device ID
1274 F13.0
Device ID = 734BH for SST36VF1601E and 734AH for SST36VF1602E
Note: X can be V or V , but no other value.
IL
IH
FIGURE 15: SOFTWARE ID ENTRY AND READ
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESSES
555
2AA
555
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
XXAA
XX55
XX98
15-0
1274 F14.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 16: CFI ENTRY AND READ
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
23
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
555
2AA
555
ADDRESSES
DQ
15-0
XXAA
XX55
XXF0
T
IDA
CE#
OE#
T
WP
WE#
T
WPH
1274 F15.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 17: SOFTWARE ID EXIT/CFI EXIT
THREE-BYTE SEQUENCE FOR
CFI QUERY ENTRY
ADDRESS A
555
2AA
555
19-0
CE#
OE#
WE#
T
IDA
T
WP
T
WPH
T
AA
DQ
15-0
XXAA
SW0
XX55
SW1
XX88
SW2
1274 F16.0
Note: WP# must be held in proper logic state (V or V ) 1 µs prior to and 1 µs after the command sequence
IL
IH
X can be V or V but no other value.
IH,
IL
FIGURE 18: SEC ID ENTRY
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
24
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
RY/BY#
0V
T
RP
RST#
CE#/OE#
T
RHR
1274 F17.0
FIGURE 19: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS)
T
RY
RY/BY#
RST#
T
RP
CE#
OE#
T
BR
1274 F18.0
FIGURE 20: RST# TIMING DIAGRAM (DURING SECTOR- OR BLOCK-ERASE OPERATION)
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
25
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
V
V
IHT
V
V
OT
IT
INPUT
REFERENCE POINTS
OUTPUT
ILT
1274 F19.0
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
V
V
V
OT - VOUTPUT Test
IHT - VINPUT HIGH Test
ILT - VINPUT LOW Test
FIGURE 21: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
1274 F20.0
FIGURE 22: A TEST LOAD EXAMPLE
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
26
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Start
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XXA0H
Address: 555H
Load
Address/Data
Wait for end of
Program (T
BP
Data# Polling
,
bit, or Toggle bit
operation)
Program
Completed
1274 F21.0
Note: X can be V or V , but no other value.
IL
IH
FIGURE 23: PROGRAM ALGORITHM
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
27
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Program/Erase
Initiated
Program/Erase
Initiated
Program/Erase
Initiated
Read
byte/word
Read DQ
7
Wait T
,
BP
T
T
SCE SE
,
or T
BE
Read same
byte/word
Is DQ =
7
true data?
No
Program/Erase
Completed
Yes
No
Does DQ
match?
Program/Erase
Completed
6
Yes
Program/Erase
Completed
1274 F22.0
FIGURE 24: WAIT OPTIONS
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
28
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
CFI Query Entry
Command Sequence
Sec ID Query Entry
Command Sequence
Software Product ID Entry
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX90H
Address: 555H
Load data: XX98H
Address: 555H
Load data: XX88H
Address: 555H
Wait T
Wait T
Wait T
IDA
IDA
IDA
Read Software ID
Read CFI data
Read Sec ID
X can be V or V , but no other value
IL IH
1274 F23.0
FIGURE 25: SOFTWARE PRODUCT ID/CFI/SEC ID ENTRY COMMAND FLOWCHARTS
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
29
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Software ID Exit/CFI Exit/Sec ID Exit
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXF0H
Address: XXH
Load data: XX55H
Address: 2AAH
Wait T
IDA
Load data: XXF0H
Address: 555H
Return to normal
operation
Wait T
IDA
Return to normal
operation
X can be V or V but no other value
IL
IH,
1274 F24.0
FIGURE 26: SOFTWARE PRODUCT ID/CFI/SEC ID EXIT COMMAND FLOWCHARTS
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
30
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
Chip-Erase
Sector-Erase
Block-Erase
Command Sequence
Command Sequence
Command Sequence
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XX80H
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XXAAH
Address: 555H
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX55H
Address: 2AAH
Load data: XX10H
Address: 555H
Load data: XX30H
Load data: XX50H
Address: SA
Address: BA
X
X
Wait T
Wait T
Wait T
BE
SCE
SE
Chip erased
to FFFFH
Sector erased
to FFFFH
Block erased
to FFFFH
1274 F25.0
Note: X can be V or V but no other value.
IL
IH,
FIGURE 27: ERASE COMMAND SEQUENCE
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
31
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
PRODUCT ORDERING INFORMATION
SST 36 VF 1601E - 70
-
4C
-
B3K
E
XX XX XXXXX - XXX
-
XX - XXX
X
Environmental Attribute
E1 = non-Pb
Package Modifier
K = 48 balls or leads
Package Type
B3 = TFBGA (6mm x 8mm)
E =TSOP (type 1, die up, 12mm x 20mm)
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
Bank Split
1 = 12 Mbit + 4 Mbit
2 = 4 Mbit + 12 Mbit
Device Density
160 = 1 Mbit x16 or
2 Mbit x8
Voltage
V = 2.7-3.6V
Product Series
36 = Concurrent SuperFlash
1. Environmental suffix “E” denotes non-Pb solder.
SST non-Pb solder devices are “RoHS Compliant”.
Valid combinations for SST36VF1601E
SST36VF1601E-70-4C-B3KE SST36VF1601E-70-4C-EKE
SST36VF1601E-70-4I-B3KE SST36VF1601E-70-4I-EKE
Valid combinations for SST36VF1602E
SST36VF1602E-70-4C-B3KE SST36VF1602E-70-4C-EKE
SST36VF1602E-70-4I-B3KE
SST36VF1602E-70-4I-EKE
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
32
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
PACKAGING DIAGRAMS
TOP VIEW
8.00 0.20
BOTTOM VIEW
5.60
0.80
0.45 0.05
(48X)
6
5
4
3
2
1
6
5
4
4.00
0.80
6.00 0.20
3
2
1
A
B C D E F G H
H
G F E D C B A
A1 CORNER
A1 CORNER
1.10 0.10
SIDE VIEW
0.12
SEATING PLANE
1mm
0.35 0.05
Note:
1. Complies with JEDEC Publication 95, MO-210, variant 'AB-1', although some dimensions may be more stringent.
2. All linear dimensions are in millimeters.
3. Coplanarity: 0.12 mm
4. Ball opening size is 0.38 mm ( 0.05 mm)
48-tfbga-B3K-6x8-450mic-4
48-BALL THIN-PROFILE, FINE-PITCH BALL GRID ARRAY (TFBGA) 6MM X 8MM
SST PACKAGE CODE: B3K
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
33
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
1.05
0.95
Pin # 1 Identifier
0.50
BSC
0.27
0.17
12.20
11.80
0.15
0.05
18.50
18.30
DETAIL
1.20
max.
0.70
0.50
20.20
19.80
0˚- 5˚
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 DD dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 mm
1mm
48-tsop-EK-8
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
48-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 12MM X 20MM
SST PACKAGE CODE: EK
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
34
16 Mbit Concurrent SuperFlash
SST36VF1601E / SST36VF1602E
Data Sheet
TABLE 15: REVISION HISTORY
Number
Description
Date
00
01
Oct 2004
Mar 2005
•
•
Initial release of data sheet
Updates to data sheet Tables 1, 4, 5, 8, 9, and 13. Added RoHS compliance information
on page 1 and in the “Product Ordering Information” on page 33
•
•
•
•
•
•
•
Updated sector information in Table 8, “Device Geometry Information” on page 16
Updated Active Current values and test conditions in Table 9 on page 18
Updated OE timings in Table 13 on page 19
Added a Reset footnote to Table 4 on page 13
Updated the footnote for Table 1 on page 4
Corrected the Address Format in footnote 1 in Table 5 on page 14
Clarified the solder temperature profile under “Absolute Maximum Stress Ratings” on
page 17
02
03
Jul 2005
•
•
•
Updated “Erase-Suspend/Erase-Resume Operations” on page 3
Updated TES parameter from 20 µs to 10 µs in Table 14 on page 19
Made changes to support Pb-free packages only
Nov 2005
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2005 Silicon Storage Technology, Inc.
S71274-03-000
11/05
35
相关型号：
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Flash, 1MX16, 70ns, PBGA48, 6 X 8 MM, ROHS COMPLIANT, MO-210AB-1, TFBGA-48
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