SST31LF021-70-4C-WH [SST]
2 Mbit Flash + 1 Mbit SRAM ComboMemory; 2兆位闪存+ 1兆位的SRAM ComboMemory
| 型号： | SST31LF021-70-4C-WH |
| 厂家： | 
SILICON STORAGE TECHNOLOGY, INC |
| 描述： | 2 Mbit Flash + 1 Mbit SRAM ComboMemory |
| 文件： | 总24页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
SST31LF021 / 021E2 Mb Flash (x8) + 1 Mb SRAM (x8) Monolithic ComboMemories
Data Sheet
FEATURES:
•
Monolithic Flash + SRAM ComboMemory
– SST31LF021/021E: 256K x8 Flash + 128K x8 SRAM
Single 3.0-3.6V Read and Write Operations
Concurrent Operation
•
•
Fast Read Access Times:
– SST31LF021
Flash: 70 ns
SRAM: 70 ns
Flash: 300 ns
SRAM: 300 ns
•
•
– SST31LF021E
– Read from or Write to SRAM while
Erase/Program Flash
Flash Fast Erase and Byte-Program:
– Sector-Erase Time: 18 ms (typical)
– Bank-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Bank Rewrite Time: 4 seconds (typical)
Flash Automatic Erase and Program Timing
– Internal VPP Generation
•
•
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Low Power Consumption:
•
•
– Active Current: 10 mA (typical) for Flash and
20 mA (typical) for SRAM Read
– Standby Current: 10 µA (typical)
Flash End-of-Write Detection
– Toggle Bit
– Data# Polling
•
•
Flash Sector-Erase Capability
– Uniform 4 KByte sectors
•
•
•
CMOS I/O Compatibility
JEDEC Standard Command Set
Package Available
Latched Address and Data for Flash
– 32-lead TSOP (8mm x 14mm)
PRODUCT DESCRIPTION
The SST31LF021/021E devices are a 256K x8 CMOS
flash memory bank combined with a 128K x8 or 32K x8
CMOS SRAM memory bank manufactured with SST’s
proprietary, high performance SuperFlash technology. Two
pinout standards are available for these devices. The
SST31LF021 conform to JEDEC standard flash pinouts
and the SST31LF021E conforms to standard EPROM
pinouts. The SST31LF021/021E devices write (SRAM or
flash) with a 3.0-3.6V power supply. The monolithic
SST31LF021/021E devices conform to Software Data
Protect (SDP) commands for x8 EEPROMs.
The SST31LF021/021E operate as two independent mem-
ory banks with respective bank enable signals. The SRAM
and flash memory banks are superimposed in the same
memory address space. Both memory banks share com-
mon address lines, data lines, WE# and OE#. The memory
bank selection is done by memory bank enable signals.
The SRAM bank enable signal, BES# selects the SRAM
bank and the flash memory bank enable signal, BEF#
selects the flash memory bank. The WE# signal has to be
used with Software Data Protection (SDP) command
sequence when controlling the Erase and Program opera-
tions in the flash memory bank. The SDP command
sequence protects the data stored in the flash memory
bank from accidental alteration.
Featuring high performance Byte-Program, the flash
memory bank provides a maximum Byte-Program time of
20 µsec. The entire flash memory bank can be erased and
programmed byte-by-byte in typically 4 seconds, when
using interface features such as Toggle Bit or Data# Poll-
ing to indicate the completion of Program operation. To
protect against inadvertent flash write, the SST31LF021/
021E devices have on-chip hardware and Software Data
Protection schemes. Designed, manufactured, and tested
for a wide spectrum of applications, the SST31LF021/
021E devices are offered with a guaranteed endurance of
10,000 cycles. Data retention is rated at greater than 100
years.
The SST31LF021/021E provide the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Byte-Program concurrently. All flash
memory Erase and Program operations will automatically
latch the input address and data signals and complete the
operation in background without further input stimulus
©2001 Silicon Storage Technology, Inc.
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory are trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71137-03-000 10/01
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392
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
requirement. Once the internally controlled Erase or Pro-
gram cycle in the flash bank has commenced, the SRAM
bank can be accessed for Read or Write.
SRAM Operation
With BES# low and BEF# high, the SST31LF021/021E
operate as a 128K x8 or 32K x8 CMOS SRAM, with fully
static operation requiring no external clocks or timing
strobes. The SRAM is mapped into the first 128 KByte
address space of the device. Read and Write cycle times
are equal.
The SST31LF021/021E devices are suited for applications
that use both nonvolatile flash memory and volatile SRAM
memory to store code or data. For all system applications,
the SST31LF021/021E devices significantly improve per-
formance and reliability, while lowering power consumption,
when compared with multiple chip solutions. The
SST31LF021/021E inherently use less energy during
Erase and Program than alternative flash technologies.
When programming a flash device, the total energy con-
sumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter Erase time, the total energy consumed dur-
ing any Erase or Program operation is less than alternative
flash technologies. The monolithic ComboMemory elimi-
nates redundant functions when using two separate mem-
ories of similar architecture; therefore, reducing the total
power consumption.
SRAM Read
The SRAM Read operation of the SST31LF021/021E are
controlled by OE# and BES#, both have to be low with
WE# high, for the system to obtain data from the outputs.
BES# is used for SRAM bank selection. When BES# and
BEF# are high, both memory banks are deselected. OE#
is the output control and is used to gate data from the out-
put pins. The data bus is in high impedance state when
OE# is high. See Figure 2 for the Read cycle timing dia-
gram.
SRAM Write
The SRAM Write operation of the SST31LF021/021E are
controlled by WE# and BES#, both have to be low for the
system to write to the SRAM. BES# is used for SRAM bank
selection. During the Byte-Write operation, the addresses
and data are referenced to the rising edge of either BES#
or WE#, whichever occurs first. The Write time is measured
from the last falling edge to the first rising edge of BES# and
WE#. See Figure 3 for the Write cycle timing diagram.
The SuperFlash technology provides fixed Erase and Pro-
gram times, independent of the number of Erase/Program
cycles that have occurred. Therefore the system software
or hardware does not have to be modified or de-rated as is
necessary with alternative flash technologies, whose Erase
and Program times increase with accumulated Erase/Pro-
gram cycles.
The SST31LF021/021E devices also improve flexibility by
using a single package and a common set of signals to
perform functions previously requiring two separate
devices. To meet high density, surface mount requirements,
the SST31LF021/021E devices are offered in 32-lead
TSOP packages. See Figure 1 for the pinouts.
Flash Operation
With BEF# active, the SST31LF021/021E operate as a
256K x8 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with the
JEDEC standard SDP command sequences. Address and
data are latched during the SDP commands and internally
timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control oper-
ation of either the SRAM or the flash memory bank. Bus
contention is eliminated as the monolithic device will not
recognize both bank enables as being simultaneously
active. If both bank enables are asserted (i.e., BEF# and
BES# are both low), the BEF# will dominate while the
BES# is ignored and the appropriate operation will be exe-
cuted in the flash memory bank. SST does not recommend
that both bank enables be simultaneously asserted. All
other address, data, and control lines are shared; which
minimizes power consumption and area. The device goes
into standby when both bank enables are raised to VIHC.
Flash Read
The Read operation of the SST31LF021/021E devices are
controlled by BEF# and OE#, both have to be low, with
WE# high, for the system to obtain data from the outputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected and
only standby power is consumed. OE# is the output control
and is used to gate data from the output pins. The data bus
is in high impedance state when OE# is high. See Figure 4
for the Read cycle timing diagram.
©2001 Silicon Storage Technology, Inc.
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
Flash Erase/Program Operation
Flash Bank-Erase Operation
SDP commands are used to initiate the flash memory bank
Program and Erase operations of the SST31LF021/021E.
SDP commands are loaded to the flash memory bank
using standard microprocessor write sequences. A com-
mand is loaded by asserting WE# low while keeping BEF#
low and OE# high. The address is latched on the falling
edge of WE# or BEF#, whichever occurs last. The data is
latched on the rising edge of WE# or BEF#, whichever
occurs first.
The SST31LF021/021E flash memory bank provides a
Bank-Erase operation, which allows the user to erase the
entire flash memory bank array to the ‘1’s state. This is use-
ful when the entire bank must be quickly erased. The Bank-
Erase operation is initiated by executing a six-byte Software
Data Protection command sequence with Bank-Erase com-
mand (10H) with address 5555H in the last byte sequence.
The internal Erase operation begins with the rising edge of
the sixth WE# or BEF# pulse, whichever occurs first. During
the internal Erase operation, the only valid Flash Read oper-
ations are Toggle Bit and Data# Polling. See Table 4 for the
command sequence, Figure 10 for timing diagram, and Fig-
ure 19 for the flowchart. Any SDP commands loaded during
the Bank-Erase operation will be ignored.
Flash Byte-Program Operation
The flash memory bank of the SST31LF021/021E devices
are programmed on a byte-by-byte basis. Before the Pro-
gram operations, the memory must be erased first. The
Program operation consists of three steps. The first step is
the three-byte load sequence for Software Data Protection.
The second step is to load byte address and byte data.
During the Byte-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#, which-
ever occurs last. The data is latched on the rising edge of
either BEF# or WE#, whichever occurs first. The third step
is the internal Program operation which is initiated after the
rising edge of the fourth WE# or BEF#, whichever occurs
first. The Program operation, once initiated, will be com-
pleted, within 20 µs. See Figures 5 and 6 for WE# and
BEF# controlled Program operation timing diagrams and
Figure 16 for flowcharts. During the Program operation, the
only valid Flash Read operations are Data# Polling and
Toggle Bit. During the internal Program operation, the host
is free to perform additional tasks. Any SDP commands
loaded during the internal Program operation will be
ignored.
Flash Write Operation Status Detection
The SST31LF021/021E flash memory bank provides two
software means to detect the completion of a flash memory
bank Write (Program or Erase) cycle, in order to optimize
the system Write cycle time. The software detection
includes two status bits: Data# Polling (DQ7) and Toggle Bit
(DQ6). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Program
or Erase operation. The actual completion of the nonvola-
tile write is asynchronous with the system; therefore, either
a Data# Polling or Toggle Bit Read may be simultaneous
with the completion of the Write cycle. If this occurs, the
system may possibly get an erroneous result, i.e., valid
data may appear to conflict with either DQ7 or DQ6. In
order to prevent spurious rejection, if an erroneous result
occurs, the software routine should include a loop to read
the accessed location an additional two (2) times. If both
reads are valid, then the device has completed the Write
cycle, otherwise the rejection is valid.
Flash Sector-Erase Operation
The Sector-Erase operation allows the system to erase the
flash memory bank on a sector-by-sector basis. The sector
architecture is based on uniform sector size of 4 KByte.
The Sector-Erase operation is initiated by executing a six-
byte command load sequence for Software Data Protec-
tion with Sector-Erase command (30H) and sector address
(SA) in the last bus cycle. The address lines A17-A12 will be
used to determine the sector address. The sector address
is latched on the falling edge of the sixth WE# pulse, while
the command (30H) is latched on the rising edge of the
sixth WE# pulse. The internal Erase operation begins after
the sixth WE# pulse. The End-of-Erase can be determined
using either Data# Polling or Toggle Bit methods. See Fig-
ure 9 for timing waveforms. Any SDP commands loaded
during the Sector-Erase operation will be ignored.
Flash Data# Polling (DQ7)
When the SST31LF021/021E flash memory bank is in the
internal Program operation, any attempt to read DQ7 will
produce the complement of the true data. Once the Pro-
gram operation is completed, DQ7 will produce true data.
Note that even though DQ7 may have valid data immedi-
ately following the completion of an internal Write opera-
tion, the remaining data outputs may still be invalid: valid
data on the entire data bus will appear in subsequent suc-
cessive Read cycles after an interval of 1 µs. During inter-
nal Erase operation, any attempt to read DQ7 will produce
a ‘0’. Once the internal Erase operation is completed, DQ7
will produce a ‘1’. The Data# Polling is valid after the rising
edge of the fourth WE# (or BEF#) pulse for Program opera-
tion. For Sector or Bank-Erase, the Data# Polling is valid
©2001 Silicon Storage Technology, Inc.
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
after the rising edge of the sixth WE# (or BEF#) pulse. See
Figure 7 for Data# Polling timing diagram and Figure 17 for
a flowchart.
Concurrent Read and Write Operations
The SST31LF021/021E provide the unique benefit of
being able to read from or write to SRAM, while simulta-
neously erasing or programming the flash. The device will
ignore all SDP commands when an Erase or Program
operation is in progress. This allows data alteration code to
be executed from SRAM, while altering the data in flash.
The following table lists all valid states. SST does not rec-
ommend that both bank enables, BEF# and BES#, be
simultaneously asserted.
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any con-
secutive attempts to read DQ6 will produce alternating 0s
and 1s, i.e., toggling between 0 and 1. When the internal
Program or Erase operation is completed, the toggling will
stop. The flash memory bank is then ready for the next
operation. The Toggle Bit is valid after the rising edge of the
fourth WE# (or BE#) pulse for Program operation. For Sec-
tor or Bank-Erase, the Toggle Bit is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 8 for
Toggle Bit timing diagram and Figure 17 for a flowchart.
CONCURRENT READ/WRITE STATE TABLE
Flash
SRAM
Read
Write
Program/Erase
Program/Erase
Flash Memory Data Protection
Note that Product Identification commands use SDP;
therefore, these commands will also be ignored while an
Erase or Program operation is in progress.
The SST31LF021/021E flash memory bank provides both
hardware and software features to protect nonvolatile data
from inadvertent writes.
Product Identification
Flash Hardware Data Protection
The Product Identification mode identifies the devices as
either SST31LF021 or SST31LF021E and the manufac-
turer as SST. This mode may be accessed by hardware or
software operations. The hardware device ID Read opera-
tion is typically used by a programmer to identify the correct
algorithm for the SST31LF021/021E flash memory banks.
Users may wish to use the software Product Identification
operation to identify the part (i.e., using the device ID) when
using multiple manufacturers in the same socket. For
details, see Table 3 for hardware operation or Table 4 for
software operation, Figure 11 for the software ID entry and
read timing diagram and Figure 18 for the ID entry com-
mand sequence flowchart.
Noise/Glitch Protection: A WE# or BEF# pulse of less than
5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, BEF# high, or WE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
The SST31LF021/021E provide the JEDEC approved
Software Data Protection scheme for all flash memory
bank data alteration operations, i.e., Program and Erase.
Any Program operation requires the inclusion of a series of
three-byte sequence. The three-byte load sequence is
used to initiate the Program operation, providing optimal
protection from inadvertent Write operations, e.g., during
the system power-up or power-down. Any Erase operation
requires the inclusion of six-byte load sequence. The
SST31LF021/021E devices are shipped with the Software
Data Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP command
sequence, invalid SDP commands will abort the device to
the Read mode, within TRC.
TABLE 1: PRODUCT IDENTIFICATION
Address
Data
Manufacturer’s ID
Device ID
0000H
BFH
SST31LF021
SST31LF021E
0001H
0001H
18H
19H
T1.4 392
Product Identification Mode Exit/Reset
In order to return to the standard Read mode, the Software
Product Identification mode must be exited. Exiting is
accomplished by issuing the Exit ID command sequence,
which returns the device to the Read operation. Please
note that the software reset command is ignored during an
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
internal Program or Erase operation. See Table 4 for soft-
ware command codes, Figure 12 for timing waveform and
Figure 18 for a flowchart.
Design Considerations
SST recommends a high frequency 0.1 µF ceramic capac-
itor to be placed as close as possible between VDD and
VSS, e.g., less than 1 cm away from the VDD pin of the
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm of
the VDD pin.
FUNCTIONAL BLOCK DIAGRAM
SRAM
Address Buffers
Control Logic
BES#
BEF#
OE#
A
- A
0
I/O Buffers
MS
DQ - DQ
7 0
WE#
Address Buffers
& Latches
SuperFlash
Memory
392 ILL B1.2
Note: A
MS
= Most Significant Address
SST31LF021E
SST31LF021
SST31LF021
SST31LF021E
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
OE#
A10
A11
A9
2
A8
3
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
A8
A13
A14
A17
WE#
4
A13
A14
A17
BES#
5
Standard Pinout
Top View
6
7
V
8
V
DD
DD
BES#
A16
A15
A12
A7
9
V
V
WE#
A16
A15
A12
A7
SS
SS
Die Up
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
DQ2
DQ1
DQ0
A0
A6
A1
A1
A6
A5
A2
A2
A5
A4
A3
A3
A4
392 ILL F01.3
FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP (8MM X 14MM)
©2001 Silicon Storage Technology, Inc.
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5
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
TABLE 2: PIN DESCRIPTION
Symbol
Pin Name
Functions
AMS1-A0
Address Inputs
To provide memory addresses.
During flash Sector-Erase, A17-A12 address lines will select the sector.
A17-A0 to provide flash address
A16-A0 to provide SST31LF021/021E SRAM
addresses
DQ7-DQ0
Data Input/Output
To output data during Read cycles and receive input data during Write cycles.
Data is internally latched during a flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
OE#
WE#
VDD
SRAM Memory Bank Enable To activate the SRAM memory bank when BES# is low.
Flash Memory Bank Enable To activate the Flash memory bank when BEF# is low.
Output Enable
Write Enable
Power Supply
Ground
To gate the data output buffers.
To control the Write operations.
3.0-3.6V Power Supply
VSS
T2.3 392
1. AMS = Most significant address
TABLE 3: OPERATION MODES SELECTION
Mode
BES#
BEF#
OE#
WE#
A9 DQ
Address
Flash
Read
X1
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
AIN DOUT
AIN DIN
AIN
Program
Erase
AIN
X
X
X
Sector address,
XXH for Bank-Erase
SRAM
Read
VIL
VIL
VIHC
X
VIH
VIH
VIHC
X
VIL
X
VIH
VIL
X
AIN DOUT
AIN DIN
AIN
AIN
X
Write
Standby
X
X
X
X
X
High Z
Flash Write Inhibit
VIL
X
X
High Z / DOUT
High Z / DOUT
High Z / DOUT
X
X
X
VIH
X
X
X
VIH
X
X
Product Identification
Hardware Mode
X
X
VIL
VIL
VIL
VIL
VIH
VIH
VH Manufacturer’s ID (BFH)
Device ID2
A17-A1=VIL, A0=VIL
A17-A1=VIL, A0=VIH
Software Mode
AIN ID Code
See Table 4
T3.4 392
1. X can be VIL or VIH, but no other value.
2. Device ID 18H for SST31LF021, 19H for SST31LF021E.
©2001 Silicon Storage Technology, Inc.
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
TABLE 4: SOFTWARE COMMAND SEQUENCE
Command
Sequence
1st Bus
Write Cycle
2nd Bus
Write Cycle
3rd Bus
Write Cycle
4th Bus
Write Cycle
5th Bus
Write Cycle
6th Bus
Write Cycle
Addr1 Data
Addr1
Data Addr1 Data Addr1 Data
BA2
Data
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H
Addr1
Data Addr1 Data
Byte-Program
Sector-Erase
Bank-Erase
5555H AAH 2AAAH 55H 5555H A0H
3
SAX
30H
5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H 10H
Software ID Entry4,5 5555H AAH 2AAAH 55H 5555H 90H
Software ID Exit 5555H AAH 2AAAH 55H 5555H F0H
T4.4 392
1. Address format A14-A0 (Hex),Address A15, A16, and A17 can be VIL or VIH, but no other value, for the Command sequence.
2. BA = Program Byte address
3. SAX for Sector-Erase; uses A17-A12 address lines
4. The device does not remain in Software Product ID mode if powered down.
5. With A17-A1 = 0; SST Manufacturer’s ID = BFH, is read with A0 = 0,
SST31LF021 Device ID = 18H, is read with A0 = 1,
SST31LF021E Device ID = 19H, is read with A0 = 1
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-1.0V to VDD+1.0V
Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C
Output Short Circuit Current1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE: SST31LF021/021E
AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
See Figures 14 and 15
Range
Ambient Temp
0°C to +70°C
VDD
Commercial
Extended
3.0-3.6V
3.0-3.6V
-20°C to +85°C
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
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2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
TABLE 5: DC OPERATING CHARACTERISTICS (VDD = 3.0-3.6V)
Limits
Symbol Parameter
IDD Power Supply Current
Min
Max Units Test Conditions
Address input VIL/VIH, at f=1/TRC Min,
VDD=VDD Max, all DQs open
Read
Flash
OE#=VIL, WE#=VIH
BEF#=VIL, BES#=VIH
12
40
55
mA
mA
mA
SRAM
BEF#=VIH, BES#=VIL
BEF#=VIH, BES#=VIL
Concurrent Operation
Write
OE#=VIH, WE#=VIL
Flash (Program)
15
40
30
1
mA
mA
µA
µA
µA
V
BEF#=VIL, BES#=VIH
SRAM
BEF#=VIH, BES#=VIL
1
ISB
ILI
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
BEF#=BES#=VIHC, VDD=VDD Max
VIN=GND to VDD, VDD=VDD Max
VOUT=GND to VDD, VDD=VDD Max
VDD=VDD Min
ILO
VIL
VIH
VIHC
VOL
VOH
VH
1
0.4
Input High Voltage
0.7VDD
V
VDD=VDD Max
Input High Voltage (CMOS)
Output Low Voltage
Output High Voltage
Supervoltage for A9 pin
Supervoltage Current for A9 pin
VDD-0.3
V
VDD=VDD Max
0.2
V
IOL=100 µA, VDD=VDD Min
IOH=-100 µA, VDD=VDD Min
BEF#=OE#=VIL, WE#=VIH
BEF#=OE#=VIL, WE#=VIH, A9=VH Max
VDD-0.2
11.4
V
12.6
200
V
IH
µA
T5.3 392
1. Specification applies to commercial temperature devices only. This parameter may be higher for extended devices.
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
100
Units
µs
1
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
1
TPU-WRITE
100
µs
T6.1 392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
VI/O = 0V
Maximum
1
CI/O
I/O Pin Capacitance
Input Capacitance
12 pF
6 pF
1
CIN
VIN = 0V
T7.0 392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Data Retention
Latch Up
Minimum Specification
Units
Test Method
1
NEND
10,000
100
Cycles JEDEC Standard A117
1
TDR
Years
mA
JEDEC Standard A103
JEDEC Standard 78
1
ILTH
100 + IDD
T8.1 392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
8
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
AC CHARACTERISTICS
TABLE 9: SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
SST31LF021E-300
Symbol
TRCS
Parameter
Min
Max
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
70
300
TAAS
Address Access Time
70
70
35
300
300
150
TBES
Bank Enable Access Time
Output Enable Access Time
BES# to Active Output
TOES
1
TBLZS
0
0
15
15
1
TOLZS
Output Enable to Active Output
BES# to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
1
TBHZS
25
25
30
30
1
TOHZS
TOHS
0
10
ns
T9.4 392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 10: SRAM MEMORY BANK WRITE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
Min Max
SST31LF021E-300
Symbol
TWCS
TBWS
TAWS
Parameter
Min
300
230
230
0
Max
Unit
ns
Write Cycle Time
70
60
60
0
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
ns
ns
TASTS
TWPS
TWRS
TDSS
ns
60
0
200
0
ns
Write recovery Time
Data Set-up Time
ns
30
0
150
0
ns
TDHS
Data Hold from Write Time
ns
T10.4 392
TABLE 11: FLASH READ CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
SST31LF021E-300
Symbol Parameter
Min
Max
Min
Max
Units
ns
TRC
TBE
TAA
Read Cycle Time
70
300
Bank Enable Access Time
Address Access Time
70
70
40
300
300
150
ns
ns
TOE
TBLZ
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
ns
1
1
0
0
0
0
ns
TOLZ
TBHZ
ns
1
1
15
15
60
60
ns
TOHZ
ns
1
TOH
0
0
ns
T11.3 392
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
9
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS (VDD = 3.0-3.6V)
SST31LF021-70
Min Max
SST31LF021E-300
Symbol Parameter
Min
Max
Units
µs
TBP
Byte-Program Time
20
20
TAS
Address Setup Time
0
30
0
0
50
0
ns
TAH
Address Hold Time
ns
TBS
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
ns
TBH
TOES
TOEH
TBP
0
0
ns
0
0
ns
10
40
40
30
30
40
0
10
100
100
50
50
50
0
ns
ns
TWP
TWPH
TBPH
TDS
TDH
TIDA
TSE
WE# Pulse Width
ns
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
ns
ns
ns
Data Hold Time
ns
Software ID Access and Exit Time
Sector-Erase
150
25
150
25
ns
ms
ms
TSBE
TBS
Bank-Erase
100
100
Bank Enable Setup Time for Concurrent Operation
0
0
ns
T12.3 392
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
10
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
T
T
RCS
AAS
ADDRESS A
16-0
BEF#
BES#
OE#
T
BES
T
OES
T
T
OHZS
OLZS
V
IH
WE#
T
BHZS
T
T
OHS
BLZS
HIGH-Z
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
392 ILL F02.0
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESS A
ADDRESS
16-0
T
AWS
OE#
BEF#
BES#
WE#
T
BWS
T
WRS
T
WPS
T
ASTS
T
DSS
DATA VALID
T
DHS
DQ
7-0
392 ILL F03.0
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
11
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
T
T
AA
RC
ADDRESS A
17-0
BES#
BEF#
OE#
T
BE
T
OE
T
T
OHZ
V
OLZ
IH
WE#
T
BHZ
T
OH
T
HIGH-Z
BLZ
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
392 ILL F18.0
FIGURE 4: FLASH READ CYCLE TIMING DIAGRAM
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
17-0
T
AH
T
DH
T
WP
WE#
OE#
T
T
AS
DS
T
WPH
T
CH
BEF#
T
CS
BES#
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
392 ILL F04.0
FIGURE 5: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
12
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
17-0
BES#
BEF#
OE#
T
AH
T
DH
T
CP
T
T
AS
DS
T
CPH
T
CH
WE#
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
392 ILL F05.0
FIGURE 6: BEF# CONTROLLED FLASH PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
17-0
BES#
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
D
D#
D#
D
392 ILL F06.0
FIGURE 7: FLASH DATA# POLLING TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
13
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
ADDRESS A
17-0
BES#
T
BE
BEF#
OE#
T
OES
T
T
OE
OEH
WE#
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
392 ILL F07.0
FIGURE 8: FLASH TOGGLE BIT TIMING DIAGRAM
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555 5555 2AAA
5555
2AAA
SA
X
ADDRESS A
17-0
BES#
BEF#
OE#
T
WP
WE#
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW0
SW5
392 ILL F08.1
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF#
signals are interchangeable as long as minimum timings are met. (See Table 12)
SA = Sector Address
X
FIGURE 9: WE# CONTROLLED FLASH SECTOR-ERASE TIMING DIAGRAM
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
14
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
T
SBE
SIX-BYTE CODE FOR BANK-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
17-0
BES#
BEF#
OE#
T
WP
WE#
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW0
SW5
392 ILL F17.1
Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See Table 12)
FIGURE 10: WE# CONTROLLED FLASH BANK-ERASE TIMING DIAGRAM
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
5555
2AAA
5555
0000
0001
14-0
BES#
BEF#
OE#
T
IDA
T
WP
AA
WE#
T
WPH
55
SW1
T
AA
DQ
7-0
90
BF
DEVICE ID
SW0
SW2
MFG ID
392 ILL F09.5
Device ID = 18H for SST31LF021 and 19H for SST31LF021E.
FIGURE 11: FLASH SOFTWARE ID ENTRY AND READ
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
15
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
5555
2AAA
5555
ADDRESS A
14-0
BES#
T
IDA
BEF#
OE#
T
WP
WE#
T
WHP
SW0
AA
SW1
SW2
F0
DQ
55
7-0
392 ILL F10.0
FIGURE 12: FLASH SOFTWARE ID EXIT AND RESET
ADDRESS A
17-0
BEj#
T
BS
BEj1#
WE#
OE#
DQ
7-0
392 ILL F20.0
Note: j = F or S
j1 = S or F
FIGURE 13: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH/SRAM AND SRAM/FLASH
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
16
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
392 ILL F11.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VIT - VINPUT Test
VOT - VOUTPUT Test
VIHT - VINPUT HIGH Test
V
ILT - VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
392 ILL F12.1
FIGURE 15: A TEST LOAD EXAMPLE
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
17
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
Start
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: A0H
Address: 5555H
Load Byte
Address/Byte
Data
Wait for end of
Program (T
,
BP
DATA# Polling
bit, or Toggle bit
operation)
Program
Completed
392 ILL F13.1
FIGURE 16: BYTE-PROGRAM ALGORITHM
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
18
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
Toggle Bit
Data# Polling
Internal Timer
Byte
Program/Erase
Initiated
Byte
Program/Erase
Initiated
Byte
Program/Erase
Initiated
Read DQ
7
Read byte
Wait T
BP
SBE, or SE
,
T
T
Read same
byte
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
392 ILL F14.0
FIGURE 17: WAIT OPTIONS
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
19
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: F0H
Address: XXH
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Wait T
IDA
Load data: 90H
Address: 5555H
Load data: F0H
Address: 5555H
Return to normal
operation
Wait T
IDA
Wait T
IDA
Return to normal
operation
Read Software ID
392 ILL F15.1
FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
20
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
Chip-Erase
Sector-Erase
Command Sequence
Command Sequence
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 80H
Address: 5555H
Load data: 80H
Address: 5555H
Load data: AAH
Address: 5555H
Load data: AAH
Address: 5555H
Load data: 55H
Address: 2AAAH
Load data: 55H
Address: 2AAAH
Load data: 10H
Address: 5555H
Load data: 30H
Address: SA
X
Wait T
SBE
Wait T
SE
Chip erased
to FFH
Sector erased
to FFH
392 ILL F16.1
FIGURE 19: ERASE COMMAND SEQUENCE
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
21
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
PRODUCT ORDERING INFORMATION
Device
Speed
Suffix1
Suffix2
XX
SST31LF021x - XXX
-
XX
-
Package Modifier
H = 32 leads
Package Type
W = TSOP (type 1, die up, 8mm x 14mm)
Temperature Range
C = Commercial = 0°C to +70°C
E = Extended = -20°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Read Access Speed
70 = 70 ns
300 = 300 ns
Version
Blank = Flash Pinout
E = EPROM Pinout
Density
021 = 2 Mbit Flash + 1 Mbit SRAM
Voltage
L = 3.0-3.6V
Device Family
31 = Monolithic ComboMemory
Valid combinations for SST31LF021
SST31LF021-70-4C-WH
SST31LF021-70-4E-WH
Valid combinations for SST31LF021E
SST31LF021E-300-4C-WH
SST31LF021E-300-4E-WH
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
22
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
PACKAGING DIAGRAMS
1.05
0.95
Pin # 1 Identifier
0.50
BSC
8.10
7.90
0.27
0.17
0.15
0.05
12.50
12.30
DETAIL
1.20
max.
0.70
0.50
14.20
13.80
0˚- 5˚
32-tsop-WH-ILL.6
1mm
0.70
0.50
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions,
although some dimensions may be more stringent.
2. All linear dimensions are in millimeters (max/min).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads.
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 14MM
SST PACKAGE CODE: WH
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
23
2 Mbit Flash + 1 Mbit SRAM ComboMemory
SST31LF021 / SST31LF021E
Data Sheet
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com
©2001 Silicon Storage Technology, Inc.
S71137-03-000 10/01 392
24
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