SST31LF021E-300-4C-KH [SILICON]
Memory Circuit, Flash+SRAM, CMOS, PDSO32;
| 型号： | SST31LF021E-300-4C-KH |
| 厂家： | 
SILICON |
| 描述： | Memory Circuit, Flash+SRAM, CMOS, PDSO32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总22页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
FEATURES:
•
•
•
Organized as 256K x8 Flash + 128K x8 SRAM
Single 3.0-3.6V Read and Write Operations
ConcurrentOperation
•
•
Latched Address and Data for Flash
1
FlashFastEraseandByte-Program:
– Sector-Erase Time: 18 ms (typical)
– Bank-Erase Time: 70 ms (typical)
– Byte-Program Time: 14 µs (typical)
– Bank Rewrite Time: 4 seconds (typical)
– Read from or Write to SRAM while
Erase/Program Flash
2
•
•
Superior Reliability
•
•
Flash Automatic Erase and Program Timing
– Internal VPP Generation
3
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
FlashEnd-of-WriteDetection
Low Power Consumption:
– Toggle Bit
– Data# Polling
4
– Active Current: 10 mA (typical) for Flash
and 20 mA (typical) for SRAM Read
– Standby Current: 10 µA (typical)
•
•
•
CMOS I/O Compatibility
5
•
•
FlashSector-EraseCapability
– Uniform 4 KByte sectors
FastReadAccessTimes:
JEDEC Standard Command Set
Packages Available
– 32-Pin TSOP (8mm x 13.4mm)
6
– Flash: 300 ns
– SRAM: 300 ns
7
PRODUCTDESCRIPTION
enable signals. The SRAM bank enable signal, BES#
selects the SRAM bank and the flash memory bank
enablesignal,BEF#selectstheflashmemorybank.The
WE# signal has to be used with Software Data Protec-
tion (SDP) command sequence when controlling the
Erase and Program operations in the flash memory
bank. The SDP command sequence protects the data
stored in the flash memory bank from accidental alter-
ation.
The SST31LF021E device is a 256K x8 CMOS flash
memory bank combined with a 128K x8 CMOS SRAM
memorybankmanufacturedwithSST’sproprietary,high
performance SuperFlash technology. Two pinout stan-
dards are available for this device. The SST31LF021E
conforms to standard EPROM pinouts. The
SST31LF021E device writes (SRAM or flash) with a 3.0-
3.6V power supply. The monolithic SST31LF021E de-
vice conforms to Software Data Protect (SDP) com-
mands for x8 EEPROMs.
8
9
10
11
12
13
14
15
16
The SST31LF021E provides the added functionality of
being able to simultaneously read from or write to the
SRAM bank while erasing or programming in the flash
memory bank. The SRAM memory bank can be read or
written while the flash memory bank performs Sector-
Erase, Bank-Erase, or Byte-Program concurrently. All
flash memory Erase and Program operations will auto-
matically latch the input address and data signals and
complete the operation in background without further
input stimulus requirement. Once the internally con-
trolled Erase or Program cycle in the flash bank has
commenced,theSRAMbankcanbeaccessedforRead
or Write.
Featuring high performance Byte-Program, the flash
memory bank provides a maximum Byte-Program time
of 20 µsec. The entire flash memory bank can be erased
and programmed byte-by-byte in typically 4 seconds,
when using interface features such as Toggle Bit or
Data# Polling to indicate the completion of Program
operation. To protect against inadvertent flash write, the
SST31LF021E device has on-chip hardware and Soft-
ware Data Protection schemes. Designed, manufac-
tured,andtestedforawidespectrumofapplications,the
SST31LF021E device is offered with a guaranteed en-
durance of 10,000 cycles. Data retention is rated at
greater than 100 years.
The SST31LF021E device is suited for applications that
use both nonvolatile flash memory and volatile SRAM
memory to store code or data. For all system applica-
tions, the SST31LF021E device significantly improves
performance and reliability, while lowering power con-
sumption, when compared with multiple chip solutions.
The SST31LF021E inherently uses less energy during
Erase and Program than alternative flash technologies.
The SST31LF021E operates as two independent
memorybankswithrespectivebankenablesignals. The
SRAM and Flash memory banks are superimposed in
the same memory address space. Both memory banks
share common address lines, data lines, WE# and OE#.
The memory bank selection is done by memory bank
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of
SiliconStorageTechnology,Inc.Thesespecificationsaresubjecttochangewithoutnotice.
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
When programming a flash device, the total energy
SRAMRead
consumed is a function of the applied voltage, current,
and time of application. Since for any given voltage
range, the SuperFlash technology uses less current to
program and has a shorter Erase time, the total energy
consumedduringanyEraseorProgramoperationisless
than alternative flash technologies. The monolithic
ComboMemory eliminates redundant functions when
using two separate memories of similar architecture;
therefore, reducing the total power consumption.
The SRAM Read operation of the SST31LF021E is
controlled by OE# and BES#, both have to be low with
WE#high,forthesystemtoobtaindatafromtheoutputs.
BES#isusedforSRAMbankselection.WhenBES#and
BEF#arehigh,bothmemorybanksaredeselected.OE#
is the output control and is used to gate data from the
output pins. The data bus is in high impedance state
when OE# is high. Refer to the Read cycle timing
diagram, Figure 2, for further details.
The SuperFlash technology provides fixed Erase and
Program times, independent of the number of Erase/
Program cycles that have occurred. Therefore the sys-
tem software or hardware does not have to be modified
or de-rated as is necessary with alternative flash tech-
nologies,whoseEraseandProgramtimesincreasewith
accumulated Erase/Program cycles.
SRAMWrite
The SRAM Write operation of the SST31LF021E is
controlledbyWE#andBES#, bothhavetobelowforthe
system to write to the SRAM. BES# is used for SRAM
bank selection. During the Byte-Write operation, the
addresses and data are referenced to the rising edge of
either BES# or WE#, whichever occurs first. The Write
time is measured from the last falling edge to the first
rising edge of BES# and WE#. Refer to the Write cycle
timing diagram, Figure 3, for further details.
The SST31LF021E device also improves flexibility by
using a single package and a common set of signals to
perform functions previously requiring two separate de-
vices. To meet high density, surface mount require-
ments, the SST31LF021E device is offered in 32-pin
TSOP packages. See Figure 1 for the pinouts.
Flash Operation
With BEF# active, the SST31LF021E operates as a
256K x8 flash memory. The flash memory bank is read
using the common address lines, data lines, WE# and
OE#. Erase and Program operations are initiated with
the JEDEC standard SDP command sequences. Ad-
dress and data are latched during the SDP commands
and internally timed Erase and Program operations.
Device Operation
The ComboMemory uses BES# and BEF# to control
operation of either the SRAM or the flash memory bank.
Buscontentioniseliminatedasthemonolithicdevicewill
not recognize both bank enables as being simulta-
neously active. If both bank enables are asserted (i.e.,
BEF# and BES# are both low), the BEF# will dominate
while the BES# is ignored and the appropriate operation
willbeexecutedintheflashmemorybank. SSTdoesnot
recommend that both bank enables be simultaneously
asserted. All other address, data, and control lines are
shared; which minimizes power consumption and area.
The device goes into standby when both bank enables
Flash Read
The Read operation of the SST31LF021E device is
controlled by BEF# and OE#, both have to be low, with
WE#high,forthesystemtoobtaindatafromtheoutputs.
BEF# is used for flash memory bank selection. When
BEF# and BES# are high, both banks are deselected
and only standby power is consumed. OE# is the output
controlandisusedtogatedatafromtheoutputpins. The
data bus is in high impedance state when OE# is high.
Refer to the Read cycle timing diagram (Figure 4) for
further details.
are raised to VIHC
.
SRAM Operation
With BES# low and BEF# high, the SST31LF021E
operate as a 128K x8 CMOS SRAM, with fully static
operation requiring no external clocks or timing strobes.
The SRAM is mapped into the first 128 KByte address
space of the device. Read and Write cycle times are
equal.
Flash Erase/Program Operation
SDP commands are used to initiate the flash memory
bank Program and Erase operations of the
SST31LF021E. SDP commands are loaded to the flash
memory bank using standard microprocessor write se-
quences. A command is loaded by asserting WE# low
while keeping BEF# low and OE# high. The address is
latched on the falling edge of WE# or BEF#, whichever
occurslast.ThedataislatchedontherisingedgeofWE#
or BEF#, whichever occurs first.
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
2
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
FlashByte-ProgramOperation
Figure 10 for timing diagram, and Figure 19 for the
flowchart. Any SDP commands loaded during the Bank-
Erase operation will be ignored.
The flash memory bank of the SST31LF021E device is
programmed on a byte-by-byte basis. The Program
operation consists of three steps. The first step is the
three-byte-load sequence for Software Data Protection.
The second step is to load byte address and byte data.
During the Byte-Program operation, the addresses are
latched on the falling edge of either BEF# or WE#,
whichever occurs last. The data is latched on the rising
edge of either BEF# or WE#, whichever occurs first. The
third step is the internal Program operation which is
initiated after the rising edge of the fourth WE# or BEF#,
whichever occurs first. The Program operation, once
initiated, will be completed, within 20 µs. See Figures 5
and 6 for WE# and BEF# controlled Program operation
timingdiagramsandFigure16forflowcharts. Duringthe
Programoperation,theonlyvalidFlashReadoperations
are Data# Polling and Toggle Bit. During the internal
Program operation, the host is free to perform additional
tasks. Any SDP commands loaded during the internal
Program operation will be ignored.
1
Flash Write Operation Status Detection
The SST31LF021E flash memory bank provides two
software means to detect the completion of a flash
memorybankWrite(ProgramorErase)cycle,inorderto
optimize the system Write cycle time. The software
detection includes two status bits: Data# Polling (DQ7)
and Toggle Bit (DQ6). The End-of-Write detection mode
is enabled after the rising edge of WE#, which initiates
the internal Program or Erase operation. The actual
completion of the nonvolatile write is asynchronous with
thesystem;therefore,eitheraData#PollingorToggleBit
Read may be simultaneous with the completion of the
Write cycle. If this occurs, the system may possibly get
anerroneousresult,i.e.,validdatamayappeartoconflict
with either DQ7 or DQ6. In order to prevent spurious
rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed
location an additional two (2) times. If both reads are
valid, then the device has completed the Write cycle,
otherwise the rejection is valid.
2
3
4
5
6
7
FlashSector-EraseOperation
The Sector-Erase operation allows the system to erase
the flash memory bank on a sector-by-sector basis. The
sector architecture is based on uniform sector size of 4
KBytes. The Sector-Erase operation is initiated by ex-
ecutingasix-byte-commandloadsequenceforSoftware
Data Protection with Sector-Erase command (30H) and
sector address (SA) in the last bus cycle. The address
lines A17-A12 will be used to determine the sector
address.Thesectoraddressislatchedonthefallingedge
of the sixth WE# pulse, while the command (30H) is
latched on the rising edge of the sixth WE# pulse. The
internalEraseoperationbeginsafterthesixthWE#pulse.
TheEnd-of-ErasecanbedeterminedusingeitherData#
Polling or Toggle Bit methods. See Figure 9 for timing
waveforms. Any SDP commands loaded during the
Sector-Eraseoperationwillbeignored.
8
Flash Data# Polling (DQ7)
When the SST31LF021E flash memory bank is in the
internalProgramoperation,anyattempttoreadDQ7will
produce the complement of the true data. Once the
Program operation is completed, DQ7 will produce true
data. The flash memory bank is then ready for the next
operation. During internal Erase operation, any attempt
to read DQ7 will produce a ‘0’. Once the internal Erase
operation is completed, DQ7 will produce a ‘1’. The
Data# Polling is valid after the rising edge of the fourth
WE# (or BEF#) pulse for Program operation. For Sector
or Bank-Erase, the Data# Polling is valid after the rising
edge of the sixth WE# (or BEF#) pulse. See Figure 7 for
Data# Polling timing diagram and Figure 17 for a flow-
chart.
9
10
11
12
13
14
15
16
FlashBank-EraseOperation
TheSST31LF021EflashmemorybankprovidesaBank-
Eraseoperation,whichallowstheusertoerasetheentire
flash memory bank array to the “1’s” state. This is useful
when the entire bank must be quickly erased. The Bank-
Erase operation is initiated by executing a six-byte
SoftwareDataProtectioncommandsequencewithBank-
Erase command (10H) with address 5555H in the last
bytesequence.TheinternalEraseoperationbeginswith
the rising edge of the sixth WE# or BEF# pulse, which-
everoccursfirst.DuringtheinternalEraseoperation,the
only valid Flash Read operations are Toggle Bit and
Data# Polling. See Table 4 for the command sequence,
Flash Toggle Bit (DQ6)
During the internal Program or Erase operation, any
consecutive attempts to read DQ6 will produce alternat-
ing 0’s and 1’s, i.e., toggling between 0 and 1. When the
internal Program or Erase operation is completed, the
toggling will stop. The flash memory bank is then ready
for the next operation. The Toggle Bit is valid after the
risingedgeofthefourthWE#(orBE#)pulseforProgram
operation. For Sector or Bank-Erase, the Toggle Bit is
valid after the rising edge of the sixth WE# (or BEF#)
pulse. See Figure 8 for Toggle Bit timing diagram and
Figure 17 for a flowchart.
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
3
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
FlashMemoryDataProtection
ProductIdentification
The SST31LF021E flash memory bank provides both
hardware and software features to protect nonvolatile
data from inadvertent writes.
The product identification mode identifies the device as
theSST31LF021EandmanufacturerasSST.Thismode
may be accessed by hardware or software operations.
ThehardwaredeviceIDReadoperationistypicallyused
by a programmer to identify the correct algorithm for the
SST31LF021E flash memory bank. Users may wish to
usethesoftwareproductidentificationoperationtoiden-
tify the part (i.e., using the device code) when using
multiple manufacturers in the same socket. For details,
see Table 3 for hardware operation or Table 4 for
software operation, Figure 11 for the software ID entry
and read timing diagram and Figure 18 for the ID entry
command sequence flowchart.
Flash Hardware Data Protection
Noise/Glitch Protection: A WE# or BEF# pulse of less
than 5 ns will not initiate a Write cycle.
VDD Power Up/Down Detection: The Write operation is
inhibited when VDD is less than 1.5V.
WriteInhibitMode:ForcingOE#low, BEF#high, orWE#
high will inhibit the Flash Write operation. This prevents
inadvertent writes during power-up or power-down.
Flash Software Data Protection (SDP)
TABLE 1: PRODUCT IDENTIFICATION TABLE
The SST31LF021E provides the JEDEC approved Soft-
ware Data Protection scheme for all flash memory bank
data alteration operations, i.e., Program and Erase. Any
Program operation requires the inclusion of a series of
three-byte sequence. The three byte-load sequence is
usedtoinitiatetheProgramoperation, providingoptimal
protectionfrominadvertentWriteoperations,e.g.,during
the system power-up or power-down. Any Erase opera-
tionrequirestheinclusionofsix-byteloadsequence.The
SST31LF021EdeviceisshippedwiththeSoftwareData
Protection permanently enabled. See Table 4 for the
specific software command codes. During SDP com-
mand sequence, invalid SDP commands will abort the
device to the Read mode, within TRC.
Address
0000H
Data
Manufacturer’s Code
BF H
SST31LF021E Device Code
0001H
19 H
371 PGM T1.0
ProductIdentificationModeExit/Reset
In order to return to the standard Read mode, the
Software Product Identification mode must be exited.
Exiting is accomplished by issuing the Exit ID command
sequence, which returns the device to the Read opera-
tion. Please note that the software-reset command is
ignored during an internal Program or Erase operation.
See Table 4 for software command codes, Figure 12 for
timing waveform and Figure 18 for a flowchart.
Concurrent Read and Write Operations
The SST31LF021E provides the unique benefit of being
abletoreadfromorwritetoSRAM, whilesimultaneously
erasingorprogrammingtheFlash.Thedevicewillignore
allSDPcommandswhenanEraseorProgramoperation
is in progress. This allows data alteration code to be
executed from SRAM, while altering the data in Flash.
The following table lists all valid states. SST does not
recommendthatbothbankenables,BEF#andBES#,be
simultaneously asserted.
DesignConsiderations
SST recommends a high frequency 0.1 µF ceramic
capacitortobeplacedascloseaspossiblebetweenVDD
andVSS,e.g.,lessthan1cmawayfromtheVDD pinofthe
device. Additionally, a low frequency 4.7 µF electrolytic
capacitor from VDD to VSS should be placed within 1 cm
of the VDD pin.
CONCURRENT READ/WRITE STATE TABLE
Flash
SRAM
Read
Write
Program/Erase
Program/Erase
Note that Product Identification commands use SDP;
therefore, these commands will also be ignored while an
Erase or Program operation is in progress.
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
4
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
FUNCTIONAL BLOCK DIAGRAM OF SST31LF021E
1
1,048,576 bit
SRAM
Cell Array
Address Buffers
Control Logic
2
BES#
BEF#
OE#
A
- A
0
I/O Buffers
DQ - DQ
7 0
MS
3
WE#
4
2,097,152 bit
EEPROM
Cell Array
Address Buffers
& Latches
371 ILL B1.1
5
Note: A
= Most Significant Address
MS
6
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE#
A10
7
2
A8
3
BEF#
DQ7
DQ6
DQ5
DQ4
DQ3
A13
A14
A17
BES#
4
5
Standard Pinout
6
8
7
Top View
Die Up
V
8
DD
WE#
A16
A15
A12
A7
9
V
SS
10
11
12
13
14
15
16
DQ2
DQ1
DQ0
A0
9
A6
A1
A5
A2
10
11
12
13
14
15
16
A4
A3
371 ILL F01.0
FIGURE 1: PIN ASSIGNMENTS FOR 32-PIN TSOP (8mm x 13.4mm)
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
5
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
TABLE 2:PIN DESCRIPTION
Symbol
MS-A0
Pin Name
Address Inputs
Functions
A
To provide memory addresses. During Flash Sector-Erase A17-A12
address lines will select the sector. A17-A0 to provide flash address,
A16-A0 to provide SRAM addresses.
DQ7-DQ0 DataInput/output
To output data during Read cycles and receive input data during Write
cycles. Data is internally latched during a Flash Erase/Program cycle.
The outputs are in tri-state when OE# or BES# and BEF# are high.
BES#
BEF#
SRAM Memory Bank
Enable
Flash Memory Bank
Enable
To activate the SRAM memory bank when BES# is low.
To activate the Flash memory bank when BEF# is low.
OE#
WE#
VDD
Vss
Output Enable
Write Enable
Power Supply
Ground
To gate the data output buffers.
To control the Write operations.
To provide 3.0-3.6V supply
371PGMT2.1
Note: AMS = Most Significant Address
TABLE 3: OPERATION MODES SELECTION
Mode
BES# BEF# OE# WE#
A9
AIN
AIN
X
DQ
DOUT
DIN
X
Address
AIN
AIN
Sector address, XXh for
Bank-Erase
FlashRead
FlashProgram
Flash Erase
X
X
X
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIL
VIL
SRAM Read
SRAM Write
Standby
VIL
VIL
VIH
VIH
VIL
X
X
VIH
VIL
X
AIN
AIN
X
DOUT
DIN
High Z
AIN
AIN
X
VIHC VIHC
Flash Write Inhibit
X
X
X
X
X
VIH
VIL
X
X
X
VIH
X
X
X
X
High Z/DOUT
High Z/DOUT
High Z/DOUT
X
X
X
Product Identification
Hardware Mode
X
VIL
VIL
VIH
VH
Manufacturer
Code (BF)
A17 - A1 = VIL, A0 = VIL
Device Code (1)
ID Code
A17 - A1 = VIL, A0 = VIH
See Table 4
Software Mode
X
VIL
VIL
VIH
AIN
Note (1) Device code = 19H for SST31LF021E
371 PGM T3.0
TABLE 4: SOFTWARE COMMAND SEQUENCE FOR FLASH MEMORY BANK
Command
Sequence
1st Bus
Write Cycle
Addr(2) Data Addr(2) Data
2nd Bus
Write Cycle
3rd Bus
Write Cycle
Addr(2) Data Addr(2) Data
4th Bus
Write Cycle
5th Bus
Write Cycle
Addr(2) Data Addr(2) Data
6th Bus
Write Cycle
Byte-Program
Sector-Erase
Bank-Erase
5555H AAH
5555H AAH
5555H AAH
5555H AAH
2AAAH 55H
2AAAH 55H
2AAAH 55H
2AAAH 55H
5555H A0H
5555H 80H
5555H 80H
5555H 90H
BA(4)
Data
5555H AAH
5555H AAH
2AAAH 55H SAx(3) 30H
2AAAH 55H 5555H 10H
Software ID
Entry(5,6)
Software ID Exit
5555H AAH
2AAAH 55H
5555H F0H
371 PGM T4.0
Notes:
(2)
Address format A14-A0 (Hex), Addresses A15, A16 and A17 are a “Don’t Care” for the
Command sequence.
SAx for Sector-Erase; uses A17-A12 address lines
BA = Program Byte address
With A17 -A1 =0; SST Manufacturer Code = BFH, is read with A0 = 0,
31LF021E Device Code = 19H, is read with A0 = 1.
The device does not remain in Software Product ID Mode if powered down.
(3)
(4)
(5)
(6)
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
6
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress
Ratings”maycausepermanentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedevice
at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied.
Exposure to absolute maximum stress rating conditions may affect device reliability.)
1
Temperature Under Bias ................................................................................................................. -55°C to +125°C
Storage Temperature ...................................................................................................................... -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential ............................................................................. -0.5V to VDD+ 0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential......................................................... -1.0V to VDD+ 1.0V
Voltage on A9 Pin to Ground Potential ................................................................................................ -0.5V to 13.2V
Package Power Dissipation Capability (Ta = 25°C) ........................................................................................... 1.0W
Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240°C
2
3
4
Output Short Circuit Current(1) ................................................................................................................................................................. 50 mA
Note: (1) Outputs shorted for no more than one second. No more than one output shorted at a time.
5
OPERATING RANGE
Range
AC CONDITIONS OF TEST
Ambient Temp
0 °C to +70 °C
-40 °C to +85 °C
VDD
Input Rise/Fall Time......... 5 ns
Output Load..................... CL = 30 pF
See Figures 14 and 15
6
Commercial
Industrial
3.0-3.6V
3.0-3.6V
7
TABLE 5: DC OPERATING CHARACTERISTICS VDD = 3.0-3.6V
8
Limits
Symbol Parameter
IDD PowerSupplyCurrent
Min
Max
Units TestConditions
9
VDD = VDD Max, all DQs open, Address
input = VIL/VIH, at f=1/TRC Min.
OE# = VIL, WE# = VIH
Read
Flash
12
40
mA
mA
BEF# = VIL, BES# = VIH
BEF# = VIH, BES# = VIL
10
11
12
13
14
15
16
SRAM
Concurrent Operation
55
mA
BEF# = VIH, BES# = VIL
Write
OE# = VIH, WE# = VIL
BEF# = VIL, BES# = VIH
BEF# = VIH, BES# = VIL
Flash (Program)
SRAM
15
40
mA
mA
(1)
ISB
ILI
Standby VDD Current
Input Leakage Current
Output Leakage Current
Input Low Voltage
30
1
µA
µA
µA
V
VDD = VDD Max. BEF# = BES# = VIHC
VIN =GND to VDD, VDD = VDD Max.
VOUT =GND to VDD, VDD = VDD Max.
VDD = VDD Min.
ILO
VIL
VIH
VIHC
VOL
VOH
VH
1
0.4
Input High Voltage
0.7VDD
V
VDD = VDD Max.
Input High Voltage (CMOS) VDD-0.3
OutputLowVoltage
V
VDD = VDD Max.
0.4
V
IOL = 1 mA, VDD = VDD Min.
IOH = -0.5 mA, VDD = VDD Min.
BEF# = OE# =VIL, WE# = VIH
BEF# = OE# = VIL, WE# = VIH, A9 = VH Max.
OutputHighVoltage
VDD-0.2
11.4
V
Supervoltage for A9 pin
12.6
200
V
IH
SupervoltageCurrent
for A9 pin
µA
371PGMT5.1
Note:
(1) Specification applies to commercial temperature devices only. This parameter may be higher for Industrial devices.
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
7
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol
Parameter
Minimum
Units
(1)
TPU-READ
Power-up to Read Operation
Power-up to Write Operation
100
100
µs
µs
(1)
TPU-WRITE
371 PGM T6.0
TABLE 7: CAPACITANCE (Ta = 25 °C, f=1 Mhz, other pins open)
Parameter
Description
Test Condition
Maximum
(1)
CI/O
I/O Pin Capacitance
Input Capacitance
VI/O = 0V
VIN = 0V
12 pF
6 pF
(1)
CIN
371 PGM T7.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: RELIABILITY CHARACTERISTICS
Symbol
Parameter
Minimum Specification
Units
TestMethod
(1)
NEND
Endurance
10,000
100
Cycles
Years
Volts
JEDECStandardA117
JEDECStandardA103
JEDECStandardA114
(1)
TDR
DataRetention
(1)
VZAP_HBM
ESD Susceptibility
Human Body Model
1000
(1)
VZAP_MM
ESD Susceptibility
Machine Model
200
Volts
mA
JEDEC Standard A115
JEDEC Standard 78
(1)
ILTH
Latch Up
100 + IDD
371 PGM T8.0
Note: (1)This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 9: SRAM MEMORY BANK READ CYCLE TIMING PARAMETERS VDD = 3.0-3.6V
Symbol
TRCS
Parameter
Min
Max
Unit
ns
Read Cycle Time
300
TAAS
Address Access Time
Bank Enable Access Time
BES# to Active Output
BES# to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
300
300
ns
TBES
ns
(1)
TBLZS
15
10
ns
(1)
TBHZS
30
30
ns
(1)
TOHZS
ns
TOHS
ns
371PGMT9.1
Note: (1) This parameter is measured only for initial qualification and after the design or process change
that could affect this parameter.
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
8
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
TABLE 10:SRAMMEMORY BANK WRITE CYCLE TIMING PARAMETERS VDD=3.0-3.6V
Symbol
TWCS
TBWS
TAWS
TASTS
TWPS
TWRS
TDSS
Parameter
Write Cycle Time
Min
300
230
230
0
200
0
150
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
1
Bank Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write recovery Time
Data Set-up Time
2
3
TDHS
Data Hold from Write Time
371PGMT10.1
4
AC CHARACTERISTICS
5
TABLE 11:FLASH READ CYCLE TIMING PARAMETERS VDD=3.0-3.6V
Symbol Parameter
Min
Max
Units
TRC
TBE
TAA
TOE
TBLZ
Read Cycle Time
Bank Enable Access Time
Address Access Time
Output Enable Access Time
BEF# Low to Active Output
OE# Low to Active Output
BEF# High to High-Z Output
OE# High to High-Z Output
Output Hold from Address Change
300
ns
ns
ns
ns
ns
ns
ns
ns
6
300
300
150
7
(1)
(1)
0
0
TOLZ
TBHZ
(1)
(1)
60
60
8
TOHZ
(1)
TOH
0
ns
371PGMT11.1
9
Note: (1) This parameter is measured only for initial qualification and after the design or process
change that could affect this parameter.
10
11
12
13
14
15
16
TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS VDD = 3.0-3.6V
Symbol
TBP
TAS
TAH
TBS
Parameter
Min
Max
Units
Byte-ProgramTime
Address Setup Time
Address Hold Time
WE# and BEF# Setup Time
WE# and BEF# Hold Time
OE# High Setup Time
OE# High Hold Time
BEF# Pulse Width
WE# Pulse Width
20
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
0
50
0
0
0
10
100
100
50
50
50
0
TBH
TOES
TOEH
TBP
TWP
TWPH
TBPH
TDS
WE# Pulse Width High
BEF# Pulse Width High
Data Setup Time
TDH
Data Hold Time
TIDA
TSE
Software ID Access and Exit Time
Sector-Erase
150
25
TSBE
TBS
Bank-Erase
Bank Enable Setup Time
forConcurrentOperation
100
0
371PGMT12.1
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
9
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
T
T
RCS
AAS
ADDRESS A
16-0
BEF#
BES#
OE#
T
BES
T
OES
T
T
OHZS
OLZS
V
IH
WE#
T
BHZS
T
T
OHS
BLZS
HIGH-Z
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
371 ILL F02.0
FIGURE 2: SRAM READ CYCLE TIMING DIAGRAM
T
WCS
ADDRESS A
ADDRESS
16-0
OE#
T
AWS
BEF#
BES#
WE#
T
BWS
T
WRS
T
WPS
T
ASTS
T
DSS
DATA VALID
T
DHS
DQ
7-0
371 ILL F03.0
FIGURE 3: SRAM WRITE CYCLE TIMING DIAGRAM
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
10
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
T
T
AA
1
RC
ADDRESS A
17-0
2
BES#
BEF#
OE#
3
T
BE
T
4
OE
5
T
T
OHZ
V
OLZ
IH
WE#
T
BHZ
6
T
OH
T
HIGH-Z
BLZ
HIGH-Z
DQ
7-0
DATA VALID
DATA VALID
7
371 ILL F18.0
FIGURE 4: FLASH READ CYCLE TIMING DIAGRAM
8
9
INTERNAL PROGRAM OPERATION STARTS
T
BP
10
11
12
13
14
15
16
5555
2AAA
5555
ADDR
ADDRESS A
17-0
T
AH
T
DH
T
WP
WE#
OE#
T
T
AS
DS
T
WPH
T
CH
BEF#
T
CS
BES#
DQ
7-0
AA
SW0
55
A0
DATA
BYTE
SW1
SW2
(ADDR/DATA)
371 ILL F04.0
FIGURE 5: FLASH WE# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
11
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
INTERNAL PROGRAM OPERATION STARTS
T
BP
5555
2AAA
5555
ADDR
ADDRESS A
17-0
BES#
BEF#
OE#
T
AH
T
DH
T
CP
T
T
AS
DS
T
CPH
T
CH
WE#
T
CS
DQ
7-0
AA
SW0
55
A0
DATA
SW1
SW2
BYTE
(ADDR/DATA)
371 ILL F05.0
FIGURE 6: FLASH BEF# CONTROLLED PROGRAM CYCLE TIMING DIAGRAM
ADDRESS A
17-0
BES#
T
CE
BEF#
OE#
T
OES
T
OEH
T
OE
WE#
DQ
7
D
D#
D#
D
371 ILL F06.0
FIGURE 7: FLASH DATA# POLLING TIMING DIAGRAM
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
12
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
1
ADDRESS A
17-0
2
BES#
T
3
BE
BEF#
OE#
T
OES
T
T
OE
4
OEH
5
WE#
6
DQ
6
TWO READ CYCLES
WITH SAME OUTPUTS
7
371 ILL F07.0
FIGURE 8: FLASH TOGGLE BIT TIMING DIAGRAM
8
9
T
SE
SIX-BYTE CODE FOR SECTOR-ERASE
5555 5555 2AAA
5555
2AAA
SA
X
ADDRESS A
17-0
10
11
12
13
14
15
16
BES#
BEF#
OE#
T
WP
WE#
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
30
SW0
SW5
371 ILL F08.0
Note: The device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See table 10)
SA = Sector Address
X
FIGURE 9: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
13
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
T
SBE
SIX-BYTE CODE FOR BANK-ERASE
5555 5555 2AAA
5555
2AAA
5555
ADDRESS A
17-0
BES#
BEF#
OE#
T
WP
WE#
DQ
7-0
AA
55
SW1
80
SW2
AA
SW3
55
SW4
10
SW0
SW5
371 ILL F17.0
Note: The device also supports BEF# controlled Bank-Erase operation. The WE# and BEF# signals are
interchangeable as long as minimum timings are met. (See table 10)
FIGURE 10: FLASH WE# CONTROLLED BANK-ERASE TIMING DIAGRAM
THREE-BYTE SEQUENCE FOR
SOFTWARE ID ENTRY
ADDRESS A
14-0
5555
2AAA
5555
0000
0001
BES#
BEF#
OE#
T
IDA
T
WP
AA
WE#
T
WPH
55
SW1
T
AA
DQ
7-0
90
BF
DEVICE ID
SW0
SW2
MFG ID
371 ILL F09.0
Device ID = 19 for SST31LF021E
FIGURE 11: FLASH SOFTWARE ID ENTRY AND READ
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
14
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
1
5555
2AAA
5555
ADDRESS A
14-0
2
BES#
T
IDA
3
BEF#
OE#
4
T
WP
5
WE#
T
WHP
SW0
AA
SW1
SW2
F0
6
DQ
55
7-0
7
371 ILL F10.0
FIGURE 12: FLASH SOFTWARE ID EXIT AND RESET
8
9
ADDRESS A
17-0
10
11
12
13
14
15
16
BEj#
T
BS
BEj1#
WE#
OE#
DQ
7-0
371 ILL F20.0
Note:
j
= F or S
j1 = S or F
FIGURE 13: TIMING DIAGRAM FOR ALTERNATING BETWEEN FLASH/SRAM TO SRAM/FLASH
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
15
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
V
IHT
V
V
INPUT
REFERENCE POINTS
OUTPUT
OT
IT
V
ILT
371 ILL F11.1
AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”.
(1)
Measurement reference points for inputs and outputs are at VIT (0.5V VDD) )
(1) and VLT (0.5V VDD
Input rise and fall times (10% « 90%) are <5 ns.
Note: VIT–VINPUT Test
VOT–VOUTPUT Test
(1) Output test level per common SRAM test standards
VIHT–VINPUT HIGH Test
VILT–VINPUT LOW Test
FIGURE 14: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
TO DUT
C
L
371 ILL F12.1
FIGURE 15: A TEST LOAD EXAMPLE
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
16
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
1
Start
2
Load data: AA
Address: 5555
3
Load data: 55
Address: 2AAA
4
5
Load data: A0
Address: 5555
6
7
Load Byte
Address/Byte
Data
8
Wait for end of
9
Program (T
,
BP
Data# Polling
bit, or Toggle bit
operation)
10
11
12
13
14
15
16
Program
Completed
371 ILL F13.0
FIGURE 16: BYTE-PROGRAM ALGORITHM
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
17
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
Toggle Bit
Data# Polling
Internal Timer
Byte
Program/Erase
Initiated
Byte
Program/Erase
Initiated
Byte
Program/Erase
Initiated
Read DQ
7
Read byte
Wait T
,
T
BP
T
SBE, or SE
Read same
byte
Is DQ =
7
No
true data?
Program/Erase
Completed
Yes
No
Does DQ
match?
6
Program/Erase
Completed
Yes
Program/Erase
Completed
371 ILL F14.0
FIGURE 17: WAIT OPTIONS
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
18
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
1
Software Product ID Entry
Command Sequence
Software Product ID Exit &
Reset Command Sequence
2
Load data: AA
Address: 5555
Load data: AA
Address: 5555
Load data: F0
Address: XX
3
4
Load data: 55
Address: 2AAA
Load data: 55
Address: 2AAA
Wait T
IDA
5
Load data: 90
Address: 5555
Load data: F0
Address: 5555
Return to normal
operation
6
7
Wait T
Wait T
IDA
IDA
8
9
Return to normal
operation
Read Software ID
371 ILL F15.0
10
11
12
13
14
15
16
FIGURE 18: SOFTWARE PRODUCT COMMAND FLOWCHARTS
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
19
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
Chip-Erase
Sector-Erase
Command Sequence
Command Sequence
Load data: AA
Address: 5555
Load data: AA
Address: 5555
Load data: 55
Load data: 55
Address: 2AAA
Address: 2AAA
Load data: 80
Address: 5555
Load data: 80
Address: 5555
Load data: AA
Address: 5555
Load data: AA
Address: 5555
Load data: 55
Load data: 55
Address: 2AAA
Address: 2AAA
Load data: 10
Address: 5555
Load data: 30
Address: SA
X
Wait T
Wait T
SE
SBE
Chip erased
to FFH
Sector erased
to FFH
371 ILL F16.0
FIGURE 19: ERASE COMMAND SEQUENCE
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
20
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
Device
Speed Suffix1
- XXX XX
Suffix2
SST31LF021E
-
-
XX
1
PackageModifier
H = 32 pins
2
Numeric = Die modifier
Package Type
3
K = TSOP (die up) 8mm x 13.4mm
Temperature Range
C = Commercial = 0° to 70°C
I = Industrial = -40° to 85°C
4
Minimum Endurance
5
4 = 10,000 cycles
Read Access Speed
300 = 300 ns
6
Version
E = EPROM Pinout
7
Density
021 = 2 Mbit Flash + 1 Mbit SRAM
Voltage Range
8
L = 3.0-3.6V
Device Family
9
31 = Monolithic ComboMemory
10
11
12
13
14
15
16
SST31LF021E Valid combinations
SST31LF021E-300-4C-KH
SST31LF021E-300-4I-KH
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
© 2000 Silicon Storage Technology, Inc.
371-02 2/00
21
2 Megabit Flash + 1 Megabit SRAM ComboMemory
SST31LF021E
Advance Information
PACKAGING DIAGRAMS
.91
1.05
ALTERNATE
INDICATOR
PIN # 1
.50
BSC
.16
.27
7.90
8.30
†
0.05
0.20
11.70
11.90
0.70
0.30
13.20
13.60
32.TSOP-KH-ILL.4
Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC max is 8.1; SST max is less stringent
2. All linear dimensions are in millimeters (min/max).
3. Coplanarity: 0.1 (±.05) mm.
32-PIN THIN SMALL OUTLINE PACKAGE (TSOP) 8MM X 13.4MM
SST PACKAGE CODE: KH
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.ssti.com • Literature FaxBack 888-221-1178, International 732-544-2873
371-02 2/00
© 2000 Silicon Storage Technology, Inc.
22
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