W305BH [SPECTRALINEAR]
Frequency Controller with System Recovery for Intel Integrated Core Logic; 变频控制器系统恢复英特尔集成众核逻辑
| 型号： | W305BH |
| 厂家： | 
SPECTRALINEAR INC |
| 描述： | Frequency Controller with System Recovery for Intel Integrated Core Logic |
| 文件： | 总20页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W305B
Frequency Controller with System Recovery for Intel£ Integrated
Core Logic
• Thirteen copies of SDRAM clock
Features
• Eight copies of PCI clock
• Single chip FTG solution for Intel Solano/810E/810
• One copy of synchronous APIC clock
• Programmable clock output frequency with less than
1 MHz increment
• Three copies of 66-MHz outputs
• Three copies of 48-MHz outputs
• Integrated fail-safe Watchdog timer for system
recovery
• One copy of double strength 14.31818-MHz reference
clock
• Automatically switch to HW selected or SW
programmed clock frequency when Watchdog timer
time-out
• One RESET output for system recovery
• SMBus interface for turning off unused clocks
• Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
Key Specifications
CPU, SDRAM Outputs Cycle-to-Cycle Jitter: ............. 250 ps
• Support SMBus byte read/write and block read/write
operations to simplify system BIOS development
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter:................................................... 500 ps
• Vendor ID and Revision ID support
CPU, 3V66 Output Skew: ........................................... 175 ps
SDRAM, APIC, 48-MHz Output Skew: ....................... 250 ps
PCI Output Skew: ....................................................... 500 ps
CPU to SDRAM Skew (@ 133 MHz) ....................... 0.5 ns
CPU to SDRAM Skew (@ 100 MHz)................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead).......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... 0.5 ns
• Programmable drive strength for SDRAM and PCI
output clocks
• Programmable output skew between CPU, AGP, PCI
and SDRAM
• Maximized EMI suppression using Cypress’s Spread
Spectrum Technology
• Low jitter and tightly controlled clock skew
• Two copies of CPU clock
Pin Configuration[1]
Block Diagram
GND
VDDQ3
REF2X/FS3^
X1
X2
VDDQ3
3V66_0
3V66_1
3V66_2
GND
PCI0/FS0^
PCI1/FS1^
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
APIC
GND
VDDQ2
CPU0
CPU1
GND
SDRAM0
SDRAM1
SDRAM2
VDDQ3
GND
SDRAM3
SDRAM4
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
SDRAM10
VDDQ3
GND
SDRAM11
SDRAM12
RST#
1
2
3
4
5
6
7
8
VDDQ3
REF2X/FS3
X1
X2
XTAL
OSC
PLL REF FREQ
VDDQ2
CPU0:1
Divider,
Delay,
and
9
2
SDATA
SCLK
SMBus
Logic
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Phase
Control
Logic
PCI2/FS2^
GND
APIC
(FS0:4)
VDDQ3
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz
3V66_0:2
PCI0/FS0
3
PLL 1
PCI1/FS1
PCI2/FS2
PCI3:7
5
48MHz/FS4^
24_48MHz/SEL24_48MHz#*
SDRAM0:12
RST#
13
25
26
27
28
VDDQ3
SDATA
GND
VDDQ3
SCLK
VDDQ3
48MHz
48MHz/FS4
PLL2
24_48MHz/SEL24_48MHz#
/2
1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH or LOW.
Rev 1.0, November 20, 2006
Page 1 of 20
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
www.SpectraLinear.com
W305B
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
REF2X/FS3
3
I/O
Reference Clock with 2x Drive/Frequency Select 3. 3.3V 14.318-MHz clock
output. This pin also serves as the select strap to determines device operating
frequency as described in Table 5.
X1
4
5
I
Crystal Input. This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
X2
O
Crystal Output. An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
PCI0/FS0
11
I/O
PCI Clock 0/Frequency Selection 0. 3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in Table 5.
PCI1/FS1
PCI2/FS2
12
13
I/O
I/O
PCI Clock 1/Frequency Selection 1. 3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in Table 5.
PCI Clock 2/Frequency Selection 2. 3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in Table 5.
PCI3:7
15, 16, 18, 19, 20
7, 8, 9
O
O
PCI Clock 3 through 7. 3.3V 33-MHz PCI clock outputs. PCI0:7 can be individ-
ually turned off via SMBus interface.
3V66_0:2
66-MHz Clock Output. 3.3V output clocks. The operating frequency is
controlled by FS0:4 (see Table 5).
48MHz
22
23
O
48MHz. 3.3V 48-MHz non-spread spectrum output.
48MHz/FS4
I/O
48-MHz Output/Frequency Selection 4. 3.3V 48-MHz non-spread spectrum
output. This pin also serves as the select strap to determine device operating
frequency as described in Table 5.
24_48MHz/SEL24
_48MHz#
24
30
I/O
24- or 48-MHz Output/Select 24 or 48MHz. 3.3V 24 or 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the output
frequency for 24_48MHz output.
RST#
O
Reset#. Open-drain RESET# output.
(open-d
rain)
CPU0:1
SDRAM0:12,
APIC
52, 51
O
CPU Clock Outputs. Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:4. Voltage swing is set by
VDDQ2.
49, 48, 47, 44,
43, 42, 41, 38,
37, 36, 35, 32, 31
SDRAM Clock Outputs. 3.3V outputs for SDRAM and chipset. The operating
frequency is controlled by FS0:4 (see Table 5).
O
O
55
Synchronous APIC Clock Outputs. Clock outputs running synchronous with
the PCI clock outputs. Voltage swing set by VDDQ2.
SDATA
SCLK
26
29
I/O
I
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
VDDQ3
2, 6, 17, 25, 28,
34, 40, 46
P
3.3V Power Connection. Power supply for SDRAM output buffers, PCI output
buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
VDDQ2
GND
53, 56
P
2.5V Power Connection. Power supply for APIC and CPU output buffers.
Connect to 2.5V.
1, 10, 14, 21, 27,
33, 39, 45, 50, 54
G
Ground Connections. Connect all ground pins to the common system ground
plane.
Rev 1.0,November 20, 2006
Page 2 of 20
W305B
Output Strapping Resistor
Series Termination Resistor
Clock Load
W305B
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
10 k:
Q
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below
target but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
Overview
The W305B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® archi-
tecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Offsets Among Clock Signal Groups
Upon power-up the power on strap option pins act as a logic
input. An external 10-k: strapping resistor should be used.
Figure 1 shows a suggested method for strapping resistor
connections.
Figure 2, Figure 3, and Figure 4 represent the phase
relationship among the different groups of clock outputs from
W305B under different frequency modes.
10 ns
20 ns
30 ns
40 ns
0 ns
CPU 66 Period
CPU 66-MHz
SDRAM 100 Period
SDRAM 100-MHz
Hub-PCI
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 16.6-MHz
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
Rev 1.0,November 20, 2006
Page 3 of 20
W305B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100 Period
CPU 100-MHz
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
Hub-PC
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC16.6-MHz
Figure 3. Group Offset Waveforms (100-MHz CPU Clock, 100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 16.6-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM)
Rev 1.0,November 20, 2006
Page 4 of 20
W305B
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeat
CPU 133-MHz
SDRAM 133MHz
3V66 66-MHz
PCI 33-MHz
APIC 16.6-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM)
Serial Data Interface
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been trans-
ferred. For byte/word write and byte read operations, system
controller can access individual indexed byte. The offset of the
indexed byte is encoded in the command code.
The W305B features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
Data Protocol
The definition for the command code is given in Table 1.
The clock driver serial protocol supports byte/word write,
byte/word read, block write and block read operations from the
Table 1. Command Code Definition
Bit
Descriptions
7
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
6:0
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bit
Write
2:8
9
Slave address – 7 bit
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
11:18
Command Code – 8 bit
‘00000000’ stands for block operation
19
20:27
28
Acknowledge from slave
Byte Count – 8 bits
19
20
Acknowledge from slave
Repeat start
Acknowledge from slave
Data byte 0 – 8 bits
21:27
28
Slave address – 7 bits
Read
29:36
37
Acknowledge from slave
Data byte 1 – 8 bits
29
Acknowledge from slave
Byte count from slave – 8 bits
Acknowledge
38:45
46
30:37
38
Acknowledge from slave
Data Byte N/Slave Acknowledge...
...
39:46
Data byte from slave – 8 bits
Rev 1.0,November 20, 2006
Page 5 of 20
W305B
Table 2. Block Read and Block Write Protocol (continued)
Block Write Protocol
Block Read Protocol
Description
Bit
...
Description
Data Byte N – 8 bits
Bit
47
Acknowledge
...
Acknowledge from slave
Stop
48:55
56
Data byte from slave – 8 bits
Acknowledge
...
...
Data bytes from slave/Acknowledge
Data byte N from slave – 8 bits
Not Acknowledge
...
...
...
Stop
Table 3. Word Read and Word Write Protocol
Word Write Protocol
Word Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bit
Write
2:8
9
Slave address – 7 bit
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
11:18
Command Code – 8 bit
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
‘1xxxxxxx’ stands for byte or word operation
bit[6:0] of the command code represents the offset
of the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte low– 8 bits
Acknowledge from slave
Data byte high – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read
29:36
37
29
Acknowledge from slave
Data byte low from slave – 8 bits
Acknowledge
38
30:37
38
39:46
47
Data byte high from slave – 8 bits
NOT acknowledge
Stop
48
Table 4. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
2:8
9
Slave address – 7 bit
Write
2:8
9
Slave address – 7 bit
Write
10
Acknowledge from slave
10
Acknowledge from slave
11:18
Command Code – 8 bit
11:18
Command Code – 8 bit
‘1xxxxxxx’ stands for byte operation
bit[6:0]ofthecommandcoderepresentstheoffset
of the byte to be accessed
‘1xxxxxxx’ stands for byte operation
bit[6:0]ofthecommandcoderepresentstheoffset
of the byte to be accessed
19
20:27
28
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
19
20
Acknowledge from slave
Repeat start
21:27
28
Slave address – 7 bits
Read
29
Rev 1.0,November 20, 2006
Page 6 of 20
W305B
Table 4. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Byte Read Protocol
Description
Bit
Description
Bit
29
Acknowledge from slave
30:37
38
Data byte from slave – 8 bits
Not Acknowledge
Stop
39
W305B Serial Configuration Map
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0
The serial bits will be read by the clock driver in the following
order:
All unused register bits (reserved and N/A) should be written
to a “0” level.
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0
All register bits labeled “Initialize to 0” must be written to zero
during initialization.
Byte 0: Control Register 0
Bit
Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
SEL4
SEL3
SEL2
SEL1
SEL0
0
0
0
0
0
0
0
0
See Table 5
See Table 5
See Table 5
See Table 5
See Table 5
Spread Select2
Spread Select1
Spread Select0
‘000’ = Normal (spread off)
‘001’ = Test Mode
‘010’ = Reserved
‘011’ = Three-Stated
‘100’ = –0.5%
‘101’ = 0.5%
‘110’ = 0.25%
‘111’ = 0.38%
Byte 1: Control Register 1
Bit
Bit 7
Pin#
23
3
Name
Default
Description
Latched FS4 input
Latched FS3 input
Latched FS2 input
Latched FS1 input
Latched FS0 input
Reserved
X
X
X
X
X
0
Latched FS[4:0] inputs. These bits are read only.
Bit 6
Bit 5
13
12
11
-
Bit 4
Bit 3
Bit 2
Reserved
Bit 1
3
REF2X
1
(Active/Inactive)
Reserved
Bit 0
-
Reserved
0
Byte 2: Control Register 2
Bit
Bit 7
Pin#
20
Name
PCI7
Default
Description
(Active/Inactive)
1
1
1
1
Bit 6
19
PCI6
(Active/Inactive)
Bit 5
18
PCI5
(Active/Inactive)
Bit 4
16
PCI4
(Active/Inactive)
Rev 1.0,November 20, 2006
Page 7 of 20
W305B
Byte 2: Control Register 2 (continued)
Bit
Pin#
15
Name
Default
Description
Bit 3
Bit 2
Bit 1
Bit 0
PCI3
PCI2
PCI1
PCI0
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
13
12
11
Byte 3: Control Register 3
Bit
Bit 7
Pin#
Name
3V66_2
Default
Description
9
8
1
1
1
1
0
0
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Reserved
Bit 6
3V66_1
3V66_0
APIC
Bit 5
7
Bit 4
55
-
Bit 3
Reserved
Reserved
CPU1
Bit 2
-
Reserved
Bit 1
51
52
(Active/Inactive)
(Active/Inactive)
Bit 0
CPU0
Byte 4: Control Register 4
Bit
Bit 7
Pin#
38
41
42
43
44
47
48
49
Name
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Default
Description
1
1
1
1
1
1
1
1
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Byte 5: Control Register 5
Bit
Bit 7
Pin#
-
Name
Reserved
Reserved
Reserved
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Default
Description
0
0
0
1
1
1
1
1
Reserved
Bit 6
-
Reserved
Bit 5
-
Reserved
Bit 4
31
32
35
36
37
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
Bit 3
Bit 2
Bit 1
Bit 0
Rev 1.0,November 20, 2006
Page 8 of 20
W305B
Byte 6: Vendor ID & Revision ID Register (Read Only)
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Revision_ID3
Revision_ID2
Revision_ID1
Revision_ID0
Vendor_ID3
Vendor_ID2
Vendor _ID1
Vendor _ID0
0
0
0
0
1
0
0
0
Revision ID bit[3]
Revision ID bit[2]
Revision ID bit[1]
Revision ID bit[0]
Bit[3] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit[2] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit[1] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Bit[0] of Cypress Semiconductor’s Vendor ID. This bit is read only.
Byte 7: Control Register 7
Bit
Bit 7
Pin#
-
Name
Reserved
Default
Pin Description
0
1
1
1
1
1
1
0
Reserved
Bit 6
24
23
22
24
23
22
--
24_48MHz_DRV
48MHz_DRV
48MHz_DRV
24_48MHz
48 MHz
0 = Norm, 1 = High Drive
0 = Norm, 1 = High Drive
0 = Norm, 1 = High Drive
(Active/Inactive)
Bit 5
Bit 4
Bit 3
Bit 2
(Active/Inactive)
Bit 1
48 MHz
(Active/Inactive)
Bit 0
Reserved
Reserved
Byte 8: Watchdog Timer Register
Bit
Name
PCI_Skew1
PCI_Skew0
Default
Pin Description
Bit 7
Bit 6
0
0
PCI skew control
00 = Normal
01 = –500ps
10 = Reserved
11 = +500ps
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
WD_PRE_SCALER
1
1
1
1
1
0
These bits store the time-out value of the Watchdog timer. The scale of the
timer is determine by the pre-scaler.
The timer can support a value of 150 ms to 4.8 sec when the pre-scaler is set
to 150 ms. If the pre-scaler is set to 2.5 sec, it can support a value from 2.5
sec. to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
0 = 150 ms
1 = 2.5 sec
Byte 9: System RESET and Watchdog Timer Register
Bit
Name
Default
Pin Description
SDRAM clock output drive strength
0 = Normal
Bit 7
Bit 6
Bit 5
SDRAM_DRV
0
1 = High Drive
PCI_DRV
0
0
PCI clock output drive strength
0 = Normal
1 = High Drive
FS_Override
0 = Select operating frequency by FS[4:0] input pins
1 = Select operating frequency by SEL[4:0] settings
Rev 1.0,November 20, 2006
Page 9 of 20
W305B
Byte 9: System RESET and Watchdog Timer Register (continued)
Bit
Name
Default
Pin Description
Bit 4
Bit 3
RST_EN_WD
0
This bit will enable the generation of a Reset pulse when a watchdog timer
time-out occurs.
0 = Disabled
1 = Enabled
RST_EN_FC
0
This bit will enable the generation of a Reset pulse after a frequency change
occurs.
0 = Disabled
1 = Enabled
Bit 2
Bit 1
WD_TO_STATUS
WD_EN
0
0
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency
mode.
1 = Enable Watchdog timer. It will start counting down after a frequency change
occurs.
Note: W305B will generate system reset, re-load a recovery frequency, and
lock itself into a recovery frequency mode after a Watchdog timer time-out
occurs. Underrecoveryfrequency mode, W305B will not respond to anyattempt
to change output frequency via the SMBus control bytes. System software can
unlock W305B from its recovery frequency mode by clearing the WD_EN bit.
Bit 0
Reserved
0
Reserved
Byte 10: Skew Control Register
Bit
Name
CPU_Skew2
CPU_Skew1
CPU_Skew0
Default
Description
Bit 7
Bit 6
Bit 5
0
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
0
0
Bit 4
Bit 3
Bit 2
SDRAM_Skew2
SDRAM_Skew1
SDRAM_Skew0
0
0
0
SDRAM skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
Bit 1
Bit 0
AGP_Skew1
AGP_Skew0
0
0
AGP skew control
00 = Normal
01 = –150ps
10 = +150ps
11 = +300ps
Rev 1.0,November 20, 2006
Page 10 of 20
W305B
Byte 11: Recovery Frequency N-Value Register
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, W305B will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W305b will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B
will use the frequency ratio stated in the SEL[4:0] register.
W305B supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
W305Bwill change the output frequency whenever there is an update to either
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same
SMBus bus operation.
Byte 12: Recovery Frequency M-Value Register
Bit
Name
Default
Pin Description
Bit 7
ROCV_FREQ_SEL
0
ROCV_FREQ_SEL determines the source of the recover frequency when a
Watchdog timer time-out occurs. The clock generator will automatically switch
to the recovery CPU frequency based on the selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ROCV_FREQ_M6
ROCV_FREQ_M5
ROCV_FREQ_M4
ROCV_FREQ_M3
ROCV_FREQ_M2
ROCV_FREQ_M1
ROCV_FREQ_M0
0
0
0
0
0
0
0
If ROCV_FREQ_SEL is set, W305B will use the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] to determine the recovery
CPU output frequency.when a Watchdog timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W305b will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B
will use the frequency ratio stated in the SEL[4:0] register.
W305B supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
W305B will change the output frequency whenever there is an update to either
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same
SMBus bus operation.
Byte 13: Programmable Frequency Select N-Value Register
Bit
Name
Default
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU_FSEL_N7
CPU_FSEL_N6
CPU_FSEL_N5
CPU_FSEL_N4
CPU_FSEL_N3
CPU_FSEL_N2
CPU_FSEL_N1
CPU_FSEL_N0
0
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W305B will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0]
is updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B
will use the frequency ratio stated in the SEL[4:0] register.
W305B supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
Rev 1.0,November 20, 2006
Page 11 of 20
W305B
Byte 14: Programmable Frequency Select M-Value Register
Bit
Name
Default
Description
Bit 7
Pro_Freq_EN
0
Programmable output frequencies enabled
0 = disabled
1 = enabled
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CPU_FSEL_M6
CPU_FSEL_M5
CPU_FSEL_M4
CPU_FSEL_M3
CPU_FSEL_M2
CPU_FSEL_M1
CPU_FSEL_M0
0
0
0
0
0
0
0
If Prog_Freq_EN is set, W305B will use the values programmed in
CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output
frequency. The new frequency will start to load whenever CPU_FSELM[6:0] is
updated.
The setting of FS_Override bit determines the frequency ratio for CPU,
SDRAM, AGP and SDRAM. When it is cleared, W305B will use the same
frequency ratio stated in the Latched FS[4:0] register. When it is set, W305B
will use the frequency ratio stated in the SEL[4:0] register.
W305B supports programmable CPU frequency ranging from 50 MHz to
248 MHz.
Byte 15: Reserved Register
Bit Pin#
Name
Reserved
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved. Write with ‘1’
Reserved. Write with ‘1’
Byte 16: Reserved Register
Bit
Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Byte 17: Reserved Register
Bit Pin#
Name
Default
Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
-
-
-
-
-
-
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Rev 1.0,November 20, 2006
Page 12 of 20
W305B
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions Output Frequency
PLL Gear
Constants
(G)
FS4
SEL4
0
FS3
FS2
SEL2
0
FS1
FS0
SEL0
0
SEL3
0
SEL1
0
CPU
66.6
SDRAM
3V66
66.6
80.0
66.8
68.3
70.0
75.0
80.0
83.0
66.6
82.6
66.8
68.9
70.0
73.3
76.6
66.6
66.6
83.3
66.8
68.5
70.0
72.5
75.0
80.0
66.6
83.3
66.8
68.5
66.6
66.6
66.6
66.6
PCI
33.3
40.0
33.4
34.2
35.0
37.5
40.0
41.5
33.3
41.3
33.4
34.3
35.0
36.7
38.3
33.3
33.3
41.6
33.4
34.3
35.0
36.2
37.5
40.0
33.3
41.7
33.4
34.3
33.3
33.3
33.3
33.3
APIC
16.6
20.0
16.7
17.1
17.5
18.8
20.0
20.8
16.6
20.6
16.7
17.2
17.5
18.3
19.1
16.6
16.6
20.8
16.7
17.1
17.5
18.1
18.7
20.0
16.6
20.8
16.7
17.1
16.6
16.6
16.6
16.6
100.0
120.0
100.2
102.5
105.0
112.5
120.0
124.5
100.0
124.0
100.2
103.0
105.0
110.0
115.0
200.0
133.3
166.6
133.6
137.0
140.0
145.0
150.0
160.0
100.0
125.0
100.2
102.8
100.0
100.0
133.3
100.0
32.00494
48.00741
32.00494
32.00494
32.00494
32.00494
32.00494
32.00494
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
48.00741
96.01482
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
64.00988
32.00494
48.00741
64.00988
64.00988
0
0
0
0
1
120.0
66.8
0
0
0
1
0
0
0
0
1
1
68.3
0
0
1
0
0
70.0
0
0
1
0
1
75.0
0
0
1
1
0
80.0
0
0
1
1
1
83.0
0
1
0
0
0
100.0
124.0
100.2
103.0
105.0
110.0
115.0
200.0
133.3
166.6
133.6
137.0
140.0
145.0
150.0
160.0
133.3
166.6
133.6
137.0
66.6
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
100.0
133.3
133.3
1
1
1
1
0
1
1
1
1
1
Rev 1.0,November 20, 2006
Page 13 of 20
W305B
The Watchdog Timer and Recovery Output Frequency
features allow users to implement a recovery mechanism
when the system hangs or getting unstable. System BIOS or
other control software can enable the Watchdog timer before
they attempt to make a frequency change. If the system hangs
and a Watchdog timer time-out occurs, a system reset will be
generated and a recovery frequency will be activated.
Programmable Output Frequency, Watchdog
Timer and Recovery Output Frequency
Functional Description
The Programmable Output Frequency feature allows users to
generate any CPU output frequency from the range of 50 MHz
to 248 MHz. Cypress offers the most dynamic and the simplest
programming interface for system developers to utilize this
feature in their platforms.
All the related registers are summarized in the following table.
Table 6. Register Summary
Name
Description
Pro_Freq_EN
Programmable output frequencies enabled
0 = disabled (default)
1 = enabled
When it is disabled, the operating output frequency will be determined by either the latched value of
FS[4:0] inputs or the programmed value of SEL[4:0]. If FS_Override bit is clear, latched FS[4:0] inputs
will be used. If FS_Override bit is set, programmed value of SEL[4:0] will be used.
When it is enabled, the CPU output frequency will be determined by the programmed value of
CPUFSEL_N, CPUFSEL_M and the PLL Gear Constant. The program value of FS_Override, SEL[4:0]
or the latched value of FS[4:0] will determine the PLL Gear Constant and the frequency ratio between
CPU and other frequency outputs
FS_Override
When Pro_Freq_EN is cleared or disabled,
0 = Select operating frequency by FS input pins (default)
1 = Select operating frequency by SEL bits in SMBus control bytes
When Pro_Freq_EN is set or enabled,
0 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the latched value of FS input pins (default)
1 = Frequency output ratio between CPU and other frequency groups and the PLL Gear Constant are
based on the programmed value of SEL bits in SMBus control bytes
CPU_FSEL_N,
CPU_FSEL_M
When Prog_Freq_EN is set or enabled, the values programmed in CPU_FSEL_N[7:0] and
CPU_FSEL_M[6:0] determines the CPU output frequency. The new frequency will start to load
whenever there is an update to either CPU_FSEL_N[7:0] or CPU_FSEL_M[6:0]. Therefore, it is recom-
mended to use Word or Block write to update both registers within the same SMBus bus operation.
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM.
When FS_Override is cleared or disabled, the frequency ratio follows the latched value of the FS input
pins. When FS_Override is set or enabled, the frequency ratio follows the programmed value of SEL
bits in SMBus control bytes.
ROCV_FREQ_SEL
ROCV_FREQ_SEL determines the source of the recover frequency when a Watchdog timer time-out
occurs. The clock generator will automatically switch to the recovery CPU frequency based on the
selection on ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] & ROCV_FREQ_M[6:0]
ROCV_FREQ_N[7:0], When ROCV_FREQ_SEL is set, the values programmed in ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0] ROCV_FREQ_M[6:0] will be used to determine the recovery CPU output frequency when a Watchdog
timer time-out occurs
The setting of FS_Override bit determines the frequency ratio for CPU, SDRAM, AGP and SDRAM.
When it is cleared, the same frequency ratio stated in the Latched FS[4:0] register will be used.
When it is set, the frequency ratio stated in the SEL[4:0] register will be used.
The new frequency will start to load whenever there is an update to either ROCV_FREQ_N[7:0] and
ROCV_FREQ_M[6:0]. Therefore, it is recommended to use Word or Block write to update both registers
within the same SMBus bus operation.
Rev 1.0,November 20, 2006
Page 14 of 20
W305B
Table 6. Register Summary (continued)
Name
Description
WD_EN
0 = Stop and re-load Watchdog timer. Unlock W305B from recovery frequency mode.
1 = Enable Watchdog timer. It will start counting down after a frequency change occurs.
Note. W305B will generate system reset, re-load a recovery frequency, and lock itself into a recovery
frequency mode after a Watchdog timer time-out occurs. Under recovery frequency mode, W305B will
not respond to any attempt to change output frequency via the SMBus control bytes. System software
can unlock W305B from its recovery frequency mode by clearing the WD_EN bit.
WD_TO_STATUS
WD_TIMER[4:0]
Watchdog Timer Time-out Status bit
0 = No time-out occurs (READ); Ignore (WRITE)
1 = time-out occurred (READ); Clear WD_TO_STATUS (WRITE)
These bits store the time-out value of the Watchdog timer. The scale of the timer is determine by the
pre-scaler.
The timer can support a value of 150 ms to 4.8 sec. when the pre-scaler is set to 150 ms. If the pre-scaler
is set to 2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog timer reaches “0”, it will set the WD_TO_STATUS bit.
WD_PRE_SCALER
RST_EN_WD
0 = 150 ms
1 = 2.5 sec
This bit will enable the generation of a Reset pulse when a watchdog timer time-out occurs.
0 = Disabled
1 = Enabled
RST_EN_FC
This bit will enable the generation of a Reset pulse after a frequency change occurs.
0 = Disabled
1 = Enabled
How to Program CPU Output Frequency
“G” stands for the PLL Gear Constant, which is determined by
the programmed value of FS[4:0] or SEL[4:0]. The value is
listed in Table 5.
When the programmable output frequency feature is enabled
(Pro_Freq_EN bit is set), the CPU output frequency is deter-
mined by the following equation:
The following table lists the recommended frequency output
ranges for each PLL Gear Constant and its associated Bus
Frequency Ratio so that the maximum AGP and PCI output
frequencies are less than or equal to 83.1 MHz and 41.5 MHz,
respectively.
Fcpu = G * (N+3)/(M+3)
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively.
Table 7. Recommended CPU Frequency Range for Different PLL Gear Ratio
Recommended Output Frequency Range (CPU/SDRAM/AGP/PCI)
Bus Frequency Ratio
(CPU/SDRAM/AGP/PCI)
Lower Limits
(N=77, M=48)
Upper Limits
(N=106, M=39)
Gear Constants
G1 (32.00494)
G2 (48.00741)
G3 (64.00988)
66 / 100 / 66 / 33
100 / 100 / 66 / 33
50.2 / 75.8 / 50.2 / 25.1
75.3 / 75.3 / 50.2 / 25.1
83.1 / 124.7 / 83.1 / 41.5
124.6 / 124.6 / 83.1 / 41.5
133 / 133 / 66 / 33
or
133 / 100 / 66 / 33
100.4 / 100.4 / 50.2 / 25.1
or
100.4 / 75.3 / 50.2 / 25.1
166.1 / 166.1 / 83.1 / 41.5
or
166.1 / 124.5 / 83.1 / 41.5
G4 (96.01482)
200 / 200 / 66 / 33
150.6 / 150.6 / 50.2 / 25.1
249.2 / 249.2 / 83.1 / 41.5
Rev 1.0,November 20, 2006
Page 15 of 20
W305B
Absolute Maximum DC Power Supply
Parameter
Description
Min.
–0.5
–0.5
–65
Max.
4.6
Unit
V
VDDQ3
VDDQ2
TS
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
Storage Temperature
3.6
V
150
°C
Absolute Maximum DC I/O
Parameter
Description
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
Input ESD Protection
Min.
–0.5
–0.5
2000
Max.
4.6
Unit
V
Vi/o3
Vi/o3
3.6
V
ESD prot.
V
DC Electrical Characteristics [2]
DC parameters must be sustainable under steady state (DC)
conditions.
DC Operating Requirements
Parameter
VDD3
VDDQ3
VDDQ2
DD3 = 3.3V 5ꢀ
Description
Condition
3.3V 5%
3.3V 5%
2.5V 5%
Min.
Max.
Unit
V
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
2.5V I/O Supply Voltage
3.135
3.135
2.375
3.465
3.465
2.625
V
V
V
Vih3
Vil3
Iil
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current[3]
VDD3
2.0
VDD + 0.3
0.8
V
V
VSS – 0.3
–5
0<Vin<VDD3
+5
µA
VDDQ2 = 2.5V 5ꢀ
Voh2
Vol2
2.5V Output High Voltage
2.5V Output Low Voltage
Ioh=(–1 mA)
Iol=(1 mA)
2.0
2.4
V
V
0.4
0.4
VDDQ3 = 3.3V 5ꢀ
Voh3
Vol3
3.3V Output High Voltage
3.3V Output Low Voltage
Ioh=(–1 mA)
Iol=(1 mA)
V
V
VDDQ3 = 3.3V 5ꢀ
Vpoh3
Vpol3
Cin
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Input Pin Capacitance
Xtal Pin Capacitance
Ioh=(–1 mA)
Iol=(1 mA)
2.4
V
0.55
5
V
pF
pF
pF
nH
°C
Cxtal
Cout
Lpin
Ta
13.5
22.5
6
Output Pin Capacitance
Pin Inductance
0
0
7
Ambient Temperature
No Airflow
70
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT req
3. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
Rev 1.0,November 20, 2006
Page 16 of 20
W305B
AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V 5%, VDDQ2= 2.5V 5%fXTL = 14.31818 MHz[2]
66.6-MHz Host 100-MHz Host 133-MHz Host
Parameter
TPeriod
THIGH
Description
Host/CPUCLK Period
Min.
15.0
5.2
Max.
15.5
N/A
N/A
1.6
Min.
10.0
3.0
Max.
10.5
N/A
N/A
1.6
Min.
7.5
Max.
8.0
Unit
ns
ns 4,7
Notes
4
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
1.87
1.67
0.4
N/A
N/A
1.6
TLOW
5.0
2.8
ns
ns
ns
5
TRISE
0.4
0.4
TFALL
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
ns
ns
ns
ns
ns
4
4
5
SDRAM CLK High Time
SDRAM CLK Low Time
SDRAM CLK Rise Time
SDRAM CLK Fall Time
1.6
1.6
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
APIC CLK Period
60.0
25.5
25.3
0.4
64.0
N/A
N/A
1.6
60.0
25.5
25.30
0.4
N/A
N/A
N/A
1.6
60.0
25.5
25.30
0.4
64.0
N/A
N/A
1.6
ns
ns
ns
ns
ns
4
4
5
APIC CLK High Time
APIC CLK Low Time
APIC CLK Rise Time
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
3V66 CLK Period
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
ns 4, 5
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
ns
ns
ns
ns
4
5
0.5
2.0
0.5
2.0
0.5
2.0
TPeriod
THIGH
TLOW
TRISE
TFALL
PCI CLK Period
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
ns 4, 7
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
ns
ns
ns
ns
4
5
0.5
2.0
0.5
2.0
0.5
2.0
tpZL, tpZH
tpLZ, tpZH
Output Enable Delay (All outputs)
1.0
1.0
10.0
10.0
1.0
1.0
10.0
10.0
1.0
1.0
10.0
10.0
ns
ns
Output Disable Delay
(All outputs)
tstable
All Clock Stabilization from
Power-Up
3
3
3
ms
Notes:
4. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
5. The time specified is measured from when V achieves its nominal operating level (typical condition V
operating within specification.
= 3.3V) until the frequency output is stable and
DDQ3
DDQ3
6. T
7. T
8. T
and T
are measured as a transition through the threshold region V = 0.4V and V = 2.0V (1 mA) JEDEC specification.
RISE
LOW
HIGH
FALL ol oh
is measured at 0.4V for all outputs.
is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
Rev 1.0,November 20, 2006
Page 17 of 20
W305B
Group Skew and Jitter Limits
Skew, Jitter
Output Group
CPU
Pin-Pin Skew Max.
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom Vdd
2.5V
Measure Point
1.25V
1.5V
175 ps
250 ps
250 ps
250 ps
175 ps
500 ps
N/A
SDRAM
APIC
250 ps
45/55
3.3V
500 ps
45/55
2.5V
1.25V
1.5V
48MHz
3V66
500 ps
45/55
3.3V
500 ps
45/55
3.3V
1.5V
PCI
500 ps
45/55
3.3V
1.5V
REF
1000 ps
45/55
3.3V
1.5V
Test Point
Output
Buffer
Test Load
Clock Output Wave
T
PERIOD
Duty Cycle
T
HIGH
2.0
1.25
0.4
2.5V Clocking
Interface
T
LOW
T
T
RISE
FALL
T
PERIOD
Duty Cycle
T
HIGH
2.4
1.5
0.4
3.3V Clocking
Interface
T
LOW
T
T
RISE
FALL
Figure 6. Output Buffer
Layout Example
Rev 1.0,November 20, 2006
Page 18 of 20
W305B
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
10 mF
.005 mf
10 mF
.005 mF
C1
C2
C3
C4
G
G
G
G
G
G
G
V
1
56
55
54
53
V
G
2
3
4
G
V
G
G
5
52
G
V
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G
G
G
G
V
V
V
G
G
G
G
G
V
G
G
G
G
G
G
G
+3.3V
5
:
C6
G
ꢁꢂꢃꢀP
C5
10 PF
G
G
V
F
G
G
FB = Dale ILB1206 - 300 (300:ꢀ@ 100 MHz) or TDK ACB 2012L-120
µF
µF C2 & C4 = .005
C6 = 0.1 PF
Cermaic Cap C1, C3 & C5 = 10 - 22
= VIA to GND plane layer
V =VIA to respective supply plane layer
G
Note: Each supply plane or strip should have a ferrite bead and capacitors
Rev 1.0,November 20, 2006
Page 19 of 20
W305B
Ordering Information
Ordering Code
W305BH
Package Type
56-pin SSOP (300 mils)
Operating Range
Commercial
W305BHH
56-pin SSOP (300 mils) – Tape and Reel
Commercial
Lead Free
CYW305OXC
CYW305OXCT
56-pin SSOP (300 mils)
Commercial
Commercial
56-pin SSOP (300 mils) – Tape and Reel
Package Drawing Dimension
56-Lead Shrunk Small Outline Package O56
.020
28
1
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720
0.730
SEATING PLANE
0.005
0.010
0.088
0.092
0.095
0.110
.010
GAUGE PLANE
0.110
0.024
0.040
0.025
BSC
0.008
0.016
0°-8°
0.008
0.0135
While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-
cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in
normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-
tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional
processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any
circuitry or specification without notice.
Rev 1.0, November 20, 2006
Page 20 of 20
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