AM29LV800B-90REC [SPANSION]
Flash, 512KX16, 90ns, PDSO48, TSOP-48;
| 型号： | AM29LV800B-90REC |
| 厂家： | 
SPANSION |
| 描述： | Flash, 512KX16, 90ns, PDSO48, TSOP-48 光电二极管 |
| 文件： | 总48页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
Am29LV800T/Am29LV800B
8 Megabit (1,048,576 x 8-Bit/524,288 x 16-Bit)
CMOS 3.0 Volt-only, Sectored Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
■ Embedded Algorithms
— Extended voltage range: 2.7 to 3.6 volt read and
write operations for battery-powered
applications
— Embedded Erase algorithms automatically
preprogram and erase the entire chip or any
combination of designated sectors
— Standard voltage range: 3.0 to 3.6 volt read and
write operations and for compatibility with high
performance 3.3 volt microprocessors
— Embedded Program algorithms automatically
write and verify bytes or words at specified
addresses
■ High performance
■ Minimum 100,000 write cycle guarantee per
sector
— Extended voltage range:access times as fast as
100 ns
■ Package options
— 48-pin TSOP
— 44-pin SO
— Standard voltage range: access times as fast as
90 ns
■ Ultra low power consumption
— Automatic Sleep Mode: 200 nA typical
— Standby mode: 200 nA typical
— Read mode: 2 mA/MHz typical
— Program/erase mode: 20 mA typical
■ Flexible sector architecture
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
■ Ready/Busy pin (RY/BY)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Provides a hardware method of detecting
program or erase cycle completion
— Supports control code and data storage on a
single device
■ Erase suspend/resume commands
— Suspends the erase operation to read data from
or program data to another sector, then resumes
the erase operation
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
■ Hardware reset pin (RESET)
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Hardware method to reset the device to the read
mode
■ Top or bottom boot block configurations
available
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication# 20478 Rev: D Amendment/0
Issue Date: November 1997
Refer to AMD’s Website (www.amd.com) for the latest information.
P R E L I M I N A R Y
GENERAL DESCRIPTION
The Am29LV800 is an 8 Mbit, 3.0 Volt-only Flash mem-
ory organized as 1 Mbyte of 8 bits each or 512K words
of 16 bits each. For flexible erase and program capabil-
ity, the 8 Mbits of data is divided into 19 sectors of one
16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64
Kbytes. The x8 data appears on DQ0–DQ7; the x16
data appears on DQ0–DQ15. The Am29LV800 is of-
fered in 44-pin SO and 48-pin TSOP packages. This
device is designed to be programmed in-system with
other sectors. A sector is typically erased and verified
within 1.0 second. The Am29LV800 is fully erased
when shipped from the factory.
The Am29LV800 device also features hardware sector
protection. This feature will disable both program and
erase operations in any combination of nineteen sec-
tors of memory.
AMD has implemented an Erase Suspend feature that
enables the user to put erase on hold for any period of
time to read data from or program data to a sector that
was not being erased. Thus, true background erase
can be achieved.
the standard system 3.0 Volt V
supply. The device
CC
can also be reprogrammed in standard EPROM
programmers.
The Am29LV800 provides two levels of performance.
The first level offers access times as fast as 100 ns with
The device features single 3.0 Volt power supply oper-
ation for both read and write functions. Internally gen-
erated and regulated voltages are provided for the
a V
range as low as 2.7 volts, which is optimal for
CC
battery powered applications.The second level offers a
90 ns access time, optimizing performance in systems
where the power supply is in the regulated range of 3.0
to 3.6 volts.To eliminate bus contention, the device has
separate chip enable (CE), write enable (WE), and
output enable (OE) controls.
program and erase operations. A low V detector au-
CC
tomatically inhibits write operations during power tran-
sitions. The end of program or erase is detected by the
RY/BY pin. Data Polling of DQ7, or by the Toggle Bit
(DQ6). Once the end of a program or erase cycle has
been completed, the device automatically resets to the
read mode.
The Am29LV800 is entirely command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine which
controls the erase and programming circuitry. Write cy-
cles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
The Am29LV800 also has a hardware RESET pin.
When this pin is driven low, execution of any Embed-
ded Program Algorithm or Embedded Erase Algorithm
will be terminated. The internal state machine will then
be reset into the read mode. The RESET pin may be
tied to the system reset circuitry. Therefore, if a system
reset occurs during the Embedded Program Algorithm
or Embedded Erase Algorithm, the device will be auto-
matically reset to the read mode and will have errone-
ous data stored in the address locations being
operated on. These locations will need rewriting after
the Reset. Resetting the device will enable the sys-
tem’s microprocessor to read the boot-up firmware
from the Flash memory.
The Am29LV800 is programmed by executing the pro-
gram command sequence. This will invoke the Embed-
ded Program Algorithm which is an internal algorithm
that automatically times the program pulse widths and
verifies proper cell margin. Erase is accomplished by
executing the erase command sequence. This will in-
voke the Embedded Erase Algorithm which is an inter-
nal algorithm that automatically pre-programs the array
if it is not already programmed before executing the
erase operation. During erase, the device automatically
times the erase pulse widths and verifies proper cell
margin.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The Am29LV800 memory electrically erases
all bits within a sector simultaneously via Fowler-
Nordhiem tunneling.The bytes/words are programmed
one byte/word at a time using the EPROM program-
ming mechanism of hot electron injection.
This device also features a sector erase architecture.
This allows for sectors of memory to be erased and re-
programmed without affecting the data contents of
2
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Flexible Sector Architecture
■ One 8 Kword, two 4 Kwords, one 16 Kword, and
■ Individual-sector or multiple-sector erase capability
■ Sector protection is user definable
fifteen 32 Kwords sectors in word mode
■ One 16 Kbyte, two 8 Kbytes, one 32 Kbyte, and
fifteen 64 Kbyte sectors in byte mode
(x8) Address
Range
(x16) Address
Range
(x8) Address
Range
(x16) Address
Range
16 Kbytes
8 Kwords
64 Kbytes
32 Kwords
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
F0000h-FFFFFh 78000h-7FFFFh
E0000h-EFFFFh 70000h-77FFFh
D0000h-DFFFFh 68000h-6FFFFh
C0000h-CFFFFh 60000h-67FFFh
B0000h-BFFFFh 58000h-5FFFFh
A0000h-AFFFFh 50000h-57FFFh
90000h-9FFFFh 48000h-4FFFFh
80000h-8FFFFh 40000h-47FFFh
70000h-7FFFFh 38000h-3FFFFh
60000h-6FFFFh 30000h-37FFFh
50000h-5FFFFh 28000h-2FFFFh
40000h-4FFFFh 20000h-27FFFh
30000h-3FFFFh 18000h-1FFFFh
20000h-2FFFFh 10000h-17FFFh
10000h-1FFFFh 08000h-0FFFFh
08000h-0FFFFh 04000h-07FFFh
06000h-07FFFh 03000h-03FFFh
04000h-05FFFh 02000h-02FFFh
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
FC000h-FFFFFh 7E000h-7FFFFh
FA000h-FBFFFh 7D000h-7DFFFh
F8000h-F9FFFh 7C000h-7CFFFh
F0000h-F7FFFh 78000h-7BFFFh
E0000h-EFFFFh 70000h-77FFFh
D0000h-DFFFFh 68000h-6FFFFh
C0000h-CFFFFh 60000h-67FFFh
B0000h-BFFFFh 58000h-5FFFFh
A0000h-AFFFFh 50000h-57FFFh
90000h-9FFFFh 48000h-4FFFFh
80000h-8FFFFh 40000h-47FFFh
70000h-7FFFFh 38000h-3FFFFh
60000h-6FFFFh 30000h-37FFFh
50000h-5FFFFh 28000h-2FFFFh
40000h-4FFFFh 20000h-27FFFh
30000h-3FFFFh 18000h-1FFFFh
20000h-2FFFFh 10000h-17FFFh
10000h-1FFFFh 08000h-0FFFFh
64 Kbytes
32 Kwords
8 Kbytes
4 Kwords
64 Kbytes
32 Kwords
8 Kbytes
4 Kwords
64 Kbytes
32 Kwords
32 Kbytes
16 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
SA8
SA8
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
SA7
SA7
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
SA6
SA6
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
SA5
SA5
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
SA4
SA4
32 Kbytes
16 Kwords
64 Kbytes
32 Kwords
SA3
SA3
8 Kbytes
4 Kwords
64 Kbytes
32 Kwords
SA2
SA2
8 Kbytes
4 Kwords
64 Kbytes
32 Kwords
SA1
SA1
16 Kbytes
8 Kwords
64 Kbytes
32 Kwords
SA0
00000h-03FFFh 00000h-01FFFh
20478D-2
SA0
00000h-0FFFFh 00000h-07FFFh
20478D-1
Am29LV800T Sector Architecture
Am29LV800B Sector Architecture
Notes:
The address range is A18:A-1 if in byte mode (BYTE = V ).
IL
The address range is A18:A0 if in word mode (BYTE = V ).
IH
Am29LV800T/Am29LV800B
3
P R E L I M I N A R Y
PRODUCT SELECTOR GUIDE
Family Part Number
Am29LV800T/Am29LV800B
Ordering Part Number:
V
= 3.0–3.6 V
= 2.7–3.6 V
-90R
CC
V
-100
100
100
40
-120
120
120
50
-150
150
150
55
CC
Max access time (ns)
CE access time (ns)
OE access time (ns)
90
90
40
BLOCK DIAGRAM
RY/BY
DQ0–DQ7
Sector
V
V
CC
Switches
SS
Input/Output
Buffers
Erase Voltage
Generator
RESET
State
Control
WE
BYTE
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data Latch
STB
CE
OE
Y-Decoder
Y-Gating
STB
V
Detector
Timer
CC
X-Decoder
Cell Matrix
A0–A18
20478D-3
4
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
CONNECTION DIAGRAMS
SO
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
RESET
RY/BY
A18
A17
A7
2
WE
A8
3
4
A9
A6
5
A10
A11
A12
A13
A14
A15
A16
BYTE
VSS
A5
6
A4
7
A3
8
A2
9
A1
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
CE
VSS
OE
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
20478D-4
Am29LV800T/Am29LV800B
5
P R E L I M I N A R Y
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
DQ12
DQ4
VCC
WE
RESET
NC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
VSS
CE
A0
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
20478D-5
Standard TSOP
A16
BYTE
VSS
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
WE
RESET
NC
NC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
VSS
CE
A0
20478D-6
Reverse TSOP
6
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
PIN CONFIGURATION
LOGIC SYMBOL
A0–A18
= 19 addresses
19
DQ0–DQ14 = 15 data inputs/outputs
A0–A18
16 or 8
DQ15/A-1
= DQ15 data input/output (word mode),
DQ0–DQ15
(A-1)
A-1 (LSB address input, byte mode)
= Selects 8-bit or 16-bit mode
= Chip enable
BYTE
CE
CE
OE
OE
= Output enable
WE
WE
= Write enable
RESET
BYTE
RESET
RY/BY
= Hardware reset pin, active low
= Ready/Busy output
RY/BY
V
= Standard voltage range
(3.0 to 3.6 V) for -90R
CC
20478D-7
Extended voltage range
(2.7 to 3.6 V) for -100, -120, -150
V
= Device ground
SS
NC
= Pin not connected internally
Am29LV800T/Am29LV800B
7
P R E L I M I N A R Y
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-
nation) is formed by a combination of the elements below.
Am29LV800
T
-90R
E
C
OPTIONAL PROCESSING
Blank = Standard Processing
B = Burn-in
TEMPERATURE RANGE
C = Commercial (0°C to +70°C)
I = Industrial (–40°C to +85°C)
E = Extended (–55°C to +125°C)
PACKAGE TYPE
E = 48-Pin Thin Small Outline Package (TSOP)
Standard Pinout (TS 048)
F = 48-Pin Thin Small Outline Package (TSOP)
Reverse Pinout (TSR048)
S = 44-Pin Small Outline Package (SO 044)
SPEED OPTION
-xxx = 2.7 to 3.6 V V
-xxR= 3.0 to 3.6 V V
CC
CC
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T = Top Sector
B = Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29LV800
8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory
3.0 Volt-only Program and Erase
Valid Combinations
Valid Combinations
Am29LV800T-100,
Am29LV800B-100
Am29LV800T-90R,
Am29LV800B-90R
SC, SI, SE, SEB,
EC, EI, EE, EEB,
FC, FI, FE, FEB
EC, EI, FC, FI, SC, SI
Am29LV800T-120,
Am29LV800B-120
V
= 3.0–3.6 V
CC
Am29LV800T-150,
Am29LV800B-150
8
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Table 1. Am29LV800 User Bus Operations (BYTE = V )
IH
Operation
Autoselect, Manufacturer Code (Note 1)
Autoselect Device Code (Note 1)
Read
CE
L
OE
L
WE
A0
L
A1
L
A6
L
A9
DQ0–DQ15 RESET
H
V
Code
Code
H
H
H
H
H
H
H
H
ID
L
L
H
H
L
L
V
ID
L
L
H
A0
X
A1
X
A6
X
A9
X
D
OUT
Standby
H
L
X
X
HIGH Z
HIGH Z
Output Disable
H
H
H
X
X
X
X
Write
L
L
A0
L
A1
H
A6
L
A9
D (Note 2)
IN
Enable Sector Protect (Note 3)
Verify Sector Protect (Note 4)
Temporary Sector Unprotect
Reset
L
V
Pulse/H
V
Code
Code
X
ID
ID
L
L
H
X
X
L
H
L
V
ID
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
HIGH Z
L
Table 2. Am29LV800 User Bus Operations (BYTE = V )
IL
Operation
CE
OE
WE
A0
A1
A6
A9
DQ0–DQ7 DQ8–DQ15 RESET
Autoselect, Manufacturer Code
(Note 1)
L
L
H
L
L
L
V
Code
Code
HIGH Z
HIGH Z
H
H
ID
ID
Autoselect, Device Code
(Note 1)
L
L
H
H
L
L
V
Read
L
H
L
L
X
H
H
H
A0
X
A1
X
A6
X
A9
X
D
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
H
H
H
H
H
H
OUT
Standby
X
HIGH Z
HIGH Z
Output Disable
H
X
X
X
X
Write
L
L
A0
L
A1
H
A6
L
A9
D (Note 2)
IN
Enable Sector Protect (Note 3)
Verify Sector Protect (Note 4)
Temporary Sector Unprotect
Reset
L
V
Pulse/H
V
Code
Code
X
ID
ID
L
L
H
X
X
L
H
L
V
ID
X
X
X
X
X
X
X
X
V
ID
X
X
X
X
HIGH Z
L
Legend:
L = Logic 0, H = Logic 1, V = 12.0 ± 0.5 Volts, X = Don’t care. See DC Characteristics (Table 12 and 13) for voltage levels.
ID
Notes:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 6.
2. Refer to Table 6 for valid Data in (D ) during a write operation.
IN
3. Set V = 3.0 Volts ± 10%.
CC
4. Refer to Sector Protection section.
Am29LV800T/Am29LV800B
9
P R E L I M I N A R Y
USER BUS OPERATIONS
Read Mode
standby mode, the data I/O pins remain in the high im-
pedance state independent of the voltage level applied
to the OE input. See the DC Characteristics section for
more details on Standby Modes.
The Am29LV800 has three control functions which
must be satisfied in order to obtain data at the outputs:
■ CE is the power control and should be used for
Deselecting CE (CE = V or V ± 0.3 V, with RESET
IH
CC
device selection (CE = V )
IL
= V or V ± 0.3 V), will put the device into the I
IH
CC
CC3
■ OE is the output control and should be used to gate
standby mode. If the device is deselected during an
™
data to the output pins if the device is selected
Embedded Algorithm operation, it will continue to
(OE = V )
draw active power (I
), prior to entering the standby
IL
CC2
mode, until the operation is complete. Subsequent
reselection of the device for active operations
■ WE remains at V
IH
Address access time (t
stable addresses to valid output data. The chip enable
) is equal to the delay from
ACC
(CE = V ) will commence pursuant to the AC timing
IL
specifications.
access time (t ) is the delay from stable addresses
CE
Automatic Sleep Mode
and stable CE to valid data at the output pins. The out-
put enable access time (t ) is the delay from the fall-
OE
Advanced power management features such as the
automatic sleep mode minimize Flash device energy
consumption. This is extremely important in
battery-powered applications. The Am29LV800 auto-
matically enables the low-power, automatic sleep
mode when addresses remain stable for 200 ns. Auto-
matic sleep mode is independent of the CE, WE, and
OE control signals. Typical sleep mode current draw is
200 nA (for CMOS-compatible operation). Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
ing edge of OE to valid data at the output pins
(assuming the addresses have been stable at least
t
– t time).
ACC
OE
Standby Mode
The Am29LV800 is designed to accommodate two
modes for low standby power consumption. Both
modes are enabled by applying the voltages specified
below to the CE and RESET pins. These modes are
available for either TTL/NMOS or CMOS logic level de-
signs.The first mode, I
for TTL/NMOS compatible I/
CC3
Os (current consumption <1 mA max.), is enabled by
applying a TTL logic level ‘1’ (V ) to the CE control pin
Output Disable
IH
with RESET = V . I
for CMOS compatible I/Os
IH CC3
If the OE input is at a logic high level (V ), output from
IH
(current consumption <5 µA max.), is enabled when a
CMOS logic level ‘1’ (V ± 0.3 V) is applied to the CE
the device is disabled.This will cause the output pins to
be in a high impedance state.
CC
control pin with RESET = V ± 0.3 V.While in the I
CC
CC3
10
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 6.
Autoselect
The Autoselect mode allows the reading out of a binary
code from the device and will identify its manufacturer
and type.The intent is to allow programming equipment
to automatically match the device to be programmed
with its corresponding programming algorithm. The
Autoselect command may also be used to check the
status of write-protected sectors (see Table 3). This
mode is functional over the entire temperature range of
the device.
Byte 0 (A0 = V ) represents the manufacturer’s code
IL
and byte 1 (A0 = V ) the device identifier code. These
IH
two bytes are given for the Am29LV800 in Table 3. All
identifiers for manufacturer and device exhibit odd
parity with DQ7 defined as the parity bit. In order to
read the proper device codes when executing Autose-
lect, A1 must be V (see Table 3). For device identifica-
IL
tion in word mode (BYTE = V ), DQ9 and DQ13 are
IH
equal to ‘1’ and DQ8, DQ10–12, DQ14, and DQ15 are
equal to ‘0’.
To activate this mode, the programming equipment
must force V (11.5–12.5 volts) on address pin A9.
ID
Two identifier bytes may then be sequenced from the
If BYTE =V (for word mode), the device code is 22DAh
IH
device outputs by toggling address A0 from V to V .
(for top boot block) or 225Bh (for bottom boot block). If
IL
IH
All addresses are don’t cares except A0, A1, and A6
(see Table 3).
BYTE = V (for byte mode), the device code is DAh (for
top boot block) or 5Bh (for bottom boot block).
IL
The manufacturer and device codes may also be read
via the command register, for instances when the
Am29LV800 is erased or programmed in a system
In order to determine which sectors are write protected,
A1 must be at V while running through the sector
IH
addresses. If the selected sector is protected, the
device outputs a ‘1’ on DQ0.
Table 3. Autoselect/Sector Protection Codes
Code DQ DQ DQ DQ DQ DQ DQ DQ
Type
Mode A12–A18 A6 A1 A0 (HEX) DQ8–DQ15
7
6
5
4
3
2
1
0
Manufacturer Code:
AMD
X
L
L
L
L
L
01h
High-Z
0
0
0
0
0
0
0
1
DQ9 = 1,
Word
Byte
Word
Byte
X
X
X
X
22DAh DQ13 = 1,
Others = 0
29LV800 Device
(Top Boot Block)
H
1
1
0
1
1
0
1
0
DAh
High-Z
DQ9 = 1,
225Bh DQ13 = 1,
Others = 0
29LV800 Device
(Bottom Boot Block)
L
L
L
H
L
0
0
1
0
0
0
1
0
1
0
0
0
1
0
1
1
5Bh
High-Z
X
Set Sector
Addresses
Sector Protection
X = Don’t care.
H
01h*
* Outputs 01h at protected sector addresses.
Am29LV800T/Am29LV800B
11
P R E L I M I N A R Y
Table 4. Sector Address Tables (Am29LV800T)
(x8)
(x16)
A18
A17
A16
A15
A14
A13
A12
Sector Size
Address Range
Address Range
64 Kbytes
32 Kwords
SA0
SA1
0
0
0
0
X
X
X
00000h-0FFFFh
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFFh
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7BFFFh
7C000h-7CFFFh
7D000h-7DFFFh
7E000h-7FFFFh
64 Kbytes
32 Kwords
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
40000h-4FFFFh
50000h-5FFFFh
60000h-6FFFFh
70000h-7FFFFh
80000h-8FFFFh
90000h-9FFFFh
A0000h-AFFFFh
B0000h-BFFFFh
C0000h-CFFFFh
D0000h-DFFFFh
E0000h-EFFFFh
F0000h-F7FFFh
F8000h-F9FFFh
FA000h-FBFFFh
FC000h-FFFFFh
64 Kbytes
32 Kwords
SA2
64 Kbytes
32 Kwords
SA3
64 Kbytes
32 Kwords
SA4
64 Kbytes
32 Kwords
SA5
64 Kbytes
32 Kwords
SA6
64 Kbytes
32 Kwords
SA7
64 Kbytes
32 Kwords
SA8
64 Kbytes
32 Kwords
SA9
64 Kbytes
32 Kwords
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
32 Kbytes
16 Kwords
8 Kbytes
4 Kwords
1
8 Kbytes
4 Kwords
1
0
1
16 Kbyte
8 Kwords
1
1
X
Note: The address range is A18:A-1 if in byte mode (BYTE = V ). The address range is A18:A0 if in word mode (BYTE = V ).
IL
IH
12
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Table 5. Sector Address Tables (Am29LV800B)
(x8)
(x16)
A18
A17
A16
A15
A14
A13
A12
Sector Size
Address Range
Address Range
16 Kbytes
8 Kwords
SA0
SA1
0
0
0
0
0
0
X
00000h–03FFFh
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
20000h-27FFFh
28000h-2FFFFh
30000h-37FFFh
38000h-3FFFFh
40000h-47FFFh
48000h-4FFFF
50000h-57FFFh
58000h-5FFFFh
60000h-67FFFh
68000h-6FFFFh
70000h-77FFFh
78000h-7FFFFh
8 Kbytes
4 Kwords
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
04000h–05FFFh
06000h–07FFFh
08000h–0FFFFh
10000h–1FFFFh
20000h–2FFFFh
30000h–3FFFFh
40000h–4FFFFh
50000h–5FFFFh
60000h–6FFFFh
70000h–7FFFFh
80000h–8FFFFh
90000h–9FFFFh
A0000h–AFFFFh
B0000h–BFFFFh
C0000h–CFFFFh
D0000h–DFFFFh
E0000h–EFFFFh
F0000h–FFFFFh
8 Kbytes
4 Kwords
SA2
32 Kbytes
16 Kwords
SA3
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64 Kbytes
32 Kwords
SA4
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
64 Kbytes
32 Kwords
SA5
64 Kbytes
32 Kwords
SA6
64 Kbytes
32 Kwords
SA7
64 Kbytes
32 Kwords
SA8
64 Kbytes
32 Kwords
SA9
64 Kbytes
32 Kwords
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
64 Kbytes
32 Kwords
Note: The address range is A18:A-1 if in byte mode (BYTE = V ). The address range is A18:A0 if in word mode (BYTE = V ).
IL
IH
Am29LV800T/Am29LV800B
13
P R E L I M I N A R Y
user attempts to erase a protected sector, Toggle Bit
Write
will be activated for about 50 µs; the device will then
return to read mode, without having erased the pro-
tected sector.
Device erasure and programming are accomplished via
the command register. The command register is written
by bringing WE to V , while CE is at V and OE is at
IL
IL
V . Addresses are latched on the falling edge of CE or
It is possible to determine if a sector is protected in the
system by writing an Autoselect command. Performing
a read operation at the address location XX02h, where
the higher order address A18–A12 represents the sec-
tor address, will produce a logical ‘1’ at DQ0 for a pro-
tected sector.
IH
WE, whichever occurs later, while data is latched on the
rising edge of the CE or WE pulse, whichever occurs
first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/
Programming Waveforms for specific timing parameters.
Temporary Sector Unprotect
Sector Protect
The sectors of the Am29LV800 may be temporarily
unprotected by raising the RESET pin to 12.0 Volts
Sectors of the Am29LV800 may be hardware pro-
tected at the user’s factory with external programming
equipment. The protection circuitry will disable both
program and erase functions for the protected sec-
tors, making the protected sectors read-only. Re-
quests to program or erase a protected sector will be
ignored by the device. If the user attempts to write to
a protected sector, DATA Polling will be activated for
about 1 µs; the device will then return to read mode,
with data from the protected sector unchanged. If the
(V ). During this mode, formerly protected sectors
ID
can be programmed or erased with standard com-
mand sequences by selecting the appropriate byte or
sector addresses. Once the RESET pin goes to TTL
level (V ), all the previously protected sectors will be
IH
protected again.
+12.0 V
RESET
500 ns min.
20478D-8
Figure 1. Temporary Sector Unprotect Timing Diagram
Command Definitions
Autoselect Command
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device
to the read mode. Table 6 defines the valid register
command sequences. Note that the Erase Suspend
(B0h) and Erase Resume (30h) commands are valid
only while the Sector Erase operation is in progress.
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. The
Am29LV800 contains an autoselect command opera-
tion that provides device information and sector protec-
tion status to the system. The operation is initiated by
writing the autoselect command sequence into the
command register. Following the command write, a
read cycle from address XX00h retrieves the manufac-
turer code of 01h. A read cycle from address
XX01hreturns the device code DAh/5Bh for x8 configu-
ration or 22DAh/225Bh for x16 configuration (see Table
3). All manufacturer and device codes will exhibit odd
parity with the MSB of the lower byte (DQ7) defined as
the parity bit. Scanning the sector addresses (A12,
A13, A14, A15, A16, A17, and A18) while (A6, A1, A0)
= (0, 1, 0) will produce a logical‘1’code at device output
DQ0 for a write protected sector (See Table 3).
Read/Reset Command
The device will automatically power up in the read/
reset state. In this case, a command sequence is
not required to read data. Standard microproces-
sor cycles will retrieve array data. This default
value ensures that no spurious alteration of the
memory content occurs during the power transi-
tion. Refer to the AC Characteristics section for the
specific timing parameters.
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data
from the memory. The device remains enabled for
reads until the command register contents are altered.
To terminate the Autoselect operation, it is neces-
sary to write the read/reset command sequence
into the register.
14
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Table 6. Am29LV800 Command Definitions
Second Bus
Read/Write
Cycle
Fourth Bus
Read/Write
Cycle
Command
Sequence
Read/Reset
(Note 2)
Bus
Write
Cycles
First Bus
Write Cycle
Third BusWrite
Cycle
Fifth Bus
Write Cycle
Sixth Bus
Write Cycle
Req’d Addr
Data
XXF0
F0
Addr
Data
Addr
Data
Addr
Data
Addr
Data Addr Data
Word
Byte
Reset/Read
1
3
XXX
RA
RD
Word
Byte
555
AAA
555
XXAA
AA
2AA
555
2AA
XX55
55
555
AAA
555
XX90
90
X00
X00
X01
XX01
01
Autoselect
Manufacturer ID
Autoselect
Word
XXAA
XX55
XX90
22DA
Device ID
(Top Boot Block)
3
3
Byte
AAA
555
AA
555
55
AAA
555
90
X02
X01
DA
Autoselect
Device ID
(Bottom Boot
Block)
Word
XXAA
2AA
XX55
XX90
225B
Byte
AAA
555
AA
555
55
AAA
555
90
X02
5B
XX00
XX01
00
SA
X02
Word
XXAA
2AA
XX55
XX90
Autoselect
Sector Protect
Verify (Note 3)
3
SA
X04
Byte
AAA
AA
555
55
AAA
90
01
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
555
AAA
555
XXAA
AA
2AA
555
2AA
555
2AA
555
XX55
55
555
AAA
555
XXA0
A0
Program
4
6
6
1
1
PA
PD
XXAA
AA
XX55
55
XX80
80
555 XXAA 2AA XX55 555 XX10
Chip Erase
Sector Erase
AAA
555
AAA
555
AAA
555 XXAA 2AA XX55
AAA AA 555 55
AA
555
55
AAA
10
XX30
30
XXAA
AA
XX55
55
XX80
80
SA
AAA
AAA
XXB0
B0
Erase Suspend
(Note 4)
XXX
XXX
XX30
30
Erase Resume
(Note 5)
Legend:
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WEor CE pulse.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WEor CE pulse.
SA = Address of the sector to be erased or verified. Address bits A18–A12 uniquely select any sector.
Notes:
1. All values are in hexadecimal.
2. See Tables 1 and 2 for description of bus operations.
3. The data is 00h for an unprotected sector and 01h for a protected sector.The complete bus address is composed of the sector
address on A18–A12 and 02h on A7–A0.
4. Read and program functions in non-erasing sectors are allowed in the Erase Suspend mode. The Erase Suspend command
is valid only during a sector erase operation.
5. The Erase Resume command is valid only during the Erase Suspend mode.
6. Unless otherwise noted, address bits A18–A11 = X = don’t care.
Am29LV800T/Am29LV800B
15
P R E L I M I N A R Y
■ DATA Polling of DQ7
Word/Byte Programming
■ Checking the status of the toggle bit DQ6
■ Checking the status of the RY/BY pin
The device can be programmed on a word or byte ba-
sis. Programming is a four-bus-cycle operation. There
are two “unlock” write cycles.These are followed by the
program command and address/data write cycles. Ad-
dresses are latched on the falling edge of CE or WE,
whichever occurs later, while the data is latched on the
rising edge of CE or WE, whichever occurs first. The
rising edge of CE or WE, whichever occurs first, ini-
tiates programming using the Embedded Program Al-
gorithm. Upon executing the write command, the
system is not required to provide further controls or
timing. The device will automatically provide adequate
internally generated program pulses and verify the pro-
grammed cell margin.
Figure 8 illustrates the Embedded Erase Algorithm,
using a typical command sequence and bus opera-
tions.
Sector Erase
Sector erase is a six bus cycle operation.There are two
“unlock” writes.These are followed by writing the erase
“set up” command. Two more “unlock” writes are fol-
lowed by the Sector Erase command (30h). The sector
address (any address location within the desired sec-
tor) is latched on the falling edge of WE or CE (which-
ever occurs last) while the command (30h) is latched
on the rising edge of WE or CE (whichever occurs first).
The status of the Embedded Program Algorithm oper-
ation can be determined three ways:
Multiple sectors can be specified for erase by writing
the six bus cycle operation as described above and
then following it by additional writes of the Sector Erase
command to addresses of other sectors to be erased.
The time between Sector Erase command writes must
be less than 80 µs, otherwise that command will not be
accepted. It is recommended that processor interrupts
be disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80 µs from the
rising edge of the last WE (or CE) will initiate the exe-
cution of the Sector Erase command(s). If another fall-
ing edge of the WE (or CE) occurs within the 80 µs
time-out window, the timer is reset. During the 80 µs
window, any command other than Sector Erase or
Erase Suspend written to the device will reset the de-
vice back to Read mode. Once the 80 µs window has
timed out, only the Erase suspend command is recog-
nized. Note that although the Reset command is not
recognized in the Erase Suspend mode, the device is
available for read or program operations in sectors that
are not erase suspended. The Erase Suspended and
Erase Resume commands may be written as often as
required during a sector erase operation. Hence, once
erase has begun, it must ultimately complete unless
Hardware Reset is initiated. Loading the sector erase
registers may be done in any sequence and with any
number of sectors (0 to 18).
■ DATA Polling of DQ7
■ Checking the status of the toggle bit DQ6
■ Checking the status of the RY/BY pin
Any commands written to the chip during the Embed-
ded Program Algorithm will be ignored. If a hardware
reset occurs during a programming operation, the data
at that location will be corrupted.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data ‘0’ cannot be
programmed back to a ‘1’. Attempting to do so will
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success according
to the data polling algorithm. However, reading the de-
vice after executing the Read/Reset operation will
show that the data is still ‘0’. Only erase operations can
convert ‘0’s to ‘1’s.
Figure 7 illustrates the Embedded Program Algorithm,
using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles, followed by writing the erase “set
up” command. Two more “unlock” write cycles are fol-
lowed by the chip erase command.
Chip erase does not require the user to preprogram the
device to all ‘0’s prior to erase. Upon executing the Em-
bedded Erase Algorithm command sequence, the de-
vice automatically programs and verifies the entire
memory to an all zero data pattern prior to electrical
erase. The system is not required to provide any con-
trols or timings during these operations.
Sector erase does not require the user to program the
device prior to erase. The device automatically prepro-
grams all memory locations, within sectors to be
erased, prior to electrical erase. When erasing a sector
or sectors, the remaining unselected sectors or the
write protected sectors are unaffected. The system is
not required to provide any controls or timings during
sector erase operations. The Erase Suspend and
Erase Resume commands may be written as often as
required during a sector erase operation.
The Embedded Erase Algorithm erase begins on the
rising edge of the last WE or CE (whichever occurs
first) pulse in the command sequence.The status of the
Embedded Erase Algorithm operation can be deter-
mined three ways:
16
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Automatic sector erase operations begin on the rising
at which time the user can read or program from a sec-
tor that is not erase suspended. Reading data in this
mode is the same as reading from the standard read
mode, except that the data must be read from sectors
that have not been erase suspended.
edge of the WE (or CE) pulse of the last sector erase
command issued, and once the 80 µs time-out window
has expired. The status of the sector erase operation
can be determined three ways:
■ DATA Polling of DQ7
Successively reading from the erase-suspended sector
while the device is in the erase-suspend-read mode will
cause DQ2 to toggle. Polling DQ2 on successive reads
from a given sector provides the system the ability to
determine if a sector is in Erase Suspend.
■ Checking the status of the toggle bit DQ6
■ Checking the status of the RY/BY pin
Further status of device activity during the sector erase
operation can be determined using toggle bits DQ2 and
DQ3.
After entering the erase-suspend-read mode, the user
can program the device by writing the appropriate com-
mand sequence for Byte Program. This program mode
is known as the erase suspend-program mode. Again,
programming in this mode is the same as programming
in the regular Byte Program mode, except that the data
must be programmed to sectors that are not erase sus-
pended. Successively reading from the erase sus-
pended sector while the device is in the erase
suspend-program mode will cause DQ2 to toggle.
Completion of the erase suspend operation can be de-
termined two ways:
Figure 8 illustrates the Embedded Erase Algorithm,
using a typical command sequence and bus operations.
Erase Suspend
The Erase Suspend command allows the user to inter-
rupt a Sector Erase operation and then perform data
read or programs in a sector not being erased. This
command is applicable only during the Sector Erase
operation, which includes the time-out period for Sector
Erase. The Erase Suspend command will be ignored if
written during the execution of the Chip Erase opera-
tion or Embedded Program Algorithm (but will reset the
chip if written improperly during the command se-
quences.) Writing the Erase Suspend command during
the Sector Erase time-out results in immediate termina-
tion of the time-out period and suspension of the erase
operation. Once in Erase Suspend, the device is avail-
able for read (note that in the Erase Suspend mode, the
Reset/Read command is not required for read opera-
tions and is ignored) or program operations in sectors
not being erased. Any other command written during
the Erase Suspend mode will be ignored, except for the
Erase Resume command. Writing the Erase Resume
command resumes the sector erase operation.The ad-
dresses are “don’t cares” when writing the Erase Sus-
pend or Erase Resume command.
■ Checking the status of the toggle bit DQ2
■ Checking the status of the RY/BY pin
To resume the operation of Sector Erase, the Resume
command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. How-
ever, another Erase Suspend command can be written
after the device has resumed sector erase operations.
When the erase operation has been suspended, the de-
vice defaults to the erase-suspend-read mode. Reading
data in this mode is the same as reading from the stan-
dard read mode except that the data must be read from
sectors that have not been erase-suspended.
To resume the operation of Sector Erase, the Resume
command (30h) should be written. Any further writes of
the Resume command at this point will be ignored. An-
other Erase Suspend command can be written after the
chip has resumed erasing.
When the Erase Suspend command is written during a
Sector Erase operation, the chip will take between 0.1
µs and 20 µs to actually suspend the operation and go
into erase suspended read mode (pseudo-read mode),
Am29LV800T/Am29LV800B
17
P R E L I M I N A R Y
Once Erase Suspend is entered, address sensitivity
Write Operation Status
still applies. If the address of a non-erasing sector (that
is, one available for read) is provided, then stored data
can be read from the device. If the address of an eras-
ing sector (that is, one unavailable for read) is applied,
the device will output its status bits. Confirmation of sta-
tus bits can be done by doing consecutive reads to tog-
gle DQ2, which is active throughout the Embedded
Erase mode, including Erase Suspend.
Address Sensitivity of Write Status Flags
Detailed in Table 7 are all the status flags that can be
used to check the status of the device for current mode
operation. During Sector Erase, the part provides the
status flags automatically to the I/O ports.The informa-
tion on DQ2 is address sensitive. This means that if an
address from an erasing sector is consecutively read,
then the DQ2 bit will toggle. However, DQ2 will not tog-
gle if an address from a non-erasing sector is consec-
utively read. This allows the user to determine which
sectors are erasing and which are not.
In order to effectively use DATA Polling to determine if
the device has entered into erase-suspended mode, it
is necessary to apply a sector address from a sector
being erased.
Table 7. Hardware Sequence Flags
Status
DQ7
DQ7
0
DQ6
DQ5
DQ3
DQ2
RY/BY
Byte and Word Programming
Program/Erase in Auto-Erase
Toggle
Toggle
0
0
0
1
No Toggle
(Note 1)
0
0
Toggle
(Note 1)
Erase Sector Address
Erase
Suspend
1
No Toggle
Data
0
Data
0
0
Data
0
1
1
0
In Progress
Data
(Note 2)
Mode
Non-Erase Sector Address
Data
DQ7
(Note 2)
1
Program in Erase Suspend
Toggle
(Note 2)
Byte and Word Programming
Program/Erase in Auto-Erase
Program in Erase Suspend
DQ7
0
Toggle
Toggle
Toggle
1
1
1
0
1
0
No Toggle
(Note 3)
0
0
0
Exceeded
Time Limits
DQ7
No Toggle
Notes:
1. DQ2 can be toggled when the sector address applied is that of an erasing or erase suspended sector.Conversely, DQ2 cannot
be toggled when the sector address applied is that of a non-erasing or non-erase suspended sector. DQ2 is therefore used
to determine which sectors are erasing or erase suspended and which are not.
2. These status flags apply when outputs are read from the address of a non-erase-suspended sector.
3. If DQ5 is high (exceeded timing limits), successive reads from a problem sector will cause DQ2 to toggle.
DQ7: Data Polling
Erase Algorithm, an attempt to read the device will pro-
duce a ‘0’ at the DQ7 output. Upon completion of the
Embedded Erase Algorithm, an attempt to read the de-
vice will produce a ‘1’ at DQ7.
The Am29LV800 features DATA Polling as a method to
indicate to the host system that the embedded algo-
rithms are in progress or completed.
For chip erase, the DATA Polling is valid (DQ7 = 1) after
the rising edge of the sixth WE pulse in the six write
pulse sequence. For sector erase, the DATA Polling is
valid after the last rising edge of the sector erase WE
pulse. DATA Polling must be performed at sector ad-
dresses within any of the sectors being erased and not
a sector that is within a protected sector. Otherwise, the
status may not be valid.
During the Embedded Program Algorithm, an attempt
to read the device will produce the compliment of the
data last written to DQ7. Upon completion of the Em-
bedded Program Algorithm, an attempt to read the de-
vice will produce the true data last written to DQ7. Note
that just at the instant when DQ7 switches to true data,
the other bits, DQ6–DQ0, may not yet be true data.
However, they will all be true data on the next read from
the device. Please note that Data Polling (DQ7) may
give an inaccurate result when an attempt is made
to write to a protected sector. During an Embedded
Just prior to the completion of Embedded Algorithm op-
erations, DQ7 may change asynchronously while the
output enable (OE) is asserted low.This means that the
18
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
device is driving status information on DQ7 at one in- condition. The device will draw active power under this
stant of time and then that byteUs valid data at the next
instant of time. Depending on when the system sam-
ples the DQ7 output, it may read the status or valid
data. Even if the device has completed the Embedded
Algorithm operations and DQ7 has valid data, DQ0–
DQ6 may still provide write operation status. The valid
data on DQ0–DQ7 can be read on the next successive
read attempt.
condition.
The DQ5 failure condition will also appear if the user at-
tempts to write a data ‘1’ to a bit that has already been
programmed to a data ‘0’. In this case, the DQ5 failure
condition is not guaranteed to happen, since the device
was incorrectly used. Please note that programming a
data ‘0’ to a data ‘1’ should never be attempted, and
only erasure should be used for this purpose. If pro-
gramming to a data ‘1’ is attempted, the device should
be reset.
The DATA Polling feature is only active during the Em-
bedded Programming Algorithm, Embedded Erase Al-
gorithm, Erase Suspend, erase suspend-program
mode, or sector erase time-out (see Table 7).
If the DQ5 failure condition is observed while in Sector
Erase mode (that is, exceeded timing limits), then DQ2
can be used to determine which sector had the prob-
lem. This is especially useful when multiple sectors
have been loaded for erase.
If the user attempts to write to a protected sector,
DATA Polling will be activated for about 1 µs; the de-
vice will then return to read mode, with data from the
protected sector unchanged. If the user attempts to
erase a protected sector, Toggle Bit will be activated
for about 50 µs; the device will then return to read
mode, without having erased the protected sector.
DQ3: Sector Erase Timer
After the completion of the initial Sector Erase com-
mand sequence, the Sector Erase time-out will begin.
DQ3 will remain low until the time-out is complete.
DATA Polling (DQ7) and Toggle Bit (DQ6) are also valid
after the first sector erase command sequence.
See Figure 18 for the DATA Polling timing specifications
and diagrams.
DQ6:Toggle Bit
If DATA Polling or the Toggle Bit indicates the device
has been written with a valid Sector Erase command,
DQ3 may be used to determine if the sector erase timer
window is still open. If DQ3 is high (‘1’), the internally
controlled erase cycle has begun; attempts to write
subsequent commands to the device will be ignored
until the erase operation is completed as indicated by
the DATA Polling or Toggle Bit. If DQ3 is low (‘0’), the
device will accept additional sector erase commands.
To be certain the command has been accepted, the
software should check the status of DQ3 following each
Sector Erase command. If DQ3 was high on the sec-
ond status check, the command may not have been ac-
cepted.
The Am29LV800 also features a “Toggle Bit” as a
method to indicate to the host system whether the em-
bedded algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm,
successive attempts to read data from the device will
result in DQ6 toggling between one and zero. Once the
Embedded Program or Erase Algorithm is completed,
DQ6 will stop toggling and valid data can be read on
the next successive attempts. During programming, the
Toggle Bit is valid after the rising edge of the fourth WE
pulse in the four-write-pulse sequence. During Chip
erase, the Toggle Bit is valid after the rising edge of the
sixth WE pulse in the six-write-pulse sequence. During
Sector erase, the Toggle Bit is valid after the last rising
edge of the sector erase WE pulse. The Toggle Bit is
active during the Sector Erase time-out.
It is recommended that the user guarantee the time be-
tween sector erase command writes be less than 80 µs
by disabling the processor interrupts just for the dura-
tion of the Sector Erase (30h) commands. This ap-
proach will ensure that sequential sector erase
command writes will be written to the device while the
sector erase timer window is still open.
Either CE or OE toggling will cause DQ6 to toggle. If the
user attempts to write to a protected sector, DATA Polling
will be activated for about 1 µs;the device will then return
to read mode, with data from the protected sector un-
changed. If the user attempts to erase a protected sec-
tor, Toggle Bit will be activated for about 50 µs; the
device will then return to read mode, without having
erased the protected sector.
DQ2:Toggle Bit 2
This toggle bit, along with DQ6, can be used to deter-
mine whether the device is in the Embedded Erase Al-
gorithm or in Erase Suspend.
DQ5: Exceeded Timing Limits
Successive reads from the erasing sector will cause
DQ2 to toggle during the Embedded Erase Algorithm.
If the device is in the erase suspend-read mode, suc-
cessive reads from the erase-suspended sector will
cause DQ2 to toggle. When the device is in the erase
suspend-program mode, successive reads from the
byte address of the non-erase suspended sector will
DQ5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count).
Under these conditions, DQ5 will produce a ‘1’ indicat-
ing that the program or erase cycle was not success-
fully completed. Write operation status and reset
command are the only operating functions under this
Am29LV800T/Am29LV800B
19
P R E L I M I N A R Y
indicate a logic ‘1’ at the DQ2 bit. Note that a sector
Embedded Algorithms are either in progress or have
been completed. If the output is low, the device is busy
with either a program or erase operation. If the output
is high, the device is ready to accept any read/write or
erase operation. When the RY/BY pin is low, the de-
vice will not accept any additional program or erase
commands with the exception of the Erase Suspend
command. If the Am29LV800 is placed in an Erase
Suspend mode, the RY/BY output will be high. For
programming, the RY/BY is valid (RY/BY=0) after the
rising edge of the fourth WE pulse in the four write
pulse sequence. For chip erase, the RY/BY is valid
after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the RY/BY is
also valid after the rising edge of the sixth WE pulse.
which is selected for erase is not available for read in
Erase Suspend mode. Other sectors which are not se-
lected for Erase can be read in Erase Suspend.
DQ6 is different from DQ2 in that DQ6 toggles only
when the standard program or erase, or erase
suspend-program operation is in progress.
If the DQ5 failure condition is observed while in Sector
Erase mode (that is, exceeded timing limits), the DQ2
toggle bit can give extra information. In this case, the
normal function of DQ2 is modified. If DQ5 is at logic
‘1’, then DQ2 will toggle with consecutive reads only at
the sector address that caused the failure condition.
DQ2 will toggle at the sector address where the failure
occurred and will not toggle at other sector addresses.
Since the RY/BY pin is an open-drain output, several
RY/BY pins can be tied together in parallel with a
RY/BY: Ready/Busy Pin
pull-up resistor to V
.
CC
The Am29LV800 provides a RY/BY open-drain output
pin as a way to indicate to the host system that the
Table 8. Toggle Bit Status
Mode
DQ7
DQ6
Toggles
Toggles
1
DQ2
1
Program
Erase
DQ7
0
Toggles
Toggles
1 (Note 2)
Erase-Suspend Read (Note 1) (Erase-Suspended Sector)
Erase Suspend Program
1
DQ7 (Note 2)
Toggles
Notes:
1. These status flags apply when outputs are read from a sector that has been erase suspended.
2. These status flags apply when outputs are read from the byte/word addresses of the non-erase suspended sector.
CE
LAST_BUS_CYCLE
WE
RY/BY
tBUSY
20478D-9
Figure 2. RY/BY Timing Diagram
20
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Asserting RESET during a program or erase operation
RESET: Hardware Reset Pin
leaves erroneous data stored in the address locations
being operated on at the time of device reset.These lo-
cations need updating after the reset operation is com-
plete. See Figure 4 for timing specifications.
The RESET pin is an active low signal. A logic ‘0’ on this
pin will force the device out of any mode that is currently
executing back to the reset state. This allows a system
reset to take effect immediately without having to wait for
the device to finish a long execution cycle.To avoid a po-
tential bus contention during a system reset, the device
is isolated from the data I/O bus by tri-stating the data
output pins for the duration of the RESET pulse.
The device enters I
standby mode (200 nA) when
CC4
V
± 0.3V is applied to the RESET pin.The device can
SS
enter this mode at any time, regardless of the logical
condition of the CE pin. Furthermore, entering I
CC4
during a program or erase operation leaves erroneous
data in the address locations being operated on at the
time of the RESET pulse. These locations need updat-
ing after the device resumes standard operations. After
the RESET pin goes high, a minimum latency period of
50 ns must occur before a valid read can take place.
If RESET is asserted during a program or erase oper-
ation, the RY/BY pin will remain low until the reset op-
eration is internally complete.This will require between
1 µs and 20 µs. Hence the RY/BY pin can be used to
signal that the reset operation is complete. Otherwise,
allow for the maximum reset time of 20 µs. If RESET is
asserted when a program or erase operation is not ex-
ecuting (RY/BY pin is high), the reset operation will be
complete within 500 ns.
tRL
RESET
RY/BY
20 µs max
20478D-10
Figure 3. Device Reset During a Program or Erase Operation
tRL
RESET
RY/BY
0 V
20478D-11
Figure 4. Device Reset During Read Mode
Am29LV800T/Am29LV800B
21
P R E L I M I N A R Y
If the BYTE pin is set at logic ‘0’, the device is in byte
Word/Byte Configuration
configuration, and only data I/O pins DQ0–7 are active
and controlled by CE and OE. The data I/O pins DQ8–
14 are tri-stated. In byte mode, the DQ15 pin is used as
an input for the LSB (A-1) address function (see Figure 6).
The BYTE pin of the Am29LV800 is used to set device
data I/O pins in the byte or word configuration. If the
BYTE pin is set at logic ‘1’, the device is in word config-
uration, DQ0–15 are active and controlled by CE and
OE (see Figure 5).
CE
OE
BYTE
tELFH
DQ8–DQ14
DQ15/A-1
DQ8–DQ14
DQ8–DQ14
tFHQV
A-1
DQ15
20478D-12
Figure 5. Timing Diagram for Word Mode Configuration
CE
OE
BYTE
tELFL
DQ8–DQ14
DQ15/A-1
DQ8–DQ14
DQ8–DQ14
A-1
DQ15
tFLQZ
20478D-13
Figure 6. Timing Diagram for Byte Mode Configuration
22
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
be ignored until the V level is greater than V
. It is
LKO
Data Protection
CC
the user’s responsibility to ensure that the control levels
The Am29LV800 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tions. During power-up, the device automatically resets
the internal state machine to the read mode. Also, with
its control register architecture, alteration of the mem-
ory contents only occurs after successful completion of
the command sequences.
are logically correct when V is above V
(unless
CC
LKO
the RESET pin is asserted).
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or
WE will not change the command registers.
Logical Inhibit
The Am29LV800 incorporates several features to pre-
Writing is inhibited by holding any one of OE = V , CE
IL
vent inadvertent write cycles resulting from V
= V , or WE = V .To initiate a write, CE and WE must
CC
IH
IH
power-up and power-down transitions or system noise.
be logical zero while OE is a logical one.
Low V Write Inhibit
Power-Up Write Inhibit
CC
To avoid initiation of a write cycle during V power-up
CC
Power up of the device with WE = CE = V and OE =
IL
and power-down, a write cycle is locked out for V
CC
V
will not accept commands on the rising edge of WE.
IH
less than V
(lock-out voltage). If V
< V
, the
LKO
CC
LKO
The internal state machine is automatically reset to
read mode on power up.
command register is disabled and all internal program/
erase circuits are disabled. Under this condition, the
device will reset to read mode. Subsequent writes will
Am29LV800T/Am29LV800B
23
P R E L I M I N A R Y
EMBEDDED ALGORITHMS
START
Write Program Cmd Sequence
Data Poll Device
No
Verify Byte?
Yes
No
Increment Address
Last Address?
Yes
Programming Completed
20478D-14
Figure 7. Embedded Program Algorithm
Embedded Program Algorithm
Bus Operation
Standby*
Write
Command Sequence
Comments
Program
Valid Address/Data
Read
DATA Polling to Verify Programming
Compare Data Output to Data Expected
Standby*
* Device is either powered-down, erase inhibit, or program inhibit.
24
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
START
Write Erase Cmd Sequence
Data Poll from Device
No
Data = FFH?
Yes
Erasure Completed
20478D-15
Figure 8. Embedded Erase Algorithm
Embedded Erase Algorithm
Bus Operation
Standby
Write
Command Sequence
Comments
Erase
Read
DATA Polling to Verify Erasure
Compare Output to FFh
Standby
Am29LV800T/Am29LV800B
25
P R E L I M I N A R Y
Data Polling Algorithm
START
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Yes
DQ7 = Data?
No
FAIL
PASS
20478D-16
Figure 9. Data Polling Algorithm
26
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Toggle Bit Algorithm
START
No
DQ6 = Toggle?
Yes
No
DQ5 = 1?
Yes
No
DQ6 = Toggle?
Yes
FAIL
PASS
20478D-17
Figure 10. Toggle Bit Algorithm
20 ns 20 ns
+0.8 V
–0.5 V
–2.0 V
20 ns
20478D-18
Figure 11. Maximum Negative Overshoot Waveform
20 ns
V
+ 2.0 V
CC
V
+ 0.5 V
CC
2.0 V
20 ns
20 ns
20478D-19
Figure 12. Maximum Positive Overshoot Waveform
Am29LV800T/Am29LV800B
27
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGES
Storage Temperature
Commercial (C) Devices
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature (T ). . . . . . . . . . . . 0˚C to +70˚C
A
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –55°C to +125°C
Industrial (I) Devices
Ambient Temperature (T ). . . . . . . . . . –40˚C to +85˚C
A
Voltage with Respect to Ground
All pins except A9 (Note 1). . . . . –0.5 V to V +4.5 V
Extended (E) Devices
CC
Ambient Temperature (T ). . . . . . . . . –55˚C to +125˚C
A
V
(Note 1). . . . . . . . . . . . . . . . . . . . –0.5 V to +5.5 V
CC
V
V
V
Supply Voltages
CC
CC
CC
RESET, OE, A9 (Note 2) . . . . . . . . . –0.5 V to +13.0 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
for Am29LV800T/B-90R. . . . . . . . +3.0 V to 3.6 V
for Am29LV800T/B-100,
Notes:
-120, -150 . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, inputs may overshootV to –2.0V for
periods of up to 20 ns. Maximum DC voltage on input and
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
SS
I/O pins is V + 0.5 V. During voltage transitions, input
CC
and I/O pins may overshoot to V + 2.0 V for periods up
CC
to 20ns.
2. Minimum DC input voltage on A9 pin is –0.5 V. During
voltage transitions, A9 may overshoot V to –2.0 V for
SS
periods of up to 20 ns. Maximum DC input voltage on A9
is +13.5 V which may overshoot to 14.0 V for periods up
to 20 ns.
3. No more than one output shorted at a time. Duration of
the short circuit should not be greater than one second.
Stresses above those listed under “Absolute Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these
or any other conditions above those indicated in the opera-
tional sections of this specification is not implied. Exposure of
the device to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
28
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
= V to V
Min
Max
±1.0
35
Unit
µA
V
V
,
CC
IN
SS
I
Input Load Current
LI
= V
CC
CC max
I
A9 Input Load Current
Output Leakage Current
V
= V
; A9 = 13.0 V
µA
LIT
CC
CC max
V
V
= V to V
,
OUT
SS
CC
I
±1.0
µA
LO
= V
CC
CC max
5 MHz
1 MHz
5 MHz
1 MHz
16
4
CE = V OE
Byte Mode
V
IH,
IL,
=
=
I
V
Active Current (Note 1)
mA
CC1
CC
16
4
CE = V OE
V
V
IL,
IH,
Word Mode
I
I
V
V
Active Current (Notes 2 and 4)
Standby Current
CE = V OE
30
mA
CC2
CC
IL,
=
IH
V
= V
;
CC
CC max
5
5
µA
CC3
CC
CE, RESET = V ±0.3 V
CC
V
= V
;
CC
CC max
I
I
V
Reset Current
µA
µA
CC4
CC
RESET = V ± 0.3 V
SS
V
V
= V ± 0.3 V;
CC
IH
IL
Automatic Sleep Mode (Note 3)
5
CC5
= V ± 0.3 V
SS
V
Input Low Voltage
Input High Voltage
–0.5
0.8
V
V
IL
V
0.7 x V
V
+ 0.3
IH
CC
CC
Voltage for Autoselect and Temporary
Sector Unprotect
V
V
= 3.3 V
11.5
12.5
0.45
V
ID
CC
V
Output Low Voltage
I
= 4.0 mA, V = V
CC min
V
V
OL
OL
CC
V
I
I
= –2.0 mA, V = V
0.85 V
OH1
OH
OH
CC
CC min
CC min
CC
Output High Voltage
V
= –100 µA, V = V
V
–0.4
OH2
CC
CC
V
Low V Lock-Out Voltage (Note 4)
2.3
2.5
V
LKO
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 5 MHz). The
CC
frequency component typically is less than 2 mA/MHz, with OEat V
.
IH
2. I active while Embedded Erase or Embedded Program is in progress.
CC
3. Automatic sleep mode enables the low power mode when addresses remain stable for 200 ns. Typical sleep mode current is
200 nA.
4. Not 100% tested.
Am29LV800T/Am29LV800B
29
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
25
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
20478D-20
Figure 13A.
I
Current vs.Time
CC
15
10
5
0
1
2
3
Frequency in MHz
4
5
Note: T = 25 °C
20478D-21
Figure 13B.
I
vs. Frequency
CC
30
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
DC CHARACTERISTICS (Continued)
TTL/NMOS Compatible
Parameter
Symbol
Parameter Description
Input Load Current
A9 Input Load Current
Output Leakage Current
Test Description
= V to V , V = V
CC MAX
Min
Max
±1.0
35
Unit
µA
I
V
IN
LI
SS
CC CC
I
V
= V
, A9 = V
ID
µA
LIT
CC
CC MAX
I
V
= V to V , V = V
CC MAX
±1.0
30
µA
LO
OUT
SS
CC CC
Byte
mA
I
V
Active Read Current (Note 1)
CE = V , OE = V
IL
CC1
CC
IH
Word
35
I
V
V
V
Active Write Current (Note 2)
Standby Current
CE = V , OE = V
35
mA
µA
µA
µA
V
CC
CC
CC
IL
IH
I
I
I
V
= V
= V
, CE = V , RESET = V
250
250
250
0.8
CC3
CC4
CC5
CC
CC MAX
, CE = V , RESET = V
CC MAX IH
IH
IH
Standby Current During Reset
V
CC
IL
Automatic Sleep Mode (Note 3)
Input Low Level
CE = V , OE = V
IL IH
V
–0.5
2.0
IL
IH
ID
V
+
CC
0.5
V
V
Input High Level
V
Voltage for Autoselect and Sector Protect
Output Low Level
11.5
12.5
0.45
V
V
V
V
V
I
= 4.0 mA, V = V
OL
OL CC CC MIN
V
Output High Level
I
= -2.0 mA, V = V
CC MIN
2.4
2.3
OH
OH
CC
V
Low V Lock-Out Voltage (Note 4)
2.5
LKO
CC
V
= 2.7 V to 3.6 V
CC
Notes:
1. The I current listed includes both the DC operating current and the frequency dependent component (at 5 MHz).
CC
The frequency component typically is less than 2 mA/MHz, with OEat V
.
IH
2. I active while Embedded Algorithm (program or erase) is in progress.
CC
3. Automatic sleep mode enables the low power mode when addresses remain stable for 300 ns. Typical sleep mode current is
80 µA.
4. Not 100% tested.
Am29LV800T/Am29LV800B
31
P R E L I M I N A R Y
AC CHARACTERISTICS
Read-Only Operations Characteristics
Parameter Symbols
Speed Option (Note 1)
JEDEC Standard Description
Test Setup
Min
-90R -100
-120
-150
Unit
t
t
Read Cycle Time (Note 3)
Address to Output Delay
90
90
100
100
120
150
ns
AVAV
RC
CE = V
IL
t
t
Max
120
150
ns
AVQV
ACC
OE = V
IL
t
t
t
t
t
t
t
t
Chip Enable to Output Delay
OE = V
Max
Max
Max
Max
90
40
30
30
100
40
120
50
150
55
ns
ns
ns
ns
ELQV
GLQV
EHQZ
GHQZ
CE
OE
DF
DF
IL
Output Enable to Output Delay
Chip Enable to Output High Z (Notes 2, 3)
Output Enable to Output High Z (Notes 2, 3)
30
30
40
30
30
40
Output Hold Time From Addresses, CE or
OE, Whichever Occurs First (Note 3)
t
t
t
Min
0
0
0
0
ns
AXQX
OH
RESET Pin Low to Read Mode (Note 3)
Max
20
20
20
20
µs
Ready
Notes:
1. Test Conditions
Input Rise and Fall Times: 5 ns
Input Pulse Levels: 0.0 V to 3.0 V
Timing Measurement Reference Level:
Input: 1.5 V
Output: 1.5 V
2. Output Driver Disable Time
3. Not 100% tested.
3.3 V
IN3064
or Equivalent
2.7 kΩ
Device
Under
Test
C
L
6.2 kΩ
IN3064 or Equivalent
IN3064 or Equivalent
IN3064 or Equivalent
Notes:
C = 30 pF for 90 and 100 ns
L
C = 100 pF for 120 and 150 ns
L
20478D-15
Figure 14. Test Conditions
32
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
AC CHARACTERISTICS
Write (Erase/Program) Operations
Parameter Symbols
JEDEC
Standard Description
-90R
90
0
-100
100
0
-120
120
0
-150
150
0
Unit
ns
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time (Note 2)
Min
Min
Min
Min
Min
Min
Min
AVAV
WC
AS
Address Setup Time
Address Hold Time
ns
AVWL
WLAX
DVWH
WHDX
50
50
0
50
50
0
50
50
0
65
65
0
ns
AH
Data Setup Time
ns
DS
Data Hold Time
ns
DH
OES
Output Enable Setup Time (Note 2)
0
0
0
0
ns
Read (Note 2)
Output Enable
Hold TIme
0
0
0
0
ns
t
OEH
Toggle and Data Polling
(Note 2)
Min
Min
10
0
10
0
10
0
10
0
ns
ns
Read Recovery TIme Before Write
(OE High to WE Low)
t
t
GHWL
GHWL
t
t
t
t
t
t
t
t
CE Setup TIme
Min
Min
Min
Min
Typ
Typ
Typ
Min
Min
Min
Min
Min
Max
Min
Min
Min
Min
Max
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ELWL
CS
CE Hold TIme
WHEH
WLWH
WHDL
CH
Write Pulse Width
Write Pulse Width High
50
30
9
50
30
9
50
30
9
65
35
9
WP
WPH
Byte
t
t
Programming Operation
µs
WHWH1
WHWH2
WHWH1
Word
11
1
11
1
11
1
11
1
t
t
t
t
t
t
t
t
t
t
t
t
t
Sector Erase Operation (Note 1)
sec
µs
ns
ns
µs
ns
ns
ns
ns
ns
ns
µs
WHWH2
V
Setup TIme
50
0
50
0
50
0
50
0
VCS
CC
Write Recovery Time from RY/BY
RESET High Time Before Read
RESET To Power Down Time
RB
50
20
90
5
50
20
90
5
50
20
90
5
50
20
90
5
RH
RPD
BUSY
Program/Erase Valid to RY/BY Delay
CE to BYTE Switching Low or High
t
ELFL/ ELFH
BYTE Switching Low to Output HIGH Z
BYTE Switching High to Output Active
30
30
500
500
20
30
30
500
500
20
40
40
500
500
20
40
40
500
500
20
FLQZ
FHQV
VIDR
RP
Rise TIme to V
ID
RESET Pulse Width
RESET Low to RY/BY High
RRB
RESET Setup Time for Temporary Sector
Unprotect
t
Min
4
4
4
4
µs
RSP
Notes:
1. The duration of the program or erase operation is variable and is calculated in the internal algorithms.
2. Note 100% tested.
Am29LV800T/Am29LV800B
33
P R E L I M I N A R Y
KEY TO SWITCHING WAVEFORMS
WAVEFORM
INPUTS
OUTPUTS
Must be
Steady
Will be
Steady
May
Change
from H to L
Will be
Changing
from H to L
May
Change
from L to H
Will be
Changing
from L to H
Don’t Care,
Any Change
Permitted
Changing,
State
Unknown
Does Not
Apply
Center
Line is High-
Impedance
“Off” State
KS000010-PAL
SWITCHING WAVEFORMS
3.0 V
1.5 V
1.5 V
Input
Measurement Level
Output
0.0 V
20478D-16
Figure 15. Input Waveforms and Measurement Levels
34
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
SWITCHING WAVEFORMS
tRC
Addresses Stable
tACC
Addresses
CE
tOE
tDF
OE
tOEH
tCE
WE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
20478D-17
Figure 16. AC Waveforms for Read Operations
tWC
tAS
Addresses
tAH
tRC
CE
OE
tGHWL
tWP
tWHWH1_or_2
WE
tCS
tDF
tWPH
tOE
tDH
DIN
DQ7 DOUT
DATA
VCC
tDS
tOH
tCE
Notes:
1. D is the data input to the device.
IN
2. DQ7 is the output of the complement of the data written to the device.
3. D is the output of the data written to the device.
OUT
20478D-18
Figure 17. Program Operations Timings
Am29LV800T/Am29LV800B
35
P R E L I M I N A R Y
SWITCHING WAVEFORMS
tWC
tAS
555H for chip erase
Addresses
555h
2AAh
555h
555h
2AAh
SA
tAH
CE
OE
WE
tGHWL
tWP
tCS
tDS
tWPH
10h for Chip Erase
tDH
DATA
VCC
80h
AAh
55h
30h
AAh
55h
Notes:
1. SA is the sector address for Sector Erase. Addresses = Don’t Care for Chip Erase.
2. These waveforms are for the x16 mode.
20478D-19
Figure 18. AC Waveforms for Chip/Sector Erase Operations
tCH
CE
OE
tDF
tOE
tOEH
WE
tCE
tOH
*
HIGH Z
HIGH Z
DQ7=Valid Data
DQ7
DQ7
tWHWH1_or_2
DQ0-DQ6=Invalid Data
DQ0-DQ6
DQ0-DQ6 Valid Data
Note:
DQ7 = Valid Data (The device has completed the embedded operation.)
20478D-20
Figure 19. AC Waveforms for Data Polling During Embedded Algorithm Operations
36
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
WE
OE
tOEH
DQ6/DQ2
tDH
tOE
Note:
DQ6 stops toggling (The device has completed the embedded operation.)
20478D-21
Figure 20. Toggle Bit Timings (During Embedded Algorithm Operations)
CE
The rising edge of the last WE signal
WE
Entire programming
or erase operations
RY/BY
t
BUSY
Note:
DQ7 = Valid Data (The device has completed the embedded operation.)
20478D-22
Figure 21. RY/BY Timing Diagram (During Program/Erase Operations)
RESET
t
RP
t
Ready
20478D-23
Figure 22. RESET Timing Diagram
Am29LV800T/Am29LV800B
37
P R E L I M I N A R Y
SWITCHING WAVEFORMS
CE
OE
BYTE
t
ELFL
t
ELFH
Data Output
(DQ0–DQ14)
Data Output
(DQ0–DQ7)
DQ0–DQ14
DQ15/A-1
Address
Input
DQ15
Output
t
FLQZ
20478D-24
Figure 23. BYTE Timing Diagram for Read Operation
CE
The falling edge of the last WE signal
WE
BYTE
t
SET
t
(t
)
(t
)
HOLD AH
AS
20478D-25
Figure 24. BYTE Timing Diagram for Write Operations
38
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Start
RESET = V
(Note 1)
ID
Perform Erase or
Program Operations
RESET = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
Notes:
1. All protected sectors unprotected.
All previously protected sectors are protected once again.
20478D-26
Figure 25. Temporary Sector Unprotect Algorithm
t
VIDR
12 V
RESET
0 V or 3 V
0 V or 3 V
CE
WE
t
RSP
Program or Erase Command Sequence
20478D-27
Figure 26. Temporary Sector Unprotect Timing Diagram
Am29LV800T/Am29LV800B
39
P R E L I M I N A R Y
AC CHARACTERISTICS
Write (Erase/Program) Operations
Alternate CE Controlled Writes
Parameter Symbols
JEDEC
Standard Description
-90R
90
0
-100
100
0
-120
120
0
-150
150
0
Unit
ns
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time (Note 2)
Min
Min
Min
Min
Min
Min
Min
AVAV
AVWL
ELAX
DVEH
EHDX
WC
AS
Address Setup Time
Address Hold Time
Data Setup Time
ns
50
50
0
50
50
0
50
50
0
65
65
0
ns
AH
ns
DS
Data Hold Time
ns
DH
OES
Output Enable Setup Time
0
0
0
0
ns
Read (Note 2)
0
0
0
0
ns
Output Enable
Hold TIme
t
OEH
Toggle and Data Polling
(Note 2)
Min
Min
10
0
10
0
10
0
10
0
ns
ns
Read Recovery TIme Before Write
(OE High to WE Low)
t
t
GHEL
GHEL
t
t
t
t
t
t
t
t
WE Setup TIme
WE Hold TIme
Min
Min
Min
Min
Typ
Typ
Typ
0
0
0
0
0
0
0
0
ns
ns
ns
ns
WLEL
EHWH
ELEH
EHEL
WS
WH
CP
CE Pulse Width
CE Pulse Width High
50
30
9
50
30
9
50
30
9
65
35
9
CPH
Byte
t
t
t
Programming Operation
µs
WHWH1
WHWH2
WHWH1
Word
11
1
11
1
11
1
11
1
t
t
Sector Erase Operation (Note 1)
sec
ns
WHWH2
BYTE Switching Low to Output HIGH Z
(Note 2)
Min
30
30
30
30
FLQZ
Notes:
1. The duration of the program or erase operation is variable and is calculated in the internal algorithms.
2. Does not include the preprogramming time.
3. Not 100% tested.
40
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
SWITCHING WAVEFORMS
Data Polling
tWC
tAS
PA
ADDRESSES
555h
PA
tAH
WE
OE
tGHWL
tCP
tWHWH1_or_2
CE
tWS
tCPH
tDS
tDH
DQ7
DOUT
A0h
PD
Data
VCC
tVCS
20478D-33
Notes:
1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the complement of the data written to the device.
4. D
is the data written to the device.
OUT
Figure indicates last two bus cycles of four bus cycle sequence
Figure 27. Alternate CE Controlled Write Operation Timings
Am29LV800T/Am29LV800B
41
P R E L I M I N A R Y
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 2)
Max (Note 3)
Unit
s
Comments
Sector Erase Time
Chip Erase Time
1
19
9
15
Excludes 00h programming
prior to erasure (Note 4)
s
Byte Programming Time
Word Programming Time
300
360
27
µs
µs
s
11
9
Excludes system level
overhead (Note 5)
Byte Mode
Word Mode
Chip Programming Time
5.8
17
s
Minimum 100,000 cycles
guaranteed
Erase/Program Endurance
1,000,000
cycles
Notes:
1. The typical program and erase times are considerably less than the maximum times since most words/bytes program or erase
significantly faster than the worst case word/byte.The device enters the failure mode (DQ5=“1”) only after the maximum times
given are exceeded. See the section on DQ5 for further information.
2. Except for erase and program endurance, the typical program and erase times assume the following conditions: 25°C, 3.0 V
V
, 100,000 cycles. Additionally, programming typicals assume checkerboard pattern.
CC
3. Under worst case conditions of 90˚C, V = 2.7 V, 100,000 cycles.
CC
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 6
for further information on command definitions.
LATCHUP CHARACTERISTICS
Min
Max
Input Voltage with respect to V on all pins except I/O pins (Including A9 and OE)
–1.0 V
13.0 V
SS
Input Voltage with respect to V on all I/O pins
–1.0 V
V
+ 1.0 V
SS
CC
Current
–100 mA
+100 mA
Includes all pins except V . Test conditions: V = 3.0 V, one pin at a time.
CC
CC
PIN CAPACITANCE, 48-PIN TSOP
Parameter Symbol
Parameter Description
Test Setup
= 0
Typ
Max
Unit
pF
C
Input Capacitance
Output Capacitance
Control Pin Capacitance
V
6
8.5
8
7.5
12
10
IN
IN
C
V
= 0
pF
OUT
OUT
C
V
= 0
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
42
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
PIN CAPACITANCE, 44-PIN PSOP
Parameter Symbol
Parameter Description
Input Capacitance
Test Setup
= 0
Typ
6
Max
7.5
12
Unit
pF
C
V
IN
IN
C
Output Capacitance
V
= 0
8.5
8
pF
OUT
OUT
C
Control Pin Capacitance
V
= 0
10
pF
IN2
IN
Notes:
1. Sampled, not 100% tested.
2. Test conditions T = 25°C, f = 1.0 MHz.
A
DATA RETENTION
Parameter
Test Conditions
150°C
Min
10
Unit
Minimum Pattern Data Retention Time
Years
Years
125°C
20
Am29LV800T/Am29LV800B
43
P R E L I M I N A R Y
PHYSICAL DIMENSIONS*
TS 048
48-Pin Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
16-038-TS48-2
TS 048
DA101
0.08
0.20
0.10
0.21
1.20
MAX
8-8-94 ae
0˚
5˚
0.25MM (0.0098") BSC
0.50
0.70
*
For reference only, not drawn to scale. BSC is an ANSI standard for Basic Space Centering.
44
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
TSR048
48-Pin Reverse Standard Thin Small Outline Package (measured in millimeters)
0.95
1.05
Pin 1 I.D.
1
48
11.90
12.10
0.50 BSC
24
25
0.05
0.15
18.30
18.50
19.80
20.20
SEATING PLANE
16-038-TS48
TSR048
DA104
0.08
0.20
8-8-94 ae
1.20
MAX
0.10
0.21
0˚
5˚
0.25MM (0.0098") BSC
0.50
0.70
Am29LV800T/Am29LV800B
45
P R E L I M I N A R Y
PHYSICAL DIMENSIONS (continued)
SO 044
44-Pin Thin Small Outline Package (measured in millimeters)
44
23
13.10
13.50
15.70
16.30
1
22
1.27 NOM.
TOP VIEW
28.00
28.40
0.10
0.21
2.17
2.45
2.80
MAX.
0˚
8˚
SEATING
PLANE
0.60
1.00
0.35
0.50
0.10
0.35
END VIEW
SIDE VIEW
16-038-SO44-2
SO 044
DA82
11-9-95 lv
46
Am29LV800T/Am29LV800B
P R E L I M I N A R Y
Table 6, Command Definitions:
REVISION SUMMARY FOR AM29LV800
Grouped address designators PA, PD, RA, RD, and SA
under the legend heading. Modified SA definition to ac-
commodate the sector protect verify command. Since
unlock addresses only require address bits A0–A10 to
be valid, the number of hexadecimal digits in the unlock
addresses were changed from four to three. The re-
maining upper address bits are don’t care. Removed
“H” designation from hexadecimal values in table and
replaced with new Note 1. Revised Notes 5 and 6 to in-
dicate when commands are valid; are now Notes 4 and
5. Expanded autoselect section to show each function
separately: manufacturer ID, device ID, and sector pro-
tect verify. Added Note 3 to explain sector protect
codes. Deleted Note 7. Added Note 6 to indicate which
addresses are don’t care. Corrected unlock and com-
mand addresses for byte mode from “2AA” to “AAA”.
Corrected byte-mode read cycle (fourth cycle) ad-
dresses from 01h to 02h for device ID, and from SAX02
to SAX04 for sector protect verification.
Distinctive Characteristics:
Rearranged bullets. Renamed “Extended voltage
range...” bullet to “Single power supply operation.”
Under “Single power supply operation” and “High per-
formance” bullets, defined standard and extended volt-
age ranges and added 90 ns speed option. Combined
“Advanced power management” and “Low current con-
sumption” bullets into new “Ultra low power consump-
tion” bullet. Under that bullet, revised the typical
standby and automatic sleep mode current specifica-
tions from 1 µA to 200 nA; revised read current specifi-
cation from 10 mA to 2 mA/MHz. Combined “Sector
protection” and “Flexible sector architecture” bullets.
Under flexible sector architecture bullet, added tempo-
rary sector unprotect feature description. Combined
Embedded Program and Embedded Erase bullets
under new “Embedded Algorithms” bullet; removed ™
designations. Clarified descriptions of sector protec-
tion, erase suspend/resume, hardware reset pin,
ready/busy pin, and data polling and toggle bits.
RESET: Hardware Reset Pin:
Fourth paragraph: Revised standby mode specification
to 200 nA.
General Description:
Added text on -90R speed option and voltage range to
the second paragraph.
Figure 6,Timing Diagram for Byte Mode
Configuration:
Product Selector Guide:
Moved end of t
period from within the A-1 data flow
FLQZ
Added -90R voltage range and speed option.
to the start of A-1 data flow.
Connection Diagrams
Operating Ranges:
Corrected pinouts on pins 13 and 14 for the standard
TSOP drawing. (Revision C)
V
Supply Voltages: Expanded into two voltage
CC
ranges; added -90R speed option.
Corrected pinouts on pins 33 and 32 for the reverse
TSOP drawing. (Revision C)
DC Characteristics:
CMOS Compatible: Changed I
from 30 mA maxi-
CC1
Corrected pinouts for pins 13, 14, 17, and 18 on stan-
dard TSOP package. (Revision D)
mum at 6 MHz to 16 mA maximum at 5 MHz and 4 mA
maximum at 1 MHz. Changed I from 35 mA to 30
CC2
mA maximum. In Note 1, changed 6 MHz to 5 MHz. In
Note 3, changed address stable time from 300 ns to
200 ns; changed typical sleep mode current from 1 µA
to 200 nA.
Pin Configuration:
Added new voltage range to V specification.
CC
Ordering Information, Standard Products:
The -90R speed option is now listed in the example.
Revised “Speed Option” section to indicate both volt-
age ranges.
Figure 13A, I Current vs.Time, and Figure 13B,
CC
I
vs. Frequency:
CC
Figure 8A illustrates current draw during the Automatic
Sleep Mode after the addresses are stable. Figure 8B
shows how frequency affects the current draw curves
for both voltage ranges.
Valid Combinations: Added -90R speed option and
voltage range.
Automatic Sleep Mode:
AC Characteristics:
Revised addresses stable time to 200 ns and typical
current draw to 200 nA.
Read Only Operations Characteristics: Added -90R
column.
Autoselect:
Test Conditions, Figure 13:
Fourth paragraph, last sentence: Corrected to “...DQ9
and DQ13 are equal to ‘1’...”
Added 90 ns speed to C note.
L
AC Characteristics:
Table 4, Sector Address Table:
Write/Erase/Program Operations: Added the -90R col-
Corrected SA12, x8 starting address from D0000 to
C0000.
umn. Corrected t
to t
.
WAX
WLAX
Am29LV800T/Am29LV800B
47
P R E L I M I N A R Y
Figure 17, AC Waveforms for Chip/Sector Erase
Erase and Programming Performance:
Operations:
Added typical chip erase specification. Deleted col-
umn for minimum specifications. Created separate
chip program specifications for word and byte modes.
Renamed erase/program cycles specification to
erase/program endurance. Moved minimum 100,000
cycle endurance to comments section. Revised Note
1 to include write endurance, is now Note 2. Consoli-
dated and moved Note 1 and Note 3 references in
table to table head. Combined Note 2 and Note 5 into
new Note 1, which applies to the entire table; revised
to indicate that DQ5=1 after the maximum times.
Comments for program and erase now straddle pa-
rameter rows. Separated the two sentences in Note 4
into new Notes 4 and 5; added corresponding note
references to comment section.
Added” 555 chip erase” to last cycle in sequence.
Changed addresses to three hexadecimal digits to
match command definitions (Table 6).
Figure 18, AC Waveforms for Data Polling During
Embedded Algorithm Operations:
Split data signal into DQ0–DQ6 and DQ7 signals.
Figure 25,Temporary Sector Unprotect Timing
Diagram:
Corrected callout and waveform to show that t
plies whether RESET rises from either 0 V or 3 V.
ap-
VIDR
AC Characteristics:
Alternate CE Controlled Writes:Added the -90R column.
Figure 26, Alternate CE Controlled Write Operation
Timings:
Changed 5555H to 555H match command definitions
(Table 6).
Trademarks
Copyright © 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof and ExpressFlash are trademarks of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
48
Am29LV800T/Am29LV800B
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