CXD1856R [SONY]
MPEG1 Decoder; MPEG1解码器
| 型号： | CXD1856R |
| 厂家： | 
SONY CORPORATION |
| 描述： | MPEG1 Decoder |
| 文件： | 总31页 (文件大小：407K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD1856Q/R
MPEG1 Decoder
Description
120 pin QFP (Plastic)
120 pin LQFP (Plastic)
The CXD1856Q/R is a single-chip MPEG1 decoder
with a built-in CD-ROM decoder which allows
decoding of MPEG1 system, video and audio layers.
A built-in CD-ROM decoder enables direct connection
with a CD-DSP. Combining this chip with a control
microcomputer and 4-Mbit DRAM, etc. allows
configuration of a MPEG1 decoding system for video
CD players, etc.
Features
• Supply voltage: 3.3 ± 0.3V
Structure
Silicon gate CMOS IC
• Input and output voltages: LVTTL compatible
• 5V can be applied as the input voltage (excluding
some pins)
• Allows decoding of MPEG1 system, video and
audio layers
Applications
Video CD players, MPEG1 decoder boards, etc.
• Built-in CD-ROM decoder allows direct connection
with a CD-DSP
• CD-ROM decoded output can be transferred to
and stored in an external DRAM
• RGB and YCbCr video data output allowed
• Built-in video sync generator
• Audio data output can support various DAC
• Supports various special playback modes
• Video CD PAL high resolution still picture can be
decoded with a single 4-Mbit DRAM
• 8-bit parallel and 4-line serial host interfaces
• CD-DA through operation allowed
Block Diagram
MPEG
System
Decoder
MPEG
Audio
Audio
I/F
CD-DSP
I/F
CD-ROM
Decoder
Decoder
MPEG
Video
Decoder
To each circuit block
Video Postprocessor
Host
interface
DRAM
Controler
Video
I/F
&
Sync Generator
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E97815-PS
CXD1856Q/R
1. Pin Configuration
100
120 119 118 117 116 115 114 113 112 111
109 108
107
106 105 104 103 102 101
99 98
96 95 94 93 92 91
97
110
VSS
XTL0O
XTL0I
VDD
1
2
3
4
5
6
7
8
9
90 VDD
89 DCLK
88 B/Cb7
87 B/Cb6
86 B/Cb5
85 B/Cb4
HA2
HA3
84
B/Cb3
HD0
HD1
83 B/Cb2
82
81
B/Cb1
B/Cb0
HD2
HD3 10
HD4 11
HD5 12
80 G/Y7
79 G/Y6
78 G/Y5
77 G/Y4
76 G/Y3
75 VSS
13
HD6
VDD 14
VSS 15
HD7 16
MA3 17
MA4 18
74 VDD
73 G/Y2
19
72
G/Y1
MA2
MA5 20
MA1 21
VSS 22
71 G/Y0
70 R/Cr7
69 R/Cr6
68 R/Cr5
67 R/Cr4
66 R/Cr3
MA6 23
MA0 24
CKEY 25
DTVLD 26
VSS 27
65
R/Cr2
64 R/Cr1
63 R/Cr0
62 XVOE
61 VSS
VSS 28
VSS 29
VSS 30
31
32 33
34
35
36 37 38 39 40
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
– 2 –
CXD1856Q/R
2. Pin Description
Pin No.
Symbol
I/O
Description
VDD
+3.3V power supply
Connect to ground.
VSS
2
3
XTL0O
O
I
Video decoder master clock. Input the clock to XTL0I or connect an
oscillator between XTL0I and XTL0O. The recommended frequencies are
27MHz, 28.6363MHz (NTSC 8fsc) and 35.4686MHz (PAL 8fsc).
XTL0I
When the host interface operates in parallel mode, these pins are the
register address inputs. In serial mode, HA0 is the serial data input, and
HA1 to HA3 should be fixed to low level.
5, 6, 119,
120
HA0 to HA3
I
When the host interface operates in parallel mode, these pins are the
register data I/Os. In serial mode, HD0 is the serial data output, and HD1
to HD7 should be fixed to low level.
7 to 13,
16
HD0 to HD7
MA0 to MA8
I/O
O
17 to 21,
23, 24,
32, 33
DRAM address signal outputs. Connect to the DRAM address pins so that
the numbers match.
34
35
XRAS
O
O
Row address strobe signal output. Connect to the DRAM RAS signal pin.
DRAM write enable signal output. Connect to the DRAM WE signal pin.
XMWE
Used when connecting 8 Mbits of DRAM. Connect to the upper word
(256K to 512K-1) DRAM CAS signal pin (for both the upper and lower
bytes) when the DRAM configuration is 256 Kwords × 16 bits × 2, and to
the MA9 pin (for two DRAMs) when the DRAM configuration is 512 Kwords
× 8 bits × 2.
XCAS2/
MA9
36
37
O
O
DRAM column address strobe signal output. Connect to the lower word
(0 to 256K-1) DRAM CAS signal pin (for both the upper and lower bytes)
when the DRAM configuration is 256Kwords × 16 bits × 2, and to all
DRAM CAS signal pins in all other cases.
XCAS0
38 to 43, MD0 to
46 to 55 MD15
DRAM data signal I/Os. Connect to the DRAM data pins so that the
numbers match.
I/O
I
OSD enable signal. The enabled polarity is changed by the register
settings.
56
OSDEN
OSDB,
OSD data inputs. When the signal input to the OSDEN pin is enabled, the
color registered in the color table which is specified by these three inputs
(3 bits) is output as the image data.
57 to 59 OSDG,
OSDR
I
I
Video output enable signal. Image data output and DCLK output are
enabled when this pin is low, and disabled when this pin is high (high
impedance). Note that the output control register must be set to output
enable for output to be enabled.
62
XVOE
R/Cr0 to
R/Cr7
63 to 70
Image data outputs. The output data format (RGB, YCbCr, etc.) and the
correspondence between the pins and output data can be changed by
setting the registers.
71 to 73, G/Y0 to
76 to 88 G/Y7
O
B/Cb0 to
81 to 88
B/Cb7
Dot clock (DCLK) signal. The DCLK frequency is normally 13.5MHz.
DCLK can be input from this pin, or frequency divided from the clock input
and output from this pin.
89
DCLK
I/O
– 3 –
CXD1856Q/R
Pin No.
92
Symbol
HSYNC
I/O
I/O
Description
Horizontal sync signal. When using the built-in sync generator, the dot
clock (DCLK) is frequency divided and output. When not using the sync
generator, this pin is an input.
Vertical sync signal. When using the built-in sync generator, the dot clock
(DCLK) is frequency divided and output. When not using the built-in sync
generator, this pin is an input.
93
94
VSYNC
I/O
I/O
Field identification signal (FID) and horizontal sync phase reference signal
(FHREF). The signal to be used is set in the register. When set to FID, this
pin is an output if using the built-in sync generator, and an input if not
using the built-in sync generator. High corresponds to odd fields. When set
to FHREF, this pin outputs the signal obtained by frequency dividing XTL0.
When XTL0 is 8fsc, this signal is equivalent to the HSYNC cycle, and can
be used for phase comparison with the HSYNC signal.
FID/FHREF
Composite blanking signal (CBLNK) and fsc signal. The signal to be used
is set in the register. When set to CBLNK, this pin is an output if using the
built-in sync generator, and an input if not using the built-in sync generator.
When set to fsc, this pin outputs the signal obtained by frequency dividing
XTL0. The frequency division ratio can be selected from 1/8 or 1/16.
CBLNK/
FSC
95
I/O
Composite sync signal obtained by frequency dividing DCLK. This pin
cannot be input.
96
97
98
CSYNC
XSGRST
CLK0O
O
I
Sync generator reset signal input. The built-in sync generator is initialized
by setting this pin low.
Output for clock obtained by frequency dividing XTL0. The frequency
division ratio can be selected from 1, 1/2, 1/4 or 1/8.
O
99
DOUT
DATO
LRCO
BCKO
O
O
O
O
Audio digital output.
100
101
102
Audio serial data output to DAC.
L/R clock output to DAC.
Bit clock output to DAC.
Audio interface clock input. Input 256fs (11.2896MHz), 384fs
(16.9344MHz), 512fs (22.5792MHz), or 768fs (33.8688MHz), etc.
103
FSXI
I
Master clock for CD-ROM and audio decoders. Input the clock to XTL2I or
connect an oscillator between XTL2I and XTL2O. The recommended
frequency is 45MHz. Note that this clock is for the internal circuits, and the
input and output are not synchronized.
106
107
109
XTL2O
XTL2I
C2PO
O
I
C2 pointer input from CD-DSP. Indicates that the DATI input contains an
error.
I
110
111
112
113
114
LRCI
DATI
BCKI
DOIN
XHCS
I
I
I
I
I
LR clock input from CD-DSP. Indicates the L or R channel of DATI.
Serial data input from CD-DSP.
Bit clock input from CD-DSP. This clock strobes the DATI input.
Digital data input from CD-DSP.
Chip select signal input during register access.
Wait signal output during register access. Host interface operates in
parallel mode and the wait signal is output by the register switching during
DRAM access.
115
XHDT
I/O
This pin functions as an open drain, and should therefore be pulled up. It
should be pulled up when the host interface operates in serial mode as well.
– 4 –
CXD1856Q/R
Pin No.
116
Symbol
HRW
I/O
I
Description
R/W signal input when the host interface operates in parallel mode. Serial
clock input in serial mode.
Interrupt request signal output. This pin functions as an open drain, and
should therefore be pulled up.
117
118
XHIRQ
XRST
O
I
Hardware reset signal input. All operation is initialized by setting this pin
low.
Chroma key signal. While the color specified as the key is output, this pin
becomes low.
When not used, leave this pin open.
25
26
CKEY
O
O
Video data judgement signal.
While the image data within the frame memory is output, this pin becomes
high; during the border color output or blanking, low.
When not used, leave this pin open.
DTVLD
– 5 –
CXD1856Q/R
3. Electrical Characteristics
3-1. Absolute Maximum Ratings
(Ta = 25°C, VSS = 0V)
Item
Symbol
VDD
VI
Rating
–0.5 to +4.6
–0.5 to VDD + 0.5
–0.5 to +5.5
–0.5 to VDD + 0.5
–0.5 to +5.5
–0.5 to +5.5
1.0
Unit Remarks
V
Supply voltage
Input pin voltage
Input pin voltage
Output pin voltage
Output pin voltage
I/O pin voltage
1
V
2
VI
V
3
VO
V
4
VO
V
VI/O
V
Allowable power dissipation PD
Operating temperature Topr
W
°C
°C
–20 to +75
Storage temperature
Tstg
–55 to +150
1
XTL0I and XTL2I pins
2
Input pins other than those in 1 above.
3
4
XTL0O and XTL2O pins
Output pins other than those in 3 above.
3-2. Recommended Operating Conditions
(Ta = –20 to +75°C, VSS = 0V)
Item
Symbol
Min.
3.0
2.2
2.2
0
Typ.
3.3
—
Unit Remarks
V
Max.
3.6
VDD
5.0
0.8
50
Supply voltage
VDD
1
High level input voltage VIH
High level input voltage VIH
Low level input voltage VIL
V
2
—
V
—
V
Input rise time
Input fall time
Tr
Tf
0
—
ns
ns
°C
0
—
50
Operating temperature Topr
–20
—
75
1
XTL0I and XTL2I pins
2
I/O pins and input pins other than those in 1 above.
– 6 –
CXD1856Q/R
3-3. DC Characteristics
(Ta = –20 to +75°C, VSS = 0V, VDD = 3.3 ± 0.3V)
Item
Symbol Measurement conditions
Min.
—
Typ.
—
Max.
100
Unit Remarks
mA
Average operating
supply current
IDD
1
Input leak current
II
VI = 0 to 5.0V
IOH = –2mA
IOH = –100µA
IOL = 4mA
–40
VDD – 0.8
—
—
—
40
—
µA
2
High level output voltage VOH
High level output voltage VOH
Low level output voltage VOL
Low level output voltage VOL
V
2
VDD – 0.4
—
—
V
2
—
0.4
—
V
2
IOL = 100µA
—
0.04
V
VO = 0 to 5.0V,
output disabled status
2
Output leak current
IOZ
–40
—
40
µA
3
Feedback resistance
Logic threshold value
RFB
VI = 0V or VI = VDD
250k
—
1M
VDD/2
—
2.5M
—
Ω
4
LVth
V
5
High level output voltage VOH
IOH = –12mA
IOL = 12mA
VDD/2
—
—
V
5
Low level output voltage VOL
—
VDD/2
V
1
Input pins other than XTL0I and XTL2I
2
3
4
5
I/O pins and output pins other than XTL0O and XTL2O
Oscillators (between XTL0I and XTL0O, and between XTL2I and XTL2O)
XTL0I and XTL2I pins
XTL0O and XTL2O pins
3-4. Clock Signal AC Characteristics
tCX0
tCX2
tWLX0
tWLX2
XTL0I
XTL2I
tWHX0
tWHX2
Item
Symbol
fX0
Min.
—
Typ.
—
Max.
60
Unit Remarks
1
XTL0I frequency
XTL0I cycle
MHz
1
33.3
10
—
—
ns
t
t
t
CX0
XTL0I high level interval
XTL0I low level interval
XTL2I frequency
XTL2I cycle
—
—
ns
ns
WHX0
WLX0
10
—
—
2
44.7
—
45.1584
22.2
—
45.4
—
MHz
fX2
2
ns
t
t
t
CX2
XTL2I high level interval
XTL2I low level interval
1
8
—
ns
ns
WHX2
WLX2
8
—
—
When using in combination with the XTL0O pin as an oscillator, the maximum oscillation frequency is 50MHz.
When using in combination with the XTL2O pin as an oscillator, the maximum oscillation frequency is 50MHz.
2
– 7 –
CXD1856Q/R
3-5. Host Interface AC Characteristics
3-5-1. Serial Mode (write, read)
XHCS
tSCS
tWLSK
tCSK
tHCS
HRW
(SCK)
tWHSK
tSSI
tHSI
HA0
(SI)
tOHSQ
tLZSQ
tDSQ
tHZSQ
HD0
(SQ)
Item
Symbol
fSK
Min.
—
Max.
2
Unit Remarks
Serial clock frequency
Serial clock cycle
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
500
100
100
0
—
—
—
—
—
—
—
15
40
—
15
t
t
t
t
t
t
t
t
t
t
t
CSK
Serial clock high level interval
Serial clock low level interval
Chip select setup time
WHSK
WLSK
SCS
Chip select hold time
500
30
30
0
HCS
Serial input setup time
SSI
Serial input hold time
HSI
Serial output enable time
Serial output determination time
Serial output hold time
LZSQ
DSQ
OHSQ
HZSQ
—
5
Serial output disable time
0
– 8 –
CXD1856Q/R
3-5-2. Parallel Mode, Register Write
HA0 to 3
tSA
tHA
tWWL1
tWCSH
XHCS
tSW
HRW
tSD1
tHD1
input
HD0 to 7
Item
Address setup time
Address hold time
Symbol
Min.
20
20
20
70
0
Max.
—
Unit Remarks
ns
ns
ns
t
t
t
t
t
t
t
SA
—
HA
Chip disable time
—
WCSH
WWL1
SW
2
Write pulse width
—
ns
Write command setup time
HD input setup time
HD input hold time
—
ns
1
25
25
—
ns
SD1
1
—
ns
HD1
1
Specified for the edge of XHCS or HRW, whichever is earlier.
The data bus does not enter the read mode even when HRW rises ealier than XHCS.
Interval during which both XHCS and HRW are low.
2
<Notes on Operating Timing>
Pay attention to the timing shown below for the CXD1856Q/R parallel mode write.
XHCS
HRW
1. XHCS is enable after determining HRW.
2. It is recommended that XHCS rises firstly and then HRW rises, through the rising order is not so much
considered.
– 9 –
CXD1856Q/R
3-5-3. Parallel Mode, Register Read
HA0 to 8
tWCSH
tWRD1
XHCS
(CS)
tSR
tHR
XHRW
(WR)
tDQ2
tHZQ1
tDQ1
tLZQ1
valid output
HD0 to 7
Item
Chip disable time
Symbol
Min.
Max.
—
Unit Remarks
20
70
10
10
0
ns
ns
ns
ns
t
t
t
t
t
t
t
t
WCSH
WRD1
SR
Read pulse width
—
Read setup time
—
Read hold time
—
HR
1
HD output enable time (for CE)
HD output determination time (for CE)
HD output determination time (for HA)
HD output disable time (for CE)
—
ns
LZQ1
DQ1
2
—
0
60
60
15
ns
2
ns
DQ2
—
ns
HZQ1
1
HD output is enabled when both conditions are met.
HD output is determined when all conditions are met.
2
– 10 –
CXD1856Q/R
3-6. Interface for CD Signal Processing LSI
BCKFEDG = 0
tBCKI
tBCKI
BCKI
DATI
tSBC1
tHBC1
LRCI, C2PO
tHBC2
tSBC2
BCKFEDG = 1
tBCKI
tBCKI
BCKI
DATI
tSBC1
tHBC1
LRCI, C2PO
tHBC2
tSBC2
Item
Symbol
Min.
Max.
5.7
—
Unit Remarks
BCKI frequency
BCKI pulse width
MHz
ns
fBCKI
87
20
20
20
20
t
t
t
t
t
BCKI
DATI setting time (for BCKI)
DATI hold time (for BCKI)
—
ns
SBC1
HBC1
SBC2
HBC2
—
ns
LRCI, C2PO setting time (for BCKI)
LRCI, C2PO hold time (for BCKI)
—
ns
—
ns
– 11 –
CXD1856Q/R
3-7. Image Data Output, Video Sync Signal Output AC Characteristics
tCDCK
tWLDCK
DCLK
tWHDCK
tHPD
R/Cr0 to 7
G/Y0 to 7
B/Cb0 to 7
tDPD
tDHSY
tDHSY
tDVSY
tDCSY
tDCBL
tDFID
HSYNC
VSYNC
CSYNC
CBLNK
tDVSY
tDCSY
tDCBL
tDFID
FID
tDCKY
CKEY
tDDVLD
DTVLD
Item
Symbol
Min.
—
—
—
—
—
0
Typ.
13.5
74.1
37
37
—
Max.
—
Unit Remarks
1
DCLK frequency
DCLK cycle
MHz
fDCK
1
—
ns
t
t
t
t
t
t
t
t
t
t
t
t
CDCK
WHDCK
WLDCK
DPD
1
DCLK high level interval
DCLK low level interval
Image data output determination time
Image data output hold time
HSYNC output delay time
VSYNC output delay time
CSYNC output delay time
CBLNK output delay time
FID output delay time
—
ns
1
—
ns
1,
1,
1
2
2
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
HPD
—
—
—
—
—
—
—
—
30
30
30
30
30
47
48
DHSY
DVSY
DCSY
DCBL
DFID
1
—
1
—
1
—
1
—
CKEY output delay time
DTVLD output delay time
1
—
DCKY
DDVLD
—
When both inputting and outputting DCLK. For output, a load of 75pF is connected to DCLK.
2
The chart shows the case where the pixel data output is synchronized to the fall of DCLK, but is also the
same when synchronized to the rise of DCLK.
– 12 –
CXD1856Q/R
3-8. Video Sync Signal Input AC Characteristics
DCLK
tHHSY
tHVSY
tHCBL
tHFID
tSHSY
tSVSY
tSCBL
tSFID
tHHSY
tHVSY
tHCBL
tHFID
tSHSY
tSVSY
tSCBL
tSFID
HSYNC
VSYNC
CBLNK
FID
Item
Symbol
Min.
5
Max.
Unit Remarks
1
HSYNC hold time
HSYNC setup time
VSYNC hold time
VSYNC setup time
CBLNK hold time
CBLNK setup time
FID hold time
—
—
—
—
—
—
—
—
ns
t
t
t
t
t
t
t
t
HHSY
SHSY
HVSY
SVSY
HCBL
SCBL
HFID
1
5
ns
1
5
ns
1
5
ns
1
5
ns
1
5
ns
1
5
ns
1
FID setup time
1
5
ns
SFID
When both inputting and outputting DCLK. For output, a load of 75pF is connected to DCLK.
– 13 –
CXD1856Q/R
3-9. fsc System Signal Output, DCLK Output AC Characteristics
tCX0
XTL0O
FSC
tCFSC
tDFSC
tDFHR
tDDCK
tWHFSC
tWLFSC
FHREF
tCDCK
tWHDCK
DCLK
tWLDCK
Item
Symbol
fFSC
Min.
—
—
—
—
—
—
—
—
—
—
—
Typ.
Max.
—
Unit Remarks
1
FSC frequency
FSC cycle
1/(i × tCX0)
i × tCX0
i × tCX0/2
i × tCX0/2
—
1
—
t
t
t
t
t
CFSC
1
FSC high level interval
FSC low level interval
FSC output delay time
—
WHFSC
WLFSC
DFSC
1
—
15
15
—
ns
ns
2
FHREF output delay time
DCLK frequency
DFHR
—
fDCK
1/(j × tCX0)
j × tCX0
j × tCX0/2
j × tCX0/2
—
2
DCLK cycle
—
t
t
t
t
CDCK
2
DCLK high level interval
DCLK low level interval
DCLK output delay time
—
WHDCK
WLDCK
DDCK
2
—
15
ns
1
The frequency division ratio i can be selected from 8 or 16.
The frequency division ratio j can be selected from 2 or 4.
2
– 14 –
CXD1856Q/R
3-10. Audio Interface
tBCKO
tBCKO
BCKO
DATO
LRCO
tDDAT
tDLRC
Item
Symbol
Min.
Max.
3.1
—
Unit Remarks
BCKO frequency
BCKO pulse width
MHz
ns
fBCKO
160
—
t
t
t
BCKO
DDAT
DLRC
DATO delay time (for BCKO)
LRCO delay time (for BCKO)
40
ns
—
40
ns
– 15 –
CXD1856Q/R
3-11. DRAM Interface AC Characteristics
3-11-1. Write Cycle
tRP
XRAS
XCAS0 to 3
XMWE
tPC
tRCD
tCAS
tCP
tRSH
tWCS
tASC
tDS
tWCH
tASR
tRAH
tCAH
tDH
MA0 to 9
MD0 to 15
Item
Symbol
Min.
Typ.
2 × tv
2 × tv
tv
Max.
Unit Remarks
2
RAS precharge time
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
t
RP
2
RAS to CAS delay time
RAS hold time
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
RCD
RSH
PC
2
ns
2
Fast page mode cycle time
CAS pulse width
ns
2 × tv
tv
2
ns
CAS
CP
2
CAS precharge time
ns
tv
Write command setup time
Write command hold time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
Write data setup time
Write data hold time
ns
ns
WCS
WCH
ASR
RAH
ASC
CAH
DS
tv
2 × tv
tv
2
ns
2
ns
tv
2
ns
tv
2
ns
tv
ns
ns
tv
DH
tv
1
tv is the basic clock cycle for the DRAM interface circuit.
Same as the DRAM interface read cycle.
2
– 16 –
CXD1856Q/R
3-11-2. Read Cycle
XRAS
tRP
tPC
tRCD
tCAS
tCP
tRSH
XCAS0 to 3
XMWE
tRCS
tRCH
tASR
tRAH
tASC
tCAH
tMDS
MA0 to 9
tMDH
MD0 to 15
Item
Symbol
Min.
Typ.
4 × tv
tv
Max.
Unit Remarks
Read command setup time
Read command hold time
Read data setup time
Read data hold time
—
—
—
—
ns
ns
ns
ns
t
t
t
t
RCS
RCH
MDS
MDH
2
8
1
tv is the basic clock cycle for the DRAM interface circuit.
See the DRAM interface write cycle for items which appear in the timing chart but not in the table.
2
– 17 –
CXD1856Q/R
4. Description of Functions
4-1. Host Interface Function
• The CXD1856Q/R operation is controlled by writing and reading registers. Write and read can also be
performed to an external DRAM via the registers. See the separately issued Register Manual for the
relationship between the registers and operation.
• The host interface operates while XHCS is low and does not operate while XHCS is high.
• The host interface operating mode can be set to 4-line serial or 8-bit parallel. The operating mode is selected
automatically at the end of the initial access after the hardware has been reset. (See the figure below.)
Registers are not accessed correctly until this selection has been determined, or in other words until the end
of the initial access after the hardware has been reset. Also, the HA3 to HA0 inputs should all be fixed low
during the operating mode selection access.
XHCS
HRW
XHCS
HRW
Access judged as parallel mode
XHCS
HRW
8 rises
Access judged as serial mode
• The serial mode signal format is as follows.
XHCS
HRW
(SCK)
HA0
(SI)
bit0
bit0
bit1
bit1
bit2
bit2
bit3
bit4
bit4
bit5
bit5
bit6
bit6
bit7
bit7
bit8
bit8
bit9
byte0
byte1
HD0
(SO)
bit3
bit9
1) In serial mode, input data is fetched in sync with the rise of HRW (SCK). Output data is synchronized with
the fall of HRW.
2) The initial byte (byte0) of the input after XHCS changes to low is a command. This command determines
the subsequent byte processing. See the following page for a description of commands and processing.
3) Input data is processed in one byte units. Therefore, when the final data consists of a number of bits which
is less than one byte, this deficient data is not processed. Be sure to input data with a number of bits which
is an integer multiple of 8. Also, the 0x20, 0x60, 0xA0 and 0xE0 commands process data in two byte units,
so data which is an even multiple of 8 should be input when using these commands.
– 18 –
CXD1856Q/R
Successive
odd-numbered even-numbered
input bytes
Successive
Command write
bit7 ··· bit0 read
first Auto
bit inc.
2nd input byte 3rd input byte 4th input byte
input bytes
Register No.
+U/L byte select
Register No.
+U/L byte select
Register No. LSB
+U/L byte select first
00000000 write
00010000 read
Register data
don’t care
Register data
No
No
Register No.
+U/L byte select
Register No.
+U/L byte select
Register No. LSB
+U/L byte select first
don’t care
Register data Register data Register data
Register data LSB
00100000 write Register No.
00110000 read Register No.
01100000 write Register No.
01110000 read Register No.
No
(Lower byte)
(Upper byte)
(Lower byte)
(Upper byte)
first
LSB
first
don’t care
don’t care
don’t care
don’t care
No
Register data Register data Register data
Register data LSB
Yes
Yes
No
(Lower byte)
(Upper byte)
(Lower byte)
(Upper byte)
first
LSB
first
don’t care
don’t care
don’t care
don’t care
Register No.
10000000 write
Register No.
+U/L byte select
Register No. MSB
+U/L byte select first
Register data
don’t care
Register data
don’t care
+U/L byte select
Register No.
10010000 read
Register No.
+U/L byte select
Register No. MSB
+U/L byte select first
No
+U/L byte select
Register data Register data Register data
Register data MSB
10100000 write Register No.
10110000 read Register No.
11100000 write Register No.
11110000 read Register No.
Description of Commands
No
(Upper byte)
(Lower byte)
(Upper byte)
(Lower byte)
first
MSB
first
don’t care
don’t care
don’t care
don’t care
No
Register data Register data Register data
Register data MSB
Yes
Yes
(Upper byte)
(Lower byte)
(Upper byte)
(Lower byte)
first
MSB
first
don’t care
don’t care
don’t care
don’t care
1) The "write read" column indicates whether that command writes data to or reads data from the registers.
2) Bytes marked with "Register No. + U/L byte select" specify the register to be accessed as well as whether
to access the upper or lower bytes of the register. The upper 7 bits specify the register No., and the
lowermost bit specifies the upper or lower bytes. When the lowermost bit is "0", the lower bytes are
selected, when "1", the upper bytes are selected.
3) Bytes marked with "Register No." specify the register to be accessed. The upper 7 bits specify the register
No., and the lowermost bit can be either "0" or "1".
4) The "Auto inc." column indicates the presence of the register No. auto increment function. For commands
without this function, the most recently input register No. is valid. For example, in case of the command
0x00, the register data input by the odd bytes is written to the register specified by the previous byte's input.
For the command 0x20, all subsequent data is written sequentially to the register specified by the 2nd input
byte.
5) For commands with the register No. auto increment function, the register specified by the 2nd input byte is
accessed first, and then access shifts to the register No. incremented by one each time the data for one
register (2 bytes) is read or written. For example, when using the command 0x60, if 0x08 is specified by the
2nd input byte, the 3rd and 4th input bytes are written to register 0x08, and the 5th and 6th input bytes are
written to register 0x09.
6) Bytes marked with "register data" are the data to be written to the registers during write commands.
– 19 –
CXD1856Q/R
7) When executing read commands, register data output starts from the 3rd output byte (bit 16). All earlier
output data is invalid data. Access shifts to a new register each time the output for one register (2 bytes) is
finished. For example, in case of the command 0x10, the byte data specified by the 2nd input byte is output
to the 3rd output byte, the other byte data in the same register is output to the 4th byte, and the byte data
specified by the 4th input byte is output to the 5th output byte.
8) The "first bit" column indicates whether LSB first or MSB first processing is performed for input or output of
the 2nd and subsequent bytes. This specification does not apply to the 1st byte (command). Commands
are normally LSB first. If LSB first is specified, processing is performed in the order where the initial bit in
each byte is LSB and the final bit is MSB. This order is reversed for MSB first. Note that for registers, bit 15
noted in the Register Manual is MSB and bit 0 is LSB.
4-2. DRAM Interface Function
• The applicable DRAMs are speed version 70 devices (RAS access time (Trac) of 70ns or less) with the fast
page mode function.
• When the total capacity of the external DRAM is 4 Mbits, use a 2CAS type DRAM with a configuration of 256
Kwords × 16 bits. When the total capacity is 8 Mbits, use two 2CAS type DRAMs with a configuration of 256
Kwords × 16 bits or 512 Kwords × 8 bits.
• Refresh is performed automatically using RAS-only-refresh. External control is not necessary.
• The DRAM is divided into the image frame memory, audio bit stream buffer, video bit stream buffer, user
data and on-memory register areas.
• The user data area can be used freely by the user, and CD-ROM decoded output can also be transferred to
this area. This area can be used to store video CD PSD, etc.
• The desired DRAM areas can be accessed from the control microcomputer via the registers.
4-3. CD-ROM Decoder Function
• CD signal processor LSI interface
The CD-ROM decoder has a CD signal processor LSI (CD-DSP) interface which directly interfaces the serial
data output from the CD-DSP. This interface supports a wide variety of input formats to enable connection
with general CD-DSP.
• CD-ROM data decoding (supports CD-ROM XA format mode2, form1 and form2)
CD-ROM data input from the CD-DSP supports CD-ROM XA format (mode2, form1 and form2).
• Input CD-ROM data is decoded by the CD-ROM decoder block. Also, the CD-DA signal input from the CD-
DSP can be output directly from the audio interface.
• The CD-ROM decoder has the following decoding and data transfer operating modes. The real-time
correction and write-only modes facilitate the loading of video CD PSD to the external DRAM, etc.
1) Auto transfer mode
The MPEG pack data within one sector of the video CD is automatically transferred to the system
decoder, where the audio stream sector or video stream sector can be decoded. This mode transfers
2324 bytes counted from the initial byte of user data within one sector to the system decoder.
2) Real-time correction mode
This mode executes error detection and correction processing for mode2, form1 sectors. The 2048 bytes
of user data within the error processed sector are transferred to the user area of the external DRAM. The
4 bytes of header information within the sector can also be loaded in the on-memory register within the
DRAM.
3) Write-only mode
This mode transfers the 2340 bytes of header, subheader and user data within one sector to the user area
of the external DRAM. When a form1 sector is input, error detection and correction processing is
performed and then the data is transferred to the buffer memory. When a form2 sector is input, the data is
transferred as is.
– 20 –
CXD1856Q/R
CD-DSP Input Signal Formats
1) 32-bit slot, MSB first, BCKMOD1, 0 = 00, LSBFST = 0
LRCI
BCKI
Lch
Rch
0
15 16
31
MSB
LSB MSB
LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATI
C2PO
Upper
Lower
Upper
Lower
2) 32-bit slot, LSB first, BCKMOD1, 0 = 00, LSBFST = 1
LRCI
BCKI
Lch
Rch
0
15 16
31
LSB
MSB LSB
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DATI
C2PO
Upper
Lower
Upper
Lower
3) 48-bit slot, MSB first, BCKMOD1, 0 = 01, LSBFST = 0
LRCI
BCKI
Lch
Rch
0
23 24
LSB
47
MSB
MSB
LSB
DATI
D15 D14D13D12 D11D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14D13 D12D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
C2PO
Upper
Lower
Upper
Lower
– 21 –
CXD1856Q/R
4) 48-bit slot, LSB first, BCKMOD1, 0 = 01, LSBFST = 1
LRCI
BCKI
Lch
Rch
0
23 24
MSB
47
LSB
LSB
MSB
DATI
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12 D13D14 D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12D13 D14D15
C2PO
Upper
Lower
Upper
Lower
5) 64-bit slot, MSB first, BCKMOD1, 0 = 10, LSBFST = 0
LRCI
BCKI
Lch
Rch
0
31 32
LSB
63
MSB
MSB
LSB
DATI
don't care
Upper
don't care
Upper
15 1413 12 11 10
9
8
7
6
5
4
3
2
1
0
15 14 13 1211 10
9
8
7
6
5
4
3
2
1
0
C2PO
Lower
Lower
6) 64-bit slot, LSB first, BCKMOD1, 0 = 10, LSBFST = 1
LRCI
BCKI
Lch
Rch
0
31 32
63
LSB
MSB
LSB
MSB
DATI
don't care
Upper
don't care
Upper
0
1
2
3
4
5
6
7
8
9
1011 12 13 14 15
0 1 2 3 4 5 6 7 8 9 10 11 1213 14 15
C2PO
Lower
Lower
– 22 –
CXD1856Q/R
4-4. System Decoder Function
• The MPEG1 system layer (ISO/IEC 11172-1) is decoded, the audio and video bit streams are separated, and
each bit stream is transferred to the respective bit stream buffer.
• The MPEG1 bit stream input can be selected from either the built-in CD-ROM decoder or the host interface.
• The system decoder has a 128-word (256-byte) FIFO for the bit stream input.
• Audio and video sync playback are controlled according to the time stamp within the bit stream.
4-5. Video Decoder Function
• The MPEG1 video layer (ISO/IEC 11172-2) is decoded. This function supports the range where
constrained_parameter_flag = "1" and video CD high resolution still picture.
• Video CD high resolution still picture (NTSC, PAL) can be decoded with a single external 4-Mbit DRAM.
• Special decoding functions are as follows. Slow playback, fast forward and other modes can be realized by
combining these functions.
I-Play: Only I-Pictures are decoded.
Still (Pause): Decoding is paused.
1 Frame Play: Only one frame (picture) is decoded.
IP-Play: Only I and P-Pictures are decoded.
IPB-Play: Alternate frames of continuous B-Pictures and all I and P-Pictures are decoded.
• This function supports digest play.
• The various information in the bit stream is loaded to the on-memory register area within the external DRAM.
4-6. Video Post Processor and Sync Generator Functions
• The image data output format can be selected from 24-bit RGB, 24-bit YCbCr and 16-bit YCbCr. See the
following page.
• Fade in and fade out are allowed.
• Image enlargement and reduction are allowed.
• The CXD1856Q/R contains an OSD color table and selector, and OSD display is achieved by inputting the
OSD character signal.
• The video sync signal can be generated using the built-in sync generator. Image data can also be output in
sync with an externally input video sync signal.
– 23 –
CXD1856Q/R
DCLK
HSYNC
R0 to 7
G0 to 7
B0 to 7
R (n)
G (n)
B (n)
R (n + 1)
G (n + 1)
B (n + 1)
R (0)
G (0)
B (0)
R (1)
G (1)
B (1)
R (2)
G (2)
B (2)
R (3)
G (3)
B (3)
24-bit RGB output format
DCLK
HSYNC
Y0 to 7
Y (n)
Cb (n)
Cr (n)
Y (n + 1)
Cb (n + 1)
Cr (n + 1)
Y (0)
Cb (0)
Cr (0)
Y (1)
Cb (1)
Cr (1)
Y (2)
Cb (2)
Cr (2)
Y (3)
Cb (3)
Cr (3)
Cb0 to 7
Cr0 to 7
24-bit YCbCr output format
DCLK
HSYNC
Y0 to 7
C0 to 7
Y (n)
Y (n + 1)
Cr (n)
Y (0)
Y (1)
Y (2)
Y (3)
Cb (n)
Cb (0)
Cr (0)
Cb (2)
Cr (2)
16-bit YCbCr output format
Note)
• The subscript (i) indicates the data for pixel i.
• The above timing charts show the timing when the pixel data output is synchronized with the fall of DCLK.
The pixel data output can also be synchronized with the rise of DCLK.
– 24 –
CXD1856Q/R
4-7. Audio Decoder Function
• MPEG audio stream decoding is performed for MPEG1 standard (ISO/IEC 11172-3) layer 1 and layer 2.
• Monaural, dual, stereo and joint stereo decoding modes are supported.
• All MPEG1 standard sampling frequencies (32kHz, 44.1kHz, 48kHz) are supported.
• All MPEG1 standard bit rates are supported.
Layer 1: 32Kbps (monaural/stereo) to 448Kbps (monaural/stereo)
Layer 2: 32Kbps (monaural) to 384Kbps (stereo)
• The audio decoder's audio interface output port is equipped with a PCM audio output which outputs decoded
audio data in bit serial format and a digital audio interface output (digital out). The audio interface is set by
setting the internal registers.
1) LRCK and BCK generation
The LR clock and bit clock can be generated by frequency dividing the clock input from external pins XTLI
or FSXI. The generated clocks are output from the BCKO and LRCO pins, respectively. LRCO and BCKO
can be output in the desired polarity. Also, the number of slots per sample supports the three types of 32,
48 and 64 bit clocks/LRCK.
2) PCM audio output format
The PCM audio output format can be set to any of the following combinations to allow connection with a
wide range of 1-bit D/A converters.
16-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
18-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
20-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
24-bit word length, MSB first or LSB first, frontward truncation or rearward truncation
3) Digital out format
The digital out output format supports the type2, form1 format for consumer use. The output word length
can be selected from 16, 18, 20 or 24 bits.
4) Decoded channel assignment
Channels 1 and 0 of the audio sample obtained by decoding the MPEG audio stream can be assigned to
the L and R channel outputs in any combination.
5) Audio mute
The audio output contains a zero-cross mute circuit. Zero-cross detection is performed for 44 sample
sections (approximately 0.1ms when fs = 44.1kHz), and if zero-cross is not detected, the output is forcibly
muted.
6) Attenuator
The audio output contains an attenuator circuit. Attenuation of –12dB can be obtained by setting the
internal register.
7) CD-DA output mode
When playing back a CD-DA disc, the data input from the CD-DSP can be output directly from the PCM
audio output (DATO) and the digital audio interface output port (DOUT). Output ports LRCO and BCKO can
also select and output the clock inputs LRCI and BCKI from the CD-DSP.
– 25 –
CXD1856Q/R
PCM Audio Output Formats
1) 64-bit slot, frontward truncation, LSB first, OSLT1, 0 = 10, OTRUNK = 1, OLSBFST = 1
LRCO
BCKO
Lch
Rch
0
31 32
63
LSB
MSB
LSB
MSB
DATO
0
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 1718 19 20 21 22 23
0
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1011 12 13 14 15 16 17 18 1920 21 22 23
DAL1, 0 = 11
DAL1, 0 = 10
DAL1, 0 = 01
DAL1, 0 = 00
0
1
10 11 12 13 14 15 16 1718 19
0
1
1011 12 13 14 15 16 17 18 19
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10 11 12 13 14 15 16 17
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
1011 12 13 14 15 16 17
10 11 12 13 14 15
1011 12 13 14 15
2) 64-bit slot, rearward truncation, LSB first, OSLT1, 0 = 10, OTRUNK = 0, OLSBFST = 1
LRCO
BCKO
Lch
Rch
0
31 32
MSB
63
LSB
LSB
MSB
DATO
0
1
2
3
4
0
5
1
6
7
8
9
1011 12 13 14 15 16 17 18 1920 21 22 23
0
1
2
3
4
0
5
1
6
7
8
9
10 11 1213 14 15 16 17 18 19 20 2122 23
DAL1, 0 = 11
DAL1, 0 = 10
DAL1, 0 = 01
DAL1, 0 = 00
2
0
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10 11 12 13 14 1516 17 18 19
2
0
3
1
4
2
5
3
6
4
7
5
8
6
9
7
10 11 12 13 14 15 16 1718 19
8
6
9
7
10 11 1213 14 15 16 17
8
6
9
7
10 11 12 13 14 1516 17
0
1
2
3
4
5
8
9
1011 12 13 14 15
0
1
2
3
4
5
8 9 10 11 1213 14 15
LSB/MSB first setting
Data word length setting
DAL1, 0 = 11: 24 bits
DAL1, 0 = 10: 20 bits
DAL1, 0 = 01: 18 bits
DAL1, 0 = 00: 16 bits
OLSBF = 1: set to LSB first
OLSBF = 0: set to MSB first
– 26 –
CXD1856Q/R
3) 48-bit slot, frontward truncation, LSB first, OSLT1, 0 = 01, OTRUNK = 1, OLSBFST = 1
LRCO
BCKO
Lch
Rch
0
23 24
47
LSB
MSB LSB
MSB
DATO
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19D20D21D22D23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19D20D21D22D23
DAL1, 0 = 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19
DAL1, 0 = 10
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17
DAL1, 0 = 01
DAL1, 0 = 00
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15
4) 48-bit slot, rearward truncation, LSB first, OSLT1, 0 = 01, OTRUNK = 0, OLSBFST = 1
LRCO
BCKO
Lch
Rch
0
23 24
47
LSB
MSB LSB
MSB
DATO
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19D20D21D22D23 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19D20D21D22D23
DAL1, 0 = 11
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17D18D19
DAL1, 0 = 10
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15D16D17
DAL1, 0 = 01
DAL1, 0 = 00
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11D12D13D14D15
LSB/MSB first setting
Data word length setting
OLSBF = 1: set to LSB first
OLSBF = 0: set to MSB first
DAL1, 0 = 11: 24 bits
DAL1, 0 = 10: 20 bits
DAL1, 0 = 01: 18 bits
DAL1, 0 = 00: 16 bits
– 27 –
CXD1856Q/R
5) 32-bit slot, LSB first, OSLT1, 0 = 00, OLSBFST = 1
LRCO
BCKO
Lch
Rch
0
15 16
31
LSB
MSB LSB
MSB
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
DATO
6) 32-bit slot, MSB first, OSLT1, 0 = 00, OLSBFST = 0
LRCO
BCKO
Lch
Rch
0
15 16
31
MSB
LSB MSB
LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DATO
LSB/MSB first setting
Data word length: 16 bits
OLSBF = 1: set to LSB first
OLSBF = 0: set to MSB first
– 28 –
CXD1856Q/R
Digital Audio Interface Output Formats
1) 24 bits/word
Parity
Channel status
User data
Validity flag
0
3
4
27 28 29 30 31
Sync
preamble
LSB
MSB
V
U
C P
2) 20 bits/word
0
3
4
7
8
27 28 29 30 31
Sync
preamble
(0) data
LSB
MSB
V
U
C P
3) 18 bits/word
0
3
4
9
10
27 28 29 30 31
Sync
preamble
LSB
MSB
V
U
C P
(0) data
4) 16 bits/word
0
3
4
11 12
27 28 29 30 31
Sync
preamble
(0) data
LSB
MSB
V
U
C P
Data word length setting
DOL1, 0 = 11: 24 bits
DOL1, 0 = 10: 20 bits
DOL1, 0 = 01: 18 bits
DOL1, 0 = 00: 16 bits
– 29 –
CXD1856Q/R
Package Outline
Unit: mm
120PIN QFP (PLASTIC)
31.2 ± 0.2
28.0 ± 0.2
+ 0.1
0.15 – 0.05
0.1
90
61
91
60
A
120
31
0.15 ± 0.1
1
30
0.35 ± 0.1
3.45 ± 0.25
0.8
0.16
M
0.15 ± 0.1
0° to 10°
DETAIL A
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
COPPER / 42 ALLOY
4.9g
SONY CODE
EIAJ CODE
QFP-120P-L01
QFP120-P-2828-A
JEDEC CODE
PACKAGE WEIGHT
120PIN QFP (PLASTIC)
31.20 ± 0.20
28.00 ± 0.20
0.15 ± 0.05
0.10
90
61
91
60
A
120
31
1
30
0.80
0.35 ± 0.10
3.5 ± 0.2
0.16
M
0.15 ± 0.10
0° to 10°
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
QFP-120P-L022
QFP120-P-2828
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SOLDER PLATING
42 ALLOY
EIAJ CODE
JEDEC CODE
4.9 g
– 30 –
CXD1856Q/R
Package Outline
Unit: mm
120PIN LQFP (PLASTIC)
18.0 ± 0.2
16.0 ± 0.1
1.7 MAX
1.4 ± 0.1
S
90
61
0.1
S
91
60
B
A
120
31
1
30
M
0.5
0.22 ± 0.05
0.1
S
0.1 ± 0.05
0.22 ± 0.05
(0.2)
0.25
0° to 10°
DETAIL
A
DETAIL
B
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER PLATING
SONY CODE
EIAJ CODE
LQFP-120P-L01
LQFP120-P-1616
COPPER ALLOY
0.8g
JEDEC CODE
PACKAGE MASS
– 31 –
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