CXD1196AR [SONY]

CD-ROM DECODER; 的CD-ROM解码器
CXD1196AR
型号: CXD1196AR
厂家: SONY CORPORATION    SONY CORPORATION
描述:

CD-ROM DECODER
的CD-ROM解码器

解码器 消费电路 商用集成电路 CD
文件: 总28页 (文件大小:278K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
CXD1196AR  
CD-ROM DECODER  
For the availability of this product, please contact the sales office.  
Description  
80 pin LQFP (Plastic)  
The CXD1196AR is a CD-ROM decoder LSI with a  
built-in ADPCM decoder.  
Features  
CD-ROM, CD-I and CD-ROM XA format  
compatible  
Real time error correction  
Double speed playback compatible  
(when VDD=5.0±10 %)  
Absolute Maximum Ratings (Ta=25 °C)  
Can be connected to a standard SRAM up to 32  
Supply voltage  
Input voltage  
Output voltage  
VDD  
VI  
VSS –0.5 to +7.0  
VSS –0.5 to VDD +0.5  
VSS –0.5 to VDD +0.5  
V
V
V
Kbytes (256 Kbits).  
All audio output sampling frequency : 132.3 kHz  
(Built-in oversampling filter)  
VO  
Operating temperature  
Built-in de-emphasis digital filter  
Capable of VDD 3.5 V operation  
Topr  
Storage temperature  
Tstg  
–20 to +75  
°C  
°C  
–55 to +150  
Applications  
CD-ROM drive  
Recommended Operating Conditions  
Supply voltage  
Structure  
VDD +3.5 to +5.5 (+5.0 Typ.) V  
Operating temperature  
Topr  
Silicon gate CMOS IC  
–20 to +75  
°C  
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by  
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the  
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.  
—1—  
E92128B78-TE  
CXD1196AR  
Block Diagram  
XMOE XMWR MDBO-MDB7  
24-31  
MAO-MA14  
5-11.13-20  
3
4
69  
78  
DO-D7  
DMA FIFO  
DMA  
ADDRESS GEN  
64  
65  
SEQUENCER  
XRD  
CPU I/F  
XWR  
66 XCS  
68  
PRIORITY  
RESOLVER  
AO  
67 INT  
44 INTP  
C2PO 34  
DRO  
51  
DESCRAMBLER  
36  
37  
38  
CPU DMA  
BCLK  
DATA  
LRCK  
COP I/F  
53 XDAC  
SYNC CONTROL  
ADPCM  
GALOIS FIELD  
ECC  
DECODER  
CORRECTOR  
45  
46  
47  
48  
50  
WCKO  
LRCO  
DATO  
BCKO  
MUTE  
SYNDROME GEN  
DAC  
I/F  
59  
XRST  
CLOCK GEN  
DIGITAL  
FILTER  
55 54  
57  
35  
2.12.23.32.42.52.63.72  
GND  
33.73  
VDD  
XTL1 XTL2 CLK  
EMP  
—2—  
CXD1196AR  
Pin Description  
No.  
1
Symbol  
I/O  
I/O  
O
Description  
TD7  
GND  
XMOE  
XMWR  
MA0  
Test pin  
2
Ground pin  
3
Buffer memory output enable negative logic signal  
Buffer memory write enable negative logic signal  
Buffer memory address (LSB)  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Ground pin  
4
O
5
O
6
MA1  
O
7
MA2  
O
8
MA3  
O
9
MA4  
O
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
MA5  
O
MA6  
O
GND  
MA7  
O
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address  
Buffer memory address (MSB)  
Test pin  
MA8  
O
MA9  
O
MA10  
MA11  
MA12  
MA13  
MA14  
TD6  
O
O
O
O
O
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I
TD5  
Test pin  
GND  
MDB0  
MDB1  
MDB2  
MDB3  
MDB4  
MDB5  
MDB6  
MDB7  
GND  
VDD  
Ground pin  
Buffer memory data bus (LSB)  
Buffer memory data bus  
Buffer memory data bus  
Buffer memory data bus  
Buffer memory data bus  
Buffer memory data bus  
Buffer memory data bus  
Buffer memory data bus (MSB)  
Ground pin  
Power supply pin  
C2PO  
EMP  
C2 pointer positive logic signal from CD player  
Emphasis positive logic signal from CD player  
Bit clock signal from CD player  
Data signal from CD player  
LR clock signal from CD player  
Test pin  
I
BCLK  
DATA  
LRCK  
TD4  
I
I
I
I/O  
I/O  
TD3  
Test pin  
—3—  
CXD1196AR  
No.  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
65  
66  
67  
68  
69  
70  
71  
72  
73  
74  
75  
76  
77  
78  
79  
80  
Symbol  
TD2  
GND  
TD1  
INTP  
WCKO  
LRCO  
DATO  
BCKO  
N. C  
MUTE  
DRQ  
GND  
XDAC  
XTL2  
XTL1  
TD0  
CLK  
TDIO  
XRST  
TA3  
I/O  
I/O  
I/O  
I
Description  
Test pin  
Ground pin  
Test pin  
INT pin polarity control signal  
O
O
O
O
O
O
I
Word clock signal to DA converter  
LR clock signal to DA converter  
Data signal to DA converter  
Bit clock signal to DA converter  
Mute positive logic signal  
DMA request positive logic signal  
Ground pin  
Acknowledge negative logic signal for DRQ  
Crystal oscillator circuit output pin  
Crystal oscillator circuit input pin  
Test pin  
O
I
I/O  
O
I
Clock with 1/2 frequency of XTL1  
Test pin  
I
Chip reset negative logic signal  
Test pin  
I
TA2  
I
Test pin  
TA1  
I
Test pin  
GND  
XRD  
XWR  
XCS  
INT  
I
Ground pin  
CPU register read strobe negative logic signal  
CPU register write strobe negative logic signal  
Chip select negative logic signal from CPU  
Interrupt request signal to CPU  
CPU address signal  
CPU data bus (MSB)  
CPU data bus  
I
I
O
I
A0  
D7  
I
D6  
I
D5  
I
CPU data bus  
GND  
VDD  
I
Ground pin  
Power supply pin  
D4  
CPU data bus  
D3  
I
CPU data bus  
D2  
I
CPU data bus  
D1  
I
CPU data bus  
D0  
I
CPU data bus (LSB)  
Test pin  
TA0  
I
N. C  
—4—  
CXD1196AR  
Electrical Characteristics  
DC characteristics  
(VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C)  
Item  
Symbol  
Conditions  
Min.  
2.2  
Typ.  
Max.  
Unit  
V
TTL input level pin ( 1)  
VIH1  
input voltage H level  
TTL input level pin ( 1)  
VIL1  
VIH2  
VIL2  
VIH3  
VIL3  
0.8  
V
V
input voltage L level  
CMOS input level pin ( 2)  
input voltage H level  
0.7 VDD  
CMOS input level pin ( 2)  
input voltage L level  
0.3 VDD  
V
TTL schmitt input level pin ( 3)  
input voltage H level  
2.2  
V
TTL schmitt input level pin ( 3)  
input voltage L level  
0.8  
V
TTL schmitt input level pin ( 3)  
input voltage hysteresis  
CMOS schmitt input level pin ( 4)  
input voltage H level  
VIH3  
0.4  
V
–VIL3  
VIH4  
VIL4  
0.8 VDD  
V
CMOS schmitt input level pin ( 4)  
input voltage L level  
0.2 VDD  
V
CMOS schmitt input level pin ( 4)  
input voltage hysteresis  
Pull-up resistor provided input pin  
( 5) input current  
VIH4  
0.6  
–100  
100  
V
–VIL4  
IIL1  
IIL2  
IIL3  
VIN=0 V  
–40  
40  
–240  
240  
µA  
µA  
µA  
Pull-down resistor provided input pin  
( 6) input current  
VIN=0 V  
VIN=0 V  
Pull-up resistor provided bidirectional  
pin ( 7) input current  
–90  
–200  
–440  
Output voltage H level ( 8)  
Output voltage L level ( 8)  
Input leak current ( 9)  
VOH1  
VOL1  
IIL2  
VOH=–2 mA  
IOL=4 mA  
VDD–0.8  
V
V
0.4  
40  
–40  
µA  
Oscillation cell ( 10) input voltage  
H level  
VIH4  
0.7 VDD  
V
Oscillation cell input voltage L level  
Oscillation cell logic threshold value  
Oscillation cell feedback  
resistance value  
VIL4  
0.3 VDD  
2 M  
V
V
LVTH  
0.5 VDD  
1 M  
RFB  
VIN=VSS or VDD  
500 K  
Oscillation cell output voltage H level  
Oscillation cell output voltage L level  
VOH2  
VOL2  
IOH=–3 mA  
IOL=3 mA  
0.5 VDD  
V
V
0.5 VDD  
—5—  
CXD1196AR  
DC characteristics  
Item  
(VDD=3.5 V, VSS=0 V, Topr=–20 to 75 °C)  
Symbol  
Conditions  
Min.  
2.2  
Typ.  
Max.  
Unit  
V
TTL input level pin ( 1)  
VIH1  
input voltage H level  
TTL input level pin ( 1)  
VIL1  
VIH2  
VIL2  
VIH3  
VIL3  
0.6  
V
V
input voltage L level  
CMOS input level pin ( 2)  
input voltage H level  
0.7 VDD  
CMOS input level pin ( 2)  
input voltage L level  
0.3 VDD  
V
TTL schmitt input level pin ( 3)  
input voltage H level  
2.2  
V
TTL schmitt input level pin ( 3)  
input voltage L level  
0.6  
V
TTL schmitt input level pin ( 3)  
input voltage hysteresis  
CMOS schmitt input level pin ( 4)  
input voltage H level  
VIH3  
0.3  
V
–VIL3  
VIH4  
VIL4  
0.8 VDD  
V
CMOS schmitt input level pin ( 4)  
input voltage L level  
0.2 VDD  
V
CMOS schmitt input level pin ( 4)  
input voltage hysteresis  
Pull-up resistor provided input pin  
( 5) input current  
VIH4  
0.5  
–25  
25  
V
–VIL4  
IIL1  
IIL2  
IIL3  
VIN=0 V  
–10  
10  
–60  
60  
µA  
µA  
µA  
Pull-down resistor provided input pin  
( 6) input current  
VIN=0 V  
VIN=0 V  
Pull-up resistor provided bidirectional  
pin ( 7) input current  
–20  
–50  
–110  
Output voltage H level ( 8)  
Output voltage L level ( 8)  
Input leak current ( 9)  
VOH1  
VOL1  
IIL2  
VOH=–1.6 mA  
IOL=3.2 mA  
VDD–0.8  
V
V
0.4  
40  
–40  
µA  
Oscillation cell ( 10) input voltage  
H level  
VIH4  
0.7 VDD  
V
Oscillation cell input voltage L level  
Oscillation cell threshold value  
Oscillation cell feedback  
resistance value  
VIL4  
0.3 VDD  
5 M  
V
V
LVTH  
0.5 VDD  
2.5 M  
RFB  
VIN=VSS or VDD  
1.2 K  
Oscillation cell output voltage H level  
Oscillation cell output voltage L level  
VOH2  
VOL2  
IOH=–1.3 mA  
IOL=1.3 mA  
0.5 VDD  
V
V
0.5 VDD  
—6—  
CXD1196AR  
1. D7 to 0, MDB7 to 0, TD7 to 0  
2. DATA, LRCK, C2PO, EMP, INTP, TDIO, TA3 to 0  
3. XWR, XRD, XCS, A0, XDAC  
4. BCLK, XRST  
5. XDAC, TA3 to 0  
6. C2PO, INTP  
7. D7 to 0, MDB7 to 0, TD7 to 0  
8. All output pins except XTL2  
9. All input pins except 7  
10. input : XTL1, output : XTL2  
Input/Output Capacitance  
Item  
(VDD=VI=0 V, f=1 MHz)  
Symbol  
CIN  
Min.  
Typ.  
Max.  
9
Unit  
pF  
Input pin  
Output pin  
COUT  
COUT  
11  
pF  
Input/Output pin  
11  
pF  
—7—  
CXD1196AR  
AC Characteristics  
(VDD=5 V±10 %, VSS=0 V, Topr=–20 to 75 °C, Output load=50 pF)  
The values in parentheses in the table are those obtained when VDD=3.5 V, VSS=0 V, Topr=–20 to 75 °C, and  
output load=50 pF.  
Values without parentheses are common to VDD=5 V±10 % and 3.5 V.  
1. CPU interface  
(1) Read  
AO  
Thar  
XCS  
Trrl  
XRD  
D7-D0  
Tsar  
Tdrd  
Tfrd  
Item  
Symbol  
Tsar  
Thar  
Tdrd  
Tfrd  
Min.  
Typ.  
Max.  
Unit  
ns  
Address setting time (with respect to XCS & XRD )  
Address holding time (with respect to XCS & XRD )  
Data delay time (with respect to XCS & XRD )  
Data float time (with respect to XCS & XRD )  
L level XRD pulse width  
30 (70)  
20 (50)  
ns  
120 (200)  
20 (40)  
ns  
0
ns  
Trr1  
150 (250)  
ns  
(2) Write  
AO  
XCS  
Twwl  
Thaw  
XWR  
D7-D0  
Tsdw  
Thdw  
Tsaw  
Item  
Symbol  
Tsaw  
Thaw  
Tsdw  
Thwd  
Twwl  
Min.  
Typ.  
Max.  
Unit  
ns  
Address setting time (with respect to XCS & XWR )  
Address holding time (with respect to XCS & XWR )  
Data setting time (with respect to XCS & XWR )  
Data holding time (with respect to XCS & XWR )  
L level XWR pulse width  
30 (70)  
20 (50)  
50 (70)  
20 (30)  
70 (100)  
ns  
ns  
ns  
ns  
—8—  
CXD1196AR  
(3) DMA  
DRQ  
Tdar2  
Tdar1  
XDAC  
Trrl  
XRD  
Thac  
Tsac  
D7-D0  
Tdrd  
Tfrd  
Item  
Symbol  
Tdar1  
Tdar2  
Tsac  
Thac  
Tdrd  
Min.  
Typ.  
Max.  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
DRQ fall time (with respect to XDAC )  
DRQ rise time (with respect to XDAC )  
XDAC setting time (with respect to XRD )  
XDAC holding time (with respect to XRD )  
Data delay time (with respect to XRD )  
Data float time (with respect to XRD )  
L level XRD pulse width  
50 (120)  
50 (120)  
10 (30)  
10 (30)  
120 (200)  
20 (40)  
Tfrd  
0
Trrl  
150 (250)  
—9—  
CXD1196AR  
2. SRAM interface  
(1) Read  
MA14-MA0  
Tsao  
Toel  
Thao  
XMOE  
MDB7-MDB0  
Tsdo  
Thdo  
Item  
Symbol  
Tsao  
Thao  
Tsdo  
Thdo  
Toel  
Min.  
Typ.  
Max.  
Unit  
ns  
Address setting time (with respect to XMOE )  
Address holding time (with respect to XMOE )  
Data setting time (with respect to XMOE )  
Data holding time (with respect to XMOE )  
L level XMOE pulse width  
T1–30  
T1–10  
ns  
50 (100)  
10 (20)  
ns  
ns  
2 • T1  
ns  
(2) Write  
MA14-MA0  
Thamw  
Tsamw  
Tmwl  
XMWR  
MDB7-MDB0  
Tdmw  
Tfmw  
Item  
Symbol  
Min.  
Typ.  
Max.  
0
Unit  
ns  
Address setting time (with respect to XMWR )  
Address holding time (with respect to XMWR )  
Data delay time (with respect to XMWR )  
Data float time (with respect to XMWR )  
L level XMWR pulse width  
Tsamw  
Thamw  
Tdmw  
Tfmw  
T1–30  
T1–10  
ns  
ns  
10  
ns  
Tmwl  
2 • T1  
ns  
59 ns : XSLOW = ‘H’  
T1=  
{
238 ns : XSLOW = ‘L’  
Note that XSLOW is bit 7 of DRVIF register.  
When XSLOW = ‘H’ , make sure that the CXD1196AR is connected to an SRAM with an access time of  
less than 120 ns.  
When XSLOW = ‘L’ , make sure that the CXD1196AR is connected to an SRAM with an access time of less  
than 320 ns.  
—10—  
CXD1196AR  
3. DSP Interface for CD  
BCKRED= “H”  
Tbck  
Tbck  
BCLK  
DATA  
Tsb1  
Thb1  
LRCK  
C2PO  
Thb2  
Tbck  
Tsb2  
BCKRED= “L”  
Tbck  
BCLK  
DATA  
Tsb1  
Thb1  
LRCK  
C2PO  
Thb2  
Thb2  
Item  
Symbol  
Fbck  
Tbck  
Tsb1  
Thb1  
Tsb2  
Thb2  
Min.  
Typ.  
Max.  
5.7  
Unit  
MHz  
ns  
BCLK frequency  
BCLK pulse width  
85  
50  
50  
50  
50  
Data setting time (with respect to BCLK)  
Data holding time (with respect to BCLK)  
ns  
ns  
LRCK, C2PO setting time (with respect to BCLK)  
LRCK, C2PO holding time (with respect to BCLK)  
ns  
ns  
—11—  
CXD1196AR  
4. DAC interface  
Tbco  
Tbco  
BCKO  
DATO  
Tsbo  
Thbo  
WCKO  
LRCO  
Thbc  
Tsbo  
Item  
Symbol  
Fbco  
Min.  
Typ.  
8.4672  
Max.  
Unit  
MHz  
ns  
BCKO frequency  
BCKO pulse width  
Tbco  
50  
30  
DATO, WCKO, LRCO setting time  
(with respect to BCKO )  
Tsbo  
Thbo  
ns  
ns  
DATO, WCKO, LRCO holding time  
(with respect to BCKO )  
30  
—12—  
CXD1196AR  
5. XTL1 pin, XTL2 pins  
(1) Self-excited oscillation  
Item  
Symbol  
Fmax  
Min.  
Typ.  
Max.  
Unit  
Oscillation frequency  
16.9344  
MHz  
(2) When pulses are to be input to XTL1 pin  
Tw  
Twhx  
Twlx  
Vihx  
Vihx 0.9  
VDD/2  
Vihx 0.1  
Vilx  
Tr  
Tf  
Item  
Symbol  
Twhx  
Twlx  
Tw  
Min.  
20  
Typ.  
59  
Max.  
Unit  
ns  
ns  
ns  
V
H level pulse width  
L level pulse width  
Pulse interval  
Input H level  
Input L level  
Rise time  
20  
Vihx  
Vilx  
VDD–1.0  
0.8  
15  
15  
V
Tr  
ns  
ns  
Fall time  
Tf  
Note) Synchronize XTL1 clock with DSP clock for CD.  
(Use the clock generated from the same oscillator unit.)  
—13—  
CXD1196AR  
Description of Functions  
1. Description of Pins  
1.1 CD player interface  
The CXD1196AR can be directly connected to digital signal processing LSIs for CD of Sony and other  
company. The digital signal processing LSI for CD is referred to as a DSP for CD.  
(1) DATA (DATA : Input)  
Serial data stream from a CIRC LSI  
(2) BCLK (Bit Clock : Input)  
Bit clock signal for strobing DATA signal  
(3) LRCK (LR Clock : Input)  
LR clock signal indicating Lch and Rch of DATA signal  
(4) C2PO (C2 Pointer : Input)  
C2 pointer signal indicating that DATA input contains an error  
(5) EMP (Emphasis : Input)  
Emphasis indicating that the data from the DSP is emphasized. (positive logic signal)  
1.2 Buffer memory interface  
The CXD1196AR can be connected to a standard SRAM up to 32 Kbytes (256 Kbits).  
(1) XMWR (BUFFER MEMORY WRITE : OUT)  
Data write signal to buffer memory (strobe negative logic output)  
(2) XMOE (BUFFER MEMORY OUTPUT ENABLE : OUT)  
Data read signal to buffer memory (strobe negative logic output)  
(3) MA0-14 (BUFFER MEMORY ADDRESS : OUT)  
Address signals to buffer memory  
(4) MDB0-7 (BUFFER MEMORY DATA BUS : BUS)  
Buffer memory data bus signal pulled up by a typical 25 kresistor  
In an ADPCM decode playback drive, make sure that the CXD1196AR is connected to a 256 Kbit (8b ×  
32 Kw, 32 Kbyte) SRAM  
1.3 CPU interface  
(1) XWR (CPU WRITE : Input)  
Strobe signal for writing to register in chip (negative logic input)  
(2) XRD (CPU READ : Input)  
Strobe for reading out status of register chip (negative logic input signal)  
(3) D0-7 (CPU DATA BUS : Input and output)  
8-bit data bus  
(4) A0 (CPU ADDRESS : Input)  
CPU address signal for selecting internal register of the CXD1196AR  
(5) INT (CPU INTERRUPT : Output)  
Interrupt request output signal for CPU. The polarity of this signal can be controlled by the INTP pin.  
(6) INTP (INTERRUPT POLARITY : Input)  
This pin controls the polarity of the INT pin. In the IC, it is pulled up by a typical 50 kregister.  
When INTP= ‘H’ or open, the INT pin goes low active.  
When INTP= ‘L’ , the INT pin goes high active.  
(7) XCS (CHIP SELECT : Input)  
Chip select signal for CPU to select the CXD1196AR (negative logic input)  
—14—  
CXD1196AR  
(8) DRQ (DATA REQUEST : Output)  
DMA data request signal (positive logic output)  
(9) XDAC (DATA ACKNOWLEDGE : Input)  
The acknowledge signal for DRQ (negative logic input). In the IC, it is pulled up by a typical 50 kΩ  
resistor.  
1.4 DAC interface  
(1) BCKO (BIT CLOCK OUTPUT : Output)  
Bit clock output signal to DA converter  
(2) WCKO (WORD CLOCK OUTPUT : Output)  
Word clock output signal to DA converter  
(3) LRCO (LR CLOCK OUTPUT : Output)  
LR clock output signal to DA converter  
(4) DATO (DATA OUTPUT : Output)  
Data output signal to DA converter  
Fig. 1.1 shows a timing chart for interface with the DA converter.  
1.5 Miscellaneous  
(1) MUTE (MUTE : Output)  
Output H when DA data is muted  
(2) XRST (RESET : Input)  
Chip reset signal (negative logic input)  
(3) XTL1 (X’TAI1 : Input)  
(4) XTL2 (X’TAI2 : Output)  
Connect a 16.9344 MHz crystal oscillator unit between XTL1 and XTL2. (The value of the capacitor  
depends on the crystal oscillator unit.) Or input 16.9344 MHz clock to the XTL1 pin. For ADPCM or  
CD-DA playback, the clocks of the DSP for CD and this IC must be synchronized.  
(5) CLK (CLOCK : Output)  
Output 8.4672 clock.  
When this clock is not be used, the output of the CLK pin may be fixed at ‘L’.  
1.6 Test pins  
These pins are normally kept in the opened state.  
(1) TD0-7 (Input/Output) : Data bus for IC test. Pulled up by a typical 25 kresistor.  
(2) TDIO (Input) : Input pin for IC test. Pulled up by a typical 50 kresistor.  
(3) TA0-3 (Input) : Input pins for IC test. Pulled up by a typical 50 kresistor.  
—15—  
CXD1196AR  
—16—  
CXD1196AR  
2. Register Functions  
2.1 Write register  
2.1.1 Register address (REGADR) register  
This register is used for selection of the internal registers.  
(1) When A0 = XCS = ‘L’, the REGADR register is selected. When A0 = ‘H’ and XCS = ‘L’, the register  
specified by the REGADR is selected.  
(2) When the low order 4 bits of REGADR are not 0 (hex), and a register write or read is made by setting  
A0 = ‘H’ and XCS = ‘L’, the low order 4 bits of REGADR are incremented.  
(3) REGADR is cleared by rising edge of DMAEN bit (bit3) of the DMACTL register. (Cleared to 00 (hex).)  
2.1.2 DRIVE Interface (DRVIF) register  
Bit7 XSLOW (/SLOW SPEED)  
‘H’  
:
A DMA cycle is performed in 4 clocks.  
In this case, a standard SRAM with an access time of less than 120 nsec can be connected  
to the CXD1196AR.  
‘L’  
:
A DMA cycle is performed in 12 clocks. When the CXD1196R is connected to an SRAM  
with a slower access time, set this bit at ‘L’. In this case, a standard SRAM with an access  
time of less than 320 ns can be connected to the CXD1196AR. For operation at VDD = 3.5  
V, set this bit to L.  
Bit6 C2PL1ST (C2PO Ler-byte 1st)  
‘H’  
:
To input two bytes of DATA input, each with a C2PO identifying the lower or upper byte, in  
the order of the lower and upper bytes  
‘L’  
:
To input two bytes of DATA input, each with a C2PO identifying the upper or lower byte, in  
the order of the upper and lower bytes.  
Here, the upper byte means the 8 (eight) upper bits including the MSB from the DSP for CD. And the lower  
byte means the 8 (eight) lower bits including the LSB from the DSP for CD. For example, the minute byte  
of the Header is a lower byte and the sec byte is a upper byte.  
Bit5 LCHLOW (LCH LOW)  
‘H’  
‘L’  
:
:
To determine that the data is Lch data when LRCK = ‘L’  
To determine that the data is Lch data when LRCK = ‘H’  
Bit4 BCKRED (BCLK Rising Edge)  
‘H’  
‘L’  
:
:
To strobe DATA by the rising edge of BCLK  
To strobe DATA by the falling edge of BCLK  
Bit3, 2 BCKMD1, 0 (BCLK Mode 1, 0)  
Set these bits, depending on the number of BCLK clocks output by the DSP for CD during a cycle of  
WCLK.  
BCKMD1  
BCKMD0  
‘L’  
‘L’  
‘H’  
‘L’  
‘H’  
‘X’  
16BCLKs/WCLK  
24BCLKs/WCLK  
32BCLKs/WCLK  
Bit1 LSB 1ST (LSB First)  
‘H’  
‘L’  
:
:
To connect to a DSP for CD which outputs DATA on an LSB first basis  
To connect to a DSP for CD which outputs DATA on an MSB first basis  
Bit0 CLKLOW (CLK LOW)  
‘H’  
‘L’  
:
:
To fix CLK pin output at ‘L’  
To output 8.4672 MHz clock from CLK pin output  
The values of the individual bits of this register must be changed with the decoder in the disabled state.  
Table 2.1.1 shows the values of bits of bit 6 through 1 to be set when the CXD1196AR is connected to  
Sony DSPs for CD. Fig. 2.2.1 (1) through (3) show input timing charts.  
—17—  
CXD1196AR  
DRVIF register  
Sony DSP for CD  
Timing chart  
Fig. 2.1.1 (1)  
Fig. 2.1.1 (2)  
Fig. 2.1.1 (3)  
bit6 bit5 bit4 bit3 bit2 bit1  
CDL30 series  
CDL35 series  
L
L
L
L
L
L
H
L
L
L
H
H
X
L
L
CDL40 series  
(48-bit slot mode)  
CDL40 series  
H
H
H
(64-bit slot mode)  
Table 2.1.1 DRVIF Register Settings  
(Note 1)  
CXD1125Q/QZ, CXD1130Q/QZ, CXD1135Q/QZ,  
CXD1241Q/QZ, CXD1245Q, CXD1246Q/QZ,  
CXD1247Q/QZ/R, etc.  
CDL30 series  
CDL35 series  
CDL40 series  
CXD1165Q, CXD1167Q/QZ/R, etc.  
CXD2500Q/QZ, etc.  
2.1.3 Chip Control (CHPCTL) register  
Bit7-5 RESERVED  
Bit4 CHPRST (Chip Reset)  
When this bit is set at ‘H’, the CXD1196AR is internally initialized. The bit setting will automatically  
change to ‘L’ when the internal initialization of the CXD1196AR is completed. Therefore, there is no  
need for the CPU to change the setting at ‘L’. Initialization of the CXD1196AR will be completed in  
500ns after the bit has been set at ‘H’ by the CPU.  
Bit3 CD-DA (CD-Digital Audio)  
‘H’  
:
When a CD-DA disc is to be played back, this bit is set at ‘H’.  
The decoder must be placed in the disabled state (DECCTL register) when this bit is set at  
‘H’.  
‘L’  
:
When a CD-ROM disc is to be played back, this bit is set at ‘L’.  
Bit2 SWOPN (Sync Window Open)  
‘H’  
:
When this bit is set at ‘H’, the window for detection of SYNC mark will open. In this case,  
the SYNC protection circuit in the CXD1196AR will be disabled.  
‘L’  
:
When this bit is set at ‘L’, the window for detection of SYNC mark will be controlled by the  
SYNC protection circuit in the CXD1196AR.  
Bit1 RPSTART (Repeat Correction Start)  
When the DECODER is placed in the repeat correction mode, and this bit set at ‘H’, the error  
correction of the current sector will begin. The bit setting will automatically change to ‘L’ when  
correction begins. Therefore, there is no need for the CPU to change the setting at ‘L’.  
Bit0 ADPEN (ADPCM Enable)  
When the current sector is an ADPCM sector, the CPU sets this bit at ‘H’ in less than 11.5 ms after a  
decoder interrupt (DECINT). When the current sector is not an ADPCM sector, the CPU changes the  
bit setting at ‘L’ in less than 11.5 ms after a decoder interrupt (DECINT).  
—18—  
CXD1196AR  
2.1.4 DECODER CONTROL (DECCTL) Register  
Bit7 AUTOCI (Auto Coding Information)  
‘H’  
:
To perform ADPCM playback according to the coding information from the drive. In this  
case, the CI register need not be set.  
‘L’  
:
To perform ADPCM playback according to the value of the CI register.  
Bit6 RESERVED  
Should be kept at ‘L’ at all times.  
Bit5 MODESEL (Mode Select)  
Bit4 FORMSEL (Form Select)  
When AUTODIST = ‘L’, the sector is corrected as the following MODE and FORM.  
MODESEL  
FORMSEL  
‘L’  
‘H’  
‘H’  
‘L’  
‘L’  
‘L’  
MODE1  
MODE2, FORM1  
MODE2, FORM2  
Bit3 AUTODIST (Auto Distinction)  
‘H’  
‘L’  
:
:
Errors are corrected according to the MODE byte and FORM bit read from the drive.  
Errors are corrected according to bit 5 MODESEL and bit4 FORMSEL.  
Bit2-0  
:
DECMD 2-0 (Decoder Mode 2-0)  
DECMD2  
DECMD1  
DECMD0  
‘L’  
‘L’  
‘H’  
‘H’  
‘H’  
‘H’  
‘L’  
‘H’  
‘L’  
‘L’  
‘H’  
‘H’  
‘X’  
‘X’  
‘L’  
‘H’  
‘L’  
‘H’  
Decoder disable  
Monitor only mode  
Write only mode  
Real time correction mode  
Repeat correction mode  
Inhibit  
These bits are set at ‘L’ when the CDDA bit (bit3) of the CHPCTL register is ‘H’.  
2.1.5 Interrupt Mask (INTMSK) Register  
When the individual bits of this register are set at ‘H’, an interrupt request from the CXD1196AR to the CPU  
is enabled in response to the corresponding interrupt status. (That is, when the interrupt status is created,  
the INT pin is made active.) The value of the individual bits of the register does not affect the  
corresponding interrupt status.  
Bit7 ADPEND (ADPCM End)  
When this chip has completed the ADPCM decode for a sector, if the ADPCM decode for the next  
sector is not enabled, the ADPEND status is created.  
Bit6 DECTOUT (Decoder Time Out)  
If no SYNC mark is detected during a period of 3 sectors (40.6 ms in normal speed playback mode)  
after the DECODER has been set in the monitor only, and real time correction modes, the DECTOUT  
status is created.  
Bit5 DMACMP (DMA Complete)  
When DMA is ended by DMAXFRC, the DMACMP status is created.  
—19—  
CXD1196AR  
Bit4 DECINT (Decoder Interrupt)  
If a SYNC mark is detected or internally inserted during execution of the write only, monitor only and  
real time correction modes by the DECODER, the DECINT status is created. When the SYNC mark  
detected window is open, however, if the SYNC mark spacing is less than 2352 bytes, the DECINT  
status is not created. During execution of the repeat correction mode by the DECODER, the  
DECINT status is created each time a correction ends.  
Bit3 CIERR (Coding Information Error)  
When AUTOCI bit of DECCTL register is set at “H” and ADPCM decode playback is done, if there is  
an error in a CI byte of an ADPCM sector, the CIERR status is created. ADPCM decode playback of  
this sector will not be done.  
Bit2-0 RESERVED  
2.1.6 Clear Interrupt Status (INCTCLR) Register  
When the individual bit of this register is set at ‘H’, the corresponding interrupt status is cleared. The  
individual bit is automatically set at ‘L’ after the interrupt status has been cleared. Therefore, there is no  
need for the CPU to change the setting at ‘L’.  
Bit7 ADPEND (ADPCM End)  
Bit6 DECTOUT (DECODER Time Out)  
Bit5 DMACMP (DMA Complete)  
Bit4 DECINT (DECODER Interrupt)  
Bit3 CIERR (Coding Information Error)  
Bit2-0 RESERVED  
2.1.7 Coding Information (CI) Register  
When ADPCM decoding is to be done by setting AUTOCI = ‘L’, the coding information is written to this  
register. The bit configuration is the same as that of the coding information byte of the sub header.  
2.1.8 DMA Address Counter-L (DMAADRC-L)  
2.1.9 DMA Address Counter-H (DMAADRC-H)  
This counter retains the address to be used by the CPU when reading data from the buffer. When the data  
to be sent to the CPU is read from the buffer, the contents of the DMAADRC are output from MA0-14.  
Each time data to be sent to the CPU is read from the buffer, the DMAADRC is incremented.  
The CPU sets the head address of DMA in the DMAADRC before starting DMA. The CPU can read and  
set the contents of the DMAADRC at any time. Do not change the contents of the DMAADRC during  
execution of DMA.  
—20—  
CXD1196AR  
2.1.10 DMAXFRC-L  
2.1.11 DMA Control (DMACTL) register  
Bit7 DMAXFRC11  
Bit11 (MSB) of DMAXFRC (Transfer Counter)  
Bit6 DMAXFRC10  
bit10 of DMAXFRC  
Bit5 DMAXFRC9  
bit9 of DMAXFRC  
Bit4 DMAXFRC8  
bit8 of DMAXFRC  
Bit3 DMAEN (CPU DMA Enable)  
‘H’  
‘L’  
:
:
To enable DMA  
To inhibit DMA  
Bit2-0 RESERVED  
The DMAXFRC (DMA Transfer Counter) is a counter which indicates the number of DMA transfers. Each  
time the data to be transferred to the CPU is read from the buffer, the counter is decremented. When the  
value of the DMAXFRC reaches 0, DMA ends. At this point, interrupt request may be output to the CPU.  
When data transfer is not to be ended by DMAXFRC as in the case of data transfer in the I/O mode,  
DMAXFRC should be set at 0 when data transfer is started (when DMAEN bit is set at ‘H’). The CPU can  
read and set the contents of DMAXFRC at any time. During execution of DMA, do not change the contents  
of DMAXFRC.  
2.1.12 DRVADRC-L (Drive Address Counter-L)  
2.1.13 DRVADRC-H  
The DRVADRC is a counter which retains the address for writing the data from the drive to the buffer.  
When the drive data is written to the buffer, the value of DRVADRC is output from MA01-14 pins. Each  
time a byte of data from the drive is written to the buffer, the DRVADRC is incremented.  
Before execution of the write only mode and real time correction mode of the DECODER, the CPU sets the  
buffer write head address in the DRVADRC.  
The CPU can read and set the contents of DRVADRC at any time. During execution of DMA, do not  
change the contents of DRVADRC.  
—21—  
CXD1196AR  
—22—  
CXD1196AR  
2.2 Read register  
In the descriptions of the registers STS, HDRFLG, HDR, SHDR and CMADR, what is referred to as the  
current sector refers to the sector where registers are valid for a decoder interrupt (DECINT). In the monitor  
only and write only modes, the sector from the DSP for CD just before a decoder interrupt is called the  
current sector. In the real time correction mode and repeat correction mode, the sector that has gone  
through error detection and correction is referred to as the current sector.  
2.2.1 Register Address (REGADR) Register  
2.2.2 DMADATA Register  
When data transfer (buffer read) is to be made in the I/O mode, the CPU reads data from this register.  
2.2.3 Interrupt Status (INTSTS) Register  
The values of the individual bits of this register indicate the respective associated values of interrupt status.  
These bits are not affected by the values of the individual bits of the INTMSK register.  
Bit7 ADPEND (ADPCM End)  
Bit6 DECTOUT (DECODER Time Out)  
Bit5 DMACMP (DMA Complete)  
Bit4 DECINT (DECODER Interrupt)  
Bit3 CIERR (Coding Information Error)  
2.2.4 Status (STS) Register  
Bit7 DRQ (Data Request)  
This bit indicates the value of the DRQ pin.  
Bit6 ADPBSY (ADPCM BUSY)  
This bit goes ‘H’ during ADPCM playback.  
Bit5 ERINBLK (Erasure in Block)  
On all the bytes of the current sector except the SYNC byte, this bit goes ‘H’ if there is one or more  
bytes from the DSP for CD whose C2 pointer is ON.  
Bit4 CORINH (Correction Inhibit)  
When the DECCTL register is set AUTODIST bit = ‘H’, this bit goes ‘H’ if the error flag is ON in the  
MODE (and FORM) byte.  
Bit3 EDCOK  
Indicates EDC check showed there were no errors in the current sector.  
Bit2 ECCOK  
Indicates there are no more errors from the Header to P parity bytes in the current sector. (In the  
MODE2, FORM2 sector, this bit is treated as a DON’T CARE bit.)  
Bit1 SHRTSCT (Short Sector)  
Indicates the Sync Mark interval was less than 2351 bytes. On this sector, neither ECC nor EDC is  
executed.  
Bit0 NOSYNC  
Indicates that the SYNC Mark, not detected in the predetermined position, is one internally inserted.  
2.2.5 Header Flag (HDRFLG) Register  
Indicates the value of the error pointer of the Header and Sub Header registers.  
—23—  
CXD1196AR  
2.2.6 Header (HDR) Register  
It is a 4-byte register indicating the Header byte of the current sector. The CPU can find the value of the  
Header byte of the current sector from the Minute byte as it sets the REGADR register at X4 hex and  
successively reads data.  
2.2.7 Sub Header (SHDR) Register  
It is a 4-byte register indicating the Sub Header byte of the current sector. The CPU can find the value of  
the Sub Header byte of the current sector from the File byte as it sets the REGADR register at 08 hex and  
successively reads data.  
2.2.8 Current Minute Address L (CMADR-L) Register  
2.2.9 Current Minute Address H (CMADR-H) Register  
Indicates the buffer memory address where the Minute bytes of the current sector (after correction) is in  
store.  
2.2.10 MODE/FORM (MDFM) Register  
Bit4-2 RMODE2-0  
RMODE2 : Indicates the logic sum of the value of the high-order 6 bits of the raw MODE byte and the  
pointer.  
RMODE1, 0 : Respectively indicate the values of the low-order 2 bits of the raw MODE byte.  
Bit1 CMODE (Correction Mode)  
Bit0 CFORM (Correction Form)  
These bits indicate which of the MODEs and FORMs this IC determined that the current sector was  
associated with when it corrected errors.  
CFORM  
‘X’  
CMODE  
‘L’  
MODE1  
‘L’  
‘H’  
‘H’  
‘H’  
MODE2, FORM1  
MODE2, FORM2  
2.2.11 ADPCI (ADPCM Coding Information) Register  
Bit7 MUTE  
This bit goes ‘H’ when the DA data is muted on.  
Bit6 EMPHASIS  
This bit goes ‘H’ when the ADPCM data is emphasized.  
Bit5 EOR (End of Record)  
This bit goes ‘H’ when the Sub Mode byte bit0 = ‘H’ and there is no error in the Sub Mode byte.  
Bit4 BITLNGTH (Bit Length)  
This bit indicates the bit length of ADPCM playback coding information.  
‘H’  
‘L’  
:
:
8 bits  
4 bits  
Bit2 FS (Sampling Frequency)  
This bit indicates the ADPCM playback sampling frequency.  
‘H’  
‘L’  
:
:
18.9 kHz  
37.8 kHz  
Bit0 M/S (MONO/STEREO)  
This bit indicates “monaural” or “stereo” of ADPCM playback coding information.  
‘H’  
‘L’  
:
:
Stereo  
Monaural  
—24—  
CXD1196AR  
2.2.12 DMAXFRC-L  
2.2.13 DMAXFRC-H  
2.2.14 DMAADRC-H  
2.2.15 DMAADRC-H  
2.2.16 DRVADRC-L  
2.2.17 DRVADRC-H  
REG  
A0  
RA  
X
bit7  
bit6  
bit5  
bit4  
RA4  
bit3  
RA3  
bit2  
RA2  
bit1  
RA1  
bit0  
RA0  
REGADR  
L
L
L
L
L
L
L
RESERVED  
DRVIF  
H
X0  
L
L
L
L
L
C2PO  
L1st  
LCH  
BCK  
RED  
CHP  
RST  
FORM  
SEL  
DEC  
INT  
BCK  
MD1  
CD-  
DA  
BCK  
MD0  
SW  
LSB  
1st  
H
H
H
H
H
H
H
H
H
H
H
H
X1 XSLOW  
CLKL  
LOW  
CLR  
RPS  
TART  
DEC  
MD1  
ADP  
EN  
CHPCTL  
DECCTL  
INTMSK  
INTCLR  
CI  
X2  
X3  
X4  
X5  
X6  
L
L
L
ADP  
MODE  
SEL  
OPEN  
DEC  
MD2  
AUTO  
CI  
AUTO  
DIST  
CI  
DEC  
MD0  
ADP  
END  
ADP  
END  
DEC  
DMA  
CMP  
DMA  
CMP  
L
L
L
L
L
TOUT  
DEC  
ERR  
CI  
DEC  
INT  
L
TOUT  
EMPH  
ASIS  
ERR  
BIT  
FS  
MONO  
STE  
L
L
L
L
L4H8  
L3H1  
DMA  
ADRC-L  
DMA  
X7 bit7  
X8  
bit6  
bit5  
bit13  
bit5  
xfrc9  
bit5  
bit13  
bit4  
bit3  
bit11  
bit3  
bit2  
bit10  
bit2  
L
bit1  
bit9  
bit1  
L
bit0  
bit8  
bit0  
L
L
bit14  
bit6  
bit12  
bit4  
ADRC-H  
DMA  
X9 bit7  
XA xfrc11  
XB bit7  
XFRC-L  
DMA  
EN  
DMACTL  
xfrc10  
bit6  
xfrc8  
bit4  
DRV  
ADRC-L  
DRV  
bit3  
bit2  
bit10  
bit1  
bit9  
bit0  
bit8  
XC  
L
bit14  
bit12  
bit11  
ADRC-H  
TEST2  
TEST1  
TEST0  
H
H
H
1D  
1E  
1F  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
Write Registers  
—25—  
CXD1196AR  
bit0  
REG  
REGADR  
DMA  
A0  
L
RA  
X
bit7  
bit6  
bit5  
bit4  
RA4  
bit3  
RA3  
bit2  
RA2  
bit1  
RA1  
X
X
X
RA0  
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
00 bit7  
bit6  
bit5  
bit2  
X
bit1  
X
bit0  
X
bit4  
bit3  
DATA  
ADP  
01  
DEC  
TOUT  
ADP  
BSY  
DMA  
CMP  
ERIN  
BLK  
BLO  
CK  
DEC  
INT  
CI  
INTSTS  
STS  
END  
ERR  
EDC  
OK  
COR  
INH  
ECC  
OK  
SHRT  
SCT  
NO  
02 DRQ  
03 MIN  
X4 bit7  
X5 bit7  
X6 bit7  
X7 bit7  
08 bit7  
09 bit7  
0A bit7  
0B bit7  
0C bit7  
SYNC  
CHAN  
NEL  
SUB  
HDRFLG  
SEC  
bit6  
bit6  
bit6  
bit6  
bit6  
bit6  
bit6  
bit6  
bit6  
bit14  
X
CI  
MODE  
bit4  
FILE  
bit3  
bit3  
bit3  
bit3  
bit3  
bit3  
bit3  
bit3  
bit3  
bit11  
MODE  
HDR  
MIN  
bit5  
bit5  
bit5  
bit5  
bit5  
bit5  
bit5  
bit5  
bit5  
bit13  
X
bit2  
bit2  
bit2  
bit2  
bit2  
bit2  
bit2  
bit2  
bit2  
bit10  
bit1  
bit1  
bit1  
bit1  
bit1  
bit1  
bit1  
bit1  
bit1  
bit9  
bit0  
bit0  
bit0  
bit0  
bit0  
bit0  
bit0  
bit0  
bit0  
bit8  
HDR  
bit4  
SEC  
HDR  
bit4  
BLOCK  
HDR  
bit4  
MODE  
SHDR  
FILE  
bit4  
SHDR  
CH  
bit4  
SHDR  
S-MODE  
SHDR  
CI  
bit4  
bit4  
CMADR  
L
bit4  
CMADR  
H
0D  
XE  
X
X
bit12  
RAW  
MD2  
BIT  
RAW  
MD1  
RAW  
MD0  
FS  
C
C
MDFM  
ADPCI  
MODE  
FORM  
MONO  
STE  
EMPH  
ASIS  
XF MUTE  
18 bit7  
EOR  
bit5  
bit13  
bit5  
bit13  
bit5  
bit13  
X
X
X
L4H8  
L3H1  
DMA  
XFRC-L  
DMA  
bit6  
bit14  
bit6  
bit14  
bit6  
bit14  
X
bit2  
bit10  
bit2  
bit10  
bit2  
bit10  
X
bit1  
bit9  
bit1  
bit9  
bit1  
bit9  
X
bit0  
bit8  
bit0  
bit8  
bit0  
bit8  
X
bit4  
bit12  
bit4  
bit12  
bit4  
bit12  
X
bit3  
bit11  
bit3  
bit11  
bit3  
bit11  
X
19  
1A bit7  
1B  
1C bit7  
X
XFRC-H  
DMA  
ADRC-L  
DMA  
X
ADRC-H  
DRV  
ADRC-L  
DRV  
1D  
X
X
ADRC-H  
TEST  
10  
0 to 2  
to 2  
Read Registers  
—26—  
CXD1196AR  
32K Byte SRAM  
CXD2500  
3
4
5-11  
13-20  
24-31  
D/A CONVERTER  
32  
38  
LRCK  
LRCK  
WCKO  
LRCO  
45  
46  
DA16  
DATA  
BCLK  
34  
35  
44  
61  
37  
36  
34  
35  
DA15  
C2PO  
EMPH  
DATO 47  
C2PO  
EMP  
CXD1196AR  
BCKO  
MUTE  
48  
50  
INTP  
30  
44  
59  
XRST  
CXD2500 : 48-bit slot mode  
DRVIF register : LLHLHL  
64 65 66 67 68  
69-71  
74-78  
Note)  
CXD2500 is in 64-bit slot mode;  
CXD2500  
DA12 38  
DA14 36  
37  
CXD1196A  
38 LRCK  
37 DATA  
36 BCLK  
CPU  
DA13  
DRVIF register : LHLHXH  
VDD, GND pins excluded.  
CXD1196AR Connection Diagram  
—27—  
CXD1196AR  
Package Outline Unit : mm  
80PIN LQFP (PLASTIC)  
14.0 ± 0.2  
12.0 ± 0.1  
60  
41  
40  
61  
A
21  
(0.22)  
80  
1
20  
+ 0.05  
0.127 – 0.02  
+ 0.08  
0.18 – 0.03  
0.5  
0.13  
+ 0.2  
1.5 – 0.1  
M
0.1  
0.1 ± 0.1  
0° to 10°  
NOTE: Dimension “ ” does not include mold protrusion.  
PACKAGE STRUCTURE  
DETAIL A  
PACKAGE MATERIAL  
LEAD TREATMENT  
EPOXY RESIN  
SOLDER PLATING  
LQFP-80P-L01  
LQFP080-P-1212  
SONY CODE  
EIAJ CODE  
LEAD MATERIAL  
PACKAGE MASS  
42 ALLOY  
0.5g  
JEDEC CODE  
—28—  

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