CXD1217M [SONY]
Synchronizing Signal Generator for Video Camera; 同步信号发生器的摄像机
| 型号： | CXD1217M |
| 厂家： | 
SONY CORPORATION |
| 描述： | Synchronizing Signal Generator for Video Camera |
| 文件： | 总12页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD1217M
Synchronizing Signal Generator for Video Camera
Description
28 pin SOP (Plastic)
The CXD1217M is a synchronizing signal generator
for color video cameras.
Features
• Compatible with the respective systems, NTSC,
PALM, PAL and SECAM
• Output is synchronized with the clock of 910fH or
908fH
• 25Hz offset processing by PAL system
• Color framing by the respective systems, NTSC,
PALM and PAL
• Possible external synchronization by H reset, V
reset and line alternate reset pins
Applications
Synchronizing signal generator for color video
cameras
Structure
Silicon gate CMOS IC
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
VSS – 0.5 to +7.0
V
V
VSS – 0.5 to VDD + 0.5
VO VSS – 0.5 to VDD + 0.5
V
• Operating temperature Topr
• Storage temperature Tstg
–20 to +75
°C
°C
–55 to +150
Recommended Operating Conditions
• Supply voltage
VDD
4.5 to 5.5
V
• Operating temperature Topr
–20 to +75
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E89626A79-PS
CXD1217M
Block Diagram and Pin Configuration
INT-NTSC
10
9
4fscIN
1/4
PALM
2fH
19
OSC
fH
1/9
1/101
PAL
4fscOUT
INT-
NTSC
fH
CLOCK
ELIMINATION
PALM
1/7
1/81
1/2
PAL
fH
28
VDD
1/625
1/525
1/625, 1/525
PAL PALM
VSS 14
fv/2
fv/8
SC
PHASE
COMPARISON
1/4
24 HCOMOUT
RESET
PAL
FIELD 1
RESET
TEST 16
26
CLIN
1/4
SC
RESET
CLOUT 25
2
5
OFLD1
OFLD
1/454, 1/455
1/625, 1/525
MODE1 21
MODE2 22
2fH
1/2
DECODE
fH
7
OLALT
OBF/COLB
OBLK
3
COMPOSITE SIGNAL
CONTROL F.F.
EXT 20
LINE
6
ALTERNATE
RESET
LALTRI 15
4
OSYNC
OVD
12
8
HORIZONTAL
RESET
23
1
HRI
VRI
OHD
VERTICAL
RESET
27
OFH
17 O2FH
Note) Pin 19 output is (a) a signal based on Pin 26 in INT mode at NTSC.
(b) each signal is based on Pin 10 in other modes.
– 2 –
CXD1217M
Pin Description
Pin No.
1
Symbol
I/O
I
Description
VRI
Vertical reset signal
First field output
2
OFLD1
OBF/COLB
OSYNC
OFLD
OBLK
OLALT
OHD
O
O
O
O
O
O
O
O
I
3
Burst flag/color blanking output
Composite sync output
Even and Odd output
Composite blanking output
Line alternate output
Horizontal drive output
4fsc output
4
5
6
7
8
9
4fscOUT
4fscIN
NC
10
11
12
13
14
15
16
17
18
19
4fsc input
—
O
—
—
I
OVD
Vertical drive output
NC
VSS
GND pin
LALTRI
TEST
O2FH
NC
Line alternate reset input
Test input
I
O
—
O
2fH output (Double the frequency of Pin 27)
OSC
Sub carrier output
Internal and external synchronizing modes switchover
L: Internal synchronization H: External synchronization
20
EXT
I
21
22
23
24
25
26
27
28
MODE1
MODE2
HRI
I
I
System selecting input 1
System selecting input 2
Horizontal reset input
Phase comparator output
Clock output
I
HCOMOUT
CLOUT
CLIN
O
O
I
Clock input
OFH
O
—
Horizontal frequency output
Power supply pin
VDD
– 3 –
CXD1217M
Electrical Characteristics
DC characteristics
(VDD = 5V ± 10%, VSS = 0V, Topr = –20 to +75°C)
Item
Symbol
Conditions
IOH = –2mA
Min.
VDD – 0.5
VSS
Typ.
Max.
VDD
0.4
Unit
V
VOH
VOL
VOH
VOL
VOH
VOL
VIH
Output voltage 1
IOL = 4mA
IOH = –4mA
IOL = 4mA
IOH = –4mA
IOL = 8mA
V
VDD – 0.5
VSS
VDD
0.4
V
1
2
Output voltage 2
Output voltage 3
Input voltage
V
VDD/2
V
VDD/2
V
0.7VDD
20
V
VIL
0.3VDD
120
V
3
Input current
(Pull-down pin)
IIH
VIH = VDD
50
±30
8
µA
nA
mA
Ω
Output leak
ILZ
At high impedance
At output pin in no-load
VDD = 5V
1
current
Power current
supply
IDD
RFB
Feedback
resistance
250k
2.5M
4
1
HCOMOUT pin
2
4fscOUT and CLOUT pins
3
4
LALTRI, TEST, EXT, MODE1 and MODE2 pins
4fscOUT, 4fscIN, CLOUT and CLIN pins
I/O capacitance
(VDD = VI = 0V, fM = 1MHz)
Item
Input pin
Symbol
CIN
Conditions
Min.
—
Typ.
—
Max.
9
Unit
pF
Output pin
COUT
—
—
11
pF
– 4 –
CXD1217M
Description of Operation (See Block Diagram.)
The CXD1217 is applicable to four systems; namely, NTSC, PAL, PALM and SECAM. In order to realize them,
the following relative equations of Sub-carrier (4fsclN) and Clock (CLIN) are adopted .
Sub carrier
4fsc = 910fH
4fsc = 1135fH + 2fv
4fsc = 909fH
—
Clock
910fH
908fH
910fH
908fH
NTSC
PAL
PALM
SECAM
As it is obvious from the above equations, the 4fsc and clock frequency do not coincide with each other in the
PAL and PALM. Therefore matching of the clock frequency is carried out by providing PLL.
1 . MODE specified input
The CXD1217 provides four inputs to specify the respective modes.
EXT input: Set this pin to VDD side, and it becomes into external synchronizing mode. At this time, the
counters in connection with the PLL Ioop as shown in the upper part of the block diagram
become into stand still state.
MODE1 and MODE2 inputs: These are inputs for the system selection.
MODE1
MODE2
System
NTSC
SECAM
PALM
PAL
0
0
1
1
0
1
0
1
"0" → VSS
"1" → VDD
TEST input: An input to be used to measure IC. This input is normally kept opened.
(Because it is dropped internally to Vss with MOS resistance.)
2. Reset operation
The CXD1217 has three reset inputs ; namely, HRI, VRI, LALTRI, and it works to perform reset operation
when it detects falling edge. These three inputs are so designed as to take in synchronization with the IC
internal clock. Therefore, it is a prerequisite that both systems should have clock frequencies that are matched
as a reset operation to each other (GEN Iocked).
• H reset (HRI input)
When the HRI input is continuous with H synchronization, resetting is activated with the initial falling edge,
and for the subsequent edges they do not have to be reset unless they are deviated more than 2-bit (140ns)
against the initial edge in the internal clock. That is, if the jitter of HRI input is less than 140ns, it is absorbed.
The minimum resetting pulse width is over 0.3µs.
The phase to be reset is the advanced point of 6.3 to 6.37µs (= 90 to 91-bit × 70ns) than the HRI input as
shown in the diagram below.
HRI input
CXD1217
HD OUT output
Reset
6.3 to 6.37 [µs]
– 5 –
CXD1217M
• V reset (VRI input)
When the VRI is input as shown in figure below, OSYNC can be reset at the same phase with the SYNC signal.
Counter State
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SYNC Signal
VRI
Falling edge permitted span
a
a
Rising edge is to be behind from point
CXD1217 internal clock (2fH)
(See Timing Chart Diagram)
V reset pulse
9
10
11
12
After reset SYNC OUT
13
14
Reset State
Since the falling edge point in the diagram above (marked with ↑) is the boundary of reset, if the falling edge
of the VRI input traverses that point, it causes 1/2H deviation to the reset state.
Accordingly, if resetting is applied between two similar systems whose frequency are different, the V to which
resetting is applied generates jitter of 1/2H. (When the resetting is applied continuously.)
• LALT reset (LALTRI input)
Phase relation between LALTRI pulse polarity and 2fH is the same as in the case of V resetting.
Resetting operation is basically required only in the external synchronizing mode (GEN LOCK mode). However,
even in the internal synchronizing mode, it sometimes requires H and V outputs whose phases are deviated
against a certain output. In that case, it suffices to use two CXD1217s and conduct the operation as follows:
Clock
VRI2
CXD1217
CXD1217
VRI2
OHD1 OVD1
OHD2 OVD2
Shift Reg.
Clock
Input
Output
Delay
It suffices to set IC-1 and IC-2 into INT mode.
By varying the Delay and Shift Reg. of the above diagram, any phases of OHD2 and OVD2 can be provided
against the respective OHD1 and OVD1.
3. Color framing
In the case of internal synchronization in the individual NTSC, PAL and PALM systems, the phase
relationships between SYNC of the 1st field and sub-carrier are kept stable regardless of the power supply
being ON or OFF. However, as the PAL and PALM systems are comprised of PLL, the absolute values
concerning the phase according to variation of the ambient temperature drifts.
– 6 –
CXD1217M
Timing Chart
Output Timing Chart Diagram
CXD1217 NTSC, PALM
Field 1 ODD
2 EVEN
3 ODD
SYNC OUT
4 EVEN
12H
Field 1
2
3
4
BF/COLB OUT
(PALM)
Field 1
2
3
4
LALT OUT
(PALM)
10H
ODD
BF/COLB OUT
(NTSC)
EVEN
ODD
HD OUT
EVEN
20H
ODD
BLK OUT
VD OUT
EVEN
9H
ODD
FLD OUT
EVEN
FLD1 OUT (fv/4)
(NTSC)
3H
Field 1
Field 1
FLD1 OUT (fv/8)
(PALM)
3H
CLIN
4fscIN
(NTSC) (PALM)
SC OUT
– 7 –
CXD1217M
CXD1217 PAL, SECAM
Field 4 EVEN
1 ODD
SYNC OUT
2 EVEN
3 ODD
10H
Field 4
1
2
3
BF/COLB OUT
(PAL)
Field 4
1
2
3
LALT OUT
(PAL)
9H
9H
7H
EVEN
ODD
BF/COLB OUT
(SECAM)
9H
8.5H
7H
EVEN
ODD
HD OUT
25H
EVEN
ODD
BLK OUT
OVD
7.5H
EVEN
ODD
FLD OUT
FLD1 OUT (fv/8)
(PAL)
2.5H
2.5H
FLD1 OUT (fv/4)
(SECAM)
4fscIN
(PAL)
SC OUT
– 8 –
CXD1217M
– 9 –
CXD1217M
Application Circuit
Basic connection in individual systems
Basic connection in individual systems at internal synchronization mode (EXT input = "0") is as follows. See
waveform diagram for each output.
• NTSC
14.318MHz ( = 910fH)
VDD
19
26
28
14
25
OSC
CLOUT CLIN
VDD
VSS
HRI
VRI
23
1
Synthesizer
1/4
OLALT
4fscIN
4fscOUT
10
9
17
27
8
12
4
6
3
7
5
2
H/2 is output for LALT OUT even in NTSC mode.
MODE1, MODE2, EXT, TEST and LALTRI pins can be kept open.
(If noise annoys, connect to Vss by low impedance.)
• PAL
14.187MHz ( = 908fH)
VCO
L. P. F
VDD
OSC
19
10k
10k
28
VDD MODE1 MODE2
21
22
24
HCOMOUT
26
CLIN
25
CLOUT
14
VSS
1/4
4fsc
IN
10
9
Phase
Comparison
HRI
23
1
f'H
fH
Synthesizer
VRI
4fsc
Clock
Elimination
1/7
1/81
OUT
17.734MHz
(4fsc)
S. C.
Reset
1/2
Field
1/8
1/625
17 27
8
12
4
6
3
7
5
2
Inverter of CLIN or CLOUT pins are usable as VCO.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 10 –
CXD1217M
• PALM
14.318MHz ( = 910fH)
VCO
L. P. F
VDD
OSC
19
10k
28
VDD MODE1
21
24
26
CLIN
25
CLOUT
14
HCOMOUT
VSS
1/4
4fsc
IN
10
9
Phase
Comparison
HRI
VRI
23
f'H
fH
Synthesizer
4fsc
1
1/9
1/101
1/525
OUT
14.302MHz
(4fsc)
S. C.
Reset
1/8
Field
1
17 27
8
12
4
6
3
7
5
2
Internal inverter is usable as VCO.
• SECAM
VDD
14.187MHz ( = 908fH)
10k
25
CLOUT
26
14
28
22
MODE2
CLIN
VSS
VDD
4fscIN
10
9
HRI
23
1
Synthesizer
VRI
17 27
8
12
4
6
3
7
5
2
COLB is output to BF/COLB OUT pin.
SDR and SDB are formed in PLL using 908fH.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 11 –
CXD1217M
Package Outline
Unit: mm
28PIN SOP (PLASTIC)
+ 0.4
18.8 – 0.1
+ 0.4
2.3 – 0.15
28
15
0.15
+ 0.2
0.1 – 0.05
1
14
+ 0.1
0.15 – 0.05
1.27
0.45 ± 0.1
M
0.24
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER PLATING
42/COPPER ALLOY
SONY CODE
EIAJ CODE
SOP-28P-L02
SOP028-P-0375
PACKAGE MASS
JEDEC CODE
0.6g
– 12 –
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