CXD1185CR [SONY]
SCSI 1 Protocol Controller; 1 SCSI协议控制器
| 型号： | CXD1185CR |
| 厂家： | 
SONY CORPORATION |
| 描述： | SCSI 1 Protocol Controller |
| 文件： | 总35页 (文件大小：360K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXD1185CQ/CR
SCSI 1 Protocol Controller
For the availability of this product, please contact the sales office.
Description
CXD1185CQ
CXD1185CR
The CXD1185C is a high performance CMOS
SCSI controller LSI that conforms to ANSIX3. 131-
1986 standards. The CXD1185C is capable of
operating in both initiator and target modes. It
satisfies all standard SCSI bus features, such as
arbitration, selection and parity generation/check
functions. A 24-bit data transfer byte counter and
16-byte FIFO are built into the hardware. Two
separate buses for data and processor makes high
speed data transfer possible. 48 mA (sinking) port
is built-in to achieve reduction in the number of
external components.
64 pin QFP (Plastic)
64 pin LQFP (Plastic)
• Supports SCSI phase commands.
• All SCSI control signal are software controllable.
• All interrupt conditions are software maskable.
• Built-in 4-bit general-use I/O port.
The chip offers a set of high level commands at
SCSI phase level. It is also possible to read/write all
individual SCSI signals. The combination of the
above two makes programs simpler and at the same
time improves programmability.
• Programmable SCSI RST drive time.
• Programmable interrupt pin (IRQ) active logic level.
• Single initiator mode detection logic.
• Selection phase SCSI parity check/ignore switch.
• Pin compatible with CXD1185AQ.
Features
(CXD1185CQ only)
• Satisfies all SCSI bus features, including
arbitration, selection, parity generation/check and
synchronous data transfer.
• Comes in 64-pin QFP or 64-pin LQFP
Applications
• Maximum synchronous data transfer rate of 4.0
MB/s and maximum asynchronous data transfer
rate of 2.5 MB/s.
SCSI controller
Structure
• Provides two separate ports for the data bus and
the CPU bus.
CMOS Process
• Built-in user-programmable timer for selection
/reselection time-out operation.
Absolute Maximum Ratings (Ta=25 °C, VSS=0 V)
• Supply voltage
• Input voltage
• Output voltage
VDD
VI
VSS–0.5 to +7.0
VSS–0.5 to VDD +0.5
VSS–0.5 to VDD +0.5
V
V
V
• Supports 8-bit microcomputer bus.
• Support programmed I/O and DMA transfer.
• Built-in 48 mA (sinking) SCSI port. The SCSI port
can be used as either single-ended port or
differential port.
VO
• Operating temperature
Topr
• Storage temperature
Tstg
–20 to +75
°C
°C
• Built-in 24-bit data transfer counter.
• Built-in 16-byte FIFO.
–55 to +150
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E92905B78-TE
CXD1185CQ/CR
Block Diagram (CXD1185CQ)
Reset
Control
20
18
29
RES
RST
BSY
Arbiration
Control
+
17
22
24
ATN
MSG
C/D
33-40
SCSI
Control
C7-C0
I/O 28
Selection
Control
+
23
SEL
Time-Out
Sync Transfer Control
–1
Interrupt Request
Interrupt Mask
Transfer Byte
Counter
+
25
19
43
DRQ
REQ
ACK
44 DACK
42 IRQ
DMA Control
+
+
Configuration
57
CLK
FIFO Counter
59 INIT
60
Command
Interpreter
Command
Status
5, 7-10, 12-14
TARG
DB7-DB0
FIFO
ID
D7-D0
Differential
Control
47-54
61-64
General-Use
I/O Port
+
P3-P0
1-4
Parity
A3-A0
Generate/Check
55
DP
CS
WE
RE
30
32
31
DBP 15
Decode
—2—
CXD1185CQ/CR
Block Diagram (CXD1185CR)
Reset
Control
18
16
27
RES
RST
BSY
Arbiration
Control
+
15
20
22
ATN
MSG
C/D
31-38
SCSI
Control
C7-C0
I/O 26
Selection
Control
+
21
SEL
Time-Out
Sync Transfer Control
–1
Interrupt Request
Interrupt Mask
Transfer Byte
Counter
+
23
17
41
DRQ
REQ
ACK
42 DACK
40 IRQ
DMA Control
+
+
Configuration
55
CLK
FIFO Counter
57 INIT
58
Command
Interpreter
Command
Status
3, 5-8, 10-12
TARG
DB7-DB0
FIFO
ID
D7-D0
Differential
Control
45-52
59-62
General-Use
I/O Port
+
P3-P0
63, 64, 1, 2
Parity
Generate/Check
A3-A0
53
DP
CS
WE
RE
28
30
29
DBP 13
Decode
—3—
CXD1185CQ/CR
Pin Configuration
48
33
51
33
49
32
52
32
20
CXD1185CQ
CXD1185CR
64
1
19
64
17
1
16
Pin Description
Pin No.
Symbol
I/O
Description
CXD1185CQ CXD1185CR
1
63
64
1
A3
A2
I
I
I
I
Register select signal bit 3
Register select signal bit 2
Register select signal bit 1
Register select signal bit 0
2
3
A1
4
2
A0
5
3
DB0
VSS
I/O SCSI bus DB0 signal
GND <note 1>
6
4
7
5
DB1
DB2
DB3
DB4
VSS
I/O SCSI bus DB1 signal
I/O SCSI bus DB2 signal
I/O SCSI bus DB3 signal
I/O SCSI bus DB4 signal
GND <note 1>
8
6
9
7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DB5
DB6
DB7
DBP
VSS
I/O SCSI bus DB5 signal
I/O SCSI bus DB6 signal
I/O SCSI bus DB7 signal
I/O SCSI bus DBP signal, odd parity
GND <note 1>
ATN
BSY
ACK
RST
VSS
I/O SCSI bus ATN signal
I/O SCSI bus BSY signal
I/O SCSI bus ACK signal
I/O SCSI bus RST signal
GND <note 1>
MSG
SEL
C/D
REQ
VDD
VSS
I/O SCSI bus MSG signal
I/O SCSI bus SEL signal
I/O SCSI bus C/D signal
I/O SCSI bus REQ signal
+5 V <note1>
GND <note 1>
I/O
I/O SCSI bus I/O signal
—4—
CXD1185CQ/CR
Pin No.
Symbol
I/O
Description
CXD1185CQ CXD1185CR
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
RES
CS
I
I
I
I
Reset all registers, negative logic
Chip select signal, negative logic
RE
Internal register read signal, negative logic
Internal register write signal, negative logic
WE
C7
I/O CPU bus bit 7
I/O CPU bus bit 6
I/O CPU bus bit 5
I/O CPU bus bit 4
I/O CPU bus bit 3
I/O CPU bus bit 2
I/O CPU bus bit 1
I/O CPU bus bit 0
GND <note1>
C6
C5
C4
C3
C2
C1
C0
VSS
IRQ
DRQ
DACK
WED
RED
D0
O
O
I
Interrupt request signal
DMA request signal
DMA acknowledge signal, negative logic
Data bus write signal, negative logic <note3>
Data bus read signal, negative logic <note3>
I
I
I/O Data bus bit 0 <note3>
I/O Data bus bit 1 <note3>
I/O Data bus bit 2 <note3>
I/O Data bus bit 3 <note3>
I/O Data bus bit 4 <note3>
I/O Data bus bit 5 <note3>
I/O Data bus bit 6 <note3>
I/O Data bus bit 7 <note3>
I/O Data bus parity signal <note4>
GND <note1>
D1
D2
D3
D4
D5
D6
D7
DP
VSS
CLK
VDD
INIT
TARG
I
Clock input, 5 –16 MHz
+5 V <note1>
O
O
Initiator operation indicator signal
Target operation indicator signal
General-use port bit 0 (SCSI data output authorization)
<note2>
61
59
P0 (DOE) I/O
62
63
64
60
61
62
P1 (ARB) I/O General-use port bit 1 (arbitration in progress)
P2 (BSYO) I/O General-use port bit 2 (SCSI BSY output)
P3 (SELO) I/O General-use port bit 3 (SCSI SEL output)
<note2>
<note2>
<note2>
<Note1> All VDD and VSS pins should be connected to the power supply and ground, respectively.
<Note2> Items in parentheses ( ) indicate the meaning of the signal when operating in the SCSI differential
mode.
<Note3> In systems where the CPU and data buses are not separate, connect the WED and RED pins to
WE and RE, respectively, and Pins D7-D0 to Pins C7-C0.
<Note4> If the data bus parity signal is not used, pull up the DP pin using a resistor.
—5—
CXD1185CQ/CR
Electrical Characteristics
DC characteristics
Item
Symbol
VDD
Conditions
Min.
4.5
Typ.
5.0
Max.
Unit
V
Supply voltage
5.5
High level input voltage
Low level input voltage
SCSI bus pin input voltage hysteresis
High level output voltage
Low level output voltage
SCSI bus pin output voltage
Input leak current
VIHT
2.2
V
VILT
0.8
V
(VT+)–(VT–)
VOH
0.2
V
IOH=–2 mA
VDD–0.5
V
VOL
IOL=4 mA
0.4
0.5
10
V
VOLS
ILI1
IOL=48 mA
V
–10
–40
µA
µA
Input leak current (bidirectional pin)
ILI2
40
I/O Capacitance
Item
Symbol
CIN
Min.
Typ.
Max.
9
Unit
pF
Input pin
Output pin
COUT
CI/O
11
pF
Input/Output pin
11
pF
AC characteristics
(Ta=–20 to +75 °C, VDD=5 V±10 %)
The following capacitances are assumed : input, output pins : 65 pF, input/output pins : 125 pF
Clock input
Tcyc
CLK
Tcklw
Tckhw
Item
Symbol
Min.
5
Typ.
Max.
16
Unit
MHz
ns
Clock cycle
Tcyc
Tcknw
Tcklw
Clock pulse high level width (cycle : 16 MHz)
Clock pulse low level width (cycle : 16 MHz)
31
31
33
33
ns
Reset input
RES
Tresw
Item
Symbol
Tresw
Min.
100
Typ.
Max.
Unit
ns
Reset pulse width
—6—
CXD1185CQ/CR
Register write
A3-A0
Tahw
Tasw
CS
Tcssw
Tcshw
Tww
WE
Tchw
Tcsw
C7-C0
Tpdw
P3-P0
Item
Symbol
Tasw
Tcssw
Tww
Min.
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time (vs. WE ↓)
CS setup time (vs. WE ↓)
WE pulse width
0
0
70
30
0
Date setup time (vs. WE ↑)
Address hold time (vs. WE ↑)
CS hold time (vs. WE ↑)
Data hold time (vs. WE ↑)
Port delay time (vs. WE ↑)
Tcsw
Tahw
Tcshw
Tchw
Tpdw
0
10
100
Register read
A3-A0
Tahr
Tasr
CS
Tcssr
Tcshr
Tchr
RE
Tcdr
C7-C0
Tpsr
Tphr
P3-P0
Item
Address setup time (vs. RE ↓)
CS setup time (vs. RE ↓)
Data delay time (vs. RE ↓)
Address hold time (vs. RE ↑)
CS hold time (vs. RE ↑)
Symbol
Tasr
Min.
0
Typ.
Max.
130
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Tcssr
Tcdr
0
Tahr
0
0
5
0
Tcshr
Tchr
Date hold time (vs. RE ↑)
Port setup time (vs. RE ↓)
Port hold time (vs. RE ↑)
25
0
Tpsr
Tphr
—7—
CXD1185CQ/CR
DMA write
DRQ
Tdrlda
Tdrhda
DACK
WED
Tdahl
Tdasw
Tww
Tdahw
Tdhw
Tdsw
D7-D0, DP
Item
Symbol
Tdrlda
Tdasw
Tww
Min.
Typ.
Max.
70
Unit
ns
ns
ns
ns
ns
ns
ns
ns
DRQ fall time (vs. DACK ↓)
DACK setup time (vs. WED ↓)
WED pulse width
0
50
20
10
10
Data setup time (vs. WED ↑)
DACK hold time (vs. WED ↑)
Data hold time (vs. WED ↑)
DRQ rise time (vs. DACK ↑)
DACK fall time (vs. DACK ↑)
Tdsw
Tdahw
Tdhw
Tdrhda
Tdahl
110
50
DMA read
DRQ
Tdrlda
Tdrhda
DACK
RED
Tdasr
Tdahl
Tdahr
Tdhr
Tddr
D7-D0, DP
Item
DRQ fall time (vs. DACK ↓)
DACK setup time (vs. RED ↓)
Data delay time (vs. RED ↓)
DACK hold time (vs. RED ↑)
Data hold time (vs. RED ↑)
DRQ rise time (vs. DACK ↑)
DACK fall time (vs. DACK ↑)
Symbol
Tdrlda
Tdasr
Tddr
Min.
Typ.
Max.
70
Unit
ns
ns
ns
ns
ns
ns
ns
0
90
Tdahr
Tdhr
10
5
25
Tdrhda
tdahl
110
50
—8—
CXD1185CQ/CR
Initiator asynchronous transfer output
REQ
Tahrh
Talrl
ACK
Tdsa
Tdhr
DBn
Item
Symbol
Talrl
Min.
55
Typ.
Max.
120
Unit
ns
ACK fall time (vs. REQ ↓)
Data setup time (vs. ACK ↓)
ACK rise time (vs. REQ ↑)
Data hold time (vs. REQ ↑)
Tdsa
Tahrh
Tdhr
ns
90
ns
195
ns
Initiator asynchronous transfer input
REQ
Talrl
Tahrh
ACK
Item
ACK fall time (vs. REQ ↓)
ACK rise time (vs. REQ ↑)
Symbol
Talrl
Min.
Typ.
Max.
120
90
Unit
ns
Tahrh
ns
Target asynchronous transfer output
REQ
Trlah
Trhal
ACK
Tdsr
Tdha
DBn
Item
Data setup time (vs. REQ ↓)
REQ rise time (vs. ACK ↓)
Data hold time (vs. ACK ↓)
REQ fall time (vs. ACK ↑)
Symbol
Tdsr
Min.
55
Typ.
Max.
Unit
ns
Trhal
Tdha
Trlah
90
ns
195
120
ns
ns
Target asynchronous transfer input
REQ
Trlah
Trhal
ACK
Item
REQ rise time (vs. ACK ↓)
REQ fall time (vs. ACK ↑)
Symbol
Trhal
Min.
Typ.
Max.
90
Unit
ns
Trlah
120
ns
—9—
CXD1185CQ/CR
Initiator synchronous transfer output
CLK
REQ
ACK
Talckh
Tahckh
Tdhckh
DBn
Item
ACK fall time (vs. CLK ↑)
ACK rise time ((vs. CLK ↑)
Data hold time (vs. CLK ↑)
Symbol
Min.
Typ.
Max.
130
100
170
Unit
ns
Talckh
Tahckh
Tdhckh
ns
ns
Target synchronous transfer output
CLK
Trlckh
Trhckh
Tdhckh
REQ
ACK
DBn
Item
REQ fall time (vs. CLK ↑)
REQ rise time ((vs. CLK ↑)
Data hold time (vs. CLK ↑)
Symbol
Trlckh
Min.
Typ.
Max.
130
100
170
Unit
ns
Trhckh
Tdhckh
ns
ns
—10—
CXD1185CQ/CR
Description of Functions
1. Internal registers
The CXD1185C possesses 16 internal registers. The CPU can control the CXD1185C by reading and
writing these registers.
A summary of the registers is provided below.
Address
Read
Write
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Status
Command
SCSI data
←
Interrupt request 1
Interrupt request 2
SCSI control monitor
FIFO status
<
>
Environment setting
Selection/reset timer
<
>
SCSI ID
←
←
←
←
←
←
←
←
←
←
Transfer byte counter (low)
Transfer byte counter (middle)
Transfer byte counter (high)
Interrupt authorization 1
Interrupt authorization 2
Mode
Sync transfer control
SCSI bus control
I/O port
<
> No register assigned to this address.
1-1. Status register (R0 : R)
This register is used to monitor the status of the CXD1185C.
7
6
5
4
3
2
1
0
MRST MDBP
INIT
TARG TRBZ MIRQ
CIP
MRST : Monitors the SCSI bus RST signal, positive logic.
MDBP : Monitors the SCSI bus DBP signal, positive logic.
INIT
: “1” when the CXD1185C is in initiator status.
When this bit is set to “1”, commands which are valid in target status and in initiator status are
accepted.
TARG : “1” when the CXD1185C is in target status.
When this bit is set to “1”, commands which are valid in initiator status and in target status are
accepted.
TRBZ : When this bit is set to “1”, it indicates that the transfer byte counter count is zero.
MIRQ : Monitors the interrupt request signal (IRQ signal).
This bit is set whenever interrupt request occurs and cleared once interrupt request 1 register and
interrupt 2 register are read. This bit is not affected by the content of the interrupt authorization
register. The logic level of this bit is not affected by the SIRM bit in the environment setting register.
CIP
: Indicates that a chip command is being executed.
While this bit is “1”, no new commands can be written to the command register, with the exception
of the “Reset Chip” command.
—11—
CXD1185CQ/CR
1-2. Command register (R0 : W)
This is the register to which CXD1185C commands are written.
When a command is written to this register, status register bit 0 (CIP) is set. When the command is executed
and terminated, interrupt request register 2 bit 7 (FNC) is set, and the CIP bit and command register are
cleared.
7
6
5
4
3
2
1
0
CAT1 CAT0
DMA
TRBE CMD3 CMD2 CMD1 CMD0
CAT1, CAT0 :
Sets the category code given to the CXD1185C.
CXD1185C commands are divided into the following four categories :
CAT1
CAT0
Mode
0
0
1
1
0
1
0
1
Commands which are valid in any status
Commands which are valid in disconnected status
Commands which are valid in target status
Commands which are valid in initiator status
If the current status of the CXD1185C does not match with the category code in the command
received, the CIP and command registers are cleared. No interrupt is generated in this case.
DMA : DMA mode
When this bit is set to “1” and a transfer command is executed, DMA transfer takes place via the
data bus (D7-D0). During the DMA transfer, any attempts by the CPU to read/write SCSI data
register via CPU bus is ignored.
TRBE : Activates the transfer byte counter.
When this bit is set to “1” and a transfer command is executed, the transfer byte counter is
decremented each time a byte of data is transferred.
When the counter reaches “0” the next data request is stopped. At this point, if the mode where the
data is output to SCSI or DMA mode is “1”, the CXD1185C will continue to transfer any data
remaining in FIFO until it is empty. If a transfer command is executed when this bit is set to “0”, 1
byte of data will be transferred regardless of the value of the transfer byte counter and the
command will be terminated. In this case the transfer byte counter is not decremented. When DMA
bit is set, TRBE bit must also be set. These two bits can be set simultaneously during command
write.
—12—
CXD1185CQ/CR
CMD3, CMD2, CMD1, CMD0 :
Indicates the command code.
The CXD1185C responds to the following commands. See the command description section for
detailed information.
Category
0 0
DMA
0
TRBE
Command code
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
Command
0
0
0
0
0
0
0
0
0
0
0
0
0
No Operation
Reset Chip
Assert RST
Flush FIFO
0
0
0
0
Assert SCSI Control
Deassert SCSI Control
Assert SCSI Data
Deassert SCSI Data
Reselect
0
0
0
0 1
0
0
Select without ATN
Select with ATN
Enable Selection/Reselection
Disable Selection/Reselection
Send Message
0
0
0
1 0
Send Status
Send Data
0
0
Disconnect
Receive Message Out
Receive Command
Receive Data
1 1
Transfer Information
Transfer Pad
0
0
0
0
0
0
Deassert ACK
Assert ATN
Deassert ATN
<
> Set “1” to activate the mode, set “0” to inactivate the mode, except when the DMA bit is to “1”, TRBE bit
must also be set to “1”.
1-3. SCSI data register (R1: R/W)
This register is used when transferring data between the SCSI bus and the CPU bus.
When data is output to the SCSI bus via the CPU bus, data can be written to this register if the FIFO status
register bit 4 (FIF) is “0”.
When data is input from SCSI bus, data can be read from this register if the FIFO status register bit 7 (FIE) is
“0”.
When “Assert SCSI data” is executed, the 16 byte FIFO becomes a 1 byte FIFO. Any value written to the
register will be on the SCSI bus instantly and a read operation will return the current SCSI data bus value.
When a DMA transfer is performed via the data bus, reads and writes to the SCSI data register are
performed using the WED, RED and DACK signals.
1-4. Interrupt request registers 1 and 2
These registers show the cause of the interrupt.
When an interrupt authorized by interrupt authorization registers 1 or 2 is generated, the IRQ pin is set
immediately.
Bits in the interrupt request registers 1 and 2 are cleared once the registers are read by the CPU. When all
interrupt bits are cleared, MIRQ bit (in the status register) and the IRQ pin are cleared.
Note that interrupt bits in these registers are set regardless of the values in the interrupt authorization
registers. If interrupt requests are software polled, interrupt request registers 1 and 2 should only be read
when the MIRQ bit, in the status register, is “1”.
—13—
CXD1185CQ/CR
1-4-1. Interrupt request register 1 (R2 : R)
This register’s interrupt conditions can be masked in the interrupt authorization register 1.
When one of the bits in this register is set, MIRQ bit in the status register and IRQ signal are set. If the
interrupt bit is authorized in the interrupt authorization register 1, the IRQ pin is activated simultaneously.
7
6
5
4
3
2
1
0
STO
RSL
SWA SWOA ARBF
STO
RSL
: Selection Time Over
Indicates a time-out error during selection. Also, indicates that the SCSI bus RST signal has been
driven for the time set in the selection/reset timer if the mode register bit 4 (TMSL) is set to “1”. The
selection time-out time and SCSI bus RST signal drive time are determined by the value of the
selection/reset timer register.
: Reselected
Indicates that reselection has taken place. FNC bit in the interrupt register 2 is set after reselection.
The CPU may not write new commands to the command register until the FNC bit is set. This bit is
not set unless the “Enable Selection/Reselection” command is executed.
SWA : Selection With ATN
Indicates that selection has taken place with the SCSI bus ATN signal driven. FNC bit in the
interrupt register 2 is set after selection. The CPU may not write new commands to the command
register until the FNC bit is set. This bit is not set unless the “Enable Selection/Reselection”
command is executed.
SWOA : Selection Without ATN
Indicates that the selection has taken place. FNC bit in the interrupt register 2 is set after selection.
The CPU may not write new commands to the command register until the FNC bit is set. This bit is
not set unless the “Enable Selection/Reselection” command is executed.
ARBF : Arbitration Fail
Indicates that the CXD1185C lost in the arbitration for the right to use the SCSI bus. This bit is set
when, after receiving a selection/reselection command, the chip waited for bus free and entered
arbitration only to be encountered by another device with higher priority. As soon as this bit is set
the selection/reselection command is terminated. To participate in another arbitration a new
selection/reselection command must be written to the command register.
1-4-2. Interrupt request register 2 (R3 : R)
This register’s interrupt conditions can be masked in the interrupt authorization register 2.
When one of the bits in this register is set, MIRQ bit in the status register and IRQ signal are set. If the
interrupt bit is authorized in the interrupt authorization register 2, the IRQ pin is activated simultaneously.
7
6
5
4
3
2
1
0
FNC
DCNT SRST
PHC
DATN
DPE
SPE RMSG
FNC
: Function Complete
Indicates that the received command was executed and terminated.
DCNT : Disconnected
Indicates that a disconnect has taken place in the initiator mode.
SRST : SCSI Reset
Indicates that the SCSI bus RST pin was driven. This bit is also set when the “Assert RST”
command is executed.
—14—
CXD1185CQ/CR
PHC
: Phase Change
Indicates that the SCSI phase has been changed. This bit is set if the CXD1185C is operating in
the initiator mode and the target has changed the SCSI phase (MSG, I/O, C/D signal), and driven
REQ.
DATN : Drive ATN
Indicates that the SCSI bus ATN signal has been driven. This bit is set if the CXD1185C is
operating in the target mode and the initiator has driven the ATN signal.
: Data bus Parity Error
DPE
SPE
Indicates a parity error on the data bus. This bit is only set if environment setting register bit 5
(DPEN) is set to “1”. In initial status odd parity (environment register bit 6 set to “0”) is selected.
: SCSI bus Parity Error
Indicates a parity error on the SCSI bus. Parity check takes place during the selection phase and
data transfer phases.
RMSG : REQ in Message Phase
Indicates that the REQ signal has been driven during the message phase when the CXD1185C is in
initiator mode. This bit is used if two different batches of message data have been received during
the message phase or if the target requests the message to be resent.
1-5. Environment setting register (R3 : W)
This register is used to set the operating mode of the CXD1185C.
Normally, some value must be written to this register immediately after a hardware reset from the CPU.
7
6
5
4
3
2
1
0
DIFE SDPM DPEN SIRM
FS1
FS0
DIFE : Selects the differential mode.
When this bit is set to “1”, general-use I/O port Pins P3-P0 are assigned for differential mode bits.
SDPM : Selects the data bus parity condition.
This bit is set to “0” for odd parity and to “1” for even parity. However, its value is irrelevant if the
DPEN bit is set to “0”.
DPEN : Enables parity generation/check for the data bus.
If this bit is set to “1”, data bus parity signal is input/output via the DP pin.
SIRM : Select the IRQ signal logic level.
After a hardware reset is performed, the IRQ signal output is positive logic. To change the IRQ
signal to negative logic. “1” must be set in this bit. At this time, the logic level of MIRQ bit is not
affected.
FS1, FS0 :
Used to select the CXD1185C clock division ratio.
The appropriate values, as shown in the table below, must be written into these bits to match the
external clock frequency applied to the CXD1185C :
Input frequency (MHz)
FS1
0
FS0
0
Clock division ratio
16-13
12-9
8-5
4
3
2
0
1
1
For the changes made to these bits , “Chip Reset” command must be executed.
Bits FS1 and FS0 are set for a clock division ratio of “4” after a hardware reset.
—15—
CXD1185CQ/CR
1-6. SCSI control monitor register (R4 : R)
Current status of all SCSI bus control signals can be read directly from this register.
7
6
5
4
3
2
1
0
MBSY MSEL MMSG MCD
MIO
MREQ MACK MATN
MBSY : Monitors the SCSI bus BSY signal. Positive logic.
MSEL : Monitors the SCSI bus SEL signal. Positive logic.
MMSG : Monitors the SCSI bus MSG signal. Positive logic.
MCD : Monitors the SCSI bus C/D signal. Positive logic.
MIO
: Monitors the SCSI bus I/O signal. Positive logic.
MREQ : Monitors the SCSI bus REQ signal. Positive logic.
MACK : Monitors the SCSI bus ACK signal. Positive logic.
MATN : Monitors the SCSI bus ATN signal. Positive logic.
1-7. Selection/reset timer register (R4 : W)
This register is used to set the selection time-out time or the SCSI bus RST drive time.
The real selection time-out time can be calculated by the following equation :
Div
TIME (µs)
=
× (VAL+1) × 8,192
fcyc
fcyc : Input frequency (MHz)
Div : Clock division ratio (See section on Environment setting register)
VAL : Value written to the selection/reset timer register
Generally the selection time-out time is set to 250 ms.
When the selection/reset timer register is used to set the drive time for the RST signal, “1” must be written to
mode register bit 4 (TMSL).
The real RST signal drive time can be calculated by the following equation :
Div
TIME (µs)
=
× (32 × VAL+38)
fcyc
fcyc : Input frequency (MHz)
Div : Clock division ratio (See section on Environment setting register)
VAL : Value written to the selection/reset timer register
1-8. FIFO status register (R5 : R)
This register is for monitoring the FIFO status.
7
6
5
4
3
2
1
0
FIE
FIE
FC3
FC2
FC1
FC0
FIE
FIF
: FIFO Empty
Indicates that the FIFO is empty.
: FIFO Full
Indicates that the FIFO is full.
FC3, FC2, FC1, FC0 :
Indicates the number of bytes of data stored in the FIFO.
—16—
CXD1185CQ/CR
1-9. SCSI ID register (R6 : R/W)
This register is used to set the SCSI owner ID and the target ID for selection.
The upper three bits in this register have different meanings each for reads and writes.
7
6
5
4
3
2
1
0
(Read)
(Write)
SID2
SID1
SID0 SMOD
OID2
OID1
OID0
7
6
5
4
3
2
1
0
TID2
TID1
TID0
OID2
OID1
OID0
SID2, SID1,SID0
:
Indicates which device last selected/reselected the CXD1185C.
SMOD : When this bit is set to “1”, it shows that the chip was selected in single initiator environment. The
values in SID2, SID1, SID0 field become invalid. This bit is updated during selection phase.
TID2, TID1, TID0
The target ID is written to these bits prior to selection.
OID2, OID1, OID0 :
:
The owner ID is written to these bits.
1-10. Transfer byte counter (high, middle, low) (R9, R8, R7 : R/W)
The 24-bit counter calculates the number of transfer bytes during data transfer between SCSI bus and the
CPU bus or data bus. To activate the transfer byte counter, command register bit 4 (TRBE) must be set
when writing to the command register.
When data is output to the SCSI bus, the transfer byte counter is decremented at each rise of the WE or
WED signal. When data is input from the SCSI bus, it is decremented at each fall of the ACK signal when in
the initiator mode and at each fall of the REQ signal when in the target mode.
1-11. Interrupt authorization registers 1 and 2 (RA, RB : R/W)
These registers are used to determine on which interrupt the IRQ pin should be activated.
The bit positions in these two registers correspond to the bit positions in the interrupt request registers. The
IRQ pin will be activated if an interrupt bit becomes “1” and the corresponding bit in the interrupt authorization
register is also set to “1”. See section on Interrupt request registers land 2 for the meanings of each bit.
1-12. Mode register (RC : R/W)
This register is used for setting the modes of the CXD1185C.
7
6
5
4
3
2
1
0
HDPE HSPE HATN TMSL SPHI SSPE
BDMA
HDPE : When this bit is set to “1”, data transfer will be terminated if a parity error is detected on the data
bus during a data transfer. However, this bit is irrelevant if environment setting register bit 5
(DPEN) is set to “0”.
HSPE : When this bit is set to “1”, data transfer will be terminated if a parity error is detected on the SCSI
bus during a data transfer.
HATN : When this bit is “1” in target mode, data transfer will be terminated if an ATN signal is driven on the
SCSI bus.
TMSL : When this bit is set to “1”, the selection/reset timer register is used to set the duration of the SCSI
bus RST signal. This bit must not be overwritten with a new value if status register bit 0 (CIP) is set
to “1”. If it is required to drive RST signal when the CIP bit is “1”, first execute “Reset Chip”
command, then overwrite this bit.
—17—
CXD1185CQ/CR
SPHI : When this bit is set to “0”, if target changes the phase signal during the execution of a transfer
command and the REQ pin is active, interrupt request register 2 bit 4 (PHC) is set immediately. If
this bit is set to “1”, in the mode in which data is input from the SCSI bus, the PHC bit is not set until
all the FIFO contents are transferred to the CPU bus or the DMA bus.
SSPE : This bit makes it possible to change the behavior of the chip when there is parity error during
selection phase. When this bit is set to “1”, the chip will not respond to the selection. When this bit
is set to “0”, the chip will respond to the selection and causes a SCSI parity error interrupt.
BDMA : Burst DMA mode. When this bit is set to “1”, the DRQ pin outputs “1” for the whole of the DMA transfer.
1-13. Synchronous transfer control register (RD : R/W)
This register is used to set the transfer cycle and the offset for synchronous transfers.
7
6
5
4
3
2
1
0
TPD3 TPD2 TPD1 TPD0 TOF3 TOF2 TOF1 TOF0
TPD3, TPD2, TPD1, TPD0
:
Bits used to set the transfer cycle for synchronous transfers.
The transfer cycle is designated according to the following equation :
Div
fcyc × 2
RATE (µs) =
× (VAL+2)
fcyc : Input frequency (MHz)
Div : Clock division ratio (see section on Environment setting register)
VAL : Value written to TPD3-0
TOF3, TOF2, TOF1, TOF0
:
Bits used to set the offset for synchronous transfers.
The asynchronous transfer mode is selected by writing “0” to all of these bits.
1-14. SCSI bus control register (RE : R/W)
This register is used to control the control signals used by the SCSI bus.
Reading this register consists simply of reading the value which was written there previously. However, if the
“Assert SCSI Control” command is executed, “0”s will be read out. The “Assert SCSI Control” command
must be executed in order to output this register’s value to the SCSI bus.
7
6
5
4
3
2
1
0
ABSY ASEL AMSG ACD
AIO
AREQ AACK AATN
ABSY : When this bit is set to “1”, the SCSI bus BSY signal is driven.
ASEL : When this bit is set to “1”, the SCSI bus SEL signal is driven.
AMSG : When this bit is set to “1”, the SCSI bus MSG signal is driven.
However, it is not driven unless the CXD1185C is in the target mode.
ACD
: When this bit is set to “1”, the SCSI bus C/D signal is driven.
However, it is not driven unless the CXD1185C is in the target mode.
: When this bit is set to “1”, the SCSI bus I/O signal is driven.
However, it is not driven unless the CXD1185C is in the target mode.
AIO
AREQ : When this bit is set to “1”, the SCSI bus REQ signal is driven.
However, it is not driven unless the CXD1185C is in the target mode.
AACK : When this bit is set to “1”, the SCSI bus ACK signal is driven.
However, it is not driven unless the CXD1185C is in the initiator mode.
AATN : When this bit is set to “1”, the SCSI bus ATN signal is driven.
However, it is not driven unless the CXD1185C is in the initiator mode.
—18—
CXD1185CQ/CR
1-15. I/O port (RF : R/W)
This register is used for input/output switching of the general-use 4-bit port and for reading/writing the
contents of the port.
7
6
5
4
3
2
1
0
PCN3 PCN2 PCN1 PCN0 PRT3 PRT2 PRT1 PRT0
PCN3, PCN2, PCN1, PCN0 :
These bits are used for input/output switching of individual bits when Pins P3-P0 are used as a general-use
port. When a “1” is written to any of these bits, the corresponding port is set to the output mode.
All these bits are cleared when a hardware reset is performed. Note that first “0” must be written to all these
bits before writing a “1” to environment setting register bit 7 (DIFE).
PRT3, PRT2, PRT1, PRT0
This is the 4-bit I/O port.
:
The values written to whichever of these four bits have been set to output mode by PCN3-PCN0 are output
via Pins P3-P0. By reading these bits it is possible to monitor the values of Pins P3-P0 directly.
2. Command Description
This section gives description of all the commands supported by the CXD1185C.
With the exception of “Reset Chip”, the following commands can only be written to the command register
when the CIP bit in the status register (bit 0) is “0”.
2-1. Commands valid in any status
The following commands can be issued when the CXD1185C is in any of its three statuses : disconnected,
initiator or target.
• No Operation
This command has no effect on the CXD1185C.
However, the FNC bit is set when the command is completed.
• Reset Chip
This command initializes the CXD1185C.
Except for the environment setting register, all registers of the CXD1185C are cleared. If the clock division
ratio is changed in the environment setting register, this command must be executed.
This command can be executed regardless of the value of the CIP bit.
• Assert RST
This command drives the SCSI bus RST pin.
When this command is executed, interrupt request register 2 bit 5 (SRST) is set and an interrupt is
generated. The SCSI RST signal is active for 25 µs. However, if the RST signal drive duration needs to
be changed, it is necessary to set mode register bit 4 (TMSL) to “1” and write the drive duration to the
selection/reset timer register before executing this command.
• Flush FIFO
Initializes FIFO.
—19—
CXD1185CQ/CR
• Assert SCSI Control
Outputs the value of the SCSI bus control register to the SCSI bus.
In initiator mode ACK and ATN signals can be asserted.
In target mode REQ, MSG, C/D and I/O signals can be asserted.
This instruction is only needed in program I/O transfer.
On program I/O, see 5-1.
• Deassert SCSI Control
Prohibits the content of the SCSI bus control register from being output to the SCSI bus.
Once the “Assert SCSI Control” command is executed, the SCSI bus control signal is output from the SCSI
bus control register until this command is executed.
Therefore, the drive of SCSI bus control signal must be prohibited depending on needs.
• Assert SCSI Data
Outputs the value of the SCSI data register to the SCSI bus.
However, data is not output in the following circumstances :
i) A phase change interrupt (PHC) is generated in initiator mode.
ii) In initiator receive mode (SCSI bus I/O signal is high).
iii) In target receive mode (SCSI bus I/O signal is low).
iv) The mode is neither initiator nor target.
This instruction is only needed in program I/O transfer.
On program I/O, see 5-1.
• Deassert SCSI Data
Prohibits the value of the SCSI data register from being output to the SCSI bus.
Once the “Assert SCSI Data” command is executed, the SCSI bus data signals are output from the SCSI
data register until this command is executed.
2-2. Commands valid in disconnected status
The following commands are valid only in disconnected status. If any of these commands are issued in any
other state, the CIP bit and the content of the command register are cleared immediately.
• Reselect
This command executes arbitration/reselection from disconnected status.
When this command is executed, the CXD1185C switches to the target mode.
Before issuing this command, the owner ID (OID2-0) and target ID (TID 2-0) values must be written in the
SCSI ID register.
• Select without ATN
This command executes arbitration/selection from disconnected status.
When this command is executed, the CXD1185C switches to the initiator mode. Before issuing this
command, the owner ID (OID2-0) and target ID (TID2-0) values must be written in the SCSI ID register.
• Select with ATN
This command executes arbitration/selection from disconnected status.
During selection the ATN signal is driven on the SCSI bus.
When this command is executed, the CXD1185C switches to the initiator mode. Before issuing this
command, the owner ID (OID2-0) and target ID (TID2-0) values must be set in the SCSI ID register. If,
after this command is executed, message-out phase is to be terminated, the “Deassert ATN” command
must be executed prior to the transfer of the last message byte.
—20—
CXD1185CQ/CR
• Enable Selection/Reselection
Activates selection/reselection interrupts.
When this command is executed, the FNC bit is set immediately and the contents of the CIP bit and
command register are cleared. Once this command is executed, RSL/SWA/SWOA interrupts (in interrupt
request 1 register) are set during selection/reselection phase. When one of the selection/reselection is
executed this will occur before the FNC interrupt.
Selection/reselection is automatically disabled for the cases below.
· Hardware reset
· Execution of “Reset Chip”
If one of the above conditions occurs, an “Enable Selection/Reselection” command must be reloaded in the
command register in order to accommodate selection/reselection interrupt.
• Disable Selection/Reselection
Prohibits any response to selection/reselection.
Once this command is executed, the RSL/SWOA/SWA interrupts in interrupt request register 1 will not be
generated.
2-3. Commands valid in target status
The following commands are valid only in target status.
If any of these commands are issued in any other state, the CIP bit and the content of the command register
are cleared immediately.
In the case of data send commands, the transfer data must not be written before the command is written in
the command register and the necessary SCSI phase change is confirmed by software. In target mode,
handshaking on the SCSI bus is terminated under the following conditions :
1. The REQ signal is in any state and if :
· a hardware reset is performed.
· the “Reset Chip” command is executed.
· the SCSI bus RST pin is driven.
2. The command completes with REQ inactive if :
· a parity error is generated on the SCSI bus or the data bus.
(However, this is not the case if the mode register HDPE and HSPE bits are set to “0”.)
· the SCSI bus ATN signal is driven.
(However, this is not the case if the mode register HATN bit is set to “0”.)
· while the transfer byte counter is in use :
the DMA bit is set to “1”, the status register TRBZ bit is set to “1” and the FIFO status register FIE bit is
set to 1, or in receive mode, the DMA bit is set to “0” and the status register TRBZ bit is set to “1”.
· while executing a single byte transfer :
the mode is send and the FIE bit is set to “1”,
or the mode is receive and FIFO status register bits FC3-FC0 are all set to “1”.
3. Handshaking is temporarily interrupted with REQ inactive if :
· while the transfer byte counter is in use :
the mode is send and the FIFO status register FIE bit is set to “1”,
or the mode is receive and the FIFO status register FIF bit is set to “1”.
· during synchronous transfer, the difference in the number of REQ and ACK reaches the offset specified
in the synchronous transfer register.
· the mode is receive, during synchronous transfer, the number of FIFO bytes remaining is fewer than the
offset specified in the synchronous transfer register.
—21—
CXD1185CQ/CR
• Send Message
The CXD1185C changes the phase to Message In by making the SCSI bus MSG and I/O signals active
and the C/D signal inactive. The message bytes are then sent.
If there is more than one message byte or if the message must be sent all at once, the transfer byte
counter must be used.
• Send Status
The CXD1185C changes the phase to Status and sends the status byte to the initiator.
It makes the SCSI bus I/O and C/D signals active and the MSG signal inactive.
• Send Data
The CXD1185C changes the phase to Data In and sends the data bytes to the initiator.
It makes the SCSI bus I/O signal active and MSG and C/D signals inactive.
If more than one data byte must be sent all at once, the transfer byte counter must be used.
• Disconnect
Makes all SCSI signals inactive, except for the RST signal.
• Receive Message Out
The CXD1185C changes the phase to Message In and receives the message bytes from the initiator.
It makes the SCSI bus MSG signal active and the I/O and C/D signals inactive.
If there is more than one message byte or if the message must be received all at once, the transfer byte
counter must be used.
• Receive Command
The CXD1185C changes the phase to Command and receives the command bytes from the initiator.
It makes the SCSI bus C/D signal active and MSG and I/O signals inactive.
If the command bytes must be received all at once, the transfer byte counter must be used.
• Receive Data
The CXD1185C changes the phase to Data Out and receives the data bytes from the initiator.
It makes the SCSI bus MSG, C/D and I/O signals inactive and receive the data bytes.
If more than one data byte must be received all at once, the transfer byte counter must be used.
2-4. Commands valid in initiator status
The following commands are valid only in initiator status.
If any of these commands are issued in any other state, the CIP bit and the content of the command register
are cleared immediately.
In the case of data send commands, the transfer data must not be written before the command is written in
the command register.
Once the execution of a transfer command is commenced in initiator mode, handshaking on the SCSI bus is
terminated under the following conditions :
1. The ACK signal is in any status and if :
· a hardware reset is performed.
· the “Reset Chip” command is executed.
· the SCSI bus RST pin is driven.
—22—
CXD1185CQ/CR
2. The command complete with ACK inactive if :
· phase change occurs and PHC bit in interrupt request register 2 is set to “1”.
If this is the case and the DMA bit is set to “1”, the DRQ signal also remains inactive.
· while the transfer byte counter is in use :
the DMA bit is set to “1”, the status register TRBZ bit is set to “1” and the FIFO status register FIE bit is
set to 1, or in receive mode, the DMA bit is set to “0” and the status register TRBZ bit is set to “1”.
· while executing a single byte transfer :
the mode is send and the FIE bit is set to 1,
or the mode is receive, FIFO status register bits FC3-FC0 are all set to “1”.
3. The command complete with ACK active if :
· the mode is receive and a parity error occurs on the SCSI bus.
(However, this is not the case if the mode register HSPE bit is set to “0”.)
· status is message-in phase, the TRBE bit is set to “0”, the REQ signal is active and a 1-byte message is
received.
Note that in the above two cases the “Deassert ACK” command must be executed afterwards.
4. Handshaking is temporarily interrupt with ACK inactive if :
· while the transfer byte counter is in use :
the mode is send and the FIFO status register FIE bit is set to “1”.
· during synchronous transfer, the difference in the number of REQ and ACK reaches the offset specified
in the synchronous transfer register.
· the mode is receive, during synchronous transfer, the number of FIFO bytes remaining is fewer than the
offset specified in the synchronous transfer register.
5. Handshaking is temporarily interrupt with ACK active if :
· while the transfer byte counter is in use :
the mode is receive and the FIFO status register FIF bit is set to “1”.
• Transfer Information
In the initiator mode, causes data transfer to take place.
• Transfer Pad
In the initiator mode, causes data transfer to take place.
Note that unlike “Transfer Information”, the data output by the CXD1185C are all “0”s and parity generation
is not performed.
In addition, no parity check is performed on any data input to the CXD1185C.
Except for these two exceptions, this command is identical to the “Transfer Information” command.
• Deassert ACK
Makes the SCSI ACK signal inactive.
• Assert ATN
Makes the SCSI ATN signal active.
• Deassert ATN
Makes the SCSI ATN signal inactive. After executing the “Select with ATN” or “Assert ATN” command, the
SCSI bus ATN signal remains active until this command is executed.
—23—
CXD1185CQ/CR
3. Reset Operation
There are four initializing methods for the CXD1185C :
• hardware reset
• execution of the “Reset Chip” command
• assertion of RST signal on the SCSI bus
• disconnect
3-1. Hardware reset
This returns the CXD1185C to its initial status.
However, environment setting register bit 1 (FS1) is set to “1”, making the initial clock division ratio to “4”. All
of the internal circuits are also initialized.
At this time, the selection/reselection interrupt are disabled.
3-2. Execution of the “Reset Chip” command
The CXD1185C can be initialized by “Reset Chip” command (command code “01”). This command is
effective regardless of the CIP bit in the status register.
This command resets all registers with the exception of the environment setting register.
All read only registers except for bits 7 and 6 of the status register and the SCSI control monitor register are
cleared.
Since the “Reset Chip” command clears all write registers, any SCSI bus signal being driven by the
CXD1185C will also be cleared.
At this time, the selection/reselection interrupt are disabled.
3-3. Assertion of RST signal on the SCSI bus
When the SCSI bus RST signal is active, signals on the SCSI bus being driven by the CXD1185C are made
inactive with the exception of the RST pin.
Bits 4 and 3 (INIT and TARG bits) are also cleared.
3-4. Disconnect
If the CXD1185C is operating in initiator mode and a disconnect interrupt is generated, a reset identical to the
one in 3-3 takes place.
4. Interrupt Operation
In this section various interrupts, generated by the CXD1185C, are discussed in greater detail. If the
internal interrupt conditions of the CXD1185C are satisfied, “1”s are written to the appropriate bits in
interrupt request registers 1 and 2 and the MIRQ bit in the status register. IRQ pin becomes active only if
the interrupt is authorized in the interrupt authorization registers.
4-1. Arbitration interrupt
When a selection command is executed, the CXD1185C waits for bus free. Once bus free is detected it
outputs the BSY signal and the owner ID to the SCSI bus and enters arbitration. If, during arbitration,
another device with higher priority enters arbitration or if the SEL signal is driven on the SCSI bus, arbitration
fails and ARBF is set to “1”. The FNC bit is also set a while later. However, if it is not in the bus free state
when the selection command is executed, the above operation is performed after bus free is detected. If
arbitration is successful it enters selection phase.
—24—
CXD1185CQ/CR
4-2. Interrupts when selected/reselected
After “Enable Selection/Reselection” is executed, if the owner ID and the SEL signal appear on the SCSI bus,
SWOA bit is set to “1”. If ATN signal also appear at the same time, SWA bit is set instead. If I/O signal
appears instead of ATN signal, then, RSL is set. When any interuppt is generated, the FNC bit is set to “1”
after a while (6 µs max.). The next command cannot be written in the command register till the bit is set.
4-3. Interrupts when selection/reselection command is executing
When any of “Reselect”, “Select without ATN” or “Select with ATN” command is executed, the CXD1185C
enters arbitration and after obtaining the right to use the SCSI bus it enters selection/reselection phased by
sending the target ID, the owner ID and SEL signal onto the bus. At this point, the value of the
selection/reset timer register is loaded into the hardware timer (not user accessible) and decrementing
begins. Note that TMSL bit in the mode register must be “1” for the loading to take place. If there is no
response from the target device by the time the hardware timer reaches “0”, selection time over occurs and
the STO bit is set to “1” and, afterward, the FNC bit is set to “1”.
4-4. Data transfer phase interrupts
• The RMSG and PHC bits are valid interrupts only when INIT bit (status register bit 4) is set to “1”. Also, the
DATN bit is valid only when the TARG bit (status register bit 3) is set to “1”. The SPE and DPE bits are
valid both in initiator and target modes.
• The RMSG bit is set to “1”, if, in initiator mode, the target device activates REQ after changing the SCSI
bus phase to either Message-In or Message-Out. If the message is of multiple byte, it is set each time
REQ in activated.
• The PHC bit is set to “1”, if, in initiator mode, the target device activates REQ after changing the SCSI bus
phase. If the new phase is either Message-In or Message-Out, RMSG bit is also set to “1”.
• The DATN bit is set to “1”, if, in target mode, the initiator asserts ATN on the SCSI bus. Once the interrupt
request register 2 is read by the CPU, the bit is cleared even if ATN continues to be active.
• The SPE bit is set when a parity error is detected on the SCSI bus during receive mode data transfer in
both initiator and target mode. In initiator mode, it is set on receiving the REQ. In target mode it is set on
receiving the ACK. The SPE bit is also set if parity error is detected during selection/reselection.
• DPE bit is set when a parity error is detected on the data bus while writing data into FIFO. It is set at the
rise of the FIFO write signal, WED. This bit is valid only if the DPEN bit in the environment setting register
is set to “1”. If the SDPM bit in the environment register is “1”, even parity check is carried out. Otherwise
odd parity check is carried out.
4-5. Other interrupt
• The SRST bit is set to “1” when the SCSI bus RST signal becomes active. It is also set if the “Assert RST”
command is executed and the CXD1185C drives the RST pin.
• The DCNT bit is set to “1” if the CXD1185C is operating in the initiator mode and the target device makes
the BSY signal on the SCSI bus inactive. Normally, in initiator mode, this bit is set at the end of a series of
SCSI operation when the SCSI bus phase becomes bus free.
5. Data Transfer
In this section procedures for transferring data to and from the CXD1185C is described. Data can be
transferred between the CPU and the CXD1185C in the following three ways :
1. Program I/O transfer
2. CPU I/O transfer
3. DMA transfer
—25—
CXD1185CQ/CR
5-1. Program I/O transfer
This method is used to transfer data between the CPU bus and the CXD1185C. The CPU manages SCSI
handshaking entirely through software. By issuing the “Assert SCSI Control” and “Assert SCSI Data”
commands, all of the SCSI bus bits can be software controlled. After the above two commands are issued,
values can be written to the SCSI bus control register and the SCSI data register to carry out the SCSI
handshake.
When the “Assert SCSI Data” command is issued, the CXD1185C internal FIFO counter is fixed at “0”. As a
result, only one byte of data can be received by the data register. Reading the SCSI data register results in
reading the SCSI data bus directly. If the CXD1185C is in neither initiator nor target mode (status register
bits 4 and 3 both set to “0”), none of the bits in the SCSI bus control register can be output to the SCSI bus
except ABSY and ASEL. If the CXD1185C is in initiator mode, the AACK and AATN bits are output to the
SCSI bus. In the target mode, the AMSG, ACD, AIO and AREQ bits are output.
When phase change (PHC) interrupt occur in initiator mode, output to the SCSI data bus is inhibited. In such
case, read the SCSI control monitor register and set the phase in the SCSI control register. When “Assert
SCSI Control” command is executed in target mode, pins on the SCSI bus, except BSY, are released.
The phase can be controlled by setting appropriate values to the SCSI bus control register. The contents of
the SCSI control register and/or SCSI data register are output continually after “Assert SCSI Control” and/or
“Assert SCSI data”. Therefore, when program I/O transfer is completed the “Deassert SCSI Control” or
“Deassert SCSI Data” command must be written to the command register.
5-2. CPU I/O transfer
This method is used to transfer data between the CPU bus and the CXD1185C without using DMA. Transfer
command can be issued when the CPU is in either the initiator or the target mode. When issuing these
commands, command register bit 5 (DMA) must be set to “0”.
• Outputting data to the SCSI bus
During the transfer, the CPU must monitor the FIFO status and make sure that it does not attempt to write
to the FIFO when it is full (FIFO is full when FIF bit in the FIFO status register is “1”) ( ). In target mode,
after issuing the transfer command, the CPU must check that the SCSI bus phase is changed to the
appropriate phase, by software, before any transfer data is written.
( ) Before writing a value to the data register a transfer command must be written to the command register.
• Reading data from the SCSI bus
After a transfer command is written to the command register, the CPU must monitor the FIE bit in the FIFO
status register so as to make sure that it does not attempt to read an empty FIFO. The CPU must monitor
the FNC bit in the status register to detect the end of transfer. The CPU, at the end of the transfer, must
continue to read any remaining data in the FIFO.
5-3. DMA transfer
This method is used to transfer data between the DMA bus and the CXD1185C. Transfer commands can be
issued when the CPU is in either the initiator or the target mode. When issuing commands command
register bit 5 (DMA) and 4 (TRBE) must be set to “1”. When a transfer is initiated the DRQ pin becomes
active. Then, when the DACK pin becomes active, the DRQ pin becomes inactive (when mode register bit 0
(BDMA) is set to “0”) and one byte of data is either written to or read from the FIFO. If the environment
setting register bit 5 (DPEN) is set to “1”, the data bus parity is calculated from the DP pin. During reads the
parity bit is generated, and during writes parity bit check takes place. During DMA transfer, the CPU bus and
data register are cut off. Hence, data register reads/writes from the CPU are ignored.
—26—
CXD1185CQ/CR
6. Programming Overview
The CXD1185C supports SCSI phase level commands. As a result, when it is operating it is possible to
perform programming without imposing a burden on the software. In this section actual methods for
programming the CXD1185C are introduced along with an explanation of all SCSI phases, assuming that
the CXD1185C is in the initiator mode and the target mode.
The below examples show cases where neither reselection phase nor sync transfer is performed.
6-1. Initiator mode
<Initial settings>
The CXD1185C is completely initialized when the power is turned on or after a hardware reset. Therefore,
the following initial settings must be performed.
1
2
Environment setting register initialization
The environment setting register is set to an initial value and initial clock division ratio of “4”. Therefore, a
new appropriate value must be written to match the external clock frequency as described in section 1-5.
If required, “1”s must be written to the other bits at the same time.
“Reset Chip” command execution
The new clock division ratio becomes valid only after executing the “Reset Chip” command. (The other
bits are valid as soon as they are written.) Therefore, if the clock division ratio is to be changed, the
“Reset Chip” command must be executed after changing the FSI and FSO bits in the environment setting
register.
3
“Enable Selection/Reselection” command execution
When either a “Hardware Reset” or “Reset Chip” command is executed, the selection/reselection
interrupts are disabled. An “Enable Selection/Reselection” command must be loaded in the command
register in order to accommodate selection/reselection interrupts.
<Arbitration/selection execution>
4
SCSI ID setting
The owner ID and target ID must be written to the SCSI ID register to prepare for selection.
5
Arbitration/selection
Write “1”s to some of the bits of interrupt authorization registers 1 and 2 (ARBF, STO, FNC, etc.) as
required. Write “Select with ATN” command into the command register. If message-out phase is not
necessary after selection, instead, write “Select without ATN” command. In this example “Select with
ATN” is assumed. Wait for the CIP bit in the status register to become “0” and read the interrupt request
registers.
If arbitration failed and ARBF bit is “1”, repeat 4. Normally, if selection time over occurs and STO bit set
to “1”, “Assert RST” command is executed.
<Message-out phase execution>
6
7
8
Switching to the message-out phase
Wait until the target device switches the SCSI bus to the message-out phase (PHC bit set to “1”).
Halting ATN signal drive
Execute “Deassert ATN” command to inactive the ATN signal on the SCSI bus.
Sending message byte
Confirm that the CIP bit is “0” in the status register. Write “Transfer Information” command to the
command register (DMA bit and TRBE bit are set to “0”s for a single byte message). Write the message
byte into the SCSI data register, After confirming that the CIP bit is to “0”, read interrupt request registers
1 and 2.
—27—
CXD1185CQ/CR
<Command phase execution>
Switching to the command phase
Wait until the target device switches the SCSI bus to the command phase (PHC bit set to “1”).
9
10 Command send
Set the number of command bytes in the transfer byte counter. Write “Transfer Information” command
into the command register. (this time set the TRBE bit to “1” and DMA bit to “0”). Write the command
bytes into the SCSI data register. After confirming that the CIP bit is set to “0”, read interrupt request
registers 1 and 2.
<Data-in phase execution>
11 Switching to the data-in phase
Wait until the target device switches the SCSI bus to the data-in phase (PHC bit set to “1”).
12 Data receive
Set the number of data bytes received in the transfer byte counter. Write “Transfer Information”
command into the command register (with both DMA bit and TRBE bit set to “1”).
Note that programming of DMA controller is also required starting DMA transfer. After confirming that the
CIP bit is set to “0”, read interrupt request registers 1 and 2.
<Status phase execution>
13 Switching to the status phase
Wait until the target devices switches the SCSI bus to the status phase (PHC bit set to “1”).
14 Status receive
Write “Transfer Information” command in the command register (both DMA bit and TRBE bit are “0”).
After confirming that the CIP bit is set to “0”, read interrupt request registers 1 and 2.
The status byte is read from the data register.
<Message-in phase execution>
15 Switching to the message-in phase
Wait until the target device switches the SCSI bus to the message-in phase (PHC bit set to “1”).
16 Message receive
Write “Transfer Information” command in the command register (both DMA bit and TRBE bit are “0”).
After confirming that the CIP bit is set to “0”, read interrupt request registers 1 and 2. The message byte
is read from the data register.
17 Halting ACK signal drive
Write “Deassert ACK” command in the command register to inactivate ACK signal. After confirming that
the CIP bit is “0”, read the interrupt request registers 1 and 2.
<Disconnect>
18 Wait until the DCNT bit is set to “1”.
All SCSI phases are covered in 1-17 above.
If a disconnect message is sent from the target device when in the data phase, the status phase is
skipped and processing continues with the message in phase. When reselection is performed from the
target device (RSL bit set to “1”), it is necessary to wait until the FNC bit is set to “1”. Then read the
monitor SCSI control register and perform the processing appropriate for the current SCSI phase.
—28—
CXD1185CQ/CR
6-2. Target mode
<Initial setting>
Refer to the paragraph for initial settings in initiator mode.
<Switching to arbitration/selection>
4
5
SCSI ID setting
Write owner ID to the SCSI ID register.
Arbitration/selection
Write “1”s to at least SWA, SWOA and FNC bits etc. in the interrupt authorization registers 1 and 2. Wait
for the initiator to complete arbitration and to begin selection. If selected, either SWA or SWOA (but, not
both) is set in the interrupt request register. If ATN was active during selection, SWA is set.
Approximately 10 µs later, FNC is set in the interrupt request register 2 and only then D1185A enters
target mode.
<Message out phase execution>
6
Message out phase execution
Write “Receive Message Out” command into the command register (in order to read 1 byte of the
message DMA and TRBE bits should, both, be “0”). When bit 0 (CIP) of the status register becomes “0”,
read interrupt request registers 1 and 2.
7
Receiving message byte
At this point message is already in the data register. Read the data register and analyze it. If there is
more than 1 byte of message to be received, repeat 5 and 6.
<Command phase execution>
8
ACK signal confirmation
Before the initiator inactivate ACK signal on SCSI bus, message byte is already fed inside FIFO. Before
executing the next command, it is necessary to confirm that MACK bit in the SCSI control monitor register
is “0”.
9
Command phase execution
Write “6” to the transfer byte counter, and write “Receive Command” (DMA bit is at “0” and TRBE bit is at
“1”) command to the command register. Read interrupt request registers 1 and 2 when bit 0 (CIP) of the
status register becomes “0”.
10 Receive command byte
6 bytes of command data are stored in the data register. Read the data register and analyze them. If it is
necessary to receive a larger number of command data, repeat 8 and 9.
<Data in phase execution>
11 ACK signal confirmation
It is necessary to confirm that MACK bit in the SCSI control monitor register is “0”.
12 Data phase execution
Set the number of transfer data (in bytes) in the transfer byte counter. Write “Send Data” (both DMA and
TRBE bits are at “1”) command in the command register. When CIP bit is “0”, read interrupt request
registers 1 and 2.
—29—
CXD1185CQ/CR
<Status phase execution>
13 ACK signal confirmation
It is necessary to confirm that MACK bit in the SCSI control monitor register is “0”.
14 Send status byte
Write “Send Status” (both DMA and TRBE bits are “0”) command in the command register. Wait until the
phase on the SCSI bus changes to status phase (monitor SCSI control monitor register). Write the status
byte in the data register. When CIP is “0”, read interrupt request registers 1 and 2.
NOTE:
In target mode, when all the following conditions are met, it is necessary to monitor and confirm the
change in the SCSI bus phase before writing anything in the data register.
1. The command causes a change in the data transfer direction from out to in (e.g. from data out phase
to status phase)
2. The command is not executed in DMA mode.
<Message in phase execution>
15 ACK signal confirmation
It is necessary to confirm that MACK bit in the SCSI control monitor register is “0”.
16 Send message
Write “Send Message” (both DMA and TRBE bits are “0”) command in the command register. If this
command causes a change in the data transfer direction from in to out, wait until the phase on the SCSI
bus changes to message in phase. Write the message byte in the data register. When CIP is “0”, read
interrupt request registers 1 and 2.
<Disconnect>
17 ACK signal confirmation
It is necessary to confirm that MACK bit in the SCSI control monitor register is “0”.
18 Disconnect execution
Write “Disconnect” command in the command register. When CIP is “0”, read interrupt request registers
1 and 2.
To perform disconnect during data phase, skip status phase and perform message-in phase sequence.
To perform reselection, it is necessary to execute “Reselect” command.
—30—
CXD1185CQ/CR
Appendix A
Register Summary
READ
7
6
5
4
3
2
1
0
Register
R0 MRST MDBP
INIT TRAG TRBZ MIRQ CIP
Status register
Data register
R1
R2
STO
RSL SWA SWOA ARBF Interrupt request register 1
R3
FNC DCNT SRST PHC DATN DPE
SPE RMSG Interrupt request register 2
R4 MBSY MSEL MMSG MCD MIO MREQ MACK MATN SCSI control monitor register
R5
R6
R7
R8
R9
RA
RB
FIE
FIE
FC3
FC2
OID2 OID1 OID0 SCSI ID register
Transfer byte counter (low)
FC1
FC0
FIFO status register
TID2 TID1 TID0
Transfer byte counter (middle)
Transfer byte counter (high)
STO
RSL SWA SWOA ARBF Interrupt authorization register 1
FNC DCNT SRST PHC DATN DPE
SPE RMSG Interrupt authorization register 2
BDMA Mode register
RC HDPE HSPE HATN TMSL SPHI
RD
RE
RF
TPD3 TPD2 TPD1 TPD0 TOF3 TOF2 TOF1 TOF0 Synchronous transfer register
ABSY ASEL AMSG ACD AIO AREQ AACK AATN SCSI bus control register
PCN3 PCN2 PCN1 PCN0 PRT3 PRT2 PRT1 PRT0 I/O port register
WRITE
7
6
5
4
3
2
1
0
Register
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
RA
RB
CAT1 CAT0 DMA TRBE CMD3 DMD2 DMD1 DMD0 Command register
Data register
<
>
DIFE SDPM DPEN SIRM
SID2 SID1 SID0
FS1
FS0
Environment setting register
Selection/reset timer register
<
>
OID2 OID1 OID0 SCSI ID register
Transfer byte counter (low)
Transfer byte counter (middle)
Transfer byte counter (high)
STO
RSL SWA SWOA ARBF Interrupt authorization register 1
FNC DCNT SRST PHC DATN DPE
SPE RMSG Interrupt authorization register 2
BDMA Mode register
RC HDPE HSPE HATN TMSL SPHI
RD
RE
RF
TPD3 TPD2 TPD1 TPD0 TOF3 TOF2 TOF1 TOF0 Synchronous transfer register
ABSY ASEL AMSG ACD AIO AREQ AACK AATN SCSI bus control register
PCN3 PCN2 PCN1 PCN0 PRT3 PRT2 PRT1 PRT0 I/O port register
<
> No register assigned to this address.
—31—
CXD1185CQ/CR
Appendix B
Command Summary
Category
0 0
DMA
0
TRBE
Command code
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
Command
0
0
0
0
0
0
0
0
0
0
0
0
0
No Operation
Reset Chip
Assert RST
Flush FIFO
0
0
0
0
Assert SCSI Control
Deassert SCSI Control
Assert SCSI Data
Deassert SCSI Data
Reselect
0
0
0
0 1
0
0
Select without ATN
Select with ATN
Enable Selection/Reselection
Disable Selection/Reselection
Send Message
0
0
0
1 0
Send Status
Send Data
0
0
Disconnect
Receive Message Out
Receive Command
Receive Data
1 1
Transfer Information
Transfer Pad
0
0
0
0
0
0
Deassert ACK
Assert ATN
Deassert ATN
<
> Set “1” to enable the mode, “0” to disable it.
However, if the DMA bit is set to “1”, the TRBE bit must also be set to “1”.
—32—
CXD1185CQ/CR
Appendix C
Changes from CXD1185AQ
The CXD1185CQ is pin compatible and comes in the same package as its predecessor, CXD1185AQ. The
CXD1185C has the identical electrical characteristics as the CXD1185AQ. This appendix summarizes the new
functions of CXD1185C.
New features
•
•
Single initiator mode detection
Selection phase SCSI parity check/ignore switch
Single initiator mode detection
The CXD1185AQ did not support single initiator mode. It was able to be selected under single initiator mode,
but since it returned “0” for the value of SID2-0, it was impossible to tell whether it was selected by ...
a. a SCSI device with ID “0” in multiple initiator environment or
b. the sole initiator in single initiator environment.
The CXD1185C has a new register bit “Single initiator MODe” flag to solve the problem.
SMOD
Single initiator MODe Flag
Register SCSI ID register (06 h)
Bit bit4 (Read Only)
SMOD
description
0
1
SID value VALID (Selected in multi initiator environment)
SID value INVALID (Selected in single initiator environment)
This flag is updated during every selection phase.
NOTE! With this flag, the CXD1185C supports single initiator in target mode. The CXD1185C still does not
support execution of single initiator mode selection. Therefore, this new feature has no significance to
users who wishes to use the CXD1185C as initiator.
Software changes
initiator Not required
target
It is now possible to separate the task after the selection for single initiator environment and multi
initiator environment.
SCSI parity check/ignore switch
The CXD1185AQ always responded to selection when selection/reselection was enabled. The CXD1185C
has an option not to respond to selection when there is SCSI parity error.
SSPE
Selection SCSI Parity Enable
Register MODE register (0C h)
Bit bit4 (R/W)
SSPE
description
0
1
Respond to selection even when SCSI parity error is ignored
Does not respond to selection when there is SCSI parity error
Initiators that does not implement the reselection phase and do not operate in multiple initiator environment are allowed to set only the
target’s SCSI bit during selection phase.
—33—
CXD1185CQ/CR
When SPPE=“0”
When SPPE=“1”
Software changes
It behaves as a CXD1185AQ. It responds to any selection and issues SPE (SCSI
Parity Error) interrupt (Interrupt request register2 (03 h), bit1)
Does not respond to selection if SCSI parity error is detected.
If SPPE bit is fixed to “0”, it behaves as a CXD1185AQ, hence no software changes are required. Setting
SPPE bit to “1” would eliminate the possibility of SPE interrupt after selection and the routine that deals with
it.
Distinguishing CXD1185AQ and CXD1185C
To distinguish the two by software, follow the steps below.
1. Write “1” to SPPE bit (bit2) of MODE register (0C h).
2. Read SPPE bit (bit2) of MODE register (0C h).
Value of SPPE bit
Chip name
CXD1185AQ
CXD1185C
0
1
—34—
CXD1185CQ/CR
Package Outline Unit : mm
CXD1185CQ
64PIN QFP(PLASTIC)
23.9 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
20.0 – 0.1
0.15
51
33
52
32
64
20
+ 0.2
0.1 – 0.05
1
19
+ 0.35
2.75 – 0.15
+ 0.15
0.4 – 0.1
1.0
M
0.24
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
EPOXY RESIN
SOLDER/PALLADIUM
PLATING
SONY CODE
EIAJ CODE
QFP-64P-L01
LEAD MATERIAL
PACKAGE MASS
42/COPPER ALLOY
1.5g
QFP064-P-1420
JEDEC CODE
64PIN LQFP (PLASTIC)
CXD1185CR
12.0 ± 0.2
10.0 ± 0.1
48
33
49
32
A
17
(0.22)
64
16
1
+ 0.08
0.18 – 0.03
+ 0.05
0.127 – 0.02
0.5
+ 0.2
1.5 – 0.1
0.13
M
0.1
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
DETAIL A
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER/PALLADIUM
SONY CODE
EIAJ CODE
LQFP-64P-L01
PLATING
LQFP064-P-1010
42/COPPER ALLOY
0.3g
JEDEC CODE
PACKAGE MASS
—35—
相关型号：
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