CXD1175AP_技术文档

CXD1175AM/AP

8-bit 20MSPS Video A/D Converter (CMOS)

Description

CXD1175AM

CXD1175AP

The CXD1175A is an 8-bit CMOS A/D converter

for video use. The adoption of a 2-step parallel

system achieves low consumption at a maximum

conversion speed of 20MSPS minimum, 35MSPS

typical.

24 pin SOP (Plastic)

24 pin DIP (Plastic)

Features

• Resolution: 8 bit ± 1/2LSB (DL)

• Maximum sampling frequency: 20MSPS

• Low power consumption: 60mW (at 20MSPS typ.)

(reference current excluded)

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage V^DD

• Reference voltage VRT,VRBVDD + 0.5 to Vss – 0.5V

7

V

• Built-in sampling and hold circuit

• Built-in reference voltage self-bias circuit

• 3-state TTL compatible output

• Power supply: 5V single

• Input voltage

(Analog)

VIN

VDD + 0.5 to Vss – 0.5V

• Input voltage

(Digital)

V^I

• Low input capacitance: 11pF

• Reference impedance: 300Ω (typ.)

• Output voltage

(Digital)

VO

• Storage temperature

Tstg

Applications

–55 to +150

°C

V

TV, VCR digital systems and a wide range of fields

where high speed A/D conversion is required.

Recommended Operating Conditions

• Supply voltage AVDD, AVss 4.75 to 5.25

DVDD, DVss

| DVss – AVss | 0 to 100 mV

Structure

Silicon gate CMOS monolithic IC

• Reference input voltage

VRB

VRT

0 and above

2.8 and below

1.8Vp-p above

V

• Analog input

VIN

• Clock pulse width

TPW1, TPW0 23ns (min) to 1.1µs (max)

• Operating ambient temperature

Topr

–40 to +85

°C

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

– 1 –

E89321F78-PS

CXD1175AM/AP

Block Diagram and Pin Configuration

DVSS

VRB

1

2

24

23

22

21

20

19

18

17

16

15

14

13

OE

DVSS

D0 (LSB)

D1

Reference voltage

VRBS

AVSS

VIN

3

4

Lower

comparators with

S/H (4 bit)

Lower data

latches

Lower encoder

(4 bit)

5

D2

6

D3

Lower

comparators with

S/H (4 bit)

AVDD

VRT

7

D4

Lower encoder

(4 bit)

8

D5

Upper data

latches

VRTS

AVDD

DVDD

9

D6

Upper

comparators with

S/H (4 bit)

Upper encoder

(4 bit)

10

11

12

D7 (MSB)

DVDD

CLK

Clock generator

– 2 –

CXD1175AM/AP

Pin Description and Equivalent Circuits

No.

Symbol

Equivalent circuit

Description

DVDD

When OE = Low, Data is output.

When OE = High, D0 to D7 pins turn

to High impedance.

1

OE

1

DVSS

Digital ground

DVSS

2, 24

Di

3 to 10 D0 to D7

D0 (LSB) to D7 (MSB) output

11, 13

12

DVDD

Digital +5V

Clock input

DVDD

DVSS

CLK

12

AVDD

16

VRTS

Shorted with VRT generates, +2.6V.

Reference voltage (Top)

16

AVDD

17

23

VRT

VRB

23

17

Reference voltage (Bottom)

Analog +5V

AVSS

14, 15, 18 AVDD

AVDD

19

VIN

Analog input

AVSS

20, 21

22

AVSS

Analog GND

AVSS

VRBS

Shorted with VRB generates +0.6V.

22

– 3 –

CXD1175AM/AP

Digital output

Compatibility between analog input voltage and the digital output code is indicated in the chart below.

Digital output code

MSB LSB

Input signal

voltage

Step

VRT

:

0

:

1 1 1 1 1 1 1 1

:

127

128

:

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

:

VRB

255

0 0 0 0 0 0 0 0

TPW1

TPW0

Clock

Amalog input

N

N + 1

N – 2

N + 3

N

N + 4

N + 1

N + 2

Data output

N – 3

N – 1

Td = 18ns

: Point for analog signal sampling.

Timing Chart 1

tr = 4.5ns

tf = 4.5ns

90%

5V

2.5V

OE input

Output 1

10%

0V

tPLZ

tPHZ

tPZL

VOH

1.3V

10%

90%

VOL (≠DVSS)

VOH (≠DVDD)

tPZH

Output 2

VOL

Timing Chart 2

– 4 –

CXD1175AM/AP

Electrical Characteristics

(Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)

Analog characteristics

Item

Symbol

Conditions

Min.

Typ.

Max.

Unit

VDD = 4.75 to 5.25V

Ta = –40 to +85°C

VIN = 0.5 to 2.5V

fIN = 1kHz ramp

MSPS

0.5

20

Conversion speed

Fc

Analog input band width

(–1dB)

MHz

mV

Envelope

18

BW

Potential difference to VRT

Potential difference to VRB

–10

0

–35

+15

+0.5

±0.3

1.0

0.5

30

–60

+45

+1.3

±0.5

EOT

EOB

EL

1

Offset voltage

Integral non-linearity error

Differential non-linearity erro

Differential gain error

Differential phase error

Aperture jitter

LSB

End point

r

ED

%

deg

ps

DG

DP

taj

NTSC 40 IRE mod ramp

Fc = 14.3MSPS

ns

4

Sampling delay

tsd

1

The offset voltage EOB is a potential difference between VRB and a point of position where the voltage

drops equivalent to 1/2 LSB of the voltage when the output data changes from “00000000” to “00000001”.

EOT is a potential difference between VRT and a potential of point where the voltage rises equivalent to

1/2LSB of the voltage when the output data changes from “11111111” to “11111110”.

– 5 –

CXD1175AM/AP

DC characteristics

(Fc = 20MSPS, VDD = 5V, VRB = 0.5V, VRT = 2.5V, Ta = 25°C)

Item

Symbol

I^DD

Conditions

Fc = 20MSPS

Min.

Typ.

12

Max.

17

Unit

mA

Supply current

NTSC ramp wave input

4.5

6.6

11

8.7

mA

pF

Reference pin current

IREF

CIN

Analog input capacitance

VIN = 1.5V + 0.07Vrms

Reference resistance

(VRT to VRB)

230

300

450

Ω

V

RREF

0.60

1.96

0.64

2.09

0.68

2.21

VRB1

Shorts VRB and VRBS

Shorts VRT and VRTS

Self-bias I

VRT1 – VRB1

VRB = AGND

Shorts VRT and VRTS

2.25

3.5

2.39

2.53

Self-bias II

VRT2

VIH

VIL

IIH

VDD = 4.75 to 5.25V

Ta = –40 to +85°C

Digital input voltage

1.0

5

VIH = VDD

µA

mA

µA

Digital input current

Digital output current

V^DD= max

VIL = 0V

5

IIL

VOH = VDD – 0.5V

–1.1

3.7

IOH

IOL

IOZH

IOZL

OE = VSS

VDD = min

VOL = 0.4V

VOH = VDD

VOL = 0V

16

OE = VDD

VDD = max

Timing

(Fc = 20MSPS, VDD = 4.75 to 5.25V, VRB = 0.5V, VRT = 2.5V, Ta = –40 to +85°C)

Item

Symbol

Conditions

Min.

Typ.

18

Max.

30

Unit

ns

Output data delay

TDL

With TTL 1 gate and 10pF load

Tri-state output

enable time

t

PZH

RL = 1kΩ, CL = 20pF

OE = 5V → 0V

ns

3

7

13

26

tPZL

Tri-state output

disable time

tPHZ

PLZ

RL = 1kΩ, CL = 20pF

OE = 0V → 5V

15

t

– 6 –

CXD1175AM/AP

Electrical Characteristics Measurement Circuit

Integral non-linearity error

3-state output measurement circuit

Differential non-linearity error measurement circuit

}

Offset voltage

+V

Measurement

point

DVDD

S2

S1: ON IF A < B

S2: ON IF B > A

RL

S1

To output pin

–V

CL

RL

A < B A > B

COMPARATOR

8

VIN

DUT

CXD1175A

A8

to

A1

A0

B8

to

B1

B0

BUFFER

Note) CL includes the capacitance of the probe

and others.

"0"

"1"

DVM

000 · · · 00

8

to

CLK (20MHz)

111 · · · 10

CONTROLLER

Maximum operational speed

Differential gain error

measurement circuit

}

Differential phase error

2.5V

ERROR RATE

Fc – 1kHz

CX20202A-1

S.G.

H.P.F

COUNTER

0.5V

1

2

1

2

TTL

ECL

10bit

D/A

VIN

8

CXD

1175A

AMP

620

–5.2V

100

40 IRE

MODULATION

2.5V

VECTOR

SCOPE

NTSC

SIGNAL

SOURCE

CLK

BURST

0

0.5V

D.G

D.P.

–40

SYNC

620

–5.2V

TTL

ECL

S.G.

(CW)

FC

Digital output current measurement circuit

VDD

VRT

VIN

VDD

VRT

2.5V

0.5V

2.5V

0.5V

IOL

IOH

VIN

VRB

CLK

OE

GND

CLK

OE

GND

+

–

+

VOL

VOH

–

– 7 –

CXD1175AM/AP

Timing Chart 3

Vi (1)

Vi (2)

Vi (3)

Vi (4)

Analog input

External clock

Upper comparators block

Upper data

S (1)

C (1)

S (2)

C (2)

S (3)

C (3)

S (4)

C (4)

MD (0)

MD (1)

MD (2)

MD (3)

Lower reference voltage

RV (0)

RV (1)

RV (2)

RV (3)

Lower comparators A block

Lower data A

S (1)

H (1)

C (1)

S (3)

H (3)

C (3)

LD (–1)

LD (1)

Lower comparators B block

Lower data B

H (0)

C (0)

S (2)

H (2)

C (2)

S (4)

H (4)

LD (–2)

LD (0)

LD (2)

Digital output

Out (–2)

Out (–1)

Out (0)

Out (1)

Operation (See Block Diagram and Timing Chart)

1. The CXD1175AM/AP is a 2-step parallel system A/D converter featuring a 4-bit upper comparators group

and 2 lower comparators groups of 4-bit each. The reference voltage that is equal to the voltage between

VRT – VRB/16 is constantly applied to the upper 4-bit comparator block. Voltage that corresponded to the

upper data is fed through the reference supply to the lower data. VRTS and VRBS pins serve for the self

generation of VRT (Reference voltage top) and VRB (Reference voltage bottom).

– 8 –

CXD1175AM/AP

2. This IC uses an offset cancel type comparator and operates synchronously with an external clock. It

features the following operating modes which are respectively indicated on the timing chart with S, H, C

symbols. That is input sampling (auto zero) mode, input hold mode and comparison mode.

3. The operation of respective parts is as indicated in the chart. For instance input voltage Vi (1) is sampled

with the falling edge of the first clock by means of the upper comparator block and the lower comparator A

block.

The upper comparators block finalizes comparison data MD (1) with the rising edge of the first clock.

Simultaneously the reference supply generates the lower reference voltage RV (1) that corresponded to

the upper results. The lower comparator block finalizes comparison data LD (1) with the rising edge of the

second clock. MD (1) and LD (1) are combined and output as Out (1) with the rising edge of the 3rd clock.

Accordingly there is a 2.5 clock delay from the analog input sampling point to the digital data output.

Operation Notes

1. VDD, VSS

To reduce noise effects, separate the analog and digital systems close to the device. For both the digital

and analog VDD pins, use a ceramic capacitor of about 0.1µF set as close as possible to the pin to bypass

to the respective GND’s.

2. Analog input

Compared with the flash type A/D converter, the input capacitance of the analog input is rather small.

However it is necessary to conduct the drive with an amplifier featuring sufficient band and drive capability.

When driving with an amplifier of low output impedance, parasite oscillation may occur. That may be

prevented by inserting a resistance of about 100Ω in series between the amplifier output and A/D input.

3. Clock input

The clock line wiring should be as short as possible also, to avoid any interference with other signals,

separate it from other circuits.

4. Reference input

Voltage between VRT to VRB is compatible with the dynamic range of the analog input. Bypassing VRT and

VRB pins to GND, by means of a capacitor about 0.1µF, stable characteristics are obtained. By shorting VRT

and VRTS, VRB and VRBS, the self-bias function that generates VRT = 2.6V and VRB = 0.6V, is activated.

5. Timing

Analog input is sampled with the falling edge of CLK and output as digital data with a delay of 2.5 clocks

and with the following rising edge. The delay from the clock rising edge to the data output is about 18ns.

6. OE pin

By connecting OE to GND output mode is obtained. By connecting to VDD high impedance is obtained.

7. About latch up

It is necessary that AVDD and DVDD pins be the common source of power supply.

This is to avoid latch up due to the voltage difference between AVDD and DVDD pins when power is ON.

– 9 –

CXD1175AM/AP

Application Circuit

+5V

R11

1k

IC1

µPC254

R12

1k

Q4

Q5

HC04

CLK

CLOCK IN

+5V

C9

47µ

R13

500

IC2

µPC254

13

12

11

10

9

+12V

C10

0.1µ

+5V

+12V

14

15

16

17

18

19

20

21

22

23

24

R6

500

D7 (MSB)

D6

R8

100

C6

47µ

C5

R3

Q2

C12

0.1µ

500

C2

D5

8

10µ

C8

Q3

Q1

D4

7

CXD1175AM/AP

R7

D3

6

500

V IN

R10

75

D2

R4

1k

5

R5

2k

R2

180

C1

470µ

R9

5k

D1

4

R1

120

C13

10p

C3

D0 (LSB)

3

47µ

C4

0.1µ

2

C7

47µ

C11

0.1µ

1

–12V

+5V

: Ceramic Chip Condenser

0.1µF

: Analog GND

: Digital GND

Note) It is necessary that AVDD and DVDD pins the common source of power supply.

The gain of analog input signal can be variable by adjustment of value of R3.

Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for

any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.

– 10 –

CXD1175AM/AP

8-bit 20MSPS ADC and DAC Evaluation Board

The CXD1175AP/CXA1106P PCB is evaluation PCB for the 8-bit high speed and low power consumption

CMOS A/D converter CXD1175AP and the 8-bit high speed bipolar D/A converter CXD1106P. This PCB

features a high speed and low power consumption CMOS A/D converter, analog input buffer, clock buffer,

latch and high speed bipolar D/A converter designed to fully enhance the performance of A/D and D/A

converters.

Block Diagram

V OUT

ANALOG CIRCUIT

MOUNT PORTION

8

V REF

8

ANALOG INPUT

BUFFER/DRIVER

V IN

CLOCK

BUFFER

Unnecessary during

self-bias usage

ANALOG CIRCUIT

MOUNT PORTION

OSC

SW

CLOCK

GND +5V –5V

Characteristics

• Resolution

8bit

• Maximum conversion rate

• Digital input level

20MHz

TTL level

±5.0V

• Supply voltage

Supply voltage

Item

Min.

Typ.

Max.

Unit

mA

+5V

–5V

150

20

Analog input

AC input voltage

Item

Min.

0.5

0

Typ.

Max.

Unit

V

Gain (VIN = 2Vp-p input)

Offset voltage

2

5

Clock input

TTL compatible

Pulse width

TCW1 25ns (min.)

TCW0 25ns (min.)

– 11 –

CXD1175AM/AP

Analog Output (CXA1106)

(RL > 10kΩ)

Item

Min.

0.9

Typ.

1.0

Max.

1.1

Unit

V

Analog output

Output Format (CXD1175A)

The table shows the output format of A/D converter.

Input signal

voltage

Digital output code

MSB LSB

Step

VRT

:

0

:

127

128

:

1

1 1

1

1 1

:

1

0

1

0 0

1 1

0

1

0

1

0 0

1 1

VRB

255

0

0 0

0

0 0

Timing Chart

Analog input

Tpw0

External clock

AD clock

Tpw1

Tdc

tPD (AD)

AD output

tDD

Latch output

DA input

ts

th

DA clock

DA output

tPD (DA)

Item

Symbol

Min.

25

Typ.

18

Max.

Unit

ns

Clock high time

Clock low time

Clock delay

TPW1

TPW0

25

Tdc

24

30

17

Data delay AD

t

PD (AD)

Data delay (latch)

Set up time

DD

S

10

2

Hold time

th

Data delay DA

t

PD (DA)

11

– 12 –

CXD1175AM/AP

( I N V B u f f e r )

7 4 S 0 4 o r 7 4 H C 0 4

C X A 1 1 0 6 ( D A C )

C X D 1 1 7 5 A ( A D C )

D D D V

D D A V

G N D

+ 5 V

– 5 V

– 13 –

CXD1175AM/AP

List of Parts

transistor

Q1

Q2

Q3

Q4

resistor

R1

R2

R3

R4

R5

R6

R7

2SC2785

51Ω

120Ω

680Ω

510Ω

390Ω

2.2kΩ

75Ω

Q5

IC

IC1

IC2

IC3

74S174

74S04

R8

R9

2.2kΩ

510Ω

75Ω

100Ω

10kΩ

2kΩ

R10

R11

VR1

VR2

VR3

VR4

VR5

oscillator

OSC

others

connector BNC071

SW AT1D2M3

2kΩ

5kΩ

capacitor

C1

C2

470µF/6.3V (chemical)

22µF/16V (chemical)

0.01µF

C3

C4

C5

10µF/16V (tamtalate)

0.1µF

C6

0.1µF

C7

0.1µF

C8

0.1µF

C9

0.1µF

C10

C11

C12

C13

C14

0.1µF

47µF/10V (chemical)

0.1µF

Method of Adjustment

1. Vgain (VR1)

Gain adjustment of the analog input.

2. Voffset (VR2)

Offset adjustment of the analog input.

3. Vref (VR3, VR4)

Adjustment of the A/D converter reference voltage.

VRB is adjusted at VR3, and VRT at VR4. Reference voltage is given with self-bias for PCB shipment.

4. Analog output gain (VR5)

Full-scale voltage of the D/A converter output is adjusted.

– 14 –

CXD1175AM/AP

Points on the PCB Pattern Layout

1. Layout so that digital current does not flow to analog GND (part 1).

(See Component Side on page 19 for part 1.)

2. Capacitor C6 (between AVSS and AVDD) and capacitor C14 (between DVSS and DVDD) are important

factors to enhance the CXD1175A performance. Those capacitors should feature good high frequency

characteristics over 0.1µF (ceramic capacitor). Layout as close to the IC as possible.

3. Analog GND (AVSS) and Digital GND (DVSS) have a common voltage and a supply source. The DVSS of

A/D converter (part 2) location as close to the voltage source is possible will give even better results. That

is, a layout where the A/D converter is close to the voltage source is recommended. (See Component Side

on page 19 for part 2.)

4. AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13) are provided in the CXD1175A, and a common

voltage source should be used for them as for part 3. (See the paragraph for Latch Up Prevention.) (See

Soldering Side on page 19 for part 3.)

5. The A/D converter samples analog signals at the falling edge of clock. Accordingly, clocks fed to the A/D

converter should not be affected by jitter.

6. In this PCB, to evaluate A/D and D/A converters independently, an independent layout has been adopted

for the analog GND of A/D and D/A converters, from the voltage generation source. For the user’s actual

PCB even a common source poses no problems. For the CXA1106, as analog signals are output with the

supply voltage as reference, take care not to let noise interfere with the analog VDD of D/A converter.

– 15 –

CXD1175AM/AP

Notes on Operation

1. Reference voltage

The self-bias function where VRT = 2.6V and VRB = 0.6V is available by shorting VRT and VRTS, VRB and

VRBS in the CXD1175A. At the PCB, either self-bias or external reference voltage can be selected

according to the way the jumper wire is connected. For shipment, the reference voltage is provided by the

self-bias. Also, when reference voltage is to be provided from the exterior, adjust the dynamic range (VRT –

VRB) to 1.8Vp-p or over.

2. Clock input

There are two modes for the PCB clock input.

1) Through an external signal generator (external clock)

2) Using a crystal oscillator (internal clock)

These two modes can be selected with a switch on the PCB.

They are given from the external clock for shipment.

3. Peripheral through hole

There is a number of through holes at the analog input, output and LOGIC areas. Those are used when

additional circuits are to be mounted on the PCB circuit.

4

The two latch ICs (74S174) on the circuit diagram are not absolutely necessary for the A/D and D/A

converter evaluation. That is, when the A/D converter output data is directly input to D/A converter input,

normal operation is maintained. However, as A/D converter output data is hardly ever subject to D/A

conversion without the digital signal processing, the PCB has been fitted with the 74S174 to show a layout

example for digital signal processing IC.

5. Analog input buffer & driver block is designed to handle conventional video band signals. Accordingly, for

tests involving frequencies higher than that, methods shown in the figure below are recommended.

R7 75Ω

V IN

19

50Ω

D1175A

S.G.

High frequency input measurement circuit

– 16 –

CXD1175AM/AP

Latch Up Prevention

The CXD1175A is a CMOS IC which requires latch up precautions. Latch up is mainly generated by the lag in

the voltage rising time of AVDD (Pins 14, 15 and 18) and DVDD (Pins 11 and 13), when power supply is ON.

1. Correct usage

a. When analog and digital supplies are from different sources

DVDD

AVDD

18

13

11

14 15

AVDD

DVDD

C14

+5V

CXD1175A

C6

DIGITAL IC

AVSS

DVSS

20 21

2

24

AVSS

DVSS

b. When analog and digital supplies are from a common source

(i)

DVDD

18

13

11

14 15

AVDD

DVDD

C14

+5V

CXD1175A

DIGITAL IC

C6

AVSS

DVSS

20 21

2

24

AVSS

DVSS

(ii)

DVDD

18

13

11

14 15

AVDD

DVDD

C14

+5V

CXD1175A

DIGITAL IC

C6

AVSS

DVSS

20 21

2

24

AVSS

DVSS

– 17 –

CXD1175AM/AP

2. Example when latch up easily occurs

a. When analog and digital supplies are from different sources

DVDD

AVDD

18

13

11

14 15

AVDD

DVDD

+5V

CXD1175A

C6

DIGITAL IC

AVSS

DVSS

20 21

2

24

AVSS

DVSS

b. When analog and digital supplies are from common source

(i)

DVDD

AVDD

18

13

11

14 15

AVDD

DVDD

+5V

CXD1175A

DIGITAL IC

C6

AVSS

DVSS

20 21

2

24

AVSS

DVSS

(ii)

DVDD

AVDD

18

13

14 15

11

AVDD

DVDD

+5V

CXD1175A

DIGITAL IC

AVSS

DVSS

20 21

2

24

AVSS

DVSS

– 18 –

CXD1175AM/AP

Silk Side

Component side

1

Soldering side

– 19 –

CXD1175AM/AP

Package Outline

CXD1175AM

Unit: mm

24PIN SOP (PLASTIC)

+ 0.4

15.0 – 0.1

+ 0.4

1.85 – 0.15

24

13

0.15

+ 0.2

0.1 – 0.05

1

0.45 ± 0.1

12

+ 0.1

0.2 – 0.05

1.27

± 0.12

M

PACKAGE STRUCTURE

MOLDING COMPOUND

EPOXY/PHENOL RESIN

SOLDER PLATING

COPPER ALLOY / 42ALLOY

0.3g

LEAD TREATMENT

LEAD MATERIAL

SONY CODE

EIAJ CODE

SOP-24P-L01

SOP024-P-0300-A

JEDEC CODE

PACKAGE WEIGHT

CXD1175AP

24PIN DIP(PLASTIC)

+ 0.4

30.2 – 0.1

24

13

0° to 15°

1

12

2.54

Two kinds of package surface:

1.All mat surface type.

2.All mirror surface type.

0.5 ± 0.1

1.2 ± 0.15

PACKAGE STRUCTURE

PACKAGE MATERIAL

LEAD TREATMENT

LEAD MATERIAL

EPOXY RESIN

SOLDER PLATING

42/COPPER ALLOY

2.0g

SONY CODE

EIAJ CODE

DIP-24P-01

DIP024-P-0400

JEDEC CODE

PACKAGE MASS

– 20 –


型号：	CXD1175AP
厂家：	SONY CORPORATION
描述：	8-bit 20MSPS Video A/D Converter (CMOS) 8位20MSPS视频A / D转换器（ CMOS ）转换器模数转换器光电二极管
文件：	总20页 (文件大小：303K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CXD1175AP [SONY]

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