CXA1202Q-Z [SONY]
REC/PB Amplifier for VCR; REC / PB放大器VCR
| 型号： | CXA1202Q-Z |
| 厂家： | 
SONY CORPORATION |
| 描述： | REC/PB Amplifier for VCR |
| 文件： | 总26页 (文件大小：427K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA1202Q-Z/CXA1202R
REC/PB Amplifier for VCR
For the availability of this product, please contact the sales office.
Description
CXA1202Q-Z
CXA1202R
CXA1202Q-Z/CXA1202R are bipolar ICs developed
as REC/PB amplifiers for VCR's.
48 pin QFP (Plastic)
48 pin LQFP (Plastic)
Features
• Built-in head amplifier feedback dumping con-
tributes to the reduction of external components
and simplification of the print circuit board design.
• Built-in BPF for PB signals medium range frequency
compensation totally eliminates external resonance
circuits (L. C. R.)
• Low range recording signal variable-level mix
amplifier allows for both metal powder and metal
evaporated tapes application.
• Consumption saving through power save function
of the REC AMP.
• 4-head system switch incorporated.
Functions
• Recording: 2-channel REC AMP, 5-input (Y, Chroma, AFM, ATF, PCM) Mix AMP.
• Playback: 2-channel low-noise head amplifier, medium range frequency compensation circuit, RF AGC,
dropout detecting circuit.
Structure
Bipolar silicon monolithic IC
Applications
• 8-mm system VCR
• β-system VCR
• VHS-system VCR
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Operating temperature
• Storage temperature
Vcc
Topr
Tstg
8
V
°C
°C
mW
mW
–10 to +75
–55 to +150
920
• Allowable power dissipation PD (CXA1202Q-Z)
PD (CXA1202R)
1100
(CXA1202R: Substrate area 40 × 25mm2, t = 0.635mm when ceramic print circuit board mounted)
Recommended Operating Condition
Supply voltage
Vcc
5 ± 0.25
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E88012-PS
CXA1202Q-Z/CXA1202R
Block Diagram and Pin Configuration
35
32
36
34
33
31
30
29
28
27
26
25
CH2
REC AMP
CH1
REC AMP
MIX2 OUT
MT 2
37
38
39
40
41
42
43
44
45
46
47
48
24 MIX1 OUT
23 MT1
46dB
46dB
RF SWP
22 MULTI
CH2
HEAD AMP
CH1
HEAD AMP
GND 2CH
PCM SEL
ME LEVEL
GND REC
ATF LEVEL
RP PB 1CH
ATF IN
21 GND 1CH
20 V RF OUT
9dB
9dB
CONTROL
LOGIC
MTFφ
MTQ
BPF
Video
SW
19
GND PB
CH2
CH1
–6dB
–6dB
VP1 VP2
SW SW
BPF
18 DOC IN
17 VCC EF
16 RF OUT
15 DOC TC
14 RF IN B
Mute
VCA
VCA
P
V
P V
MT1
MT2
DOC
DET
6dB
Medium range freq.
compensation
12dB
A
CH2
CH1
ME
LEVEL
GCA
DOC
DET
PCM
SW
VCA
MIX
AMP
VCA
ATF
SW
RF
DET AGC
RP PB 2CH
PCM IN
6dB
Normal VCA
B
6dB
RF SW
Multi
13
DOC PULSE
1
2
3
4
5
6
7
8
9
10
11
12
– 2 –
CXA1202Q-Z/CXA1202R
Pin Description
Voltage
I/O
resistance
No.
Symbol
Equivalent circuit
Description
DC
AC
VCC
1
Power-save recording at Low.
High: over 3V
Low: under 1V
(Open:
"L")
40k
20k
1
RP PB EN
—
40kΩ
GND
VCC
2
134
mVp-p
2
C IN
3.2V
20kΩ
20k 100
Input pin for Chroma signal.
GND
VCC
24k
35k
3
Output pin for VREG 4.2V.
Decoupling with capacitance.
3
4
5
VREG
AFM IN
VG
4.2V
3.2V
2.5V
—
—
20kΩ
—
GND
80
mVp-p
Same as for Pin No. 2
Input pin for AFM signal.
VCC
150
Output pin for virtual GND.
Decoupling with capacitance.
—
5
2.5k
GND
250
mVp-p
Same as for Pin No. 2
—
6
7
Y IN
Vcc
3.2V
5.0V
20kΩ
Input pin for Y signal.
Supply pin for circuits other than
REC AMP and Head AMP.
—
—
VCC
440
50 to
500
mVp-p
Emitter
follower
(IE = 1mA)
PCM RF
OUT
8
1.8V
Output pin for PB PCM signal.
8
1mA
GND
– 3 –
CXA1202Q-Z/CXA1202R
Voltage
I/O
resistance
No.
Symbol
Equivalent circuit
Description
DC
AC
VCC
500
200
Pin to apply time constant of
envelope detection for RF AGC.
Optimum load resistance across
Vcc is 150kΩ.
200
4.25V
(Load:
150kΩ
9
9
AGC TC
—
—
GND
VCC
17
200
Emitter
follower
(IE = 1mA)
AGC output pin for PB VIDEO
signal (Max. gain of AGC AMP is
about 7dB).
100
mVp-p
10 AGC OUT 2.5V
10
1mA
GND
VCC
Control signal input pin for RF SW
switching:
High (over 3V): selects RF IN A
Low (under 0.3V):
—
(Open:
"L")
50k
11 HCHG
—
50kΩ
11
selects RF IN B
GND
VCC
150
20k
12
100
mVp-p
Input pin for RF switch and 12dB
AMP.
12 RF IN A
2.5V
—
5
GND
VCC
100
Emitter
follower
(H: IE =
1mA)
DOC
13
H: 3.2V
L: 0V
Dropout detection signal output
pin; High upon dropout.
—
PULSE
13
80k 3.5k
GND
100
mVp-p
Input pin for RF switch and 12dB
AMP.
Same as for Pin No. 12
14 RF IN B
15 DOC TC
2.5V
2.5V
20kΩ
VCC
90
15
8k
3.3k
Pin to connect time constant of
dropout detection.
—
—
GND
– 4 –
CXA1202Q-Z/CXA1202R
Voltage
I/O
resistance
No.
Symbol
Equivalent circuit
Description
DC
AC
VCC
200
Emitter
follower
(IE =
400
mVp-p
Output pin of signal selected by
HCHG from RF IN A and RF IN B.
16 RF OUT
2.5V
16
500µA)
500µA
GND
VCC
17
200
Supply pin for emitter followers of
AGC OUT, DOC TC and RF OUT.
17 Vcc EF
5.0V
—
—
GND
VCC
150
8k
18
400
mVp-p
18 DOC IN
19 GND PB
2.5V
0V
8kΩ
Input pin for dropout detection.
2.5V
GND
VCC
GND pin for medium range
frequency compensation circuit,
RF AGC and DOC DET.
—
—
—
400
Emitter
follower
(IE =
50 to
500
mVp-p
20 V RF OUT 1.8V
Output pin for PB VIDEO signal.
20
500µA)
500µA
GND
GND pin for CH1 REC AMP and
CH1 Head AMP.
—
21 GND 1CH
22 MULTI
0V
—
—
—
—
(OPEN:
"L")
Multi-channel PCM REC mode at
High.
Same as for Pin No. 1
40kΩ
VCC
25k
—
(2.5V
at
OPEN
of pin)
Boost level adjusting pin for CH1
medium range frequency
compensation circuit.
Variable between 0 and +12dB at
4.2 to 0.8V.
23 MT1
—
100kΩ
47k
53k
23
5
GND
– 5 –
CXA1202Q-Z/CXA1202R
Voltage
DC
AC
I/O
resistance
No.
Symbol
Equivalent circuit
Description
VCC
400
Emitter
follower
(IE = 1mA)
203
mVp-p
24 MIX1 OUT 2.5V
Mix circuit output pin for CH1.
24
1mA
GND
VCC
100
92µA
(Y signal)
25
~
–
25 REC1 IN
1.8V
0
CH1 REC AMP input pin.
100
200
GND
VCC
Fφ adjusting pin for medium range
frequency compensation circuit;
Fφ is controlled through current
value by connecting resistance
between GNDs. Mutually affected
by MT Q. Do not connect
26
26 MT Fφ
2.5V
5.0V
—
—
—
90
capacitance.
GND
Power supply pin for CH1 REC
AMP and CH1 Head AMP.
—
27 Vcc 1CH
—
28
13
mAp-p
Open
collector
28 REC1 OUT 15mA
CH1 REC AMP output pin.
20
GND
VCC
29
90 to
900
µVp-p
CH1 head AMP positive phase
input pin (PB signal input pin).
29 PB IN 1P
2.4V
1.3kΩ
1.3kΩ
10k
GND
VCC
CH1 Head AMP inverter phase
input pin (decoupling with
capacitance).
30 PB IN 1N
2.4V
—
30
GND
– 6 –
CXA1202Q-Z/CXA1202R
Voltage
I/O
No.
31
Symbol
Equivalent circuit
Description
resistance
DC
AC
CH2 Head AMP Inverter phase
input pin (decoupling with
capacitance).
PB IN 2N
Same as for Pin No. 30
2.4V
2.4V
1.3kΩ
1.3kΩ
—
90 to
900
CH2 Head AMP positive phase
input pin (PB signal input pin).
Same as for Pin No. 29
PB IN 2P
32
µVp-p
13
mAp-p
Same as for Pin No. 28
—
CH2 REC AMP output pin.
REC2 OUT
Vcc 2CH
33
34
15mA
5.0V
Power supply pin for CH2 REC
AMP and CH2 Head AMP.
—
—
—
—
Q adjusting pin for medium range
frequency compensation circuit.
Controls Q through current value
by connecting resistance between
GNDs; Mutually effected by MT
Fφ. Do not connect capacitance.
Same as for Pin No. 26
MT Q
35
2.5V
92µA
(Y signal)
REC2 IN
~
0
36
37
1.8V
2.5V
Same as for Pin No. 25
Same as for Pin No. 24
CH2 REC AMP input pin.
–
Emitter
follower
(IE = 1mA)
203
mVp-p
MIX2 OUT
Mix circuit output pin for CH2.
—
(2.5V
at
OPEN
of pin)
Boost level adjusting pin for CH2
medium range frequency
compensation circuit; variable
between 0 and +12dB at 4.2 to 0.8V.
MT 2
38
Same as for Pin No. 23
—
100kΩ
—
(Open:
"L")
RF switching pulse input pin for
CH switchover.
RF SWP
39
40
—
—
Same as for Pin No. 1
—
40kΩ
GND pin for CH2 REC AMP and
CH2 head AMP.
GND 2CH
0V
—
PCM AREA input pin;
High: PCM REC period
During High period after recording,
MUTE is applied to PB VIDEO
output.
—
(Open:
"L")
PCM SEL
41
42
Same as for Pin No. 1
—
—
40kΩ
VCC
—
(2.1V
at
OPEN
of pin)
2.1V
Level of low range REC signals
(Chroma, AFM, ATF rec. with
VIDEO) can be boosted by 0 to
3dB by voltage (0 to 5V) applied
to this pin.
18k
24k
ME LEVEL
100kΩ
42
76k
GND
– 7 –
CXA1202Q-Z/CXA1202R
Voltage
I/O
No.
43
Symbol
Equivalent circuit
—
Description
resistance
DC
AC
GND pin for VG, VREG, LOGIC
and mix circuit.
GND REC
0V
—
—
REC Ievel of ATF signal can be
boosted by 0 to 3dB by the voltage
(0 to 5V) applied to this pin.
In multi PCM mode, priority given
to 6dB AMP.
—
(2.1V
at
OPEN
of pin)
ATF
LEVEL
Same as for Pin No. 42
Same as for Pin No. 1
44
45
100kΩ
—
—
REC/PB switchover signal for CH1:
High: PB
Low: REC
However, when RP PB EN pin is
at Low:
High: power save REC
Low: REC
—
(Open:
"L")
RP PB
1CH
40kΩ
20kΩ
VCC
100
20k
250
mVp-p
46
Input pin for ATF pilot signal.
ATF IN
46
2.5V
5
GND
REC/PB switchover signal for CH2:
High: PB
Low: REC
However, when RP PB EN pin is
at Low:
High: power save REC
Low: REC
—
(Open:
"L")
RP PB
2CH
Same as for Pin No. 1
Same as for Pin No. 2
47
48
40kΩ
20kΩ
—
250
mVp-p
Input pin for PCM signal.
PCM IN
3.2V
– 8 –
CXA1202Q-Z/CXA1202R
– 9 –
CXA1202Q-Z/CXA1202R
– 10 –
CXA1202Q-Z/CXA1202R
– 11 –
CXA1202Q-Z/CXA1202R
– 12 –
CXA1202Q-Z/CXA1202R
– 13 –
CXA1202Q-Z/CXA1202R
( P i n 2 0 ) V R F O U T
( P i n 1 0 ) A G C O U T
( P i n 8 ) P C M R F O U T
D O C D E T , R F S W
c o m p e n s a t i o n c i r c u i t ,
m e d i u m r a n g e f r e q .
C H 2 H E A D A M P
C H 1 H E A D A M P
( P i n 3 3 ) R E C 2 O U T
( P i n 2 8 ) R E C 1 O U T
( P i n 3 7 ) M I X 2 O U T
( P i n 2 4 ) M I X 1 O U T
( P i n 4 1 ) P C M S E L
( P i n 2 2 ) M U L T l
( P i n 3 9 ) R F S W P
( P i n 4 7 ) R P P B 2 C H
( P i n 4 5 ) R P P B 1 C H
( P i n 1 ) R P P B E N
– 14 –
CXA1202Q-Z/CXA1202R
1. Description of input condition
"High" … Control logic input, over 3V.
"Low" .… Control logic input, under 1V.
"—" …… Independent of High, Low.
2. Description of operation mode
O ……… Operating
X ……… Not operating
• In recording mode
V ......... VIDEO signal is output.
P ......... PCM signal is output.
MP....... ATF signal that passed through fixed 6-dB AMP in mix circuit is output, mixed with PCM signal.
• In playback mode
CH1 ...... CH1 signal is output.
CH2 ...... CH2 signal is output.
MUTE ... MUTE is applied to PB VIDEO signal in PCM after recording; at the same time, RF AGC gain is held.
– 15 –
CXA1202Q-Z/CXA1202R
A N I F R
N I 1 C E R
G H C H
φ F T M
T U O
C G A
µ 7 4 0 . 0
k 8 . 5
T U O
F R M C P
P 1 N I B P
N I
Y
P 2 N I B P
µ 7 4 0 . 0
µ 7 4 0 . 0
N I M F A
N I C
N I 2 C E R
N E B P P R
– 16 –
CXA1202Q-Z/CXA1202R
Description of Operations
The functional blocks, voltage supply and GND pins of CXA1202Q-Z and CXA1202R are configured as follows:
Block name
Voltage supply pin
GND pin
43
7
Mix AMP + SW section
27
34
27
34
21
CH1
CH2
CH1
CH2
REC AMP section
Head AMP section
40
21
40
Medium range frq. compensation
circuit + SW section
7
19
7, 17 (Output emitter follower section)
7, 17 (Output emitter follower section)
7, 17 (Peak hold section)
7
19
19
19
43
RF AGC section
RF SW section
Dropout detecting section
Control logic section
Standard voltage supply section in IC
(VREG, VG)
7
43
Individual blocks are described in the following paragraphs.
[Mix AMP + SW]
Here, each of Y, Chroma, AFM, ATF and PCM signals is input at a prescribed input level so that they are
mixed together internally to achieve an appropriate current value at the head, and output to MIX1 OUT pin
(CH1 signal) and MIX2 OUT (CH2 signal) at a correct timing.
Control is possible at ATF LEVEL pin (0 to 3dB at 0 to 5V, OPEN not allowed) when only the ATF recording
level is to be increased as required, and at ME LEVEL pin (0 to 3dB at 0 to 5V, OPEN not allowed) when only
the low range signal (Chroma + AFM + ATF) recording level is to be increased.
In MULTI PCM mode, the ATF recording level is boosted by 6dB.
In SW, the signal is output to MIX1 OUT and MIX2 OUT pins under control of the control logic section.
[REC AMP]
Mix AMP + SW output is input after it is converted into a suitable current by an external resistor, to drive the
head. Adjustment of the external resistor makes it possible to set a gain and DC bias current to match that of
the head.
Feedback dumping is applied to inhibit head resonance (refer to the Application Circuit), and take care that
capacitance coupling will not occur across the input and output.
Control signals of RP PB EN, RP PB 1CH and RP PB 2CH permit power saving in the channels while
recording (refer to the Control Logic Truth Table). Power saving of about 85mW is possible through a single
channel.
– 17 –
CXA1202Q-Z/CXA1202R
[Head AMP]
The playback signal from the head is amplified with low noise and high gain. For example, the equivalent input
1
√
noise level at 1MHz is 662pVrms/ Hz.
In PB, the total input capacitance 2 will be about 75pF. To inhibit resonance between this capacitance and the
head inductance, a feedback dumping is incorporated.
Connect a bypass capacitor for PB IN 1N and PB IN 2N pins between these pins and the rotary transformer
Vcc. So far as this capacitor is over 0.2µF, the low-Ievel frequency response does not deteriorate. Beside the
0.1µF good frequency response capacitor connected to pin VREG, by adding a capacitor of over 10µF,
degradation of noise level at low range can be prevented.
Take care not to allow capacitance coupling between PB output and Head AMP input.
1 and 2 See the next page.
[Medium range frequency compensation circuit + SW]
This corrects the frequency response of the PB signal. It is possible to set to and Q magnitude by means of the
external resistance value of MT Fφ and MTQ pins (refer to the Fφ graph). The amount of boost may be
adjusted through the external volumes of MT1 and MT2 pins (refer to the graph showing the effect of standard
response MT2 pin voltage on the amount of boost).
By controlling the control logic section, SW is changed over with the timing of RF SW (switching pulse), to
output PCM RF signals and VIDEO RF signals. Mute is applicable to VIDEO RF signals during PCM after
recording within the PCM recording area period.
[RF AGC]
The played back VIDEO RF signal are output here to achieve a constant level of 100mVp-p. The time constant
for AGC is set by means of the resistance and capacitance external to AGC TC pin.
At the input section of the detector a HPF with a cutoff frequency of about 1MHz is incorporated. This is to
permit detection within the Y signal band.
In PCM after recording, MUTE applies during the PCM recording area period to keep the gain on an
unchanged level.
[RF SW]
Signals input to RF IN A and RF IN B pins are selected by means of HCHG control signals and output via the
12-dB amplifier to RF OUT pin. This switch is utilized for SP/LP head changeover when a 4-head system is
employed.
[Dropout detection]
Dropout is detected here from RF signals of played-back VIDEO and dropout pulse is output. The time
constant is set by means of the external resistance and capacitance external to DOC TC pin.
The detection level is set in the interior with 400mVp-p input as standard to obtain optimum level.
Use an external coupling capacitance value of input of 47pF to achieve HPF function.
[Control Logic]
The IC is controlled from this section as it will save power when circuit blocks are not in use. Therefore, power
saving is automatically executed while all the power supplies are switched on. Many SWs are also available to
switch inputs or outputs with complicated timing. Internal logic circuits to control them are provided.
It is possible to achieve all possible combinations of inputs/outputs necessary for the basic operations by
means of the 13 modes shown in the Control Logic Truth Table.
L is set when the control logic pin is open.
[Standard voltage supplies in the IC]
VREG 4.2V and VG 2.5V are provided as the standard voltage supplies in the IC.
– 18 –
CXA1202Q-Z/CXA1202R
1
(Reference) Test Method of Head AMP C/N
(1) input signal
Level –42.0dBm [signal source: 50Ω]
(generates a voltage of 100µVp-p at both ends of 1Ω).
(2) Signal injection circuit
50Ω
49Ω
CXA1202Q-Z
CXA1202R
head AMP
1Ω
Signal source
B
A
Head inductance
1.55µH
Winding ratio
3:5
Fig. 1
The signal is input from A and B in Fig. 1. The equipment used for the input is shown in Fig. 2.
BNC
51Ω
1200Ω
A
1Ω
B
To drum GND
Notes) 1. A chip resistance is used for 1Ω (ordinary carbon resistance produces inductance.)
2. 49Ω is composed of 51Ω/1200Ω.
Fig. 2
During signal
(3) SPECTRUM ANALYZER setting conditions:
RBW:
VBW:
Sweep time: 500s
Span: 500kHz
10kHz
1Hz
C/N
During shortcircuit between A – B
5MHz
Span 500kHz
(4) Keep the medium range frequency compensation circuit flat. (Voltage of Pins MT1 and MT2 is made
equal to that of Pin VREG)
(5) Observe the output at Pin 20 V RF OUT.
2
The total input capacitance includes all capacitances of REC AMP, rotary transformer, shielding wire, etc.,
in addition to the input capacitance of the Head AMP alone (47pF).
– 19 –
CXA1202Q-Z/CXA1202R
A N I F R
N I 1 C E R
φ F T M
G H C H
H C 1 C C V
T U O
C G A
T U O
1 C E R
C T
C G A
µ 7 4 0 . 0
P 1 N I B P
N 1 N I B P
N 2 N I B P
P 2 N I B P
7 3 1 0 2 X C
2 N I B P
T U O
F R M C P
C C V
F P B
Q E
N I
Y
F R C E R
G V
T U O O C V
µ 7 4 0 . 0
µ 1 . 0
T U O
2 C E R
N I M F A
G E R V
H C 2 C C V
µ 0 1
µ 7 4 0 . 0
Q T M
N I
C
N I 2 C E R
N E B P P R
Q 4 0 2 1 A X C
F P L
F P L
N I t o l i P B P
T U O t o l i P C E R
– 20 –
CXA1202Q-Z/CXA1202R
Precautions
1. Do not connect parasite capacitance to REC AMP dumping.
C1
C1
Effect of C2
C2
Effect of C1
28
25
Frequency
REC AMP
2. Do not bring Head AMP input near PB output.
Normally, there is a gain of 67dB between Head Amp input (Pins 29, 30) and RFOUT (Pin 16). During no
signal, the gain is 74dB (as AGC reaches maximum gain). Bringing those closer on the pattern may cause
oscillations in the vicinity of 6 to 7MHz.
3. Use 150kΩ for RF AGC time constant, Resistance
Because a change in this R causes a change in the AGC output level, change the time constant using the
value of capacitance.
4. Watch the time constant of dropout detection.
Time constant: t = C × (R1//R2)
VCC
C: over 150pF
R2
R1
R2
R1, R2: 5 ×
= 1.2 to 2.0V
R1 + R2
Oscillations may occur unless this condition is satisfied.
15
DOC TC
C
5. Take AFM PB output from V RF OUT (Pin 20)
Passing AFM signal through RF AGC causes AGC to reach maximum gain when playing back a virgin tape.
As a result MUTE may not apply to AFM IC (CX20137, CX20037).
6. Adjust tape path by mixing V RE OUT signal and PCM RF OUT signal. In the absence of a signal before
switching, observe the envelope comprising the combination of the VIDEO area and the PCM area by
mixing outputs from V RF OUT (Pin 20) and PCM RF OUT (Pin 8).
RF SWP
V RF OUT
PCM RF OUT
After mixing
– 21 –
CXA1202Q-Z/CXA1202R
Mix AMP Chroma gain vs. ME LEVEL pin voltage
Mix AMP ATF gain vs. ATF LEVEL pin voltage
5
5
4
3
2
1
4
3
2
1
0
1
2
3
4
5
0
1
2
3
4
5
ME LEVEL pin voltage [V]
ATF LEVEL pin voltage [V]
Conditions: Input: Pin 2, 126mVp-p, 750kHz
Conditions: Input: Pin 46, 250mVp-p, 100kHz
Output: Pin 24
Logic A
Output: Pin 24
Logic A
Mix AMP Y output secondary distortion
factor vs. Frequency
REC AMP frequency response
–40
–50
–60
5
0
–5
–10
2
4
6
8
10
0
2
4
6
8
10 12 14 16 18 20
f – Frequency [MHz]
f – Frequency [MHz]
Conditions: Input: Pin 6, 250mVp-p
Output: Pin 37
Conditions: Input: At resistance (2.2kΩ) with Pin 25, 200mVp-p
Output: Pin 28, load resistance: 100Ω
Logic A
Logic A
REC AMP secondary distortion factor
vs. input level, output current
REC AMP distortion factor vs. Frequency
–40
–50
–60
–40
–50
Second
–60
Third
Input level
Output current
–16–14–12–10 –8 –6 –4
8 10 1315 20
0 [dBm]
[mAp-p]
2
4
6
8
10
f – Frequency [MHz]
6
Conditions: Input: At resistance (2.2kΩ) with Pin 25, 5MHz
Output: Pin 28, load resistance: 100Ω
Logic A
Conditions: Input: At resistance (2.2kΩ) with Pin 25, 200mVp-p
Output: Pin 28, load resistance: 100Ω
Logic A
– 22 –
CXA1202Q-Z/CXA1202R
V RF OUT secondary distortion factor vs.
Input level
Head AMP output level vs. Frequency
5
0
–40
–50
–60
–5
2
4
6
8
10
–6 –4 –2
0
2
4
6
8 10 12
f – Frequency [MHz]
Input level [dB]
Conditions: Input: 25µm-wide head for NTSC, 100mVp-p at head tip
Output: Pin 20
Conditions: Input: Pin 29, 0dB = 200mVp-p, 5MHz
Output: Pin 20
Logic H
Logic H, medium range freq. conpensation circuit boost: 0
CH1 → CH2 crosstalk at PCM RF OUT vs.
Frequency
CH1 → CH2 crosstalk at RF OUT vs. Frequency
–30
–40
–50
–30
–40
–50
2
4
6
8
2
4
6
8
f – Frequency [MHz]
Crosstalk
f – Frequency [MHz]
Crosstalk
Conditions: Input: Pin 29, 200µVp-p
Output: Pin 8
Conditions: Input: Pin 29, 200µVp-p
Output: Pin 20
29
32
29
32
20
2
Logic H
Logic I
0.1µF
0.1µF
Medium range freq. compensation circuit
MT2 pin voltage vs. Amount of boost
Crosstalk in MUTE at V RF OUT vs. Frequency
14
12
–50
–60
–70
10
8
6
4
2
0
1
2
3
4
5
2
4
6
8
10
f – Frequency [MHz]
MT2 pin voltage [V]
Crosstalk
Conditions: MT Fφ pin: 18kΩ
MT Q pin: 33kΩ
Conditions: Input: Pin 29, 200µVp-p
Output: Pin 20
29
20
Pin 41 voltage: 5V
Logic H
– 23 –
CXA1202Q-Z/CXA1202R
Medium range freq. compensation circuit MT Fφ,
MT Q pin connection resistance value vs. Fφ
Medium range freq. compensation circuit MT Fφ,
MT Q pin connection resistance value vs. Q
12
MT Q pin connection
resistance value [kΩ]
MT Q pin connection
resistance value [kΩ]
10
4.0
10
15
22
8
3.0
33
47
68
10
15
6
4
2
2.0
1.0
22
33
47
68
20
40
60
80
20
40
60
80
MT Fφ pin connection resistance value [kΩ]
MT Fφ pin connection resistance value [kΩ]
Medium range freq. compensation circuit
boost amount vs. Operating temperature
Medium range freq. compensation circuit Fφ, vs.
Operating temperature
200
100
13
12
11
10
0
–100
–200
–20
0
20
40
60
80
–20
0
20
40
60
80
Topr – Operating temperature [°C]
Topr – Operating temperature [°C]
Conditions: Input: Pin 29
Output: Pin 20
Conditions: Input: Pin 29
Output: Pin 20
Pin 23 voltage: 4.2V
Logic H
Pin 23 voltage: 4.2V
Q pin connection resistance value: 33kΩ
Fφ pin connection resistance value: 18kΩ
RF AGC Control characteristics
AGC output level vs. Operating temperature
VCC
150kΩ
0.047µF
2
1
0
9
1
0
–1
–2
–3
–4
–5
–6
–1
–16–12 –8 –4
0
4
8
12 16 18
–20
0
20
40
60
80
0dB = head tip, 100µVp-p [dB]
Topr – Operating temperature [°C]
Conditions: Input: 25µm-wide head for NTSC, 5MHz
Conditions: Input: Pin 29, 5MHz, 170µVp-p
Output: Pin 10
Logic I
Output: Pin 10
Logic H
Pin 9 time constant: R: 150kΩ, C = 0.047µF
– 24 –
CXA1202Q-Z/CXA1202R
Dropout detection ON level vs.
Operating temperature
Dropout detection OFF level vs.
Operating temperature
VCC
150kΩ
VCC
150kΩ
15
15
220pF
220pF
100kΩ
100kΩ
–10
–11
–12
–13
–14
–15
–4
–5
–6
–7
–8
–9
–20
0
20
40
60
80
–20
0
20
40
60
80
Topr – Operating temperature [°C]
Topr – Operating temperature [°C]
Conditions: Input: Pin 14
400mVp-p to 0dB at Pin 16
Conditions: Input: Pin 14
400mVp-p to 0dB at Pin 16
Logic H
Logic H
RF SW Crosstalk (A → B) vs. Frequency
0
–10
–20
–30
–40
–50
–60
2
4
6
8
10
16
f – Frequency [MHz]
Crosstalk
0.01µ
0.01µ
Conditions: Input: Pin 12, 100mVp-p
Output: Pin 16
12
14
Logic H
Pin 11 = 3V
– 25 –
CXA1202Q-Z/CXA1202R
Package Outline
Unit: mm
48PIN QFP (PLASTIC)
CXA1202Q-Z
15.3 ± 0.4
+ 0.1
0.15 – 0.05
+ 0.4
12.0 – 0.1
0.15
36
25
24
37
+ 0.2
0.1 – 0.1
48
13
1
12
+ 0.15
0.3 – 0.1
0.8
0.24
M
+ 0.35
2.2 – 0.15
PACKAGE STRUCTURE
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
SOLDER / PALLADIUM
PLATING
SONY CODE
EIAJ CODE
QFP-48P-L04
QFP048-P-1212
42/COPPER ALLOY
0.7g
JEDEC CODE
PACKAGE MASS
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
48PIN LQFP (PLASTIC)
CXA1202R
9.0 ± 0.2
7.0 ± 0.1
36
25
24
13
37
A
48
(0.22)
0.13
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.2
1.5 – 0.1
+ 0.08
0.18 – 0.03
0.1
M
0.1 ± 0.1
0° to 10°
NOTE: Dimension “ ” does not include mold protrusion.
PACKAGE STRUCTURE
DETAIL A
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
EPOXY RESIN
SOLDER/PALLADIUM
SONY CODE
EIAJ CODE
LQFP-48P-L01
LQFP048-P-0707
PLATING
42/COPPER ALLOY
0.2g
JEDEC CODE
PACKAGE MASS
– 26 –
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