CXA1203M/N [ETC]
8mm VCR PAL JOG ; 8毫米VCR PAL JOG\n
| 型号： | CXA1203M/N |
| 厂家： | 
ETC |
| 描述： | 8mm VCR PAL JOG
|
| 文件： | 总28页 (文件大小：294K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CXA1203M/N
8mm VCR PAL JOG
Description
CXA1203M
CXA1203N
The CXA1203M/N compensates the color alignment
in variable speed mode for PAL-system 8mm VCRs.
This IC is also available for the SECAM system with
the built-in SECAM detector and BELL and C-BELL
filters.
24 pin SOP (Plastic)
24 pin SSOP (Plastic)
Features
• Color alignment compensation which does not
require 1H delay line
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage VCC 7.0
• Operating temperature Topr –20 to +75
• Storage temperature Tstg –55 to +150
• Allowable power dissipation
• No AFC (fH) adjustment necessary
• Built-in SECAM detector
V
°C
°C
• Built-in BELL and C-BELL filters
• Available for the PAL-M system
PD
CXA1203M
CXA1203N
567
536
mW
mW
Functions
V-Invert circuit, TH/DL APC, 2fsc PLL, SQ DET,
EX burst circuit, AFC (fH), Timing generator,
SECAM detector, BELL filter, C-BELL filter
Recommended Operating Conditions
Supply voltage 4.5 to 5.5
(5.0V typ.)
V
Structure
Silicon monolithic IC
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
– 1 –
E01Z33-PS
CXA1203M/N
V R E G
I R E F
G N D
C S y n c
C O U T
H D
L P F
A F C
L P F
D A P C
L P F
S Q I D
f s c I N
S E C A M
J U M P
S E C A M
A D J
D G A I N
D L D P
I N
S A M
7 5 % C
M O D E
1 / 2 F H M
A C K
S E C A M
B E L L I N
A φ D J
P B C I N
F I L T E R
B L
C C V
– 2 –
CXA1203M/N
Pin Description
Voltage
Pin
Symbol
No.
Equivalent circuit
Description
DC
AC
5.0V
(typ.)
1
VCC
—
—
Supply voltage pin
3.0V
60k
VCC
Input pin of PAL playback
chrominance signal.
The chroma ACK operates to
cut off the output at Pin 15
when the DC bias voltage at
Pin 2 is 0.7V or less.
350mVp-p
150mVp-p
(burst)
PR
47k
PB C
IN
2
2
15.2p
SECAM detector output pin.
H → SECAM
L → PAL
The SECAM or PAL mode is
fixed by applying an external
DC voltage.
SECAM: 3.0 to 5.0V
PAL: 0 to 1.0V
20k
VCC
10k
(Sub)
PR
3.8V
(H)
8k
SECAM
ACK
20k
3
—
3
0V
(L)
VCC
(×2)
PR
Output pin of the pulse
3.2V
1.7V
1/2
FHMP
4
—
4
obtained by dividing down the
AFC (fH-PLL) output by 2.
(×2)
4k/2
Connecting pin of the
28k
8k
VCC
charging and discharging
capacity to produce the
triangular wave chronized
with the C Sync signal.
All timing pulses used in the
IC are produced from this
triangular wave.
(×3)
3.5V
1.0V
PR
5
75% C
—
(Sub)
5
(×3)
20k/3
– 3 –
CXA1203M/N
Voltage
Pin
No.
Symbol
Equivalent circuit
Description
DC
AC
VCC
Input pin to switch the polarity
of the 1/2FHT pulse for the
SECAM detector.
PR
2.8V
(H)
6
DLDP
1.4Vp-p
6
1.4V
(L)
Output pin of the AFC ID
1
signal in TEST mode .
8k
Output pin to switch the
polarity of the 1/2FHT pulse.
Mode selection 1 is possible
by applying an external DC
voltage.
PAL-M: 0 to 0.5V
Normal: OPEN
RESET: 3.6 to 4.1V
TEST: 4.3 to 5.0V
100k
VCC
2.8V
(H)
(Sub)
SECAM
JUMP
7
1.4Vp-p
PR
1.4V
(L)
7
20k
20k
10k
10k
4k
VCC
100k
PR
Connecting pin of the time
constant of the LPF for the
SECAM detector.
SECAM
LPF
8
(Sub)
8
2.5V
—
4k
2k
10k
10k
VCC
1k
20k
6.5k
(Sub) (Sub)
Connecting pin of the time
constant of the LPF for the
AFC (fH-PLL).
(×4)
(×2)
PR
AFC
LPF
9
2.0V
—
9
4k/2
1k
– 4 –
CXA1203M/N
Voltage
AC
Pin
No.
Symbol
Equivalent circuit
Description
DC
VCC
20k
(×2)
PR
4.0V
Output pin of the HD pulse
produced in the AFC (fH-PLL).
10 HD
—
10
1k
0.4V
(×2)
(Sub)
20k
46k
20k
Input pin of the composite
sync signal.
2.0V
11 C Sync
The internal threshold voltage
is 2.0V and the polarity is
active HIGH.
PR
11
12 GND
—
—
—
GND pin
VCC
(×32)
Output pin of the regulated
voltage source in the IC
(4.2V).
Connected to
about 30
elements
VREG
13
4.2V
—
13
23p
8k
40k
VCC
Connecting pin of the
standard resistance to
produce the reference
current source in the IC.
(Sub)
PR
14 IREF
2.1V
—
14
(×2)
IREF
4k
10k
– 5 –
CXA1203M/N
Voltage
DC AC
Pin
No.
Symbol
Equivalent circuit
Description
VCC
In PAL
mode
2.1V 350mVp-p
150mVp-p
(burst)
Output pin of the playback
PAL signal (TH, DL and EX
burst) , SECAM signal and
PR
(×4)
2.5k
15
15 C OUT
2
PAL-M signal.
VCC
Connecting pin of the time
constant of the LPF for the
TH/DL APC loop.
The TH/DL lock phase can
be varied by applying an
external DC current.
PR
DL APC
LPF
16
2.4V
—
16
PR
Output pin of the SQ detector.
The TH or DL output signal at
Pin 15 can be selected by
applying an external DC
voltage.
8k
VCC
4.0V
(H)
(Sub)
PR
17 SQ ID
—
17
0V
(L)
20k
DL: 0 to 2.0V
TH: 3.0 to 5.0V
10k
VCC
PR 10.4p
Input pin of the fsc.
18
—
18 fsc IN
350mVp-p
(chrominance subcarrier)
30k
4k
– 6 –
CXA1203M/N
Voltage
Pin
No.
Symbol
Equivalent circuit
Description
DC
AC
VCC
Control pin of the DL signal
gain.
15k
PR
The gain can be varied by
applying an external DC
voltage. The internally fixed
gain is obtained at 5.0V.
Output pin of the S/H circuit
in TEST mode.
19
DL GAIN 5.0V
19
13.4k
13.4k
ADJ
(typ.)
2670
VCC
PR 15.2p
10k
40k
20
SECAM
IN
Input pin of the SECAM
detector in REC mode.
150mVp-p
(burst)
—
20
20k
8k
Mode selection 1 is possible
by applying an external DC
voltage.
VCC
(Sub)
PR
—
—
21 MODE
REC: 0 to 1.3V
21
PB: 1.7 to 2.8V
JOG: 3.2 to 5.0V
VCC
15.2p
4k
83mVp-p
(SECAM
burst)
Input pin of the SECAM
signal.
Input pin of the SECAM
detector in playback mode.
13.5k
38k
15.2p
PR
BELL
22
22
IN
—
15k
117mVp-p
(PAL
100k
burst)
– 7 –
CXA1203M/N
Voltage
Pin
No.
Symbol
Equivalent circuit
Description
DC
AC
VCC
30k
EX burst phase adjustment
pin.
PR
(Sub)
23
The phase can be varied by
applying an external DC
voltage. The internally fixed
phase is obtained at 5.0V.
VCO output pin in TEST
mode.
5.0V
(typ.)
23
—
φADJ
38k 38k
(×2)
10k
2k
200
Connecting pin of the time
constant of the BELL and
C-BELL filters.
BELL
FILTER
(×2)
24
3.0V
—
24
4k
1k
70
(×5)
(×3)
Notes)
1
Refer to Mode Description.
2
PAL playback signal (TH, DL and EX burst)
The DL signal is symmetrical to the TH signal (PAL playback signal) about the B-Y axis.
The burst signal produced from the fsc (chrominance subcarrier) in the IC is known as the EX burst.
The EX burst is inserted into the playback chrominance signal in JOG mode.
– 8 –
CXA1203M/N
Mode Description
Mode
PAL
Control pin
Voltage
0 to 1.0V
Description
Fixed PAL mode
—
Pin 3
High impedance
3.0 to 5.0V
Automatic selection of PAL or SECAM
Fixed SECAM mode
SECAM
The PAL-M signal is output from Pin 15 by inputting
an NTSC signal to Pin 2.
(For details, see "Notes on Use".)
PAL-M
RESET
0 to 0.5V
Pin 7
The logic block (AFC ID, 150% masking and 1/2
division) in the AFC (fH-PLL) is turned off.
3.6 to 4.1V
The operation of the AFC ID, VCO and S/H blocks in
the AFC (fH-PLL) is checked.
TEST
DL
4.3 to 5.0V
0 to 2.0V
The DL signal is output from Pin 15.
The TH or DL signal selected by the SQ detector
decision is output.
—
Pin 17
Pin 21
High impedance
TH
REC
PB
3.0 to 5.0V
0 to 1.3V
The TH signal is output from Pin 15.
REC mode
1.7 to 2.8V
Playback mode
The EX burst is inserted into the original burst signal
portion in PAL playback mode.
JOG
3.2 to 5.0V
– 9 –
CXA1203M/N
– 10 –
CXA1203M/N
– 11 –
CXA1203M/N
– 12 –
CXA1203M/N
– 13 –
CXA1203M/N
– 14 –
CXA1203M/N
– 15 –
CXA1203M/N
– 16 –
CXA1203M/N
Fig. 1. Electrical Characteristics Test Circuit
5V
100k
VSE
5V
4.43MHz
H
SW5
BPF
0.1µ
1.2k
SW4
G
1k
V17
0.01µ
Vfsc
50k
5V
5V
SW3
33p
0.1µ
820
1500p
10µ
V21
50k
39
20k
20k
2k
1µ
F
E
100k
24
23
22
21
20
19
18
17
16
15
14
13
TH
Dummy
CONV1
PB
PB
XPB
REC (Se)
MODE
BELL
C-BELL
DL
MAIN
SW
AMP
LIM
PB (Se)
REC
PB (PAL)
SWD
TH/DL
PAL-M
V-I2
CW
1/2FHM
TH/DL
(1/2FHTA)
LIM2
SW
PAL
BF Xch
TH/DL
–90°
×2
LPF2
LIM1
(1/2FHTA)
PAL-M
V-I1
PAL-M
LPF1
BF
BF
SQ
P.D.
LPF3
TH/DL
XFHM
1/2FHM
XSHP
MASK 75 – 1
D
U ERRI
D ERRI
D
1/2FHM
AFC
ID
BF
Gen
1/2FHTAB
SWD1/2FHM
SWD1/2FHT
HD
D
75%
MASK2
EDGE
75%
75%
→ 150%
1/2
VCO
S/H
TRIG MASK1
MASK
75 – 2
LPF
SA CONT
CONT
SWD SECAM
1/2FHM
EDGE
TRIG
CLG PLS
1/2FHT DETPLS
CLP PLS
Clamp
BELL IN
SECAM IN
SECAM
Peak
Hold
Secam
P. D.
LPF2
S/H
FM
DEMOD
LPF1
Normal
1/2
FHT
Jump
P. D.
TEST
RST
Normal
H ID
1
2
3
4
5
6
7
8
9
10
11
12
3.3µ
1000p
4.7k
10k
110p
50k
5k
0.047µ
10k
V2
4.7µ
SW1
V3
SW2
A
0.01µ
Vsync
V7
VCC
VPAL
B
C
D
– 17 –
CXA1203M/N
Description of Functions
1. Gain Adjustment Amplifier (DL Signal)
This amplifier adjusts the gain of the DL signal in PAL or PAL-M mode. The amplifier gain varies according
to the DC voltage applied to Pin 19. When 5V is applied to Pin 19, the internally fixed gain is obtained and
the levels of the TH signal and the DL signal (4.43MHz component in PAL mode, 3.58MHz component in
PAL-M mode) become the same.
×
2. fsc –90° PLL, 2 and EX Burst Block
cos ωt
cos (ωt – 90°)
fsc
cos ωt
2fsc
cos (2ωt – 90°)
–90°
18
23
LIM
V → I
LPF1
φADJ
cos (ωt – 180°)
EX Burst
√2 cos (ωt – 45°)
√2 cos (ωt – 135°)
cos ωt
1/2fH
Fig. 2
The fsc –90° PLL consists of the –90° phase shifter, multiplier, LPF (low pass filter) 1 and V/I converter.
A signal delayed by 90° to the fsc is obtained in this PLL. By changing the DC voltage at Pin 23, the
amount of phase shift is varied. allowing adjustment of the phase of the EX burst and the duty (DC offset)
of the 2fsc. By applying 5V at Pin 23, the internally fixed phase shift is obtained. The 2fsc is produced
from the multiplier output (×2 output).
The EX burst is produced by adding the fsc (or inverted fsc) to the fsc with 90° delay produced in the –90°
PLL.
The fsc and the inverted fsc are switched in a period of 1/2fH, so the phase of the EX burst changes every
1H.
– 18 –
CXA1203M/N
3. SQ DET (Sequence Detector)
Chrominance signal
SQ
P.D.
fsc
SQ
17
LPF3
1/2fH
Burst Flag Gate
Fig. 3
The SQ DET detects the color alignment of the chrominance signal. The SQ PD is the phase detector which
operates for a burst period only. This detects the color alignment by comparing the phase of the fsc signal
inverted every 1H with the phase of the burst of the chrominance signal.
Output at Pin 17
4V
0V
–180°
–135°
–90°
–48°
0
+48°
+90°
+135°
+180°
–112°
+112°
Phase of the burst signal
(on the bias of fsc and fsc)
Fig. 4
The above figure shows the relation between the phase of the burst signal, the phase of the fsc (fsc) and
the output at Pin 17 (SQ). As shown in the figure, the hysteresis angle is about 64°. If the relation is as
shown in the figure below, the detector judges it as the correct sequence and set the output at Pin 17 to
HIGH.
fsc
Burst
+135°
B-Y
B-Y
–135°
Burst
fsc
Fig. 5
Therefore, the center phase of the burst signal (about the B-Y axis) should be –90° to the fsc.
– 19 –
CXA1203M/N
4. V-Invert (V Axis Inversion Circuit)
For color alignment, the DL signal which is produced by inverting the chrominance signal (TH signal) about
the B-Y axis is necessary.
The V-Invert block produces the DL signal from the TH signal. Fig. 6 shows the principle of the V-Invert
block.
TH: cos (ωt ± θ)
To
BPF
Playback chrominance
signal
Y/C MIX BLOCK
cos (ωt ± θ)
DL: cos (ωt ± θ)
cos (3ωt ± θ)
cos 2ωt
θ
θ
×2
Rejected by the BPF.
fsc (cos ωt)
Fig. 6
Define the B-Y axis of the playback chrominance signal as cos ωt and input the playback chrominance
signal and the 2fsc (cos 2ωt) to the multiplier. By means of the frequency conversion of the 2fsc, the input
chrominance signal is inverted about the B-Y axis. The three fold frequency component (cos 3ωt) is also
output, but this component is rejected by the BPF in a later stage.
Fig. 7 shows the actual V-Invert block.
TH/DL
BF Xch
Dummy
CONV1
TH
DL
Playback chrominance
signal
15
Main
SW
C OUT
SWD
1/2fH
PAL
φ
V-I
LPF2
PAL-M
2fsc
BF Gate fsc
EX Burst
Fig. 7
The V-Invert circuit constructs the TH/DL APC loop that keep the phase difference between the burst of the
TH signal and the burst of the DL signal to be 90°. This circuit detects the phase of the bursts of the TH and
DL signals and varies the delay time of the phase shifter φ with reference to the error current of APC loop.
In PAL-M mode, the APC is applied to the fsc and the DL signal. Therefore, the input burst signal has a
phase of 90° to the fsc. The CONV1 is a multiplier to obtain the DL signal.
The Dummy supplies the same gain loss and the same phase delay as produced in CONV1 to the TH
signal so that there is no gain and phase difference between the TH signal and the DL signal.
The main SW outputs the TH or DL signal according to the TH/DL select signal (output at Pin 17). When a
BF Xch pulse is supplied (in JOG mode only), the EX burst is output.
– 20 –
CXA1203M/N
5. fH PLL
AFC
ID
C Sync
11
HD
1/2
10
HD
VCO
LPF
S/H
XSHP
1/2fH
SWD 1/2fH
Fig. 8
The AFC ID compares the C Sync frequency with the VCO frequency. When a frequency difference is
present, the AFC ID outputs an up or down error and roughly compensates the VCO frequency. In this
case, the AFC ID detects if the frequency difference continues for a period of 15H × 6 (5760µs), and AFC
ID error is available only when the frequency difference continues for that period.
The AFC ID also detects the existence of C Sync. When the C Sync is missing in various speed mode, the
AFC ID cuts off its output and maintains the state immediately before the output cutout.
The phase lock of the C Sync and VCO frequencies is carried out in the PLL loop composed of the S/H and
LPF circuits.
6. BELL and C-BELL Filters
The Bell Filter is applied to the SECAM color TV signal to suppress the level near the chrominance subcarrier
(FOR, FOB). In REC mode, the CXA1203 employs the BELL filter (having the inverted characteristics from the
Bell Filter) to obtain the chrominance subcarrier of the same amplitude at every hue. The output signal from
the BELL filter is sent to the record signal processing block of chrominance signal in the CXA1200.
In playback mode, the chrominance signal processed in the CXA1200 is input to the C-BELL (having the
same characteristics as the Bell Filter) filter of the CXA1203 to equalize the input signal with the SECAM
color TV signal. The output from the C-BELL Filter is mixed with the Y signal in the CXA1200 and sent to
the CXA1201. The typical input level of the BELL Filter is 32mVp-p, and that of the C-BELL Filter is 83mVp-p.
7. SECAM Detector Circuit
The SECAM detector circuit employed in the CXA1203 converts the chrominance subcarrier frequency 1 to
a voltage, and detects the color system by the voltage variation: PAL system if no voltage variation is
present, or SECAM system if the voltage varies every 1H. When the color alignment is carried out in
SECAM mode, the SECAM ACK output (Pin 3) is always set to HIGH by inputting the SECAM JUMP output
(Pin 7) to the DLDP (Pin 6).
1
PAL system:
color burst signal (4.43361875MHz)
SECAM system: line ID signal FOR: 4.40625MHz
FOB: 4.25000MHz
– 21 –
CXA1203M/N
Fig. 9. Application Circuit 1 (for PAL/SECAM mode)
5V
5V
20k
1k
0.01µ
100p
fsc IN
20k
1k
10p
1k
20k
33k
BELL IN
SECAM IN
5V 5V
5V
2.2k
0.01µ
PB
BPF
CHROMA
OUT
1.2k
1k
22k
1k
1.5k
1k
0.01µ
33p
1µ
0.1µ
100k
820
100k
20k
10µ
1500p
100k
39
100k
20
24
23
22
21
19
18
17
16
15
14
13
TH
Dummy
PB
PB
XPB
REC (Se)
MODE
BELL
C-BELL
DL
MAIN
SW
AMP
CONV1
LIM2
LIM
PB (Se)
PB (PAL)
REC
SWD
1/2FHM
TH/DL
PAL-M
V-I2
CW
TH/DL
(1/2FHTA)
SW
PAL
BF Xch
TH/DL
–90°
×2
LPF2
LIM1
(1/2FHTA)
PAL-M
V-I1
LPF1
BF
BF
SQ
P.D.
LPF3
PAL-M
TH/DL
XFHM
1/2FHM
XSHP
MASK 75 – 1
D
U ERRI
D ERRI
D
1/2FHM
AFC
ID
BF
Gen
1/2FHTAB
HD
D
75%
MASK2
EDGE
75%
75%
→ 150%
SWD1/2FHM
SWD1/2FHT
1/2
VCO
S/H
TRIG MASK1
MASK
75 – 2
LPF
SA CONT
CONT
SWD SECAM
1/2FHM
EDGE
TRIG
CLG PLS
1/2FHT DETPLS
CLP PLS
Clamp
BELL IN
SECAM IN
SECAM
Peak
Hold
Secam
P. D.
LPF2
S/H
FM
DEMOD
LPF1
Normal
1/2
FHT
Jump
P. D.
TEST
RST
Normal
H ID
1
2
3
4
5
6
7
8
9
10
11
12
Vcc
5V
5V
10k
4.7k
10µ
0.01µ
3.3µ
110p
0.022µ
15k
1000p
4.7µ
0.01µ
1k
10k
390k
27k
SECAM ACK
C Sync
PB CHROMA IN
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 22 –
CXA1203M/N
5V
5V
Fig. 10. Application Circuit 2 (for PAL mode only)
20k
1k
0.01µ
100p
fsc IN
20k
1k
10p
1k
20k
33k
5V 5V
5V
2.2k
0.01µ
PB
BPF
CHROMA
OUT
1k
22k
1k
1.5k
1k
0.01µ
1µ
100k
20k
100k
100k
20k
10µ
1500p
100k
24
23
22
21
20
19
18
17
16
15
14
13
TH
Dummy
PB
PB
XPB
REC (Se)
MODE
BELL
C-BELL
DL
MAIN
SW
AMP
CONV1
LIM2
LIM
PB (Se)
REC
PB (PAL)
SWD
1/2FHM
TH/DL
PAL-M
V-I2
CW
TH/DL
(1/2FHTA)
SW
PAL
BF Xch
TH/DL
–90°
×2
LPF2
LIM1
(1/2FHTA)
PAL-M
V-I1
PAL-M
LPF1
BF
BF
SQ
P.D.
LPF3
TH/DL
XFHM
1/2FHM
XSHP
MASK 75 – 1
D
U ERRI
D ERRI
D
1/2FHM
1/2FHTAB
SWD1/2FHM
SWD1/2FHT
AFC
ID
BF
Gen
HD
D
75%
MASK2
EDGE
75%
75%
→ 150%
1/2
VCO
S/H
TRIG MASK1
MASK
75 – 2
LPF
SA CONT
CONT
SWD SECAM
1/2FHM
EDGE
TRIG
CLG PLS
1/2FHT DETPLS
CLP PLS
Clamp
BELL IN
SECAM IN
SECAM
Peak
Hold
Secam
P. D.
LPF2
S/H
FM
DEMOD
LPF1
Normal
1/2
FHT
Jump
P. D.
TEST
RST
Normal
H ID
1
2
3
4
5
6
7
8
9
10
11
12
Vcc
10k
4.7k
10µ
0.01µ
1000p
110p
4.7µ
0.01µ
10k
C Sync
PB CHROMA IN
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 23 –
CXA1203M/N
Notes on Use
1. Phase Adjustment in PAL Playback Mode
The phase of the EX burst signal can be adjusted with the phase of the input fsc (chrominance subcarrier).
The phase of the DL signal can be adjusted by applying a current to Pin 16.
Adjust the phase of the fsc so that the phase of the EX burst signal in JOG playback mode matches the
phase of the color burst signal in normal playback mode at the PB CHROMA output (Pin 15).
Then, adjust the current to be applied to Pin 16 so that the DL signal becomes symmetrical to the TH signal
about the B-Y axis.
2. PAL-M Mode
R-Y
R-Y
EX burst
B-Y
B-Y
TH and DL
signals
Input signal
fsc
fsc
Input
Output
Fig. 11
Input an NTSC signal to Pin 2, the fsc signal (3.58MHz) to Pin 18 and the C Sync signal (15.75MHz) to Pin 11.
Then the PAL-M playback signal is obtained at PB CHROMA output (Pin 15).
To adjust the phase, first input a burst signal with the same phase as the B-Y axis, and adjust the phase of
the fsc to be input so that the phase of the TH signal matches the center phase of the EX burst at Pin 15.
Then adjust the current to be applied to Pin 16 so that the phase of the DL signal matches the center phase
of the EX burst. In PAL-M mode, Pin 17 (SQ ID) should be fixed to "L".
3. PAL Only Mode
In PAL only mode, a part of the SECAM detector block is turned off by fixing Pin 22 (BELL IN) to "H". This
reduces the current consumption to 1.2mA. The connections for other pins are the same as shown in "Fig. 10
Application Circuit 2 (for PAL mode only)".
– 24 –
CXA1203M/N
Example of Representative Characteristics
VREG supply voltage characteristic
BELL Filter characteristic
4.25
16.0
14.0
12.0
10.0
8.0
4.24
4.23
4.22
4.21
6.0
4.0
2.0
0
4.50
4.75
5.00
5.25
5.50
3.786
4.286
4.786
Vcc (Pin 1) [V]
f – Frequency [MHz]
Vcc = 5.0V
SECAM/REC mode
Input level: 32mVp-p (BELL IN)
Output: C OUT (Pin 15)
C-BELL Filter characteristic
TH/DL/EX burst output level vs. Ambient temperature
160
16.0
14.0
12.0
10.0
8.0
6.0
4.0
2.0
0
TH
140
DL
120
EX burst
100
3.786
4.286
4.786
–10
0
25
50
75
f – Frequency [MHz]
Ta – Ambient temperature [°C]
Vcc = 5.0V
Vcc = 5.0V
SECAM/PB mode
PAL/PB mode
Input level: 83mVp-p (BELL IN)
Output: C OUT (Pin 15)
Input level: 150mVp-p (PB C IN)
fsc: 350mVp-p
Output: 4.43MHz BPF OUT
(The output level is the average during 2H.)
– 25 –
CXA1203M/N
TH/DL/EX burst phases vs. Ambient temperature
SQ DET input/output vs. Ambient temperature
112
120
100
80
110
108
106
104
Output at Pin 17
L → H
102
100
98
EX burst
TH
Output at Pin 17
H → L
60
96
DL
94
92
–10
40
0
25
50
75
0
25
50
75
Ta – Ambient temperature [°C]
Ta – Ambient temperature [°C]
Vcc = 5.0V
Vcc = 5.0V
PAL/PB mode
Input level: 150mVp-p
(PB C IN)
fsc: 350mVp-p
Output: C OUT (Pin 15)
The phase is the absolute value
determined by measuring the
center angle of the TL, DL or EX
burst during 2H with reference to
the fsc (at Pin 18).
PAL/RESET mode
Input level: 150mVp-p
(PB C IN)
fsc: 350mVp-p
Output: SQ ID (Pin 17)
The phase of the input
signal is the absolute value
of the phase delay to the
fsc. This is determined by
delaying the phase of the
input signal to the fsc and
measuring the phase delay
when the output changes.
Relation of the phase of each pulse to the C Sync signal
C Sync
(Pin 11)
A
B
HD
(Pin 10)
C
D
EX burst
(Pin 15)
Phases of the HD and EX burst vs. Ambient temperature
C
5.0
D
B
4.0
3.0
2.0
1.0
0
A
0
25
50
75
Ta – Ambient temperature [°C]
– 26 –
CXA1203M/N
Package Outline
Unit: mm
24PIN SOP (PLASTIC)
CXA1203M
+ 0.4
1.85 – 0.15
+ 0.4
15.0 – 0.1
0.15
24
13
+ 0.2
0.1 – 0.05
12
1
+ 0.1
1.27
0.45 ± 0.1
0.2 – 0.05
0.24
M
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SOLDER PLATING
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
SOP-24P-L01
SOP024-P-0300
42/COPPER ALLOY
0.3g
JEDEC CODE
24PIN SOP (PLASTIC)
Kokubu Ass'y
+ 0.4
1.85 – 0.15
+ 0.4
15.0 – 0.1
0.15
24
13
+ 0.2
0.1 – 0.05
12
1
+ 0.1
1.27
0.45 ± 0.1
0.2 – 0.05
0.24
M
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SOLDER PLATING
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
SONY CODE
EIAJ CODE
SOP-24P-L01
SOP024-P-0300
42/COPPER ALLOY
0.3g
JEDEC CODE
LEAD PLATING SPECIFICATIONS
ITEM
SPEC.
LEAD MATERIAL
COPPER ALLOY
Sn-Bi Bi:1-4wt%
5-18µm
SOLDER COMPOSITION
PLATING THICKNESS
– 27 –
CXA1203M/N
Package Outline
Unit: mm
24PIN SSOP (PLASTIC)
CXA1203N
+ 0.2
1.25 – 0.1
7.8 ± 0.1
0.1
24
13
A
1
b
12
0.13
M
0.65
B
b=0.22 ± 0.03
0.1 ± 0.1
DETAIL B : PALLADIUM
0° to 10°
NOTE: Dimension " " does not include mold protrusion.
PACKAGE STRUCTURE
DETAIL
A
EPOXY RESIN
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PALLADIUM PLATING
SONY CODE
EIAJ CODE
SSOP-24P-L01
P-SSOP24-7.8x5.6-0.65
COPPER ALLOY
0.1g
JEDEC CODE
PACKAGE MASS
– 28 –
Sony Corporation
相关型号：
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