USB97C202-MN-05 [SMSC]
USB Bus Controller, CMOS, PQFP100, 12 X 12 MM, 1.40 MM HEIGHT, STQFP-100;
| 型号： | USB97C202-MN-05 |
| 厂家： | 
SMSC CORPORATION |
| 描述： | USB Bus Controller, CMOS, PQFP100, 12 X 12 MM, 1.40 MM HEIGHT, STQFP-100 时钟 外围集成电路 |
| 文件： | 总20页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB97C202
USB2.0 ATA/
ATAPI Controller
Datasheet
Product Features
2.5 Volt, Low Power Core Operation
3.3 Volt I/O with 5V input tolerance
Complete USB Specification 2.0 Compatibility
Double Buffered Bulk Endpoint
−
−
−
Bi-directional 512 Byte Buffer for Bulk Endpoint
64 Byte RX Control Endpoint Buffer
64 Byte TX Control Endpoint Buffer
−
Includes USB2.0 Transceiver
Internal or External Program Memory Interface
−
A Bi-directional Control and a Bi-directional Bulk
Endpoint are provided.
−
48K Byte Internal ROM or optional 64K Byte
External Code Space using Flash, SRAM, or
EPROM Memory
Complete System Solution for interfacing ATA or
ATAPI devices to USB2.0 bus
On Board 12Mhz Crystal Driver Circuit
−
Supports USB Mass Storage Compliant Bootable
BIOS
Internal PLL for 480Mhz USB2.0 Sampling,
30Mhz MCU clock, and 60Mhz ATA clock
−
−
−
Supports ATA6 Drive capacities up to 2048GB
True UDMA Mode 4 transfer rates
Support for ATAPI Devices:
- CD-ROM
Supports firmware upgrade via USB bus if “boot
block” Flash program memory is used for optional
external program memory
- CD-R
- CD-RW
- DVD
- DVD/R/W
7 GPIOs for special function use: LED indicators,
button inputs, etc.
−
Inputs capable of generating interrupts with either
edge sensitivity
−
−
USB High Speed LED
8051 8 bit microprocessor
Serial EEPROM interface for VID/PID/Serial
Number Customization (Required for internal ROM
operation)
−
Provides low speed control functions
−
30 Mhz execution speed at 4 cycles per instruction
average
Can share drive in MP3 player and 1394/USB
applications by isolating the IDE Interface with
other controllers.
100 Pin STQFP (12x12x1.4 body, 2mm footprint)
or 100 Pin TQFP (14x14x1.4 body, 2mm
footprint) package.
−
768 Bytes of internal SRAM for general purpose
scratchpad or program execution while re-flashing
external ROM
ORDERING INFORMATION
Order Number(s):
USB97C202-MN-04 for 100 pin STQFP package
USB97C202-MN-05 for 100 pin STQFP package
USB97C202-MD-05 for 100 pin TQFP package
SMSC USB97C202
Page 1
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
80 Arkay Drive
Hauppauge, NY 11788
(631) 435-6000
FAX (631) 273-3123
Copyright © SMSC 2004. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete
information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no
responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without
notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information
does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of
SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's
standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or
errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon
request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure
could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC
and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms
of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems
Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES
OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND
ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.
IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;
OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON
CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR
NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
SMSC USB97C202
Page 2
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
USB97C202 Datasheet Revision History
DATE
REVISED
Rev 1.6
(11-05-04)
Rev 1.6
(9-29-04)
Rev 1.6
NAME
SECTION/FIGURE/ENTRY
Features
CORRECTION
H. Wurzburg
Modified third sub bullet under 7
GPIO’s
Changed the firmware extension from
-04 to -05 for the order numbers
M.Bohm
M.Bohm
Ordering Information, cover
Chapter 9 Package Outline, page 19
Added the 100 pin TQFP package
(9-29-04)
Rev. 1.5
(02-04-04)
Rev. 1.5
(11-07-03)
Rev. 1.5
(11-04-03)
Rev. 1.5
(11-04-03)
Rev. 1.5
(11-04-03)
P. Konasewich References to TQFP package
changed to STQFP package.
M. Bohm
M. Bohm
M. Bohm
M. Bohm
Cover – Ordering Information
Removed USB97C202-MN-03.
Revised Input Leakage.
Table 7.1 - DC Electrical
Characteristics, page 15
Chapter 2 - Pin Table, page 6
Changed test pin names to nTEST0,
nTEST1 & nTEST2
Changed nTest[0:2] to nTEST[0:2]
and clarified the functionality of the
XNOR test function.
Table 5.1 - USB97C202 Pin
Descriptions, page 9
H. Wurzburg
Table 5.1 - USB97C202 Pin
Descriptions, page 9
Ordering information, Cover
Revised description of the following
Rev. 1.4
(04/02/03)
1/23/03
pins: GPIO1 and GPIO4.
Added order numbers USB97C202-
MN-03 and USB97C202-MN-04
Features, Cover
Added feature bullet: Can share drive
1/09/03
in MP3 player and 1394/USB
applications by isolating the IDE
Interface with other controllers.
Table 5.1 - USB97C202 Pin
Descriptions, page 9
Added the following description: In
part number USB97C202-MN-03 or
later ROM codes.
1/09/03
SMSC USB97C202
Page 3
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Table of Contents
USB97C202 DATASHEET REVISION HISTORY .........................................................................................................3
CHAPTER 1
CHAPTER 2
CHAPTER 3
CHAPTER 4
CHAPTER 5
GENERAL DESCRIPTION................................................................................................................5
PIN TABLE........................................................................................................................................6
PIN CONFIGURATION .....................................................................................................................7
BLOCK DIAGRAM............................................................................................................................8
PIN DESCRIPTIONS.........................................................................................................................9
5.1 Buffer Type Descriptions................................................................................................................13
CHAPTER 6
TYPICAL APPLICATION ................................................................................................................14
CHAPTER 7
DC PARAMETERS .........................................................................................................................15
7.1 Maximum Guaranteed Ratings ......................................................................................................15
7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD = 2.5V......................................................................17
CHAPTER 8
AC SPECIFICATIONS ....................................................................................................................18
8.1 ATA/ATAPI.....................................................................................................................................18
8.2 USB2.0 Timing...............................................................................................................................18
CHAPTER 9
PACKAGE OUTLINES....................................................................................................................19
List of Figures
Figure 3.1 - 100 PIN STQFP & TQFP............................................................................................................................7
Figure 9.1 - 100 Pin STQFP Package Outline, 12x12x1.4 Body, 2MM Footprint (Rev A)............................................19
Figure 9.2 - 100 Pin TQFP Package Outline, 14x14x1.4 Body, 2MM Footprint ...........................................................20
List of Tables
Table 5.1 - USB97C202 Pin Descriptions ......................................................................................................................9
Table 5.2 - USB97C202 Buffer Type Descriptions.......................................................................................................13
Table 7.1 - DC Electrical Characteristics.......................................................................................................................15
Table 9.1 - 100 Pin STQFP Package Parameters (Rev A) ..........................................................................................19
Table 9.2 - 100 Pin TQFP Package Parameters..........................................................................................................20
SMSC USB97C202
Page 4
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 1 General Description
The USB97C202 is a USB2.0 Mass Storage Class Peripheral Controller intended for use with standard
ATA-5 and -6 hard drives and standard ATAPI-5 devices.
The device consists of a USB2.0 PHY and SIE, buffers, Fast 8051 microprocessor with expanded
scratchpad and 768 of program SRAM, internal 48 KB program ROM, and an ATA-66 compatible
interface.
Provisions for optional external Flash Memory up to 64K bytes for program storage is provided. A serial
EEPROM which can be modified via USB from the host provides unique VID/PID/Serial numbers, as well
as optional configuration information.
Internal 768 Bytes of scratchpad SRAM are also provided. This internal SRAM can also be used for
program storage to implement program upgrade via USB download to external “boot block” Flash program
memory, if desired.
Seven GPIO pins are provided for controlling external power control elements and sensing specialized
drive functions. Provisions are made to allow dynamic attach and re-attach to the USB bus to allow hot
swap of drives to be implemented.
ATA-6 HDD or
ATAPI-5 Optical drive
USB2.0
BUS
ATA-66
USB97C202
HS Indicator
Serial EEPROM
(VID/PID/options)
SMSC USB97C202
Page 5
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 2 Pin Table
DISK DRIVE INTERFACE (27 Pins)
IDE_D0
IDE_D4
IDE_D1
IDE_D5
IDE_D2
IDE_D6
IDE_D3
IDE_D7
IDE_D8
IDE_D9
IDE_D10
IDE_D14
IDE_IRQ
IDE_nCS1
IORDY
IDE_D11
IDE_D15
IDE_DACK
IDE_SA0
IDE_D12
IDE_nIOR
IDE_DRQ
IDE_SA1
IDE_D13
IDE_nIOW
IDE_nCS0
IDE_SA2
USB INTERFACE (7 Pins)
USBD+
RTERM
USBD-
FS+
LOOPFLTR
FS-
RBIAS
MEMORY/IO INTERFACE (28 Pins)
MD0
MD4
MA0
MA4
MA8
MD1
MD5
MA1
MA5
MA9
MA13
nIOR
MD2
MD6
MA2
MD3
MD7
MA3
MA6
MA7
MA10
MA14
nMWR
MA11
MA15
nIOW
MA12
nMRD
MISC (15 Pins)
ROMEN
GPIO4/EE_DIO
XTAL1/CLKIN
nTEST2
GPIO1/HS
GPIO5/ATA RESET
XTAL2
GPIO2/EE_CS
GPIO6/A16
nRESET
GPIO3/VBUS
GPIO7/EE_CLK
nTEST0
nTEST2
CLKOUT
POWER, GROUNDS, and NO CONNECTS (23 Pins)
SMSC USB97C202
Page 6
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 3 Pin Configuration
75
51
IDE_D3
IDE_D13
IDE_D2
GND
RBIAS
VDDA
FS+
USB+
IDE_D14
IDE_D1
IDE_D15
IDE_D0
VDDIO
USB-
FS-
RTERM
VSSA
XTAL1/CLKIN
XTAL2
IDE_DRQ
IDE_nIOW
IDE_nIOR
IORDY
VSSP
LOOPFLTR
USB97C202
VDDP
GND
N.C.
N.C.
MD7
MD6
MD5
MD4
GND
MD3
MD2
MD1
MD0
IDE_DACK
IDE_IRQ
IDE_SA1
IDE_SA0
VDD
IDE_SA2
IDE_nCS0
IDE_nCS1
VDDIO
nMWR
nMRD
nRESET
1
25
Figure 3.1 - 100 PIN STQFP & TQFP
SMSC USB97C202
Page 7
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 4 Block Diagram
Auto address generators
512 Bytes EP2 TX/RX Buffer B
512 Bytes EP2 TX/RX Buffer A
1.25KB
SRAM
Address
Address
Address
64 Bytes EP1RX
64 Bytes EP1TX
64 Bytes EP0RX
64 Bytes EP0TX
EP0TX_BC
EP0RX_BC
EP1TX_BC
EP1RX_BC
Address
Address
32 Bit
60MHz
Latch phase 1
Latch phase 2
Future phase 3
Latch phase 0
RAMWR_A/B
RAMRD_A/B
Address
Address
Clocked byPhase 2 Clock
Data @ 32 bit
15MHz
ATA/ATAPI
Drive
ATA-66
Interface
Clocked byPhase 0 Clock
SIE
32 bit 15MHz Data Buss
( Serial Interface Engine )
SIE Control Regs
USB 2.0 PHY
GPIO
7 pins
Configuration and Control
( Transciever )
768 Byte
Program/Scratchpad
SRAM
ROMEN
48KB ROM
Clock Generation
Osc
Interrupt Controller
Program Memory/ IO
Bus
MEM/IO Bus
29pins
OPTIONAL
External PHY
FAST 8051
CPU CORE
CLOCKOUT
12 MHz
Debug
2 pins
Serial 2 wire ( Data/Strobe)
Clocked byPhase 1 Clock
SMSC USB97C202
Page 8
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 5 Pin Descriptions
Table 5.1 - USB97C202 Pin Descriptions
DISK DRIVE INTERFACE
IDE DMA
Request
IDE_DRQ
IS
This pin is the active high DMA request from
the ATA/ATAPI interface.
IDE IO Read IDE_nIOR
O20
This pin is the active low read signal for the
Strobe
interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
IDE Register IDE_SA1
Address 1
O20
O20
O20
IO20
O20
O20
This pin is the register select address bit 1
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
IDE Register IDE_SA0
Address 0
This pin is the register select address bit 0
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
This pin is the register select address bit 2
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
This pin is the bi-directional data bus bit 15
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
This pin is active low write signal for the
ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
IDE Register IDE_SA2
Address 2
IDE Data
IDE_D15
IDE IO Write IDE_nIOW
Strobe
IDE DMA
IDE_nDACK
This pin is the active low DMA acknowledge
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
Acknowledge
IDE Interrupt IDE_IRQ
Request
IS
This pin is the active high interrupt request
signal for the ATA/ATAPI interface.
IDE Data
IDE_D13
IO20
This pin is the bi-directional data bus bit 13
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
IDE Data
IDE_D14
IO20
This pin is the bi-directional data bus bit 14
signal for the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
SMSC USB97C202
Page 9
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
DISK DRIVE INTERFACE
IDE Chip
Select 0
IDE_nCS0
IDE_nCS1
IDE_D[0:12]
IORDY
O20
O20
IO20
I
This pin is the active low chip select 0 signal for
the ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
This pin is the active low select 1 signal for the
ATA/ATAPI interface.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
These pins are bits 0-12 of the ATA/ATAPI bi-
directional data bus.
In part number USB97C202-MN-03 or later ROM
codes, this pin is high impedance when VBUS is
removed.
This pin is the active high IORDY signal from
the IDE drive.
IDE Chip
Select 1 0
IDE Data
IO Ready
USB INTERFACE
USB Bus
Data
USB-
USB+
IO-U
These pins connect to the USB bus data
signals.
USB
LOOPFLTR
This pin provides the ability to supplement the
internal filtering of the transceiver with an
external network, if required.
Transceiver
Filter
USB
RBIAS
A 9.09 Kohm precision resistor is attached
from ground to this pin to set the transceiver’s
internal bias currents.
Transceiver
Bias
Termination
Resistor
RTERM
A precision 1.5Kohm precision resistor is
attached to this pin from a 3.3V supply.
Full Speed
FS-
FS+
IO-U
These pins connect to the USB- and USB+
pins through 31.6 ohm series resistors.
USB Data
MEMORY/IO INTERFACE
Memory Data MD[7:0]
Bus
IO12PU When ROMEN=0, these signals are used to
transfer data between the internal CPU and the
external program memory. When ROMEN=1, a
weak internal pull up is activated to prevent
these pins from floating.
Memory
MA[15:0]
O12
O12
O12
O12
O12
These signals address memory locations within
Address Bus
the external memory.
Memory Write nMWR
Program Memory Write; active low
Program Memory Read; active low
XDATA space Read; active low
XDATA space Write; active low
Strobe
Memory Read nMRD
Strobe
IO Read
nIOR
Strobe
IO Write
Strobe
nIOW
SMSC USB97C202
Page 10
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
MISC
Crystal
XTAL1/
CLKIN
ICLKx 12Mhz Crystal or external clock input.
Input/External
This pin can be connected to one terminal of
the crystal or can be connected to an external
12Mhz clock when a crystal is not used.
Clock Input
Crystal Output XTAL2
OCLKx 12Mhz Crystal
This is the other terminal of the crystal, or left
open when an external clock source is used to
drive XTAL1/CLKIN. It may not be used to
drive any external circuitry other than the
crystal circuit.
Clock Output CLKOUT
O8
IP
This pin produces a 30Mhz clock signal
independent of the processor clock divider. It is
held inactive and low whenever the internal
processor clock is stopped or is being obtained
from the ring oscillator.
When left unconnected or tied high, the
USB97C202 uses the internal ROM for
program execution. When tied low, an external
program memory should be connected to the
memory/data bus. The state of this pin latched
internally on the rising edge of nRESET.
Internal ROM ROMEN
Enable
General
GPIO[1:7]
IO20
These general purpose pins may be used
either as inputs, edge sensitive interrupt inputs,
or outputs. When using internal ROM mode,
these pins have the following assignments:
Purpose I/O
GPIO1: USB HS Indicator; active high. In part
number USB97C202-MN-03 or later ROM
codes, this pin also goes high during USB data
transfers.
GPIO2: Serial EEPROM (93LC66 type) Chip
Select
GPIO3: USB VBUS Detect Input
GPIO4: Serial EEPROM Data In/OutGPIO5:
ATA Drive Reset
GPIO6: A16 control line for external program
Flash memory when using firmware upgrade
capability (external ROM operation only)
GPIO7: Serial EEPROM Clock output
RESET input nRESET
IS
IP
This active low signal is used by the system to
reset the chip. The active low pulse should be
at least 100ns wide.
Test input
nTEST[0:2]
These signals are used for testing the chip.
User should normally leave them unconnected.
For board continuity testing, all pads (except
RBIAS, FSDP, USBDP, USBDM, FSDM,
RTERM, XTAL1, XTAL2, LOOPFLTR and
nTEST[0:2]) are included in an XNOR chain
which is enabled by pulling nTEST2 low. nIOR
is the output of the chain (the chain begins at
pin 2) and will reflect the toggling of a signal
on each pin. Circuit board continuity of the pin
solder connections after assembly can be
checked in this manner
SMSC USB97C202
Page 11
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
POWER, GROUNDS, and NO CONNECTS
+2.5V Core power
VDD
VDDIO
VDDP
VSSP
VDDA
VSSA
GND
+3.3V I/O power
+2.5 Analog power
Analog Ground Reference
+3.3V Analog power
Analog Ground Reference
Ground Reference
NC
No Connect. These pins should not be
connected externally.
SMSC USB97C202
Page 12
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
5.1
Buffer Type Descriptions
Table 5.2 - USB97C202 Buffer Type Descriptions
BUFFER
DESCRIPTION
I
IS
IP
Input
Input with Schmitt trigger
Input with weak pull-up
Input/Output with 8 mA drive
Output with 8mA drive
Output with 12mA drive
IO8
O8
O12
IO12PU
Input/Output with 12 ma drive and
controlled weak pull up
IO12
IO20
Input/Output with 12 ma drive
Input/output with 20mA drive
O20
O20PU
ICLKx
OCLKx
I/O-U
Output with 20mA drive
Output with 20mA drive and weak pullup
XTAL clock input
XTAL clock output
Defined in USB specification
SMSC USB97C202
Page 13
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 6 Typical Application
IDE_D[0:15]
IDE supports :
IDE_D7
IDE_D8
Mode1, Mode2, Mode3, Mode4
Ultra DMA 33/66
Primary IDE
IDE_D6
IDE_D9
R1
100
1%
P1
nRESET
1
3
2
4
1/8W
IDE_D7
IDE_D6
IDE_D5
IDE_D4
IDE_D3
IDE_D2
IDE_D1
IDE_D0
IDE_D8
5
6
8
IDE_D9
7
IDE_D10
IDE_D11
IDE_D12
IDE_D13
IDE_D14
IDE_D15
IDE_D5
IDE_D10
IDE_D4
IDE_D11
R2
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
5.62K
1/8W
1%
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
IDE_DRQ
IDE_nIOW
IDE_nIOR
IORDY
IDE_D3
IDE_D12
IDE_D2
IDE_D13
IDE_DACK
IDE_IRQ
IDE_SA1
IDE_SA0
IDE_nCS0
IDE_SA2
IDE_nCS1
IDE_D1
IDE_D14
IDE_D0
IDE_D15
R6
C1
0.047uF
25V
10%
2.21K
1/8W
1%
R7
1.0K
1/8W
1%
R7
DVDD
1.0K
1/8W
1%
R8
R9
DVDD
4.75K
1/8W
1%
332
1/8W
1%
DVDD
LED1
T1 GREEN
GPIO3
R13
10K
1M
R14
P2
VDD
VCCEXT
C8
DVDD
R11 31.6
1
2
3
4
VCC
FS-
USB-
1
1
2
D-
D+
GND
R12 31.6
FS+
USB+
2
C2
.1uF
C3
.1uF
C4
C5
.1uF
C6
.1uF
C7
.1uF
C9
.1uF
C10
.1uF
USB TYPE B
.1uF
.1uF
3.3V Regulator
VCCEXT
VR1
R15
9.09K
1/10W
1%
3
2
VDDIO
VIN
VOUT
+
+
IDE_nIOW
C11
10uF
C12
10uF
IDE_nCS0
IDE_nCS1
IDE_SA0
IDE_SA2
IDE_nIOR
IDE_DACK
IDE_SA1
IDE_D13
VDDA
VDDIO,VDDA
R16
1.5K1/10W
VDDIO
5%
IDE_IRQ
IDE_D14
IDE_DRQ
IDE_D15
2.5V Regulator
C13
.1uF
C14
.1uF
C15
.1uF
C16
.1uF
C17
.1uF
VCCEXT
VR2
3
2
VDD
VIN
VOUT
VDD
+
+
C18
10uF
C19
10uF
U1
VDDIO
IDE_D12
IDE_D11
3
59
8
VDDIO
VDD
MA13
MA12
GND
MA11
MA10
MA9
51
54
56
57
60
52
62
61
58
55
53
83
50
48
45
43
42
38
75
74
73
72
70
90
MA13
MA12
IDE_D12
9
7
IDE_D11
GND
IDE_D10
IDE_D9
11
12
13
14
16
15
17
18
19
21
95
22
23
24
32
99
98
97
96
94
88
MA11
MA10
MA9
IDE_D10
IDE_D9
VDDIO
IDE_D8
IDE_D7
IDE_D6
IDE_D5
IDE_D4
VSSA
IDE_D8
IDE_D7
IDE_D6
IDE_D5
IDE_D4
MA8
MA8
MA7
MA7
MA[0:15]
VDDIO
MA6
MA6
MA5
MA4
MA3
13
D0
14
12
11
10
9
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA15
MA5
A0
USB97C202
MA4
D1
15
A1
A2
IDE_D3
IDE_D2
IDE_D1
IDE_D0
IDE_D3
IDE_D2
IDE_D1
IDE_D0
VDDIO
IORDY
ROMEN
GPIO1
GPIO2
GPIO3
GPIO4
N.C.
MA3
D2
17
GND
MA2
D3
18
A3
MA2
MA1
MA0
8
D4
19
A4
7
MA1
D5
20
A5
6
MA0
D6
21
A6
IORDY
5
VDD
MD0
MD1
MD2
MD3
MD4
VDDP
D7
A7
27
26
23
25
4
A8
A9
GPIO2
A10
A11
A12
A13
A14
A15
GPIO3
2
NC
30
28
29
3
NC
U3
8
7
6
5
1
2
3
4
VDDIO 32
VCC
N.C.
N.C.
VSS
CS
VCC
GND
nRESET
22
24
31
1
CE
OE
WE
VPP
16
CLK
DI
VDDIO
U2
DO
Q1
R18
1K
93LC66A Serial EEPROM
Y1
R17
39VF512-70 or equiv OTP/EPROM
R3
120
OPTIONAL for test purposes only, if used tie ROMEN
low;otherwise do not populate
12.00Mhz
10K
C21
22pf
C22 C20 1µf
22pf
D1
LED
Title
USB97C202 Typical Application
Rev
A
Size
C
Document Number
Friday, June 07, 2002
Date:
Sheet
1
of
1
SMSC USB97C202
Page 14
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 7 DC Parameters
7.1
Maximum Guaranteed Ratings
Operating Temperature Range........................................................................................................................... 0oC to +70oC
Storage Temperature Range............................................................................................................................-55o to +150oC
Lead Temperature Range (soldering, 10 seconds)..................................................................................................... +325oC
Positive Voltage on any pin, with respect to Ground ........................................................................................................5.5V
Negative Voltage on any pin, with respect to Ground......................................................................................................-0.3V
Maximum VDDA, VDDIO ......................................................................................................................................................+4.0V
Maximum VDD, VDDP.........................................................................................................................................................+3.0V
*Stresses above the specified parameters could cause permanent damage to the device. This is a stress rating only and
functional operation of the device at any other condition above those indicated in the operation sections of this
specification is not implied.
Note:
When powering this device from laboratory or system power supplies, it is important that the Absolute
Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage
spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC
power line may appear on the DC output. When this possibility exists, it is suggested that a clamp circuit
be used.
Table 7.1 - DC Electrical Characteristics
(TA = 0°C - 70°C, VDDIO, VDDA = +3.3 V ± 10%, VDD, VDDP = +2.5 V ± 10%,)
PARAMETER
I Type Input Buffer
SYMBOL
MIN
2.0
TYP
MAX
UNITS
COMMENTS
VILI
VIHI
0.8
V
V
TTL Levels
Low Input Level
High Input Level
ICLK Input Buffer
VILCK
VIHCK
0.4
V
V
Low Input Level
2.2
High Input Level
Input Leakage
(All I and IS buffers)
IIL
-10
-10
+10
+10
uA
uA
VIN = 0
Low Input Leakage
High Input Leakage
IIH
VIN = VDDIO
SMSC USB97C202
Page 15
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
PARAMETER
O8 Type Buffer
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
VOL
0.4
V
I
OL = 8 mA @ VDDIO
Low Output Level
High Output Level
Output Leakage
= 3.3V
I
OH = -4mA @ VDDIO
VOH
2.4
-10
V
= 3.3V
IOL
+10
0.4
uA
V
IN = 0 to VDDIO
(Note 7.1)
I/O8 Type Buffer
VOL
VOH
IOL
V
V
IOL = 8 mA @ VDDIO
= 3.3V
Low Output Level
I
OH = -4 mA @ VDDIO
2.4
-10
High Output Level
Output Leakage
= 3.3V
+10
0.4
µA
V
IN = 0 to VDDIO
(Note 7.1, Note 7.3)
I/O12 Type Buffer
VOL
V
V
IOL = 12 mA @ VDDIO
= 3.3V
Low Output Level
I
OH = -6mA @ VDDIO
VOH
2.4
-10
High Output Level
= 3.3V
V
IN = 0 to VDDIO
IOL
+10
0.4
µA
V
Output Leakage
(Note 7.1, Note 7.3)
I/O20 Type Buffer
VOL
I
OL = 20 mA @ VDDIO
Low Output Level
High Output Level
= 3.3V
I
OH = -5 mA @ VDDIO
VOH
2.4
-10
V
= 3.3V
V
IN = 0 to VDDIO
IOL
+10
µA
Output Leakage
(Note 7.1, Note 7.3)
SMSC USB97C202
Page 16
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
COMMENTS
IO-U
Note 7.2
Supply Current Unconfigured
ICCINIT
ICC
65
85
mA
mA
mA
mA
VDDIO, VDDA
DD, VDDP
VDDIO, VDDA
VDD, VDDP
V
Supply Current Active
85
120
Note 7.1 Output leakage is measured with the current pins in high impedance.
Note 7.2 See appendix A for USB DC electrical characteristics.
Note 7.3 Output leakage is valid only on pins without internal weak pull ups or pull downs.
7.1.1 Capacitance TA = 25°C; FC = 1MHz; VDD = 2.5V
LIMITS
PARAMETER
Clock Input Capacitance
Input Capacitance
Output Capacitance
SYMBOL MIN TYP MAX UNIT
TEST CONDITION
All pins except USB pins
(and pins under test tied
to AC ground)
CIN
CIN
COUT
20
10
20
pF
pF
pF
SMSC USB97C202
Page 17
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 8 AC Specifications
8.1
ATA/ATAPI
The USB97C202 conforms to all timing diagrams and specifications for ATAPI-5 as set forth in the
T13/1321D Revision 3 NCITS specification. Please refer to this specification for more information.
8.2
USB2.0 Timing
The USB97C202 conforms to all timing diagrams and specifications for USB peripheral silicon building
blocks as set forth in the USB-IF USB2.0 specification. Please refer to this specification for more
information.
SMSC USB97C202
Page 18
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Chapter 9 Package Outlines
Figure 9.1 - 100 Pin STQFP Package Outline, 12x12x1.4 Body, 2MM Footprint (Rev A)
Table 9.1 - 100 Pin STQFP Package Parameters (Rev A)
MIN
~
NOMINAL
MAX
1.60
0.15
1.45
14.20
12.20
14.20
12.20
0.20
0.75
~
REMARKS
Overall Package Height
Standoff
~
A1
A2
D
0.05
1.35
13.80
11.80
13.80
11.80
0.09
0.45
~
~
~
Body Thickness
X Span
~
~
X body Size
D1
E
~
Y Span
~
Y body Size
E1
H
~
Lead Frame Thickness
Lead Foot Length
Lead Length
0.60
L
1.00
L1
e
0.40 Basic
Lead Pitch
Lead Foot Angle
Lead Width
0o
0.13
0.08
0.08
~
~
0.16
~
~
~
7o
0.23
~
0.20
0.08
θ
W
R1
R2
ccc
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the true position of the leads is ± 0.035 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC USB97C202
Page 19
Revision 1.6 (11-05-04)
DATASHEET
USB 2.0 ATA/ATAPI Controller
Datasheet
Figure 9.2 - 100 Pin TQFP Package Outline, 14x14x1.4 Body, 2MM Footprint
Table 9.2 - 100 Pin TQFP Package Parameters
MIN
~
NOMINAL
MAX
1.60
0.15
1.45
16.20
14.10
16.20
14.10
0.20
0.75
~
REMARKS
~
Overall Package Height
Standoff
A1
A2
D
0.05
1.35
15.80
13.90
15.80
13.90
0.09
0.45
~
~
~
Body Thickness
X Span
~
~
X body Size
D1
E
~
Y Span
~
Y body Size
E1
H
~
Lead Frame Thickness
Lead Foot Length
Lead Length
0.60
L
1.00
L1
e
0.50 Basic
Lead Pitch
Lead Foot Angle
Lead Width
0o
0.17
0.08
0.08
~
~
0.22
~
~
~
7o
0.27
~
0.20
0.08
θ
W
R1
R2
ccc
Lead Shoulder Radius
Lead Foot Radius
Coplanarity
Notes:
1. Controlling Unit: millimeter.
2. Tolerance on the position of the leads is ± 0.04 mm maximum.
3. Package body dimensions D1 and E1 do not include the mold protrusion.
Maximum mold protrusion is 0.25 mm.
4. Dimension for foot length L measured at the gauge plane 0.25 mm above the seating plane.
5. Details of pin 1 identifier are optional but must be located within the zone indicated.
SMSC USB97C202
Page 20
Revision 1.6 (11-05-04)
DATASHEET
相关型号：
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