USB97C102_技术文档

USB97C102

Multi-Endpoint USB Peripheral Controller with

Integrated 5 Port HUB

FEATURES

!"

High Performance USB Peripheral Controller

Engine

-

Additional USB and ISA Suspend Resume

Events

-

Integrated USB Transceiver

Serial Interface Engine (SIE)

8051 Microcontroller (MCU)

Patented Memory Management Unit (MMU)

4 Channel 8237 DMA Controller (ISADMA)

4K Byte On Board USB Packet Buffer

Quasi-ISA Peripheral Interface

USB Bus Snooping Capabilities

GPIOs

Internal 8MHz Ring Oscillator for Immediate

Low Power Code Execution

24, 16, 12, 8, 4, and 2 MHz PLL Taps For on

the Fly MCU and DMA Clock Switching

Independent Clock/Power Management for

SIE, MMU, DMA and MCU

!"

DMA Capability with ISA Memory

-

Four Independent Channels

Transfer Between Internal and External

Memory

Transfer Between I/O and Internal Memory

External Bus Master Capable

!"

Pin Compatible with SMSC USB97C100

Complete USB Specification 1.1 Compatibility

-

Isochronous, Bulk, Interrupt, and Control Data

Independently Configurable per Endpoint

Dynamic Hardware Allocation of -Packet

Buffer for Virtual Endpoints

Multiple Virtual Endpoints (up to 16 TX, 16 RX

Simultaneously)

Scatter Gather DMA

-

Four Independent Channels

Up to 16 Transfers can be Programmed to

Occur Consecutively Without MCU

InterventionExternal MCU Memory Interface

1M Byte Code and Data Storage via 16K

Windows

Flash, SRAM, or EPROM

Downloadable via USB, Serial Port, or ISA

Peripheral

-

Multiple Alternate Address Filters

Dynamic Endpoint Buffer Length Allocation (0-

1280 Byte Packets)

-

!"

USB Full (12Mbps) and Low Speed Capability

MMU and SRAM Buffer Allow Buffer Optimization

and Maximum Utilization of USB Bandwidth

!"

Quasi-ISA Interface Allows Interface to New and

"Legacy" Peripheral Devices

-

128 Byte Page Size

10 Pages Maximum per Packet

32 Deep Receive Packet Queue

Up to 5 Deep Transmit Packet Queue, per

Endpoint

-

1M ISA Memory Space via 4K MCU Window

64K ISA I/O Space via 256 Byte MCU Window

4 External Interrupt Inputs

4 DMA Channels

Variable Cycle Timing

8 Bit Data Path

-

Hardware Generated Packet Header Records

Each Packet Status Automatically

Simultaneous Arbitration Between MCU, SIE,

and ISA DMA Accesses

!"

3.3 Volt, Low Power Operation

5 Volt Tolerant Operation on I/O Signal Pins

On Board Crystal Driver Circuit

128 Pin QFP Package

!"

Extended Power Management

Standard 8051 "Stop Clock" Modes

-

GENERAL DESCRIPTION

The USB97C102 is a flexible, general purpose USB peripheral interface and controller ideally suited for multiple

endpoint applications. The USB97C102 provides an ISA-like bus interface, which will allow virtually any PC peripheral

to be placed at the end of a USB connection. Its unique dynamic buffer architecture overcomes the throughput

disadvantages of existing fixed FIFO buffer schemes allowing maximum utilization of the USB connection’s overall

bandwidth. This architecture minimizes the integrated microcontroller’s participation in the USB data flow, allowing

back-to-back packet transfers to block oriented devices. The efficiency of this architecture allows floppy drives to

coexist with other peripherals such as serial and parallel ports on a single USB link.

SMSC DS – USB97C102

Rev. 03/23/2000

The USB97C102 allows external program code to be downloaded over the USB to allow easy implementation of

varied peripheral USB Device Classes and combinations. This also provides a method for convenient field upgrades

and modifications.

80 Arkay Drive

Hauppauge, NY 11788

(631) 435-6000

FAX (631) 273-3123

Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems

Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are

included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given.

Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to

make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest

specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices

described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of

the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement").

The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published

specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life

support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses

without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this

document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com.

SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES

OF MERCHANTABILITY, FITNESS FOR

A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL

WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE.

IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES;

OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON

CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR

NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE

POSSIBILITY OF SUCH DAMAGES.

SMSC DS – USB97C102

Page 2

Rev. 03/23/2000

TABLE OF CONTENTS

FEATURES....................................................................................................................................................................... 1

GENERAL DESCRIPTION ............................................................................................................................................... 1

PIN CONFIGURATION..................................................................................................................................................... 4

DESCRIPTION OF PIN FUNCTIONS............................................................................................................................... 5

BUFFER TYPE DESCRIPTIONS...................................................................................................................................... 7

CODE DEBUGGER INTERFACE................................................................................................................................ 7

FUNCTIONAL DESCRIPTION.......................................................................................................................................... 9

Serial Interface Engine (SIE)......................................................................................................................................... 9

Micro Controller Unit (MCU) .......................................................................................................................................... 9

SIEDMA 9

Memory Management Unit (MMU) Register Description ............................................................................................... 9

ISADMA 9

Applications................................................................................................................................................................... 9

Code Space................................................................................................................................................................. 12

Data Space.................................................................................................................................................................. 13

ISADMA Memory Map................................................................................................................................................. 15

MCU Block Register Summary.................................................................................................................................... 15

SGDMA Block Register Summary............................................................................................................................... 16

MMU Block Register Summary ................................................................................................................................... 17

SIE Block Register Summary ...................................................................................................................................... 17

MCU REGISTER DESCRIPTION ................................................................................................................................... 19

MCU Runtime Registers.............................................................................................................................................. 19

FIFO Status Registers................................................................................................................................................. 22

MCU ISA Interface Registers ...................................................................................................................................... 29

8237 (ISADMA) REGISTER DESCRIPTION .................................................................................................................. 31

Memory Map ............................................................................................................................................................... 31

Runtime Registers....................................................................................................................................................... 33

MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION ........................................................................... 44

MMU Interface Registers............................................................................................................................................. 44

MMU Free Pages Register.............................................................................................................................................. 47

32 BYTE DEEP TX COMPLETION FIFO REGISTER .................................................................................................... 47

Tx FIFO POP Register.................................................................................................................................................... 49

SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION ................................................................................. 52

Packet Header Definition............................................................................................................................................. 52

SIE Interface Registers................................................................................................................................................ 53

ALTERNATE ADDRESS ENDPOINT MAPPING............................................................................................................ 56

Multiple Endpoint Mapping .......................................................................................................................................... 56

USB HUB BLOCK........................................................................................................................................................... 64

SIU System Interface Unit ........................................................................................................................................... 64

HIU Hub Interface Unit ................................................................................................................................................ 64

HUB Block Register Summary..................................................................................................................................... 65

Disconnecting the USB Hub from the USB function.................................................................................................... 67

USB97C100 Compatibility Mode................................................................................................................................. 67

DC PARAMETERS ......................................................................................................................................................... 68

MAXIMUM GUARANTEED RATINGS ........................................................................................................................ 68

USB PARAMETERS....................................................................................................................................................... 70

USB DC PARAMETERS ............................................................................................................................................. 70

USB AC PARAMETERS ............................................................................................................................................. 71

MECHANICAL OUTLINE................................................................................................................................................ 80

SMSC DS – USB97C102

Page 3

Rev. 03/23/2000

PIN CONFIGURATION

SA10

SA9

1

102

101

nMASTER

2

VCC

3

SA8

SA7

100

99

READY

EXTCLK

4

SA6

5

98

FALE

6

GND

SA5

SA4

97

96

95

94

93

7

nPWREN5

nPWROK5

nPWREN4

nPWROK4

nPWREN3

nPWROK3

nPWREN2

nPWROK2

GND

SA3

8

9

SA2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

SA1

92

91

90

89

88

87

86

85

84

SA0

SA13

SA14

SA15

SA16

SA17

SA18

SA19

GND

IRQ3

IRQ2

IRQ1

IRQ0

VCC

USBD+

USBD-

PD+5

PD-5

USB97C102

83

82

PD+4

PD-4

PD+3

81

80

GND

PD+2

PD-3

PD-2

79

78

77

76

75

74

73

72

71

nTEST

PWRGD

AVDD

FA19

FA18

FA11

FA9

RESET_IN

TST_OUT

XTAL1

XTAL2

GND

CLKOUT

FA8

70

69

FA13

FA14

FA17

GND

nFWR

GPIO0

GPIO1

GPIO2

GPIO3

GPIO4

68

67

66

65

FA16

FIGURE 1 - PIN CONFIGURATION

SMSC DS – USB97C102

Page 4

Rev. 03/23/2000

DESCRIPTION OF PIN FUNCTIONS

Table 1 - USB97C102 Pin Configuration

QFP PIN

NUMBER

BUFFER

TYPE

SYMBOL

READY

PIN DESCRIPTION

ISA INTERFACE

100

Channel is ready when high.

IP

ISA memory or slave devices use this signal to lengthen a bus

cycle from the default time. Extending the length of the bus cycle

can only be done when the bus cycles are derived from the Internal

DMA controller core. 8051 MCU generated Memory or I/O accesses

cannot and will not be extended even if READY is asserted low by

an external ISA slave device. The external slave device negates this

signal after decoding a valid address and sampling the command

signals (nIOW, nIOR, nMEMW, and nMEMR). When the slave’s

access has completed, this signal should be allowed to float high.

104, 106,

108, 110

DRQ[3:0]

DMA Request channels 3-0; active high.

I

These signals are used to request DMA service from the DMA controller.

The requesting device must hold the request signal until the DMA

controller drives the appropriate DMA acknowledge signal (nDACK[3:0]).

105, 107,

109, 111

nDACK

[3:0]

DMA Acknowledge channels 3-0; active low.

O8

These signals are used to indicate to the DMA requesting device that it

has been granted the ISA bus.

103

TC

DMA Terminal Count; active high.

O8

This signal is used to indicate that a DMA transfer has completed.

System Address Bus

19-13, 127-7, SA[19:0]

9-12

These signals address memory or I/O devices on the ISA bus.

System Data Bus

112-115, 117- SD[7:0]

120

I/O8

O8

These signals are used to transfer data between system devices.

Address Enable

122

AEN

This signal indicates address validation to I/O devices. When low this

signal indicates that an I/O slave may respond to addresses and I/O

commands on the bus. This signal is high during DMA cycles to prevent

I/O slaves from interpreting DMA cycles as valid I/O cycles.

123

124

nIOW

nIOR

I/O Write; active low.

O8

This signal indicates to the addressed ISA I/O slave to latch data from

the ISA bus.

I/O Read; active low.

This signal indicates to the addressed ISA I/O slave to drive data on the

ISA bus.

125

126

nMEMR

nMEMW

Memory read; active low

This signal indicates to the addressed ISA memory slave to drive

data on the ISA bus.

O8

Memory write; active low

This signal indicates to the addressed ISA memory slave to latch data

from the ISA bus.

102

nMASTER

External Bus master, active low

IP

This signal forces the USB97C102 to immediately tri-state its external

bus, even if internal transactions are not complete. All shared ISA

signals are tri-stated, except 8237 nDACKs, which can be used in gang

mode to provide external bus-master handshaking. This pin must be

used with some handshake mechanism to avoid data corruption.

21-24

IRQ[3:0]

Interrupt Request 3-0; active high

I

These signals are driven by ISA devices on the ISA bus to interrupt the

8051.

SMSC DS – USB97C102

Page 5

Rev. 03/23/2000

QFP PIN

NUMBER

30

BUFFER

TYPE

SYMBOL

XTAL1/

PIN DESCRIPTION

24MHz Crystal or clock input.

ICLKx

Clock In

This pin can be connected to one terminal of the crystal or can be

connected to an external clock when a crystal is not used.

31

99

XTAL2

24MHz Crystal

OCLKx

ICLK

This is the other terminal of the crystal.

Alternate clock to 8237

EXTCLK

CLKOUT

An external clock can be used for the internal 8237. This clock can be

used to synchronize the 8237 to other devices.

33

Clock output.

O8

This clock frequency is the same as the 8051 running clock.

This clock is stopped when the 8051 is stopped. Peripherals should not

use this clock when they are expected to run when the 8051 is stopped.

This clock can be used to synchronize other devices to the 8051.

USB INTERFACE

87, 86

USBD-

USB Upstream Connection signals

IOUSB

O24

USBD+

These are two point-to-point signals and driven differentially.

USB Power Enable

A low signal on this pin applies power to the associated USB port (port

#5 through #2). This output signal is active low.

96, 94, 92,

90.

nPWREN[5:2]

USB Over-Current Sense

Input to indicate an over-current condition for a bus powered USB

device on an external downstream port (port #5 through #2).

95, 93, 91,

89.

nPWROK[5:2]

I

85, 84, 83,

82, 81, 78,

79, 77.

nPD+[5:2],

nPD -[5:2]

USB Downstream Connection Signals

IOUSB

These are two point-to-point signals and driven differentially. They are

used as standard “Walk Up” USB Port Connections

FLASH INTERFACE

Flash ROM Data Bus

These signals are used to transfer data between 8051 and the external

FLASH.

45-52

FD[7:0]

IO8

O8

75, 74, 68,

65, 64, 69,

70, 63, 73,

43, 72, 71,

62-58,

FA[19:0]

Flash ROM Address Bus

These signals address memory locations within the FLASH.

56-54

42

NFRD

NFWR

nFCE

FALE

Flash ROM Read; active low

Flash ROM Write; active low

Flash ROM Chip Select; active low

Flash ROM address latch enable

POWER SIGNALS

O8

66

44

98

25,57,76,

101,121

VCC

+3.3 Volt Power

Ground Reference

8, 20, 32, 53, GND

67, 80, 88,

97, 116

MISCELLANEOUS

41-34

27

GPIO[7:0]

General Purpose I/O.

I/O24

I

These pins can be configured as inputs or outputs under software

control.

PWRGD

Active high input.

This signal is used to indicate to that chip that a good power level has

been reached. When inactive/low, all pins are Tri-stated except

TST_OUT and a POR is generated.

SMSC DS – USB97C102

Page 6

Rev. 03/23/2000

QFP PIN

NUMBER

28

BUFFER

TYPE

SYMBOL

PIN DESCRIPTION

Power on reset; active high

RESET_IN

I

This signal is used by the system to reset the chip. It also generates an

internal POR.

29

26

TST_OUT

nTEST

XNOR Chain output

O8

IP

This signal is used for testing the chip via an internal XNOR Chain.

Test input

This signal is a manufacturing test pin. User can pull it high or leave it

unconnected.

BUFFER TYPE DESCRIPTIONS

Table 2 - USB97C102 Buffer Type Description

DESCRIPTION

Input (no pull-up)

BUFFER

I

IP

O8

Input 90µA with internal pull-up

Output with 8mA drive

I/O8

I/O16

O24

I/ODP24

ICLKx

OCLKx

ICLK

IOUSB

Input/output with 8mA drive

Input/output with 16mA drive

Output, 24mA sink, 12mA source.

Input/Output drain , 24mA sink, 12mA source with 90µA pull-up

XTAL clock input

XTAL clock output

Clock input (TTL levels)

Defined in USB specification V1.1

CODE DEBUGGER INTERFACE

This interface is made available by driving NTEST=0 and TSTOUT=0 (In this mode, TSTOUT is an input of the chip).

In this mode, the pin functions are defined as follows:

QFP PIN

NUMBER

BUFFER

TYPE

SYMBOL

PIN DESCRIPTION

64, 69, 70, FA[15:0]

63, 73, 43,

72, 71, 62-

58,

8051 Address Bus

I

56-54

42

66

112-115,

117-120

44

NFRD

NFWR

FD[7:0]

Data Read Strobe; active low

Data Write; active low

Data Bus

I

I/O8

nFCE

FA19

FA18

FA17

FA16

8051 T1IN timer signal

8051 T0IN timer signal

8051 WAKE interrupt signal

8051 INT1 interrupt signal

8051 INT0 interrupt signal

O8

75

74

68

65

SMSC DS – USB97C102

Page 7

Rev. 03/23/2000

USB97C102 BLOCK DIAGRAM

To Upstream

USB Device

To Walk-up

USB Ports

Dual Speed USB

XCVR

Dual Speed USB

XCVR

Dual Speed USB

XCVR

Dual Speed USB

XCVR

End Point

Control

Serial Interface Engine

Dual Speed USB

XCVR

Internal HUB

Memory

Management

Unit

Map RAM

SIE DMA

RX/

Arbiter

TX

Queue

4k Data Buffer RAM

FD[7:0]

Flash/

SRAM

Interface

nFRD

8051 SGDMA Control

SGDMA WRAPPER

nFWR

nFCE

Start DMA

Queue Ctrl

8051 CPU

General

Purpose

IO

GPIO[7:0]

GPIO

8237

Done DMA

Queue Ctrl

SD[7:0],

SA[19:0]

97C102 Block Diagram

NIOW,

nIOR,

nMEMW,

nMEMR

DRQ[3:0],

nDACK[3:0],

TC,AEN

IRQ[3:0]

SMSC DS – USB97C102

Page 8

Rev. 03/23/2000

FUNCTIONAL DESCRIPTION

The USB97C102 incorporates a USB Serial Interface Engine (SIE), 8051 Microcontroller Unit (MCU), Serial Interface

Engine DMA (SIEDMA), a programmable 8237 ISA bus DMA controller (ISADMA), 4K bytes of SRAM for data stream

buffering, and a patented MMU (Memory Management Unit) to dynamically manage buffer allocation. The semi-

automatic nature of the SIEDMA, ISADMA, and MMU blocks frees the MCU to provide enumeration, protocol and

power management. A bus arbiter integrated into the MMU assures that transparent access between the SIEDMA,

ISADMA, and MCU to the SRAM occurs.

Serial Interface Engine (SIE)

The SIE is a USB low-level protocol interpreter. The SIE controls the USB bus protocol, packet generation/extraction,

parallel-to-serial/serial-to-parallel conversion, CRC coding/decoding, bit stuffing, and NRZI coding/decoding.

The SIE can be dynamically configured as having any combination of 0-16 transmit, and 0-16 receive endpoints, for

up to 4 independent addresses. There are 3 alternate and one local address. The alternate addresses, for example,

can be used for Hub addresses. The SIE can also "Receive All Addresses" for bus snooping.

Micro Controller Unit (MCU)

The 8051 embedded controller is a static CMOS MCU which is fully software compatible with the industry standard

Intel 80C51 micro-controller. All internal registers of the USB97C102 blocks are mapped into the external memory

space of the MCU.

A detailed description of the microcontroller’s internal registers and instruction set can be found in the “USB97C102

Programmer’s Reference Guide”.

SIEDMA

This is a simplified DMA controller, which automatically transfers data between SIE and SRAM via MMU control. The

SIEDMA appends a status header containing frame number, endpoint, and byte count to each incoming packet

before notifying the MCU of its arrival. This block’s operation is transparent to the firmware.

Memory Management Unit (MMU) Register Description

This patented MMU consists of a 4k buffer RAM which is allocated in 32 pages of 128 bytes. Packets can be

allocated with up to 10 pages each (1280 bytes). The buffer can therefore concurrently hold up to 32 packets with a

64 byte payload. For isochronous pipes, it can hold 3 packets with a 1023 byte payload each, and still have room for

two more 64 byte packets.

This block supports 16 independent transmit FIFO queues (one for each endpoint), and a single receive queue. Each

endpoint can have up to five transmit packets queued. The receive queue can accept 32 packets of any size

combination before forcing the host to back off.

The arbiter makes the single-ported buffer RAM appear to be simultaneously available to the MCU, the four channels

of the ISADMA, and the SIEDMA for receiving and transmitting packets.

ISADMA

This is an industry standard 8237 DMA controller to transfer data between the ISA bus and the SRAM under MMU

control. This DMA contains status and control registers which can be accessed and programmed by the 8051

controller. The 8237 can run at 2, 4, or 8 MHz internally, or via an external clock to synchronize it with another

source.

SGDMA

A four channel Scatter-Gather DMA will run the 8237 DMA controller once the MCU indicates which packets to

transfer. The SGDMA performs scattering/gathering operations from the MMU to/from the external ISA memory.

It also allows ISA device to/from MMU transfer.

Applications

The USB97C102 enables entirely new I/O applications, as well as new form factors for existing Legacy I/O

applications. PC98 compliance encourages the elimination ofDMA, IRQ and addressing conflicts via total on-board

ISA elimination. With the USB97C102, the ISA bus can be eliminated from motherboards without sacrificing the huge

infrastructure of Legacy I/O ports. By moving these devices to the flexible USB bus, new form factors such as monitor

peripheral clusters are also possible (mouse, keyboard, serial, parallel ports in a USB connected monitor). PC

system designers are no longer constrained by the physical borders of the motherboard. The USB97C102 is ideal for

USB peripherals which require considerable bandwidth, such as floppy drives, audio, IR, etc. The following block

diagrams illustrate these applications.

SMSC DS – USB97C102

Page 9

Rev. 03/23/2000

TYPICAL PC MOTHERBOARD APPLICATION

Upstream USB

USB

South

Bridge

Floppy

PS/2

Serial

Parallel

FIR

37C67X

97C102

SIO

SPKR

MIC

ISA AUDIO

Downstream USB Walkup Ports

FIGURE 2 – USB97C102 CONFIGURED IN A PC MOTHERBOARD

TYPICAL MONITOR APPLICATION

FLOPPY

USB

Upstream

37C67X

SIO

PS/2

97C102

SERIAL/FIR

ISA

CODEC

PARALLEL

USB Downstream

Walkup Ports

FIGURE 3 – USB97C102 CONFIGURED FOR MONITOR, HUB, AND PERIPHAL CONSTELLATION

SMSC DS – USB97C102

Page 10

Rev. 03/23/2000

TYPICAL FLOPPY DRIVE APPLICATION

USB Upstream

37C78

FDC

97C102

USB Downstream

Walkup Ports

FIGURE 4 – USB97C102 CONFIGURED FOR FLOPPY DRIVE APPLICATION AND WALKUP PORTS

TYPICAL SIGNAL CONNECTIONS

SRAM

USB UPSTREAM

FDC

SD[7..0]

LPT

UART

IR

SA[10..0]

IRQ[3..0]

FDC37C669FR

USB97C102

nDACK[3..0]

DRQ[3..0]

TC

nIOR

nIOW

24MHz

FLASH

FIGURE 5 – USB97C102 CONFIGURED WITH FDC CONTROLLER AND WALKUP PORTS

SMSC DS – USB97C102

Page 11

Rev. 03/23/2000

MCU Memory Map

The 64K memory map is as follows from the 8051's viewpoint:

Code Space

Table 3 - MCU Code Memory Map

CODE SPACE

8051 ADDRESS

ACCESS

0xC000-0xFFFF

Movable 16k FLASH page 1 of 64 16k pages in

External FLASH (0x0000-0xFFFF) selected by

MEM_BANK Register Default: 0x4000-

0x7FFF FLASH

External FLASH

0x8000-0xBFFF

0x4000-0x7FFF

Movable 16k FLASH page 1 of 64 16k pages in

External FLASH (0x0000-0xFFFF) selected by

MEM_BANK2 Register Default: 0x0000-0x3FFF FLASH

Movable 16k FLASH page 1 of 64 16k pages in

External FLASH (0x0000-0xFFFF) selected by

MEM_BANK Register Default: 0x4000-

0x7FFFLASH

External FLASH

0x0000-0x3FFF

Fixed 16k FLASH Page

0x0000-0x3FFF FLASH

External FLASH

FLASH Address Map

16k

8051 MCU External Data Address

Space

16k

0xFFFF

1 of 64 -16K

Flash Page

...

0xC000

16k

1 of 64 - 16K

Flash Page

0x8000

1 of 64 - 16K

Flash pages

0x4000

Fixed 16k Flash

Page

0x0

MCU to External Code Space Map Diagram

SMSC DS – USB97C102

Page 12

Rev. 03/23/2000

Data Space

Table 4 - MCU Data Memory Map

DATA SPACE

8051 ADDRESS

ACCESS

0xC000-0xFFFF

0x8000-0xBFFF

0x7000-0x7FFF

Movable 16k FLASH page 1 of 64 16k pages in

External FLASH (0x00000-0xFFFFF) selected by

MEM_BANK Register Default: 0x04000-

0x07FFF FLASH

Movable 16k FLASH page 1 of 64 16k pages in

External FLASH (0x00000-0xFFFFF) selected by

MEM_BANK2 Register Default: 0x004000-

0x037FFF FLASH

External FLASH

Internal

0x7F80-0x7F9F SIE Reg

0x7F70-0x7F7F ISA Reg

0x7F50-0x7F6F MMU Reg

0x7F20-0x7F2F Power Reg

0x7F10-0x7F1F Configuration Reg

0x7F00-0x7F0F Runtime Reg

Note 1.

0x6000-0x6FFF

0x5000-0x5FFF

0x4000-0x4FFF

0x6000

MMU Data Register

0x5000-0x5FFF

ISA MEMORY Window

Internal

ISA

0x4000-0x40FF

ISA

ISA I/O Window

0x3000-0x3FFF

0x2000-0x2FFF

0x1000-0x1FFF

0x0000-0x00FF

Not used

Internal

Registers and SFR’s

Note 1:

The MCU, MMU, and SIE block registers are external to the 8051, but internal to the USB97C102. These

addresses will appear on the FLASH bus, but the read and write strobes will be inhibited.

SMSC DS – USB97C102

Page 13

Rev. 03/23/2000

ISA RAM Address Map

FLASH Address Map

4k (0x800)

16k

4k

8051 MCU External Data Address

Space

0xFFFF

...

1 of 64 - 16K

Flash Page

...

0xC000

4k

16k

1 of 64 - 16K

Flash Page

0x8000

4k - ISA Mem

0x5000

0x4000

0x100h

ISA I/O

0x0000

16k

...

16k

MCU to External Data I/O and Memory Map Diagram

SMSC DS – USB97C102

Page 14

Rev. 03/23/2000

ISADMA Memory Map

The Internal Memory buffer is virtualized into the 8237's 64K address map as 32 independent 1k blocks. After the

MMU has allocated a given packet size for a specific PNR, the MMU will make that packet appear to the 8237 as a

contiguous block of data in the address ranges depicted in table 5.

Table 5 - ISADMA Memory Map

8237 MEMORY ADDRESS

DESCRIPTION

0x8000-0xFFFF

32 blocks of 1K Window to Packet

0x0000-0x7FFF

32K Window to External ISA RAM

MCU Block Register Summary

Table 6 - MCU Block Register Summary

R/W DESCRIPTION

RUNTIME REGISTERS

INT0 Source Register

ADDRESS

NAME

PAGE

7F00

7F01

7F02

7F03

7F06

7F07

ISR_0

IMR_0

ISR_1

IMR_1

DEV_REV

DEV_ID

R/W

R

19

20

21

INT0 Mask Register

INT1 Source Register

INT1 Mask Register

Device Revision Register

Device ID Register

R

UTILITY REGISTERS

7F18

7F19

7F1A

7F1B

GPIOA_DIR

GPIOA_OUT

GPIOA_IN

UTIL_CONFI

G

R/W

R

GPIO Configuration Register

GPIO Data Output Register

GPIO Data Input Register

23

24

R/W

Miscellaneous Configuration Register

POWER MANAGEMENT REGISTERS

7F27

7F28

7F29

7F2A

7F2B

7F2C

7F2D

CLOCK_SEL

MEM_BANK2

MEM_BANK

WU_SRC_1

WU_MSK_1

WU_SRC_2

WU_MSK_2

R/W

8051 and 8237 Clock Select Register

26

27

28

29

Flash Bank Select 2

Flash Bank Select

Wakeup Source

Wakeup Mask

Wakeup Source

Wakeup Mask

ISA BUS CONTROL REGISTERS

7F10

7F11

7F12

7F13

7F14

7F15

7F16

7F17

7F70

7F71

7F72

7F73

7F74

7F7E

7F7F

GP1Data

GP1Status

GP2Data

GP2Status

GP3Data

GP3Status

GP4Data

GP4Status

BUS_REQ

IOBASE

MEMBASE

BUS_STAT

BUS_MASK

MCU_TEST2

MCU_TEST1

R/W

R

R/W

R

R/W

R

R/W

R

R/W

R

R/W

N/A

GP FIFO Data Port #1

GP FIFO status Port #1

GP FIFO Data Port #2

GP FIFO status Port #2

GP FIFO Data Port #3

GP FIFO status Port #3

GP FIFO Data Port #4

GP FIFO status Port #4

ISA Bus Request Register

8051 ISA I/O Window Base Register

8051 ISA Memory Window Base Register

ISADMA Request Status

ISADMA Request Interrupt Mask

Reserved for Test

21

22

21

22

21

22

29

31

30

31

Reserved for Test

SMSC DS – USB97C102

Page 15

Rev. 03/23/2000

SGDMA Block Register Summary

Table 7 – SGDMA Block Register Summary

ADDRESS

NAME

R/W

DESCRIPTION

PAGE

CHANNEL 0 REGISTERS

7FB0

7FB1

7FB2

7FB3

7FB4

7FB5

7FB6

7FB7

7FB8

7FB9

SGDMA_START_FIFO0

SGDMA_DONE_FIFO0

SGDMA_ADHI0

R/W Packet Number Start FIFO Register

R/W Packet Number Done FIFO Register

R/W ISA Address High Byte Register

R/W ISA Address Low Byte Register

R/W Transfer Size High Register

39

40

41

SGDMA_ADLO0

SGDMA_SIZEHI0

SGDMA_SIZELO0

SGDMA_TOTAL_PKTS0

SGDMA_DONE_PKTS0

SGDMA_STS0

R/W Transfer Size Low Register

R

Total Packets in Channel Register

Total Packets in Done FIFO Register

Status Register

SGDMA_CMD0

R/W Command Register

CHANNEL 1 REGISTERS

7FBA

7FBB

7FBC

7FBD

7FBE

7FBF

7FC0

7FC1

7FC2

7FC3

SGDMA_START_FIFO1

SGDMA_DONE_FIFO1

SGDMA_ADHI1

SGDMA_ADLO1

SGDMA_SIZEHI1

SGDMA_SIZELO1

SGDMA_TOTAL_PKTS1

SGDMA_DONE_PKTS1

SGDMA_STS1

R/W Packet Number Start FIFO Register

R/W Packet Number Done FIFO Register

R/W ISA Address High Byte Register

R/W ISA Address Low Byte Register

R/W Transfer Size High Register

39

40

41

R/W Transfer Size Low Register

R

Total Packets in Channel Register

Total Packets in Done FIFO Register

Status Register

SGDMA_CMD1

R/W Command Register

CHANNEL 2 REGISTERS

7FC4

7FC5

7FC6

7FC7

7FC8

7FC9

7FCA

7FCB

7FCC

7FCD

SGDMA_START_FIFO2

SGDMA_DONE_FIFO2

SGDMA_ADHI2

SGDMA_ADLO2

SGDMA_SIZEHI2

SGDMA_SIZELO2

SGDMA_TOTAL_PKTS2

SGDMA_DONE_PKTS2

SGDMA_STS2

R/W Packet Number Start FIFO Register

R/W Packet Number Done FIFO Register

R/W ISA Address High Byte Register

R/W ISA Address Low Byte Register

R/W Transfer Size High Register

39

40

41

R/W Transfer Size Low Register

R

Total Packets in Channel Register

Total Packets in Done FIFO Register

Status Register

SGDMA_CMD2

R/W Command Register

CHANNEL 3 REGISTERS

7FCE

7FCF

7FD0

7FD1

7FD2

7FD3

7FD4

7FD5

7FD6

7FD7

SGDMA_START_FIFO3

SGDMA_DONE_FIFO3

SGDMA_ADHI3

SGDMA_ADLO3

SGDMA_SIZEHI3

SGDMA_SIZELO3

SGDMA_TOTAL_PKTS3

SGDMA_DONE_PKTS3

SGDMA_STS3

R/W Packet Number Start FIFO Register

R/W Packet Number Done FIFO Register

R/W ISA Address High Byte Register

R/W ISA Address Low Byte Register

R/W Transfer Size High Register

39

40

41

R/W Transfer Size Low Register

R

Total Packets in Channel Register

Total Packets in Done FIFO Register

Status Register

SGDMA_CMD3

R/W Command Register

PIO REGISTERS

7FD8

7FD9

7FDA

7FDB

7FDC

PIO_ADHI

PIO_ADMID

PIO_ADLO

PIO_DATA

PIO_CSR

R/W Upper Byte of the ISA Address

R/W Middle Byte of the ISA Address

R/W Lower Byte of the ISA Address

R/W PIO Data Register

42

43

R/W PIO Command Register

SMSC DS – USB97C102

Page 16

Rev. 03/23/2000

MMU Block Register Summary

Table 8 - MMU Block Register Summary

ADDRESS

NAME

R/W

DESCRIPTION

MMU REGISTERS

PAGE

6000

7F40

7F41

7F42

7F43

7F44

7F45

7F46

7F47

7F48

7F49

7F4A

7F4B

7F4C

7F4D

7F4E

7F4F

7F50

7F51

7F52

7F53

7F54

7F55

7F56

7F57

7F58

7F59

7F60

7F61

7F62

7F63

7F64

7F65

7F66

7F67

7F6E

7F6F

MMU_DATA

TX_FIFO0

TX_FIFO1

TX_FIFO2

TX_FIFO3

TX_FIFO4

TX_FIFO5

TX_FIFO6

TX_FIFO7

TX_FIFO8

TX_FIFO9

TX_FIFOA

TX_FIFOB

TX_FIFOC

TX_FIFOD

TX_FIFOE

TX_FIFOF

PRL

PRH

MMUTX_SEL

MMUCR

ARR

PNR

PAGS_FREE

TX_MGMT

RXFIFO

R/W

R

8051-MMU Data Window Register FIFO

TX_FIFO Counter 0

TX_FIFO Counter 1

TX_FIFO Counter 2

TX_FIFO Counter 3

TX_FIFO Counter 4

TX_FIFO Counter 5

TX_FIFO Counter 6

TX_FIFO Counter 7

TX_FIFO Counter 8

TX_FIFO Counter 9

TX_FIFO Counter A

TX_FIFO Counter B

TX_FIFO Counter C

TX_FIFO Counter D

TX_FIFO Counter E

TX_FIFO Counter F

8051-MMU Pointer Register (Low)

8051-MMU Pointer Register (High) & R/W

8051-MMU TX FIFO Select for Commands

8051-MMU Command Register

8051-MMU Allocation Result Register

8051-MMU Packet Number Register

Pages Free In the MMU

TX Management Register 2

RX Packet FIFO Register (All EPs)

POP TX FIFO

TX Packet FIFO Status Register (EP0-3)

TX Packet FIFO Status Register (EP4-7)

TX Packet FIFO Status Register (EP8-11)

TX Packet FIFO Status Register (EP12-15)

Reserved for Test

44

45

46

47

48

49

50

51

R/W

W

R

R/W

R

N/A

R/W

N/A

POP_TX

TXSTAT_A

TXSTAT_B

TXSTAT_C

TXSTAT_D

MMU_TESTx

TX_MGMT

MMU_TESTx

Reserved for Test

TX Management Register 1

Reserved for Test

51

SIE Block Register Summary

ADDRESS

Table 9 - SIE Block Register Summary

NAME

R/W

DESCRIPTION

PAGE

SIE Control Registers

7F80

7F81

7F82

7F83

7F84

7F85

7F86

7F87

7F88

7F89

7F8A

EP_CTRL0

EP_CTRL1

EP_CTRL2

EP_CTRL3

EP_CTRL4

EP_CTRL5

EP_CTRL6

EP_CTRL7

EP_CTRL8

EP_CTRL9

EP_CTRL10

R/W

Endpoint 0 Control Register

53

Endpoint 1 Control Register

Endpoint 2 Control Register

Endpoint 3 Control Register

Endpoint 4 Control Register

Endpoint 5 Control Register

Endpoint 6 Control Register

Endpoint 7 Control Register

Endpoint 8 Control Register

Endpoint 9 Control Register

Endpoint 10 Control Register

SMSC DS – USB97C102

Page 17

Rev. 03/23/2000

ADDRESS

7F8B

7F8C

7F8D

7F8E

7F8F

7F90

7F91

7F92

7F93

7F94

7F95

7F96

7F97

7F98

7F99

7F9A

7F9B

7F9C

7F9D

7F9E

7F9F

7FA9

7FAA

7FAB

7FAC

7FAD

7FAE

7FAF

7FEC

7FED

7FEE

7FEF

NAME

EP_CTRL11

EP_CTRL12

EP_CTRL13

EP_CTRL14

EP_CTRL15

FRAMEL

FRAMEH

SIE_ADDR

SIE_STAT

SIE_CTRL1

SIE_TST1

SIE_TST2

SIE_EP_TEST

SIE_CONFIG

ALT_ADDR1

SIE_TST3

R/W

R

R/W

R

R/W

R

DESCRIPTION

Endpoint 11 Control Register

Endpoint 12 Control Register

Endpoint 13 Control Register

Endpoint 14 Control Register

Endpoint 15 Control Register

USB Frame Count Low

USB Frame Count High

USB Local Address Register

SIE Status Register

SIE Control Register 1

Reserved Test Register

SIE Configuration Register

Secondary Local Address Register #1

Reserved Test Register

PAGE

53

54

57

58

55

SIE_TST4

SIE_TST5

SIE_TST6

Reserved Test Register

ALT_ADDR2

ALT_ADDR3

SIE_CTRL2

EPCMD

NONCTRL_EP1

NONCTRL_EP2

Reserved

Secondary Local Address Register #2

Secondary Local Address Register #3

SIE Control Register 2

Endpoint Command Register

Non-Control Endpoint Register 1 (High)

Non-Control Endpoint Register 2 (Low)

Reserved

Mem-Management Command Register

Mem-Management State Register

IN NAK Register Low

55

58

59

60

61

62

63

MMPCMD

R/W

MMPSTATE

IN_NAKLO

IN_NAKHI

OUT_NAKLO

OUT_NAKHI

IN NAK Register High

OUT NAK Register Low

OUT NAK Register High

Table 10 - HUB Block Register Summary

ADDRESS

7FA0

NAME

R/W

HUB REGISTERS

DESCRIPTION

PAGE

IdVendor-Low

Byte

IdVendor-High

Byte

IdProduct-Low

Byte

R/W

Low byte Vendor ID in little endian format

(Bit 0 is the LSB)

High byte Vendor ID in little endian

format (Bit 0 is the LSB)

Low byte Product ID value in little endian

format (Bit 0 is the LSB). This value is

initialized by firmware upon

7FA1

7FA2

initialization/power up. This value must

be initialized prior to the Hub device

participating in and USB enumeration

transactions.

7FA3

IdProduct-High

Byte

R/W

High byte Product ID value in little endian

format (Bit 0 is the LSB). This value is

initialized by firmware upon

initialization/power up. This value must

be initialized prior to the Hub device

participating in and USB enumeration

transactions.

7FA4

BcdDevice - Low

Byte

This 8-bit value defines the USB device

release number, which is assigned by

the system manufacture.

SMSC DS – USB97C102

Page 18

Rev. 03/23/2000

ADDRESS

NAME

R/W

HUB REGISTERS

DESCRIPTION

PAGE

7FA5

BcdDevice - High

Byte

R/W

This 8-bit value defines the USB device

release number, which is assigned by

the system manufacture.

7FA6

HubControl1

R/W

Hub Control register 1

65

MCU REGISTER DESCRIPTION

MCU Runtime Registers

Table 11 - Interrupt 0 Source Register

ISR_0

(0x7F00 - RESET=0x00)

INTERRUPT 0 SOURCE REGISTER

DESCRIPTION

BIT

NAME

R/W

7

IRQ3

R/W External interrupt input.

0 = Inactive

1 = Active

6

5

4

IRQ2

IRQ1

IRQ0

R/W External interrupt input.

0 = Inactive

1 = Active

R/W External interrupt input.

0 = Inactive

1 = Active

R/W External interrupt input.

0 = Inactive

1 = Active

3

2

RX_PKT

R/W 1 = A Packet Number (PNR) has been successfully queued on

the RXFIFO.

TX_EMPTY

R/W 1 = Whenever an enabled TX Endpoint's FIFO becomes

empty. This will occur when the last queued packet in one of

the 16 TX queues is successfully transferred to the Host.

R/W 1 = A Packet was successfully transmitted.

R/W 1 = When a selected 8237 channels in

1

0

TX_PKT

ISADMA

BUS_STAT/BUS_MASK register pair either reached Terminal

Count or have a new DMA Request Pending.

The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

Note 1:

TX_EMPTY is useful for warning of USB performance degradation. This interrupt indicates that the next time

the Host polls the affected endpoint, it will receive a NAK for that endpoint, thus reducing effective overall

bandwidth due to retries. Firmware must use TX_STAT A, B, and C to determine which endpoint queue is

empty.

Note 2:

Note 3:

When ISADMA causes an interrupt, the 8237 CH_STAT register should also be read and serviced when the

bit causing the interrupt is to be rearmed. When ISR_0 is read and the ISADMA bit is cleared, any other low-

to-high transitions in the BUS_STAT register bits that are not masked will still cause an interrupt.

If an expected IN token at EP1 (when in isochronous mode) does not arrive, the packet number will be

removed from the TX_FIFO and saved in the TX_COMPLETION_FIFO and a TX_PKT interrupt will be sent

to the MCU. It is the responsibility of the MCU to remove pages assigned to that packet. (Note if the MCU

masks the TX_PKT interrupt, it will not be notified).

SMSC DS – USB97C102

Page 19

Rev. 03/23/2000

Table 12 - Interrupt 0 Mask

IMR_0

(0x7F01- RESET=0xFF)

INTERRUPT 0 MASK REGISTER

DESCRIPTION

External interrupt input mask

BIT

NAME

R/W

7

6

5

4

3

2

1

0

IRQ3

0 = Enable Interrupt

1 = Mask Interrupt

External interrupt input mask

0 = Enable Interrupt

1 = Mask Interrupt

External interrupt input mask

0 = Enable Interrupt

1 = Mask Interrupt

External interrupt input mask

0 = Enable Interrupt

1 = Mask Interrupt

Received Packet MMU Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Transmit Queue Empty MMU Interrupt

0 = Enable Interrupt

1 = Mask Interrupt

Transmit Packet MMU Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

ISADMA Status Change Interrupt Mask

0 = Enable Interrupt

IRQ2

IRQ1

R/W

IRQ0

RX_PKT

TX_EMPTY

TX_PKT

ISADMA

1 = Mask Interrupt

Table 13 - Interrupt 1 Source Register

ISR_1

(0x7F02- RESET=0x00)

INTERRUPT 1 SOURCE REGISTER

DESCRIPTION

BIT

NAME

Reserved

EOT

R/W

[7:5]

4

R/W

Reserved

1 = The SIE returned to Idle State. Marks the end of each

transaction.

3

2

SOF

R/W

1 = When a Start of Frame token is correctly decoded.

Generated by the write strobe to the Frame Count register.

1 = MCU Software Allocation Request complete interrupt. This

interrupt is not generated for hardware (SIEDMA) allocation

requests.

ALLOC

1

0

RX_OVRN

PWR_MNG

R/W

1 = A receive condition has occurred that will stop the current

receive buffer to not be processed. The SIE automatically

recovers from this condition after its cause has been alleviated

(e.g. any partially allocated packets will be released. See Note

2).

1 = A wakeup or power management event in the WU_SRC_1

or WU_SRC_2 registers has gone active.

Note 1:

Note 2:

The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

The RX_OVRN interrupt should be considered by firmware as a general Receive Overrun of the SIE,

meaning that a packet destined for the RAM buffer could not be received and was not acknowledged back to

the Host. The firmware should check to see if the RX Packet Number FIFO Register (RXFIFO) is full. If it is

empty, then there may be too many transmit packets queued for the device to receive anything, or the last

packet may have been corrupted on the wire. If it is not empty, then one or more receive packets must be

dequeued before the device can continue to receive packets. In the normal course of operation, the MCU

should respond to a RX_PKT interrupt as often as possible and let the buffering logic do its job.

Note 3:

The RX_OVRN Interrupt can also be triggered if a non-isochronous packet exceeds 64 bytes or if an

isochronous packet exceeds the programmed limit (SIE_CTRL2 – Page 58). When a packet that is too long

is detected, the packet will be discarded from memory and the RX Overrun Interrupt will be triggered. For

non-isochronous packets, the hardware will stall the Rx Endpoint at the handshake after reception.

SMSC DS – USB97C102

Page 20

Rev. 03/23/2000

Note 4:

The RX_OVRN Interrupt can also be triggered if an Enpoint receives a packet while it is stalled. The packet

will be discarded from memory.

Table 14 - Interrupt 1 Mask

IMR_1

(0x7F03- RESET=0xFF)

INTERRUPT 1 MASK REGISTER

BIT

[7:5]

4

NAME

Reserved

EOT

R/W

DESCRIPTION

Reserved

EOT interrupt mask

R/W

0 = Enable Interrupt

1 = Mask Interrupt

3

2

1

0

SOF

Start of Frame Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

ALLOC

MCU Software Allocation Complete Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

RX_OVRN

PWR_MNG

Receive Overrun Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Power Management Wakeup Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Table 15 - Device Revision Register

DEV_REV

(0x7F06- RESET=0x00)

DEVICE REVISION REGISTER

DESCRIPTION

This register defines additional revision information

used internally by SMSC. The value is silicon revision

dependent.

BIT

[7:0]

NAME

BCD ‘00’

HEX 0x00

R/W

R

Table 16 - Device Identification Register

DEV_ID

(0x7F07- RESET=0x26)

DEVICE IDENTIFICATION REGISTER

DESCRIPTION

This register defines additional revision information

used internally by SMSC

BIT

NAME

BCD '26'

HEX 0x26

R/W

R

[7:0]

Table 17 – 8051 GP FIFO1

GP_FIFO1

(0x7F10- RESET=0xXX)

8051 GP FIFO1

DESCRIPTION

BIT

NAME

R/W

[7:0]

GP_FIFO1

R/W

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

Table 18 – 8051 GP FIFO2

GP_FIFO2

(0x7F12 - RESET=0xXX)

NAME

8051 GP FIFO2

DESCRIPTION

BIT

R/W

[7:0]

GP_FIFO2

R/W

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

Table 19 – 8051 GP FIFO3

GP_FIFO3

(0x7F14 - RESET=0xXX)

NAME

8051 GP FIFO3

DESCRIPTION

BIT

R/W

[7:0]

GP_FIFO3

R/W

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

SMSC DS – USB97C102

Page 21

Rev. 03/23/2000

Table 20 – 8051 GP FIFO4

8051 GP FIFO4

GP_FIFO4

(0x7F16 - RESET=0xXX)

NAME

BIT

[7:0]

R/W

DESCRIPTION

8 byte deep GP FIFO. This data FIFOs must not be read

unless the associated status bit indicates that FIFO is not

empty.

GP_FIFO4

FIFO Status Registers

Table 21 – 8051 GP FIFO 1 STATUS

GPFIFO1_STS

(0x7F11 – RESET=0x01)

8051 GP FIFO STATUS

DESCRIPTION

BIT

[7:2]

1

NAME

Reserved

R/W

R

Reserved

GPFIFO1_FULL

R

GP FIFO 1 full status

0 = Not FULL

1 = FULL

0

GPFIFO1_EMPTY

R

GP FIFO 1 empty status

0 = Has one or more TX packet

1 = Empty

Table 22 – 8051 GP FIFO 2 STATUS

GPFIFO2_STS

(0x7F13 – RESET=0x01)

8051 GP FIFO 2 STATUS

DESCRIPTION

BIT

[7:2]

1

NAME

Reserved

R/W

R

Reserved

GPFIFO2_FULL

R

GP FIFO 2 full status

0 = Not FULL

1 = FULL

0

GPFIFO2_EMPTY

R

GP FIFO 2 empty status

0 = Has one or more TX packet

1 = Empty

Table 23 – 8051 GP FIFO 3 STATUS

GPFIFO3_STS

(0x7F15 – RESET=0x01)

8051 GP FIFO 3 STATUS

DESCRIPTION

BIT

[7:2]

1

NAME

Reserved

R/W

R

Reserved

GPFIFO3_FULL

R

GP FIFO 3 full status

0 = Not FULL

1 = FULL

0

GPFIFO3_EMPTY

R

GP FIFO 3 empty status

0 = Has one or more TX packet

1 = Empty

Table 24 – 8051 GP FIFO 4 STATUS

GPFIFO4_STS

(0x7F17 – RESET=0x01)

8051 GP FIFO STATUS

BIT

[7:2]

1

NAME

Reserved

GPFIFO4_FULL

R/W

R

DESCRIPTION

Reserved

GP FIFO 4 full status

0 = Not FULL

1 = FULL

0

GPFIFO4_EMPTY

R

GP FIFO 4 empty status

0 = Has one or more TX packet

1 = Empty

SMSC DS – USB97C102

Page 22

Rev. 03/23/2000

Table 25 - GPIO Direction Register

GPIOA_DIR

(0x7F18- RESET=0x00)

MCU UTILITY REGISTERS

DESCRIPTION

GPIO7 Direction

0 = In

1 = Out

GPIO6 Direction

0 = In

1 = Out

GPIO5 Direction

0 = In

1 = Out

GPIO4 Direction

0 = In

1 = Out

GPIO3 Direction

0 = In

1 = Out

GPIO2 Direction

0 = In

1 = Out

GPIO1 Direction

0 = In

1 = Out

GPIO0 Direction

0 = In

BIT

7

NAME

GPIO7

R/W

6

5

4

3

2

1

0

GPIO6

GPIO5

GPIO4/SOF

GPIO3/T1

GPIO2/T0

GPIO1/TXD

GPIO0/RXD

1 = Out

Note:

The Timer inputs T[1:0] can be configured as outputs and left unconnected so that software can write to the

bits to trigger the timer. Otherwise, the Timer inputs can be used to count external events or internal SOF

receptions.

Table 26 - GPIO Output Register

GPIOA_OUT

(0x7F19- RESET=0x00)

GPIO DATA OUTPUT

REGISTER A

BIT

7

6

5

4

3

2

1

0

NAME

GPIO7

GPIO6

R/W

DESCRIPTION

R/W

GPIO7 Output Buffer Data

GPIO6 Output Buffer Data

GPIO5 Output Buffer Data

GPIO4 Output Buffer Data

GPIO3 Output Buffer Data

GPIO2 Output Buffer Data

GPIO1 Output Buffer Data

GPIO0 Output Buffer Data

GPIO5

GPIO4/SOF

GPIO3/T1

GPIO2/T0

GPIO1/TXD

GPIO0/RXD

Table 27 - GPIO Input Register

GPIOA_IN

(0x7F1A- RESET=0xXX)

GPIO INPUT REGISTER A

DESCRIPTION

BIT

NAME

GPIO7

GPIO6

R/W

7

6

5

4

3

2

1

0

R

GPIO7 Input Buffer Data

GPIO6 Input Buffer Data

GPIO5 Input Buffer Data

GPIO4 Input Buffer Data

GPIO3 Input Buffer Data

GPIO2 Input Buffer Data

GPIO1 Input Buffer Data

GPIO0 Input Buffer Data

GPIO5

GPIO4/SOF

GPIO3/T1

GPIO2/T0

GPIO1/TXD

GPIO0/RXD

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Table 28 - Utility Configuration Register

UTIL_CONFIG

(0x7F1B- RESET=0x00)

UTILITY CONFIGURATION REGISTER

DESCRIPTION

Reserved

GPIO4/SOF Output Select Mux

0 = GPIO4

BIT

[7:5]

4

NAME

Reserved

GPIO4/SOF

R/W

R

R/W

1 = SOF port

3

2

1

0

GPIO3/T1

GPIO2/T0

R/W

P3.5 Timer 1 input trigger source

0 = GPIO3

1 = SOF FRAME write strobe

P3.4 Timer 0 input trigger source

0 = GPIO2

1 = SOF FRAME write strobe

GPIO1/TXD Output Select Mux

0 = GPIO1

GPIO1/TXD

GPIO0/RXD

1 = P3.1

P3.0 RXD/GPIO0 Input Select Mux

0 = RXD<=GPIO0

1 = RXD<='0'

Note 1:

Note 2:

Note 3:

In Counter mode, the 8051 must sample T[1:0] as a '1' in one instruction cycle, and then '0' in the next. So

for 12MHz, the SOF Pulse must be active for at least 1us.

Missing SOF packets can be reconstructed by using the Timer mode to count the number of 8051 instruction

cycles since the last valid Frame was received.

A GPIO can be used to output nSOF pulses. This can be done by configuring a GPIO as an output and

writing to the GPIO out register to generate low pulses each time a SOF packet is received.

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GPIO out data

(0x7F19[7:3])

GPIO Direction Bit

(0x7F18[7:3])

GPIO[7:3]

GPIO in data

(0x7F1A[7:3])

GPIO2 data out (0x7F19[2])

GPIO2 Dir (0x7F18[2])

GPIO2 data in (0x7F1A[2])

Internal SOF

0X7F1B[2]

Pin # 36

0

1

8051 "T0 timer P3.4"

S

GPIO3 data out (0x7F19[3])

GPIO3 Dir (0x7F18[3])

GPIO3 data in (0x7F1A[3])

Internal SOF

0X7F1B[3]

Pin # 37

0

1

8051 "T1 timer P3.5"

S

GPIO0 data out (0x7F19[0])

GPIO0 Dir (0x7F18[0])

Pin # 34

GPIO0 data in (0x7F1A[0])

0

1

RXD "Uart P3.0"

0X7F1B[0]

"0"

S

GPIO1 data out (0x7F19[1])

TXD "Uart P3.1"

0

1

S

GPIO1 Dir (0x7F18[1])

Pin # 35

0X7F1B[1]

GPIO1 data in (0x7F1A[1])

GPIO4 data out (0x7F19[4])

SOF port of SIE

0

1

S

GPIO4 Dir (0x7F18[4])

Pin # 38

0X7F1B[4]

GPIO4 data in (0x7F1A[4])

FIGURE 6 - GPIO MUXING BLOCK DIAGRAM

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MCU POWER MANAGEMENT REGISTERS

Table 29 - MCU/ISADMA Clock Source Select

CLOCK_SEL

(0x7F27 - RESET=0x40)

MCU/ISADMA CLOCK SOURCE SELECT

DESCRIPTION

BIT

NAME

R/W

7

SLEEP

R/W

When PCON. 0 = 1 and SLEEP has been set to 1, the ring

oscillator will be gated off, then all oscillators will be turned

off for maximum power savings. (These two signals can be

used to generate nFCE)

6

5

ROSC_EN

R/W

0 = Ring Oscillator Disable.

1 = Ring Oscillator Enable. ROSC_EN must be set to 1

before the MCU can be switched to the internal Ring

Oscillator Clock source.

MCUCLK_SRC overrides MCUCLK_x clock select and

switches the MCU to the Ring Oscillator.

0 = Use Ring Oscillator. ROSC_EN must be enabled by

the MCU first.

MCUCLK_SRC

1 = Use clock specified in MCU_CLK_[1:0]

[4:3]

2

MCU_CLK[1:0]

R/W

[4:3] = 00: 8MHz

[4:3] = 01: 12MHz

[4:3] = 10: 16MHz

[4:3] = 11: 24MHz

Selects an external clock source for the 8237 ISADMA

controller for synchronizing the DMA with another block.

NOTE: This will initially be an external input, but may

eventually be used within the block to optimize

performance, or as some other internal clock source.

0 = Use ISADMACLK[1..0] select

ISADMACLK_EXT

1 = Use EXT_IN clock source for 8237

[1:0]

ISADMACLK[1:0]

R/W

[1:0] = 00: Stopped

[1:0] = 01: 2MHz

[1:0] = 10: 4MHz

[1:0] = 11: 8MHz

Note 1:

The 8051 may program itself to run off of an internal Ring Oscillator having a frequency range between 4 and

12MHz. This is not a precise clock, but is meant to provide the 8051 with a clock source, without running the

24MHz crystal oscillator or the PLL

Note 2:

Note 3:

Switching between fast and slow clocks is recommended to save power.

Clock switching can be done on the fly as long as both clocks are running. When switching, it takes a total of

six clocks (3 clocks of the original clock plus 3 clocks of the switching clock) to guarantee the switching.

Time TBD is required from ROSC_EN=1 to MCUCLK_SRC=0.

Note 4:

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Table 30 - FLASH Bank Select Register 2

MEM_BANK2

(0x7F28 - RESET=0x00)

FLASH BANK SELECT REGISTER 2

DESCRIPTION

BIT

[7:6]

[5:0]

NAME

Reserved

A[19:14]

R/W

R

R/W

Reserved

This register selects which 16k page resides at 0x8000-0xBFFF in

Code Space and 0x8000-0xBFFF in Data Space.

Table 31 - FLASH Bank Select Register

MEM_BANK

(0x7F29 - RESET=0x01)

FLASH BANK SELECT REGISTER

DESCRIPTION

BIT

[7:6]

[5:0]

NAME

Reserved

A[19:14]

R/W

R

R/W

Reserved

This register selects which 16k page resides at 0x4000-0x7FFF in

Code Space and 0xC000-0xFFFF in Data Space. The 0x0000-

0x3FFF page will always reflect the 16K FLASH page 0 (0x00000-

0x03FFF).

Table 32 - Wakeup Source 1 Register

WU_SRC_1

(0x7F2A – RESET=0x00)

WAKEUP SOURCE 1

DESCRIPTION

BIT

[7:3]

2

NAME

Reserved

USB_Reset

R/W

Reserved

This bit is set when the SIE detects simultaneous logic lows on D+

and D- (Single-Ended 0) for 32 to 64 full speed bit times, or 4 to 8 low

speed bit times (or 2.5<t<5.5us). The USB_Reset signal may be as

long as 10ms. SETUP tokens can be NAK'd for up to 10ms after the

Reset signal is released.

1

0

Resume

Suspend

R/W

This bit is set on detection of Global Resume state (when there is a

transition from the "J" state while in Global Suspend).

Suspend – If 3ms of IDLE state are detected by the hardware, then

this bit will be set.

Note 1:

Note 2:

Note 3:

Only low to high transitions for the associated inputs sets these bits.

The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

Unmasked Wakeup Source bits generate an INT1 PWR_MNG interrupt, and restart the 8051 when its clock

is stopped. This restarts the Ring Oscillator and crystal oscillator for the MCU to resume from <500µA

operation.

Note 4:

To initiate USB Remote Wakeup, the SIE_Resume bit should be used in the SIE_CONFIG register.

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Table 33 - Wakeup Mask 1 Register

WU_MSK_1 (Note 1)

(0x7F2B - RESET=0x07 )

WAKEUP MASK 1

DESCRIPTION

BIT

NAME

R/W

[7:3]

2

Reserved

USB_Reset

R

R/W

Reserved

External wakeup event.

0 = Enabled

1 = Masked

1

0

Resume

Suspend

R/W

External wakeup event.

0 = Enabled

1 = Masked

Internal wakeup event.

0 = Enabled

1 = Masked

Suspend – If 3ms of IDLE state are detected by the hardware,

then this bit, when set (1) will cause an interrupt to the MCU

Note 1:

Interrupt events enabled by these bits are routed to the PWR_MNG Bit 0 in the ISR_1 register.

Table 34 - Wakeup Source 2 Register

WU_SRC_2

(0x7F2C - RESET=0x00)

WAKEUP SOURCE 2

BIT

[7:4]

3

NAME

'0'

IRQ3

R/W

DESCRIPTION

Reserved

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

2

1

0

IRQ2

IRQ1

IRQ0

R/W

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

External Interrupt state since WU_SRC_2 was last read.

0 = Unchanged

1 = Changed

Note 1:

Note 2:

Note 3:

Any transition from high to low, or low to high on the associated input sets these bits.

The bits in this register are cleared by writing a ‘1’ to the corresponding bit.

Since this register will report any status change, when devices are to be powered down while monitored, the

appropriate bits must be masked until the device is armed correctly.

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Table 35 - Wakeup Mask 2 Register

WU_MSK_2

(0x7F2D - RESET=0x0F)

WAKEUP MASK 2

DESCRIPTION

BIT

[7 :4]

3

NAME

'0'

R/W

R

Reserved

IRQ3

R/W

External wakeup event enable.

0 = Enabled

1 = Masked

2

1

0

IRQ2

IRQ1

IRQ0

R/W

External wakeup event enable.

0 = Enabled

1 = Masked

External wakeup event enable.

0 = Enabled

1 = Masked

External wakeup event enable.

0 = Enabled

1 = Masked

Note:

Interrupt events enabled by these bits are be routed to the PWR_MNG Bit 0 in the ISR_1 register.

MCU ISA Interface Registers

Table 36 – ISA Bus Request Register

ISA BUS REQUEST REGISTER

BUS_REQ

(0x7F70 – RESET=0x00)

BIT NAME R/W

DESCRIPTION

7

6

5

4

3

INH_TC3

R/W

This bit inhibits DMA channel 3 TC.**See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

This bit inhibits DMA channel 2 TC.** See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

This bit inhibits DMA channel 1 TC.** See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

This bit inhibits DMA channel 0 TC.** See Note Below

0 = TC is driven onto the ISA bus via EOP as before.

1 = TC is forced inactive.

Writing a '1' holds the 8237 hardware reset input active. Writing

'0' releases it for normal operation. May be used for clock

switching or power management functions.

This bit reflects the status of the 8237's AEN pin. This bit does

not generate an interrupt

The 8051 can grant the bus when it is ready via HLDA. This

should tri-state any common signals between the 8051 and the

8237 on the ISA bus.

INH_TC2

INH_TC1

INH_TC0

RESET_8237

2

1

AEN

R

HLDA

R/W

0

HREQ

R

This bit reflects the status of the 8237's HREQ bus request pin.

This bit does not generate an interrupt.

Note:

HLDA Example: When the 8051 is running at 24MHz, and the 8237 is running at 2MHz, the 8237 may take

up to 1.5us to complete a transfer after deasserting HLDA When running the 8051 at 24MHz, wait states

must be added when the 8237 is running at 2 or 4 MHz. When running the 8051 at 12MHz, wait states must

be added when the 8237 is running at 2 MHz.

Note**:

The “Inhibit” function is not valid for Memory-to-Memory DMA cycles

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Table 37 - ISA Bus Status Register

BUS_STAT

(0x7F73 - RESET=0xXX)

ISA BUS STATUS REGISTER

DESCRIPTION

Channel 3 DMA Request

BIT

NAME

R/W

7

6

5

4

3

2

1

0

CH3RQ

R

0 = No Request Pending

1 = Request Pending

Channel 2 DMA Request

0 = No Request Pending

1 = Request Pending

Channel 1 DMA Request

0 = No Request Pending

1 = Request Pending

Channel 0 DMA Request

0 = No Request Pending

1 = Request Pending

Channel 3 Terminal Count Reached

0 = No

CH2RQ

CH1RQ

CH0RQ

CH3TC

CH2TC

CH1TC

CH0TC

1 = Yes

Channel 2 Terminal Count Reached

0 = No

1 = Yes

Channel 1 Terminal Count Reached

0 = No

1 = Yes

Channel 0 Terminal Count Reached

0 = No

1 = Yes

Note 1:

Note 2:

Each bit in this register reflects the current value of the corresponding bit in the 8237 CH_STAT status

register.

The 8237 clears bits 3..0 in the CH_STAT status register when the 8051 reads it through the ISA Bus I/O

Window.

Note 3:

Note 4:

Reading the BUS_STAT register does not clear or otherwise affect the BUS_STAT register.

The ISADMA bit in ISR_0 is latched high whenever any bit in BUS_STAT that is enabled in BUS_MASK

transitions from low to high.

Note 5:

This register is intended (1) to provide a view into the status of the 8237 without having to assume control of

the ISA bus during DMA transfers, and (2) to provide a means for generating the ISADMA interrupt in ISR_0

which indicates that a DMA transfer has completed and that the 8051 should take control of the bus and

setup the 8237 for its next transfer. Bits 7-4 can be used to generate additional interrupt requests from the

DREQ pins, or simply to monitor channel request status by masking them.

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Table 38 - ISA Bus Status Mask Register

BUS_MASK

(0x7F74 - RESET=0xFF)

ISA BUS STATUS MASK REGISTER

DESCRIPTION

BIT

NAME

R/W

7

CH3RQ_MASK

R/W

Channel 3 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 2 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 1 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 0 DMA Request ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 3 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 2 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 1 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

1 = Mask Interrupt

Channel 0 Terminal Count ISADMA Interrupt Mask

0 = Enable Interrupt

6

5

4

3

2

1

0

CH2RQ_MASK

CH1RQ_MASK

CH0RQ_MASK

CH3TC_MASK

CH2TC_MASK

CH1TC_MASK

CH0TC_MASK

1 = Mask Interrupt

Table 39 - ISA I/O Window Base Register

IOBASE

(0x7F71 - RESET=0x00)

ISA I/O WINDOW BASE REGISTER

DESCRIPTION

BIT

NAME

R/W

[7:0]

SA[15:8]

R/W

When the 8051 reads or writes to the ISA I/O Window,

this register is combined with the 8 bit offset in the 256

byte window and presented as the 64k I/O Space address

during an 8051-ISA IOR or IOW cycle

Table 40 - ISA Memory Window Base Register

MEMBASE

(0x7F72 - RESET=0x00)

ISA MEMORY WINDOW BASE REGISTER

BIT

NAME

R/W

DESCRIPTION

[7:0]

SA[19:12]

R/W

When the 8051 reads or writes to the ISA Memory

Window, this register is combined with the 12 bit

offset in the 4k byte window and presented as the

1Mbyte Memory address during an 8051-ISA

MEMR or MEMW cycle.

8237 (ISADMA) REGISTER DESCRIPTION

Memory Map

Table 41 - ISADMA Memory Map

8237 MEMORY ADDRESS

DESCRIPTION

0xFC00-0xFFFF

0xF800-0xFBFF

0xF400-0xF7FF

0xF000-0xF3FF

0xEC00-0xEFFF

0xE800-0xEBFF

0xE400-0xE7FF

0xE000-0xE3FF

0xDC00-0xDFFF

1k Window to Packet with PNR=0x1F

1k Window to Packet with PNR=0x1E

1k Window to Packet with PNR=0x1D

1k Window to Packet with PNR=0x1C

1k Window to Packet with PNR=0x1B

1k Window to Packet with PNR=0x1A

1k Window to Packet with PNR=0x19

1k Window to Packet with PNR=0x18

1k Window to Packet with PNR=0x17

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8237 MEMORY ADDRESS

0xD800-0xDBFF

0xD400-0xD7FF

0xD000-0xD3FF

0xCC00-0xCFFF

0xC800-0xCBFF

0xC400-0xC7FF

0xC000-0xC3FF

0xBC00-0xBFFF

0xB800-0xBBFF

0xB400-0xB7FF

0xB000-0xB3FF

0xAC00-0xAFFF

0xA800-0xABFF

0xA400-0xA7FF

0xA000-0xA3FF

0x9C00-0x9FFF

0x9800-0x9BFF

0x9400-0x97FF

0x9000-0x93FF

0x8C00-0x8FFF

0x8800-0x8BFF

0x8400-0x87FF

0x8000-0x83FF

DESCRIPTION

1k Window to Packet with PNR=0x16

1k Window to Packet with PNR=0x15

1k Window to Packet with PNR=0x14

1k Window to Packet with PNR=0x13

1k Window to Packet with PNR=0x12

1k Window to Packet with PNR=0x11

1k Window to Packet with PNR=0x10

1k Window to Packet with PNR=0x0F

1k Window to Packet with PNR=0x0E

1k Window to Packet with PNR=0x0D

1k Window to Packet with PNR=0x0C

1k Window to Packet with PNR=0x0B

1k Window to Packet with PNR=0x0A

1k Window to Packet with PNR=0x09

1k Window to Packet with PNR=0x08

1k Window to Packet with PNR=0x07

1k Window to Packet with PNR=0x06

1k Window to Packet with PNR=0x05

1k Window to Packet with PNR=0x04

1k Window to Packet with PNR=0x03

1k Window to Packet with PNR=0x02

1k Window to Packet with PNR=0x01

1k Window to Packet with PNR=0x00

0x0000-0x7FFF

32K Window to External ISA RAM

The actual packet may be composed of up to 10 different 128 byte non-contiguous packets, but the MMU re-maps

the internal addresses automatically such that the 8237 and 8051 only need to reference the packet number and

offset within the packet. For example, suppose a 312 (0x138) byte packet is received by the SIEDMA from the host.

The patented MMU allocates 384 bytes for the packet (including an 8 byte status header) and returns a PNR tag of

0x0A. The SIEDMA engine will place 0x0A in the receive packet queue and notify the 8051. The 8051 will take that

PNR, examine the packet through its own PNR/Pointer registers, and determine the offset for the payload data it

wants to transfer from the packet, say 0x027. The address it must calculate for the 8237 base address register would

therefore be 0xA827 (0xA800+0x027). Each channel can be programmed with a different (or same) Packet Number

and offset and the data will appear to it as ordinary contiguous RAM (see table 32 for more information).

Software written to this model will work for virtually any Endpoint number and Buffer size combination.

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Runtime Registers

The DMA controller has a block of 16 R/W registers which normally occupy I/O locations 0x00-0x0F on the ISA bus.

When they are located at 0x0000-0x000F on the ISA bus, the 8051 can access them by programming the IOBASE

Register to 0x00, and reading or writing from 0x4000-0x400F.

Table 42 - 8237 Registers in ISA I/O Space

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

0x000F

Channel 0: Current Address H/L

Channel 0: Byte Count H/L

Channel 1: Current Address H/L

Channel 1: Byte Count H/L

Channel 2: Current Address H/L

Channel 2: Byte Count H/L

Channel 3: Current Address H/L

Channel 3: Byte Count H/L

Status/Command Register

Write Request Register

Write Single Mask Register

Write Mode Register

Clear Byte Ptr F/F - Read Temp Register

Master Clear

Clear Mask

Write All Mask Bits

Note:

To write to these registers, HLDA must be logic low.

Table 43 - 8237 Address Programming Guide

8237 INTERNAL ADDRESS PROGRAMMING GUIDE

NAME DESCRIPTION

BIT

15

INT_EXT

Indicates whether this address refers to Internal Buffer RAM or

External ISA Memory Space

0 = External

1 = Internal

When this bit is set to zero (0), I/O capability is added to External

Memory DMA. This capability can only be used for DMA channels 2

or 3.

[14:10]

[9:0]

PN[4:0]/SA[14:10]

PTR[9:0]/SA[9:0]

External Address -or- Internal Packet Number

SA[14..10] when INT_EXT=0

PN[4..0] when INT_EXT=1

External Address -or- Internal Packet Offset Pointer

SA[9..0] when INT_EXT=0

PTR[9..0] when INT_EXT=1

Note:

SA[19..15] are driven low when the 8237 is accessing external ISA memory. PTR10 is driven low when the

8237 is accessing internal buffer RAM. Note that the actual transfer size for the ISADMA is limited to 1024

bytes, which limits the payload data to 1016 bytes per transfer when the 8 byte header is skipped. Also note

that the 8051 still has access to 1Meg of external RAM through the MEMBASE register and it is independent

of the 8237's 32k external limit.

Table 44 - Channel 0 Current Address Register

CH0_ADDR

(ISA 0x0000)

CHANNEL 0 CURRENT ADDRESS

BIT

[7:0]

NAME

CH0_ADDRL

CH0_ADDRH

R/W

DESCRIPTION

Lower 8 bits of Base and Current Address when Byte F/F = 0

Upper 8 bits of Base and Current Address when Byte F/F = 1

Note:

Byte F/F is an internal Flip Flop which reflects which byte (high or low) is being written. The CLEAR_FF

register should be written to before writing this register to guarantee which byte (high or low) is being written.

See the Address Programming Table for 16 bit Address definitions.

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Table 45 - Channel 0 Byte Count Register

CHANNEL 0 BYTE COUNT

CH0_CNT

(ISA 0x0001)

NAME

CH0_CNTL

CH0_CNTH

BIT

[7:0]

R/W

DESCRIPTION

Lower 8 bits of Byte Count when Byte F/F = 0

Upper 8 bits of Byte Count when Byte F/F = 1

Note:

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See Address Programming Table for 16 bit Address definitions.

Table 46 - Channel 1 Current Address Register

CH1_ADDR

(ISA 0x0002)

CHANNEL 1 CURRENT ADDRESS

BIT

[7:0]

NAME

CH1_ADDRL

CH1_ADDRH

R/W

DESCRIPTION

Lower 8 bits of Base and Current Address when Byte F/F = 0

Upper 8 bits of Base and Current Address when Byte F/F = 1

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See the Address Programming Table for 16 bit Address definitions.

Table 47 - Channel 1 Byte Count Register

CH1_CNT

(ISA 0x0003)

CHANNEL 1 BYTE COUNT

BIT

[7:0]

NAME

CH1_CNTL

CH1_CNTH

R/W

DESCRIPTION

Lower 8 bits of Byte Count when Byte F/F = 0

Upper 8 bits of Byte Count when Byte F/F = 1

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See Address Programming Table for 16 bit Address definitions.

Table 48 - Channel 2 Current Address Register

CH2_ADDR

(ISA 0x0004)

CHANNEL 2 CURRENT ADDRESS

BIT

[7:0]

NAME

CH2_ADDRL

CH2_ADDRH

R/W

DESCRIPTION

Lower 8 bits of Base and Current Address when Byte F/F = 0

Upper 8 bits of Base and Current Address when Byte F/F = 1

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See the Address Programming Table for 16 bit Address definitions.

Table 49 - Channel 2 Byte Count Register

CH2_CNT

(ISA 0x0005)

CHANNEL 2 BYTE COUNT

BIT

[7:0]

NAME

CH2_CNTL

CH2_CNTH

R/W

DESCRIPTION

Lower 8 bits of Byte Count when Byte F/F = 0

Upper 8 bits of Byte Count when Byte F/F = 1

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See Address Programming Table for 16 bit Address definitions.

Table 50 - Channel 3 Current Address Register

CH3_ADDR

(ISA 0x0006)

CHANNEL 3 CURRENT ADDRESS

BIT

[7:0]

NAME

CH3_ADDRL

CH3_ADDRH

R/W

DESCRIPTION

Lower 8 bits of Base and Current Address when Byte F/F = 0

Upper 8 bits of Base and Current Address when Byte F/F = 1

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See the Address Programming Table for 16 bit Address definitions.

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Table 51 - Channel 3 Byte Count Register

CHANNEL 3 BYTE COUNT

CH3_CNT

(ISA 0x0007)

NAME

CH3_CNTL

CH3_CNTH

BIT

[7:0]

R/W

DESCRIPTION

Lower 8 bits of Byte Count when Byte F/F = 0

Upper 8 bits of Byte Count when Byte F/F = 1

Note:

The CLEAR_FF register should be written to before writing this register to guarantee which byte (high or low)

is being written. See Address Programming Table for 16 bit Address definitions.

Table 52 - Channel Status Register

CH_STAT

(ISA 0x0008)

CHANNEL STATUS REGISTER

BIT

NAME

R/W

DESCRIPTION

7

CH3RQ

R

Channel 3 DMA Request

0 = No Request Pending

1 = Yes Request Pending

Channel 2 DMA Request

0 = No Request Pending

1 = Yes Request Pending

Channel 1 DMA Request

0 = No Request Pending

1 = Yes Request Pending

Channel 0 DMA Request

0 = No Request Pending

1 = Yes Request Pending

Channel 3 Terminal Count Reached

0 = No

6

5

4

3

2

1

0

CH2RQ

CH1RQ

CH0RQ

CH3TC

CH2TC

CH1TC

CH0TC

R

1 = Yes

Channel 2 Terminal Count Reached

0 = No

1 = Yes

Channel 1 Terminal Count Reached

0 = No

1 = Yes

Channel 0 Terminal Count Reached

0 = No

1 = Yes

Note 1:

Note 2:

These bits are also visible outside of I/O space in the BUS_STAT register.

These bits are cleared when this register is read through the ISA I/O Window.

Table 53 - 8237 Command Register

CH_CMD

(ISA 0x0008)

COMMAND REGISTER

BIT

NAME

R/W

DESCRIPTION

7

DACK_SENS

W

DACK Sense

0 = Active High

1 = Active Low

DREQ Sense (1 = Active Low, 0 = Active High)

Write Timing Select

0 = Late Timing

1 = Extended

6

5

DREQ_SENS

WRITE_TIME

W

4

3

2

PRIORITY

COMP_TIME

CTRL_EN

W

Priority

0 = Fixed

1 = Rotating

Timing

0 = Normal

1 = Compressed

Controller Enable

0 = Enable

1 = Disable

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CH_CMD

(ISA 0x0008)

NAME

COMMAND REGISTER

DESCRIPTION

BIT

R/W

1

ADDR_HOLD

W

Channel 0 Address Hold

0 = Disable

1 = Hold Enable

Memory-to-Memory

0 = Disable

0

MEM2MEM

W

1 = Enable

Table 54 - 8237 Write Single Request Register

CH_REQ

(ISA 0x0009)

WRITE REQUEST REGISTER

BIT

[7:3]

2

NAME

Reserved

SET_CLR

R/W

W

DESCRIPTION

Reserved

Force Internal DMA Request Bit

0 = Clear

1 = Set

[1:0]

SEL[1:0]

W

'00' = Select Channel 0 DREQ

'01' = Select Channel 1 DREQ

'10' = Select Channel 2 DREQ

'11' = Select Channel 3 DREQ

Table 55 - 8237 Write Single Mask Register

CH_MASK

(ISA 0x000A)

WRITE SINGLE MASK REGISTER

BIT

[7:3]

2

NAME

Reserved

SET_CLR

R/W

R

W

DESCRIPTION

Reserved

Set Channel Mask Bit

0 = Clear

1 = Set

[1:0]

SEL[1:0]

W

'00' = Select Channel 0 Mask Bit

'01' = Select Channel 1 Mask Bit

'10' = Select Channel 2 Mask Bit

'11' = Select Channel 3 Mask Bit

Table 56 - Write Mode Register

DMA_MODE

(ISA 0x000B)

NAME

WRITE MODE REGISTER

DESCRIPTION

'00' = Demand Mode Select

BIT

[7:6]

R/W

W

MODE[1:0]

'01' = Single Mode Select

'10' = Block Mode Select

'11' = Cascade Mode Select

Auto-increment/Decrement

0 = Increment

1 = Decrement

Auto-initialization

0 = Disable

1 = Enable

'00' = Verify Transfer

'01' = Write Transfer

'10' = Read Transfer

'11' = Illegal

5

4

INC_DEC

AUTO_INIT

R/WV[1:0]

W

[3:2]

'XX' if bits 6 and 7 = '11' Or if CH_CMD register bit 0

= 1 (memory-to-memory transfer)

'00' = Select Channel 0

'01' = Select Channel 1

'10' = Select Channel 2

'11' = Select Channel 3

[1:0]

SEL[1:0]

W

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Table 57 - Clear Byte Pointer Flip Flop Register

CLEAR_FF

(ISA 0x000C)

NAME

CLEAR BYTE POINTER FLIP FLOP

DESCRIPTION

BIT

R/W

[7:0]

BPFF

W

This register must be written to clear the high/low byte

pointer flip flop prior to reading or writing new address or

word count information to the 8237.

Table 58 - Read Temporary Register

RD_TEMP

(ISA 0x000D)

NAME

READ TEMPORARY REGISTER

BIT

R/W

DESCRIPTION

[7:0]

TEMP_BYTE

R

This location holds the value of the last byte transferred in a

memory-to-memory operation.

Table 59 - Master Clear Register

MASTER CLEAR REGISTER

MSTR_CLR: (ISA 0x000D)

BIT

[7:0]

NAME

SW_RESET

R/W

W

DESCRIPTION

Writing to this register has the same effect on the registers

as a hardware reset. The 8237 will enter the idle state.

Table 60 - Clear Mask Register

CLEAR MASK REGISTER

CLR_MASK: (ISA 0x000E)

BIT

NAME

R/W

DESCRIPTION

[7:0]

CLR_ALL

W

Writing to this register clears the mask bits of all four

channels and allows them to receive DMA requests.

Table 61 - Clear All Mask Bits Register

ALL_MASK

(ISA 0x000F)

NAME

WRITE ALL MASK BITS REGISTER

DESCRIPTION

BIT

[7:4]

3

2

1

R/W

W

Reserved

CH3_MASK

CH2_MASK

CH1_MASK

CH0_MASK

Channel 3 Mask Bit (1 = Set Mask, 0 = Clear Mask)

Channel 2 Mask Bit (1 = Set Mask, 0 = Clear Mask)

Channel 1 Mask Bit (1 = Set Mask, 0 = Clear Mask)

Channel 0 Mask Bit (1 = Set Mask, 0 = Clear Mask)

0

W

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SCATTER-GATHER DMA (SGDMA) REGISTER DESCRIPTION

FIGURE 7

). Each register set

The SGDMA has four DMA channels with each channel having its own set of registers (

starts at a different starting BASE address: Channels 0, 1,2, and 3 have starting BASE addresses 7FB0, 7FBA,

7FC4, and 7FCE, respectively. The tables on the following pages describe each register of one register set, using ‘x’

to denote the DMA channel (x ranges from 0 to 3). The address of each register is denoted as BASE+n, where n is

the offset from BASE.

BASE

Address

Effective

Address

OFFSET 0 - SGDMA_START_FIFO0

7FB0

7FBA

7FC4

7FCE

7FB0

7FB1

7FB2

7FB3

OFFSET 1 - SGDMA_DONE_FIFO0

OFFSET 2 - SGDMA_ADHI0

OFFSET 3 - SGDMA_ADLO0

SGDMA Channel 0 Registers

SGDMA Channel 1 Registers

SGDMA Channel 2 Registers

SGDMA Channel 3 Registers

OFFSET 9 - SGDMA_CMD0

OFFSET 0 - SGDMA_START_FIFO1

OFFSET 1 - SGDMA_DONE_FIFO1

OFFSET 2 - SGDMA_ADHI1

7FB9

7FBA

7FBB

7FBC

7FBD

OFFSET 3 - SGDMA_ADLO1

OFFSET 9 - SGDMA_CMD1

OFFSET 0 - SGDMA_START_FIFO2

OFFSET 1 - SGDMA_DONE_FIFO2

OFFSET 2 - SGDMA_ADHI2

7FC3

7FC4

7FC5

7FC6

7FC7

OFFSET 3 - SGDMA_ADLO2

OFFSET 9 - SGDMA_CMD2

OFFSET 0 - SGDMA_START_FIFO3

OFFSET 1 - SGDMA_DONE_FIFO3

OFFSET 2 - SGDMA_ADHI3

7FCD

7FCE

7FCF

7FD0

7FD1

OFFSET 3 - SGDMA_ADLO3

OFFSET 9 - SGDMA_CMD3

7FD7

FIGURE 7 – SGDMA REGISTER SPACE

SMSC DS – USB97C102

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The SGDMA also contains a PIO engine that permits the MCU to access the ISA bus on a cycle stealing basis with

the DMA transfers (there is only one PIO engine).

Table 62 – SGDMA Packet Number Start FIFO Register

SGDMA_START_FIFOx [x=0..3]

(BASE+0 – RESET = 0x00)

SGDMA_START_FIFO

BIT

NAME

R/W

DESCRIPTION

[7:5]

[4:0]

Reserved

PCKTNUM

R/W

Reserved – Read back as 0

Packet Number to queue on

SGDMA_START_FIFOx [x=0..3].

Note 1:

Note 2:

This register is used when the channel is configured for an MMU memory operation.

When the channel is enabled (CHANNEL_ENABLE=1 in register SGDMA_CMDx [x=0..3]), only the SGDMA

can read from these registers. The MCU can only read from these registers when the channel is disabled

(CHANNEL_ENABLE=0 in register SGDMA_CMDx [x=0..3]), and not busy (DMA_BUSY=0 in register

SGDMA_STSx [x=0..3]). It is the MCU’s responsibility to ensure that this FIFO does not overflow.

Table 63 – SGDMA Packet Number Done FIFO Register

SGDMA_DONE_FIFOx [x=0..3]

(BASE+1 – RESET = 0x00)

SGDMA_DONE_FIFO

BIT

NAME

R/W

DESCRIPTION

[7:5]

[4:0]

Reserved

PCKTNO

R/W

Reserved – Read back as 0.

Packet Number on top of the

SGDMA_DONE_FIFOx [x=0..3].

Note 1:

Note 2:

This register is used when the channel is configured for an MMU memory operation.

The SGDMA puts the packet number on this FIFO when the DMA transfer is complete, or when the MCU

disables a channel that was enabled and busy (meaning a DMA transfer was in progress). When this

register is read, the FIFO is popped. It is the MCU’s responsibility to ensure that this FIFO does not

overflow.

Table 64 – SGDMA ISA Address High Byte Register

SGDMA_ADHIx [x=0..3]

(BASE+2 – RESET = 0x00)

SGDMA_ADHI

BIT

[7:0]

NAME

ADHIx [x=0..3]

R/W

DESCRIPTION

Contains the high byte of the ISA

Address to use.

Table 65 – SGDMA ISA Address Low Byte Register

SGDMA_ADLOx [x=0..3]

(BASE+3 – RESET = 0x00)

SGDMA_ADLO

DESCRIPTION

BIT

NAME

R/W

[7:0]

ADLOx [x=0..3]

R/W

Contains the low byte of the ISA Address

to use.

Note 1:

Note 2:

The SGDMA_ADHIx [x=0..3] and SGDMA_ADLOx [x=0..3] registers are used when the channel [0..3] is

configured for an ISA memory operation.

The MCU must not write to these registers unless the channel is disabled (CHANNEL_ENABLED=0 in

register SGDMA_CMDx [x=0..3]) and not busy (DMA_BUSY=0 in register SGDMA_STSx [x=0..3]).

Table 66 – SGDMA Transfer Size High Register

SGDMA_SIZEHIx [x=0..3]

(BASE+4 – RESET = 0x00)

SGDMA_SIZEHI

BIT

[7:0]

NAME

SIZEHIx

[x=0..3]

R/W

DESCRIPTION

Contains the high byte of the payload

data size (in bytes)

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Table 67 – SGDMA Transfer Size Low Register

SGDMA_SIZELOx [x=0..3]

(BASE+5 – RESET = 0x00)

SGDMA_SIZELO

DESCRIPTION

Contains the low byte of the payload

data size (in bytes).

BIT

[7:0]

NAME

SIZEHIx

[x=0..3]

R/W

Note 1:

Note 2:

The SGDMA_SIZEHIx [x=0..3] and SGDMA_SIZELOx [x=0..3] registers are used when the channel [0..3] is

configured for an ISA memory operation or for a MMU operation without a Packet Header.

The MCU must not write to these registers unless the channel is disabled (CHANNEL_ENABLED = 0 in

register SGDMA_CMDx [x=0..3]) and not busy ((DMA_BUSY=0 in register SGDMA_STSx [x=0..3]).

Table 68 – SGDMA Total Packets in Channel Register

SGDMA_TOTAL_PKTSx [x=0..3]

(BASE+6 – RESET = 0x00)

SGDMA_TOTAL_PKTS

BIT

[7:5]

[4:0]

NAME

Reserved

NUMPCKTS

R

DESCRIPTION

Reserved – Read back as 0

Number of packets currently in the

channel [0..3]

Note 1:

This register contains a count of the total number of packets in the corresponding SGDMA channel [0..3]. It

is incremented when the MCU puts a packet number into the SGDMA_START_FIFOx [x=0..3] and is

decremented when the MCU pops a packet from the SGDMA_DONE_FIFOx [x=0..3].

Table 69 – SGDMA Total Packets in the Done FIFO Register

SGDMA_DONE_PCKTSx [x=0..3]

(BASE+7 – RESET = 0x00)

SGDMA_DONE_PCKTS

BIT

[7:5]

[4:0]

NAME

Reserved

NUMPCKTS

R

DESCRIPTION

Reserved – Read back as 0

Number of packets in the

SGDMA_DONE_FIFOx [x=0..3]

Note 1:

This register contains a count of the total number of packets in the SGDMA_DONE_FIFOx [x=0..3]. It is

incremented when the SGDMA puts a packet number into the SGDMA_DONE_FIFOx [x=0..3] and is

decremented when the MCU pops a packet from the SGDMA_DONE_FIFOx [x=0..3].

Table 70 – SGDMA Status Register

SGDMA_STSx [x=0..3]

(BASE+8 – RESET = 0x00)

SGDMA_STS

BIT

7

6

NAME

DMA_BUSY

ISA_DONE

R

DESCRIPTION

Will be Set (1) while an SGDMA transfer is in progress

Will be Set (1) after an ISA memory – ISA device transfer is

completed. Resets to 0 when the channel is disabled

(CHANNEL_ENABLE=0 in register SGDMA_CMDx [x=0..3])

(Channel 0 only)

5

M2M_INCOMPLETE

R

Set(1) only when all of the following are true:

!"

Memory-to-Memory transfer

MMU memory is the target

SGDMA_START_FIFO1 is not empty

SGDMA_SIZEHI0 = 0

SGDMA_SIZELO0 = 0

SGDMA Channel 0 is enabled

SGDMA Channel 1 is enabled

Clear(0) when they are not all true

5

Reserved

R

Reserved – Read back as 0.

(for Channels 1, 2, and 3)

4

3

Reserved

DONE_FIFO_FULLx

[x=0..3]

DONE_FIFO_EMPTYx

[x=0..3]

R

Reserved – Read back as 0.

Set(1) when SGDMA_DONE_FIFOx [x=0..3] is full

Clear(0) when SGDMA_DONE_FIFOx [x=0..3] is not full

Set(1) when SGDMA_DONE_FIFOx[x=0..3] is empty

Clear(0) when SGDMA_DONE_FIFOx[x=0..3] is not empty

2

R

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SGDMA_STSx [x=0..3]

(BASE+8 – RESET = 0x00)

SGDMA_STS

DESCRIPTION

Set(1) when SGDMA_START_FIFOx [x=0..3] is full

Clear(0) when SGDMA_START_FIFOx [x=0..3] is not full

Set(1) when SGDMA_START_FIFOx [x=0..3] is empty

Clear(0) when SGDMA_START_FIFOx [x=0..3] is not not

empty

BIT

NAME

START_FIFO_FULLx

[x=0..3]

R

1

0

START_FIFO_EMPTY

x

R

[x=0..3]

Table 71 – SGDMA Command Register

SGDMA_CMDx [x=0..3]

(BASE+9 – RESET = 0x00)

SGDMA_CMD

BIT

[7:3]

2

NAME

Reserved

PCKT_HD

R

R/W

DESCRIPTION

Reserved – Read back as 0

Set(1) to indicate that a packet header is present. Clear(0) to

indicate that there is no packet header. Applies only if MEM_OP

is set(1).

1

MEM_OP

R/W

Set(1) to indicate a MMU memory operation. Clear(0) to indicate

an ISA memory operation.

!"

When clear(0), the packet size comes from the

SGDMA_SIZEHIx/LOx [x=0..3] registers, whose value is

decremented before being written into the 8237 count

register. The memory address comes from the

SGDMA_ADHIx/LOx [x=0..3] registers.

When set(1), and PCKT_HDR=0, the packet size comes

from the SGDMA_SIZEHIx/LOx [x=0..3] registers, whose

value is decremented before being written into the 8237

count register. The High byte of the address is based on the

packet number, and the low byte of the address is 0.

When set(1), and PCKT_HDR=1, the high byte of the

address is based on the packet number and the low byte of

the address is 8.

For a MemRd transfer, the packet size is read from the

packet header – this value represents the number of bytes

of payload data plus header, so this value minus 9 is written

into the 8237 counter register. If the packet size in the

header is 8 (indicating a zero-byte payload), no DMA

transfer will occur but the SGDMA will but the packet

number into the SGDMA_DONE_FIFOx [x=0..3].

For a MemWr transfer, the SGDMA_SIZEHIx/LOx [x=0..3]

registers contain the number of bytes of payload data, so

this value is decremented before being written into the 8237

count register, and this value plus 8 is written into the packet

memory at an offset of 6.

0

CHANNEL

_ENABLE

R/W

Set(1) to enabled the channel. Clear(0) to disable the channel. If

this bit is cleared during a SGDMA cycle (before TC), then:

!"

If MEM_OP=1, the packet number is put into the

SGDMA_DONE_FIFOx [x=0..3] and the SGDMA returns to

idle, ready for another cycle.

!"

If MEM_OP=0, the SGDMA returns to idle and is ready for

another cycle.

If a memory-to-memory transfer, the packet number for the

MMU channel is put into the SGDMA_DONE_FIFO0x [0 or

1], but none of the updates to the address or size register

occur, and the SGDMA returns to idle and is ready for

another cycle.

Note 1:

The PKT_HDR and MEM_OP bits must not be changed unless the channel is disabled

(CHANNEL_ENABLRE=0 in register SGDMA_CMDx [x=0..3]) and not busy (DMA_BUSY=0 in

register SGDMA_STSx [x=0..3]).

SMSC DS – USB97C102

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Note 2:

Memory-to-memory transfer is a special case and is handled as follows. A memory-to-memory

transfer supports transfers only between MMU memory and ISA memory, in either direction. The

source must be Channel 0, the destination must be Channel 1.

!" MMU memory to ISA memory transfers

Initially, the MCU performs the following:

1) Clears the SGDMA_SIZEHI0/LO0 registers.

2) Sets the SGDMA_ADHI1/LO1 registers to the ISA Address.

After each TC, the SGDMA will add the size of the completed transfer to the SGDMA_ADHI1/LO1 registers.

If PKT_HDR=1 in the SGDMA_CMD0 register, the transfer size comes from the MMU packet header. If

PKT_HDR=0 in the SGDMA_CMD0 register, the transfer size is the value in SGDMA_SIZEHI1/LO1 registers.

!" ISA memory to MMU memory transfers

Initially, the MCU performs the following:

1) Sets the SGDMA_ADHI0/LO0 to the ISA Address.

2) Sets the SGDMA_SIZEHI0/LO0 to the ISA buffer size.

3) Sets the SGDMA_SIZEHI1/LO1 to the session transfer size.

After each TC, the SGDMA will add the session transfer size to the SGDMA_ADHI0/LO0 registers and subtract

the session transfer size from the SGDMA_SIZEHI0/LO0 registers.

The actual transfer size is the lesser of the values in the SGDMA_SIZEHI1/ LO1 and the SGDMA_SIZEHI0/LO0

registers.

If PKT_HDR=1 in register SGDMA_CMD1, then the actual transfer size plus 8 will be written to the packet

memory at an offset of 6.

When the SGDMA_SIZEHI0/LO0 registers reach a value of 0, the ISA buffer has been completely transferred. If

the SGDMA_START_FIFO1 is not yet empty when the ISA buffer has been completely transferred, the

M2M_INCOMPLETE bit in the SGDMA_STS0 register will be set.

!"

During a memory-to-memory transfer, if either Channel 0 or Channel 1 is Disabled during the SGDMA cycle,

then the packet number for the MMU channel is put into the SGDMA_DONE_FIFOxx [0 or 1]. However, none of

the updates to the address or size registers occur, and the SGDMA returns to idle and is ready for another cycle.

For memory-to-memory transfers, the SGDMA_ADHI0, SGDMA_ADLO0, SGDMA_ADHI1, SGDMA_ADLO1,

SGDMA_SIZEHI0, and SGDMA_SIZELO0 must not be read by the MCU until both channels 0 and 1 are not

Busy (DMA_BUSY=0 in SGDMA_STS0 and SGDMA_STS1).

PIO REGISTER DESCRIPTION

Table 72 – Upper Byte of the PIO ISA Address

PIO_ADHI

(0x7FD8 – RESET = 0x00)

PIO_ADHI

DESCRIPTION

Reserved – Read back as 0

The upper 4 bits of the ISA address

BIT

[7:4]

[3:0]

NAME

Reserved

PIOADDRHI

R/W

Table 73 –Middle Byte of the PIO ISA Address

PIO_ADMID

(0x7FD9 – RESET = 0x00)

PIO_ADMID

DESCRIPTION

BIT

NAME

R/W

[7:0]

PIOADDRMID

R/W

The middle byte of the ISA address

SMSC DS – USB97C102

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Table 74 –Low Byte of the PIO ISA Address

PIO_ADLO

(0x7FDA – RESET = 0x00)

PIO_ADLO

DESCRIPTION

The low byte of the ISA address

BIT

[7:0]

NAME

PIOADDRLO

R/W

Note 1:

Note 2:

The MCU must not write these registers until PIO_BUSY=0 in the PIO_CSR register.

PIO Read transfers and the first transfer of PIO Read Multiple transfers are initiated by writing to

the PIO_ADLO register.

Table 75 – PIO Data Register

PIO_DATA

(0x7FDB – RESET = 0x00)

PIO_DATA

BIT

[7:0]

NAME

PIODATA

R/W

DESCRIPTION

The Data for the PIO transfer

Note 1:

Note 2:

The MCU must not read this register until PIO_BUSY=0 in the PIO_CSR register.

PIO Write transfers are initiated by writing to the PIO_DATA register.

PIO Read Multiple transfers (except for the first transfer) are initiated by reading the PIO_DATA

register

Table 76 – PIO Command/Status Register

PIO_CSR

(0x7FDC – RESET = 0x00)

PIO_CSR

BIT

7

6

NAME

PIO_BUSY

Reserved

R/W

R

DESCRIPTION

Will be set(1) when a PIO transfer is in progress

R/W Reserved – Read back as 0

[5:3]

STROBEWIDTH

R/W Programs the width of the RD/WR strobes (nIOR, nIOW,

nMEMR, nMEMW)

5

0

1

4

0

1

0

1

3

0

1

0

1

0

1

0

1

Strobe Width

Invalid

3 DMACLKs

4 DMACLKs

5 DMACLKs

6 DMACLKs

Invalid

For ISA Read accesses, the data must be valid one

DMACLK cycle before the trailing edge of the read strobe.

R/W Set(1) to indicate an ISA memory transfer.

Clear(0)to indicate an ISA I/O transfer.

2

MEMORY

1

0

1

0

1

0

1

Transfer Type

Disable

Write

Read

[1:0]

TRANSFERTYPE

R/W

Read Multiple

Note 1:

Note 2:

The STROBEWIDTH and MEMORY bits of the PIO_CSR register must not be changed unless

TRANSFERTYPE=00 (disabled) and PIO_BUSY=0 in the PIO_CSR register.

The Ready input can be used to stretch the width of the RD/WR strobes generated by the PIO.

When the READY input is high, the strobes will be as programmed in the PIO_CSR register.

!" PIO Writes:

In order to affect the nIOW or nMEMW strobes, the READY signal must go low at least 2

DMACLK periods before the scheduled rising edge of the strobe, and then the strobe will remain low

until 3 DMACLK periods after READY goes high. PIO Reads: In order to affect the nIOR or nMEMW

strobes, the READY signal must go low at least 3 DMACLK periods before the scheduled rising edge of

the strobe, and then the strobe will remain low for 5 DMACLK periods after READY goes high. The read

Data must be valid within 4 DMACLKS after READY goes high so that the Data is available at least 1

DMACLK period before the rising edge of the read strobe.

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MEMORY MANAGEMENT UNIT (MMU) REGISTER DESCRIPTION

MMU Interface Registers

Table 77 - MMU Data Window Register

MMU_DATA

(0x6000)

NAME

MMU DATA WINDOW REGISTER

DESCRIPTION

BIT

R/W

[7:0]

[D7:D0]

R/W

Data Packet Window.

When RCV in the PRH register = '1', this is the byte pointed to by

the packet number on the top of the RXFIFO, and the packet

offset of PRH:PRL.

When RCV in the PRH register = '0', this is the byte pointed to by

the packet number in the PNR register, and the packet offset of

PRH:PRL.

Notes:

1) The Read FIFO may take at most 1.218µs after the PNH is written to present valid data.

2) The Write FIFO may take at most 2.520µs after writing the last byte of data to the FIFO to finish writing that data

to the buffer.

3) The worst case sequential access times to the FIFOs while the 8237 is simultaneously arbitrating for the MMU,

and a USB packet is currently being transferred, is 588ns.

a) (READ) Therefore, after changing the PRH register, the 8051 should wait at least 2 instruction cycles (at

12MHz) before reading from this register. After waiting, the 8051, in auto-increment mode (PRH bit 6=1),

can read a byte every cycle (at up to 16MHz).

b) (WRITE) The data register mode can be switched to write at any time, and data can be written immediately

on every instruction cycle. After writing data, the 8051 should wait at least 3 instruction cycles (at 12MHz)

before changing the PNR or PRH :PRL registers for a Read . Again, after waiting 1.218µs, the 8051 can

read a byte every instruction cycle.

Each endpoint will have a three bit up/dn counter which will maintain the number of packets queued for transmit at

that endpoint. These counters are readable through these registers (there are sixteen – from 7F40 to 7F4F).

Table 78 – Tx FIFO Counter

TX_FIFOx

(0x7F40-0x7F4F)

Tx FIFO Counter

BIT

[7:3]

[2:0]

NAME

Reserved

TxFIFO Count

R/W

R

DESCRIPTION

Reserved

This field will contain the number of packets that are queued for

transmit at each endpoint. It is incremented when there is a push

on the Tx FIFO of the corresponding endpoint, and it is

decremented when there is a pop on the Tx FIFO of the

corresponding endpoints.

Table 79 - Pointer Register (Low)

PRL

(0x7F50)

NAME

A[7:0]

POINTER REGISTER (LOW)

DESCRIPTION

LSB of the (0-1277 Max) offset of the allocated Packet Pointed to

by PNR. The byte(s) pointed to by this register can be read and

written to by the MCU at 0x6000.

BIT

[7:0]

R/W

Note 1:

Note 2:

This register must be written before PRH .

The value read from this register is not necessarily what was last written to it, but actually the last address

used to access the buffer RAM.

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Table 80 - Pointer Register (High)

POINTER REGISTER (HIGH)

PRH

(0x7F51)

NAME

RCV

BIT

7

R/W

DESCRIPTION

0 = The packet at 0x6000 is the packet pointed to by the PNR

register.

1 = The packet available at 0x6000 is the packet pointed to by the

packet on the top of the RX Packet Number FIFO.

0 = Auto-increment is disabled

1 = Causes the PRH:PRL register to be automatically

incremented each time the 0x6000 data window is accessed.

Data register direction. This bit is required for the MMU/Arbiter to

provide a transparent interface to the buffer RAM for the MCU.

When first set, the MMU immediately fills the read FIFO. The

MCU must wait 2.5us (60 Arbiter clocks) after writing to the

MMU_DATA register before changing this bit from '0' to '1'.

6

5

AUTO_INCR

READ

R/W

0 = WRITE

1 = READ

[4:3]

[2:0]

Reserved

A[10:8]

R

R/W

Reserved

MSB of the (0-1277 Max) offset of the allocated Packet Pointed to

by PNR. The byte(s) pointed to by this register can be read and

written to by the MCU at 0x6000.

Note:

This register must be written after PRL for its value to take effect.

Table 81 - Transmit FIFO Select Register

MMUTX_SEL

(0x7F52)

TRANSMIT FIFO SELECT REGISTER

BIT

[7:4]

[3:0]

NAME

Reserved

EP[3:0]

R/W

R

R/W

DESCRIPTION

Reserved

This register selects which Endpoint Commands "110" and "111"

will affect when issued to the MMU

Note:

This register must be written before writing the “Enqueue Packet into Endpoint x” or the “Reset TX Endpoint x”

command to the MMUCR.

Table 82 - MMU Command Register

MMUCR

(0x7F53)

MMU COMMAND REGISTER

BIT

[7:5]

4

NAME

R/W

W

DESCRIPTION

MMUCR COMMAND SET

Reserved, writes are ignored and read return “0”

Number of 128 byte Pages. N[3..0]=0000 indicates 1 page, and

N[3..0]=1001 indicates 10 pages, or 1280 bytes.

MMU_CMD

Reserved

N[3:0]

[3:0]

W

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MMU COMMAND Bits 7, 6, and 5 Description:

000

001

NOOP, No operation

Allocate Memory : N3-0 specify how many 128 byte pages to allocate for that packet (up to 10 pages

allowed (1280 bytes) per packet.) Immediately generates a "FAILED" code at the ARR and the code is

cleared when complete. Can generate an ALLOC interrupt to MCU upon completion. When an allocation

request cannot be completed due to insufficient memory, the FAILED bit in the ARR will remain set. Any

subsequent release of memory pages (by either the MMUCR or the SIEDMA) will cause the MMUCR to

automatically continue the allocate command until all requested pages have been successfully allocated.

Software should never issue another allocate command until the previous allocate command has been

successfully completed.

010

011

RESET MMU : Frees all buffer RAM, clears interrupts, and resets queue pointers.

Remove Packet from top of RX Queue : To be issued after MCU has completed processing the packet

number at the RXFIFO.

100

Remove and Release Top of RXFIFO : Same as (011), but also frees all memory used by the packet. This

command is especially useful as a quick way to "ignore" bad packets.

101

110

Release specific Packet : Frees all pages allocated to the packet specified in the PNR.

Enqueue Packet into Endpoint x : Places the Packet number indicated by the PNR register in the transmit

queue of the endpoint pointed to by the MMUTX_SEL register. The MMUTX_SEL register must be written

before this command is issued.

111

Reset TX Endpoint x : Resets the TX FIFO holding the packet numbers awaiting transmission and the

TXFIFO_STAT bits of the endpoint pointed to by the MMUTX_SEL register. The MMUTX_SEL register must

be written before this command is issued. This command does not release any memory allocated to packets

that are dequeued.

Table 83 - Allocation Result Register

ARR

(0x7F54)

ALLOCATION RESULT REGISTER

BIT

7

[6:5]

[4:0]

NAME

R/W

R

DESCRIPTION

FAILED

Reserved

P[4:0]

Reserved

R

Returns Packet Number (0-31, 0x00-0x1F) from an allocation

command. This can be written directly into the PNR register

Table 84 - Packet Number Register

PACKET NUMBER REGISTER

DESCRIPTION

PNR (0x7F55)

NAME

Reserved

P[4:0]

BIT

[7:5

[4:0]

R/W

R

Reserved

R/W

Packet selector to access packet at 0x6000 buffer window

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MMU Free Pages Register

MMU Free Pages bits, and a global NAK_ALLRX (this can only NACK OUT and Bulk packets) control bit for the

firmware to view the real time status of the 32 page allocation bits. This allows the MCU to set NAK_ALLRX which

would inhibit the SIE from asking the SIEDMA to allocate packets, MCU checks how many pages are left, issue an

allocate if enough are free, and then release the SIE/SIEDMA. For the current design, the number of free pages

would range from 0x00 to 0x1F (32) pages left unallocated.

The indication of pages free may be invalid during an allocation or deallocation.

Table 85 - PAGES FREE IN THE MMU

PAGS_FREE

(0x7F56 - RESET=0x20)

PAGES FREE IN THE MMU

BIT

NAME

R/W

DESCRIPTION

7

NAK_ALLRX

R/W

NACK All received packets

0 = Normal Operation (Default)

1 = NACK all RX packets

6

Reserved

0

Reserved

[5:0]

PAGS_FREE

R

These bits indicate the number of free pages in the MMU.

Note 1:

Note 2:

Firmware can set a NAK_ALLRX bit to inhibit the SIE from asking the SIEDMA to allocate any pages while

the MCU is observing the page free bits.

This register is used to indicate how many pages are left in many situations, including after an RX_OVRN,

before a multi-packet allocation, etc. This eliminates the possibility of a failed allocation, simplifying software

without adding additional hardware to abort an allocation.

32 BYTE DEEP TX COMPLETION FIFO REGISTER

Table 86 - TX Management Register 2

TX_MGMT

(0x7F57 - RESET=0x80)

TX Management Register

DESCRIPTION

BIT

NAME

R/W

7

CTX_EMTY

R

Completed TX FIFO empty status

0 = Has one or more TX packet

1 = Empty

6

CTX_FULL

R

Completed TX FIFO full status

0 = Not FULL

1 = FULL

5

[4:0]

Reserved

CTX_FIFO

R

Reserved

This is the data port for the 32 deep TX completion FIFO. This

FIFO is automatically updated by hardware with the last

successfully completed transmit packet. It is the responsibility of

software to ensure that this FIFO never overflows and/or

becomes full.

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Table 87 - Receive Packet Number FIFO Register

RXFIFO

(0x7F58)

NAME

NEXT RX PACKET NUMBER FIFO REGISTER

DESCRIPTION

1 = No pending packets from the host to be processed

1 = The SIEDMA will not accept packets from the host (via RX

Overflow)

BIT

7

6

R/W

R

RXFIFO_EMPTY

RXFIFO_FULL

5

[4:0]

Reserved

P[4:0]

R

Reserved

Packet Number

When a packet has been received, and the 8-byte header has

been written by the SIEDMA, the associated Packet Number is

placed in this FIFO.

A "complete" reception requires that the 8 byte status header is correctly written into the packet buffer, with the

correct data, and moved into the RX Packet Number FIFO. A "successful" reception requires that the CRC and PID

check bits of a "complete" reception are good. The hardware queues only "complete" packets. Firmware must

determine if "complete" packets were "successful". Corrupted token packets causes the complete data payload to be

ignored.

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Tx FIFO POP Register

This register is used to help software manage TX Queues.

This will provide a method to handle a

CLEAR_FEATURE:ENDPOINT_STALL condition gracefully. When read, this register will return the Packet Number

of the next packet waiting on the TX queue pointed to by MMUTX_SEL register, AND it will pop that Packet Number

off of the selected TX FIFO.

Table 88 - POP TX FIFO

POP_TX

(0x7F59 – RESET=0x80)

POP TX FIFO

BIT

NAME

R/W

DESCRIPTION

7

POPTX_STAT

R

POP TX FIFO empty status

0 = Has one or more TX packet

1 = Empty

[6:5]

[4:0]

Reserved

POP_TX

R

Reserved

This 5 bit value is the packet number or handle that is at the top of

the TX FIFO pointer to by MMUTX_SEL. The TX FIFO is popped

when this register is read.

Note:

It is the software's responsibility to ensure that the appropriate TX EP is disabled during this operation, and to

issue a de-allocate command if desired.

Table 89 - Transmit FIFO Status Register A

TXSTAT_A

(0x7F60 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER A

BIT

NAME

R/W

DESCRIPTION

7

EP3TX_EMPTY

R

Endpoint 3 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

6

5

EP3TX_FULL

EP2TX_EMPTY

R

Endpoint 2 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

4

3

EP2TX_FULL

EP1TX_EMPTY

R

Endpoint 1 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

2

1

EP1TX_FULL

EP0TX_EMPTY

R

Endpoint 0 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

0

EP0TX_FULL

R

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Table 90 - Transmit FIFO Status Register B

STAT_B

(0x7F61 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER B

DESCRIPTION

BIT

NAME

R/W

7

EP7TX_EMPTY

R

Endpoint 7 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

6

5

EP7TX_FULL

EP6TX_EMPTY

R

Endpoint 6 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

4

3

EP6TX_FULL

EP5TX_EMPTY

R

Endpoint 5 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

2

1

EP5TX_FULL

EP4TX_EMPTY

R

Endpoint 4 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

0

EP4TX_FULL

R

Table 91 - Transmit FIFO Status Register C

TXSTAT_C

(0x7F62 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER C

DESCRIPTION

BIT

NAME

R/W

7

EP11TX_EMPTY

R

Endpoint 11 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

6

5

EP11TX_FULL

EP10TX_EMPTY

R

Endpoint 10 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

4

3

EP10TX_FULL

EP9TX_EMPTY

R

Endpoint 9 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

2

1

EP9TX_FULL

EP8TX_EMPTY

R

Endpoint 8 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

0

EP8TX_FULL

R

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Table 92 - Transmit FIFO Status Register D

TXSTAT_D

(0x7F63 - RESET=0x55)

TRANSMIT FIFO STATUS REGISTER D

DESCRIPTION

BIT

NAME

R/W

7

EP15TX_EMPTY

R

Endpoint 15 Transmit Packet FIFO Status

Bits [7:6]='11' Invalid

Bits [7:6]='10' Empty (No Packets queued)

Bits [7:6]='01' Full (5 Packets queued)

Bits [7:6]='00' Partially Full (1, 2, 3, or 4 Packets queued)

6

5

EP15TX_FULL

EP14TX_EMPTY

R

Endpoint 14 Transmit Packet FIFO Status

Bits [5:4]='11' Invalid

Bits [5:4]='10' Empty (No Packets queued)

Bits [5:4]='01' Full (5 Packets queued)

Bits [5:4]='00' Partially Full (1, 2, 3, or 4 Packets queued)

4

3

EP14TX_FULL

EP13TX_EMPTY

R

Endpoint 13 Transmit Packet FIFO Status

Bits [3:2]='11' Invalid

Bits [3:2]='10' Empty (No Packets queued)

Bits [3:2]='01' Full (5 Packets queued)

Bits [3:2]='00' Partially Full (1, 2, 3, or 4 Packets queued)

2

1

EP13TX_FULL

EP12TX_EMPTY

R

Endpoint 12 Transmit Packet FIFO Status

Bits [1:0]='11' Invalid

Bits [1:0]='10' Empty (No Packets queued)

Bits [1:0]='01' Full (5 Packets queued)

Bits [1:0]='00' Partially Full (1, 2, 3, or 4 Packets queued)

0

EP12TX_FULL

R

Table 93 - TX Management Register 1

TX_MGMT

(0x7F67 - RESET=0x00)

TX Management Register 1

DESCRIPTION

BIT

[7:1]

0

NAME

R/W

Reserved

MEM_DALL

R

R/W

Reserved

Memory deallocate Mode

0 = Auto

1 = Manual deallocation, but the TX FIFO Pop is still

automatic.

This control bit selects between Auto and Manual memory

pages deallocation. This bit should be statically set at the

start of operation, and can not be changed during or if

about to transmit. This bit defaults to “0” for normal

operation. When set, the MCU handles freeing up the

memory pages.

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SERIAL INTERFACE ENGINE (SIE) REGISTER DESCRIPTION

Packet Header Definition

The following header contains information to determine endpoint, status, length of the received packet, and the

payload “received data”.

Table 94 - Packet Header Definition

OFFSET

<n + 7

MSB 7

6

5

4

3

2

1

LSB 0

Payload Data Byte n-1 (n is the payload data size, which is Byte Count -8)

- For 0 Length Packet, Byte Count = 0x008

- For 1 byte Packet, Byte Count = 0x009

- For any Packet, (Byte Count-1) points to last byte of payload data

Payload Data Byte 0

0x008

0x007

0x006

0x005

0x004

0x003

0x002

0x001

0x000

0

BYTE COUNT[10..8]

BYTE COUNT[7..0]

EXTENDED FRAME COUNT[15..11]

FRAME COUNT[7..0]

FRAME COUNT[10..8]

RESERVED

0

TMP_ADDRESS[6..0]

0

Bad_CR

C

0

PACKET ID[3..0]

ENDPOINT[3..0]

Last_TOG Bad_TOG

Packet Description:

1) Offset 0 to 7 is the packet header.

a) Offset 0x000 to 0x005 is generated by the SIE.

iii) Offset 0x000 bit bit 5 - Bad_TOG- This bit is set when the SIE receives an unexpected toggle. This is

not necessarily an error condition, This bit could indicate a condition when the return handshake packet

is lost. Note that this bit is not set for isochronous transfers.

LAST PACKET TOGGLE

CURRENT PACKET

VALUE

TOGGLE VALUE

“BAD TOG” BIT

0

1

0

1

0

1

0

1

iii) Offset 0x000 bit Last_TOG is the last toggle bit received.

iii) Offset 0x000 bit Bad_CRC, is set when the SIE detects a bad CRC.

b) Offset 0x006 to 0x007 is generated by the SIEDMA.

2) Offset 8 to n+7 is the actual data received from the USB bus and stored in memory.

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SIE Interface Registers

The architecture of the USB97C102 is such that there are no data FIFO's associated with individual endpoints. The

MMU does not differentiate packets by endpoint number. The firmware must read the endpoint number from the packet

header to pass the packet on to the appropriate endpoint handler. This makes the chip dynamic and flexible in allocating

buffers to store any payload size from 0 to 1280 bytes. Each endpoint can be configured separately via the following

register.

Table 95 - Endpoint Control Registers

EP_CTRL[15..0]

(0x7F8F-0x7F80 - RESET=0x00)

ENDPOINT CONTROL REGISTERS

BIT

NAME

R/W

DESCRIPTION

7

TX_ISO

R/W

Bit 7 instructs the SIE how to handle handshakes for transmit

endpoints during "IN" transactions, and how the SIEDMA

engine should handle packet queue status after packet

transmission. When a TX endpoint is configured for isochronous

operation (Bit 7 = '1'), all packet transmissions are considered

successful and the SIEDMA must move the packet number into

the TX Completion FIFO. When the TX endpoint is non-

isochronous (Bit 7 = '0'), then the SIE must receive a valid ACK

handshake from the host before the packet is released. This

guarantees data integrity for non-isochronous transactions.

Successfully transmitted packets are automatically de-queued

and the packet is released.

0 = Non-Isochronous

1 = Isochronous

6

RX_ISO

R/W

Bit 6 instructs the SIE how to handle handshakes for receive

endpoints during "OUT" and "SETUP" transactions. Once a

packet matches the 7-bit Function Address, the SIE must begin

page allocation and generate a new packet in buffer RAM. The

MCU must check PID_Valid and CRC_Valid bits and dequeue

"bad" packets. The SIE will use bit 6 to inhibit handshakes when

enabled.

0 = Non-isochronous

1 = Isochronous

5,3

4,2

TX_CONT[1:0]

RX_CONT[1:0]

R/W

0,0= Endpoint is disabled, and does not send handshakes.

0,1= Send a STALL handshake for an IN transaction directed at

this EP.

1,0= Normal Operation. ACK or NAK is sent depending on

whether data is in the EPXs TX_QUEUE.

1,1= Send a NAK handshake for an IN transaction directed at

this EP, regardless of TX_QUEUE status. (Note 3)

0,0= Endpoint is disabled, and does not send handshakes.

0,1= Send a STALL handshake for an OUT transaction directed

at this EP.

1,0= Normal Operation. ACK or NAK is sent depending on

RX_OK status

1,1= Send a NAK handshake for an OUT transaction directed at

this EP (Note 1)

1

0

TX_TOGGLE

RX_TOGGLE

R/W

R

This bit is toggled after each successful transmission.

TX_TOGGLE can be reset or cleared by the MCU but the MCU

must insure that the endpoint is disabled before modifying them.

For isochronous transmits, this bit won’t be toggled by the

hardware.

This bit reflects the last DATA0/DATA1 toggle. For isochronous

receives, this bit will still hold the received toggle, but it won’t be

checked for Toggle error.

Note 1:

Note 2:

There is one Endpoint Control Register per virtual endpoint. When the SIE decodes a token, the endpoint

number is used to index which EP_CTRL register bits should be used to respond to the SIE and SIEDMA.

This register allows firmware to throttle back RX packets to any specific endpoint(s) until the firmware

decides congestion has subsided.

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Note 3:

Note 4:

If the firmware needs to STALL an endpoint, it should first be taken off-line by setting RX_CONT1=0, and

then RX_CON0=1.

This allows firmware to manage TX endpoint(s) and hold queued data until the firmware is ready, even if the

host is asking. This is not as critical as the RX version, but it may be required for Isochronous

synchronization, as well as STALL recovery.

Note 5:

These registers can be written to at any time but the SIE won’t be affected until after the current transaction

(on the particular endpoint) is completed. If a particular register is written several times during an SIE

transaction, only the last value written will take effect after the SIE transaction is complete.

Table 96 - LSB FRAME Count Register

FRAMEL

0x7F90 Reset 0x00

FRAME COUNT REGISTER (LOW)

BIT

NAME

R/W

DESCRIPTION

[7:0]

FRAME[7:0]

R

The 11 bit Frame Number from each SOF packet is loaded with the

RISING edge of EOT when SOF_TOKEN = '1' and ACK = '1'.

Note:

This register is always the last correctly received valid SOF Frame number. Garbled and invalid SOF tokens

do not alter this register. However, the LSB FRAME/MSB FRAME Count registers will be incremented by the

hardware when a missing SOF is detected, or when there is an error in frame number. A SOF is defined as

missing if it does not occur within a range of +/- 3 USBCLKs from the expected frame length. The expected

frame length is the previous interval between SOFs.

Table 97 - MSB FRAME Count Register

FRAMEH

0x7F91 Reset 0x00

FRAME COUNT REGISTER (HIGH)

BIT

NAME

R/W

DESCRIPTION

[7:3]

EXT_FR[15:11]

R

Extended Frame Count.

The extended count bits are loaded with the RISING edge of

EOT when SOF_TOKEN = '1' and ACK = '1'. The extended

Frame count bit must also be enabled (EN_EXTFRAME = '1' in

SIE_CONFIG).

[2:0]

FRAME[10:8]

R

Frame Number from each SOF packet is loaded with the

RISING edge of EOT when SOF_TOKEN = '1' and ACK = '1'.

Note:

This register is always the last correctly received valid SOF Frame number. Garbled and invalid SOF tokens

do not alter this register. However, the LSB FRAME/MSB FRAME Count registers will be incremented by the

hardware when a missing SOF is detected, or when there is an error in frame number. A SOF is defined as

missing if it does not occur within a range of +/- 3 USBCLKs from the expected frame length. The expected

frame length is the previous interval between SOFs.

Table 98 - Local Address Register

SIE_ADDR

(0x7F92 RESET=0x00)

LOCAL ADDRESS REGISTER

BIT

NAME

R/W

DESCRIPTION

7

RX_ALL

R/W

1 = Overrides the token address decoding of the SIE such

that no compare is done. Token CRC is also ignored when

RX_ALL=1. This bit forces all packets transmitted on the wire

to be received in the RX Packet Queue

[6:0]

ADDR[6:0]

R/W

This register is only written by the 8051. It is the SIE's local

address assigned during enumeration. This is the default

SIE address. ALL endpoints will send/receive on this

address. This address can be used for the HUB address.

Note:

When RX_ALL is enabled, software should not enable any TX endpoints as they will respond to any

Address with the same endpoint and possibly cause contention on the line. Software should also set each

RX endpoint RX_ISO bit to prevent handshakes from being sent.

SMSC DS – USB97C102

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Table 99 - Alternate Address 1 Register

ALT_ADDR1

(0x7F99 - RESET=0x00)

ALTERNATE SIE ADDRESS 1

DESCRIPTION

BIT

NAME

R/W

7

EN_ALTADDR1

R/W

Alternate address.

1 = Enabled, this bit allows Endpoints 4 through 7 to be

available to this address.

0 = Disabled, this register does not affect EP_OK generation.

6

5

4

3

2

1

0

ALT6

ALT5

ALT4

ALT3

ALT2

ALT1

ALT0

R/W

Alternate address bit 6

Alternate address bit 5

Alternate address bit 4

Alternate address bit 3

Alternate address bit 2

Alternate address bit 1

Alternate address bit 0

Note 1:

The Firmware (8051) must make sure that endpoint configurations do not overlap.

Table 100 - Alternate Address 2 Register

ALT_ADDR2

(0x7F9E – RESET=0x00)

ALTERNATE SIE ADDRESS 2

BIT

NAME

R/W

DESCRIPTION

7

EN_ALTADDR2

R/W

Alternate address 2.

1 = Enabled, this bit allows Endpoints 8 through 11 to be

available to this address.

0 = Disabled, this register does not affect EP_OK generation.

6

5

4

3

2

1

0

ALT6

ALT5

ALT4

ALT3

ALT2

ALT1

ALT0

R/W

Alternate address bit 6

Alternate address bit 5

Alternate address bit 4

Alternate address bit 3

Alternate address bit 2

Alternate address bit 1

Alternate address bit 0

Table 101 - Alternate Address 3 Register

ALT_ADDR3

(0x7F9F – RESET=0x00)

ALTERNATE SIE ADDRESS 3

DESCRIPTION

BIT

NAME

R/W

7

EN_ALTADDR 3

R/W

Alternate address 3.

1 = Enabled, this bit allows Endpoints 12 through 15 to be

available to this address.

0 = Disabled, this register does not affect EP_OK generation.

6

5

4

3

2

1

0

ALT6

ALT5

ALT4

ALT3

ALT2

ALT1

ALT0

R/W

Alternate address bit 6

Alternate address bit 5

Alternate address bit 4

Alternate address bit 3

Alternate address bit 2

Alternate address bit 1

Alternate address bit 0

SMSC DS – USB97C102

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ALTERNATE ADDRESS ENDPOINT MAPPING

This section will describe Endpoint Mapping relative to the Alternate Address registers defined above. Table 102 -

Mapping of External Endpoint Numbers to Internal Endpoint Numbers, on page 56 below, describes the Endpoint

mapping relative to the SIE address embedded in the USB packet. This table describes the mapping of a USB Packet

which is transmitted (USB IN Packet) or received (USB OUT packet) on the USB Bus and is destined for a particular

USB97C102 address. Remember, that the USB97C102 has 4 possible address filters.

The translation is the conversion of the Endpoint Number. The Endpoint Number for OUT packets destined for a

particular address, the Endpoint Number is translated accordingly as defined in Table 102.

Example #1, an OUT packet:

!"

If a packet on the USB wire, which contains an address destined for the USB97C102 with a value that matches

Alternate Address #2 (ALT_ADDR2 Register- 0x7F9E) and its endpoint number = 0 and is received, then the

packet header in the MMU contains the Alternate Address #2 address value and an Endpoint Number = 8. The

External Endpoint Number “0” is converted to internal endpoint number “8” for packets directed to alternate

address #2.

Example #2, a IN packet:

!"

When the SMSC 97C102 MCU (8051) is building a packet to send to the host, the packet is enqueued onto one

of the 16 Transmit FIFO’s which maps to each Endpoint. In other words, each Endpoint has its own transmit

FIFO. When an IN token is received from the host, that is addressed to alternate address #2 and endpoint 0,

then the SIE pops a packet off of the Tx FIFO for endpoint 8.

As can be seen, endpoint translation is performed for outgoing as well as incoming packets as described in Table

102. Please refer to the SMSC USB97C102 Programmers Reference Guide for additional details.

Multiple Endpoint Mapping

When the SMSC USB97C102 Firmware Developer uses the Alternate Address registers to implement specific device

implementations, internal Endpoints are mapped multiple times relative to the External Endpoint.

Example:

If a packet is received, that is addressed to alternate address #3, then external endpoint numbers 1, 5, 9 and 13 are

all converted to internal endpoint number 13.

Table 102 - Mapping of External Endpoint Numbers to Internal Endpoint Numbers

EXTERNAL EP

(ON THE USB

WIRE)

INTERNAL EP (IN PACKET HEADER)

SIE Addr

EP 0

EP 1

EP 2

EP 3

EP 4

EP 5

EP 6

EP 7

Alt Addr 1

EP 4

EP 5

EP 6

EP 7

EP 4

EP 5

EP 6

EP 7

EP 4

EP 5

EP 6

EP 7

EP 4

EP 5

EP 6

EP 7

Alt Addr 2

EP 8

Alt Addr 3

EP 12

EP 13

EP 14

EP 15

EP 12

EP 13

EP 14

EP 15

EP 12

EP 13

EP 14

EP 15

EP 12

EP 13

EP 14

EP 15

EP 0

EP 1

EP 2

EP 3

EP 4

EP 5

EP 6

EP 7

EP 8

EP 9

EP 10

EP 11

EP 8

EP 9

EP 10

EP 11

EP 8

EP 9

EP 10

EP 11

EP 12

EP 13

EP 14

EP 15

EP 10

EP 11

EP 12

EP 13

EP 14

EP 15

EP 10

EP 11

EP 8

EP 9

EP 10

EP 11

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Table 103 - SIE Status Register

SIE STATUS REGISTER

SIE_STAT

(0x7F93 - RESET=0x03)

NAME

BIT

R/W

DESCRIPTION

7

ERR

R

Indicates that an error occurred during the last USB

transaction. Considered valid on the rising edge of EOT

Indicate that the last USB transaction ended because of an

inter-packet time out condition (i.e.:>16 bit times).

Considered valid on the rising edge of EOT.

6

TIMEOUT

R

5

4

SETUP_TOKEN

SOF_TOKEN

R

Indicates that the token received was a SETUP token.

Indicates that the SOF PID has been received. Considered

valid when EOT is '0'.

3

2

1

PRE_TOKEN

ACK

R

Indicates that the SIE detected a PRE (preamble) packet on

the USB bus. The signal is asserted when the SIE has seen

a valid SYNC followed by a valid PRE PID.

Indicates that the last USB transaction was completed

without error or time-out. Considered valid on the rising

edge of EOT.

When active '1', it indicates that the USB line is being reset.

This signal is asserted when the SIE detects a string of

single – ended 0's on the bus for a long time.

[During USB_RESET, this bit is set(1). When the firmware

sends a system reset, this bit is cleared(0)]

USB_RESET

0

EOT

R

End - of - Transaction. On transition to a '1', it indicates the

end of transaction. On transition to a '0' it indicates the

beginning of a new transaction.

Note:

This read only register reflects the status signals from the SIE state machine. This register can be polled for

test purposes, or by error handling routines for recovery.

Table 104 - SIE Control Register 1

SIE_CTRL1

(0x7F94 - RESET=0x00)

SIE CONTROL REGISTER 1

BIT

NAME

R/W

DESCRIPTION

7

SIEDMA_DISABLE

R/W

0 = Normal operation

1 = Inhibits SIEDMA operation to facilitate MCU override

Forces SIE to send Acknowledge during receive. Must be

'0' for normal operation.

6

5

FORCE_RXOK

FORCE_TTAG

R/W

0 = Normal operation

1 = Signals that the next byte written to the SIE TX_FIFO is

the last payload byte.

4

FORCE_RXOVFLO

R/W

0 = Normal operation.

1 = Forces the SIE to generate RXOVFLO and clear the

SIE RX FIFO.

3

2

FORCE_TXABORT

FORCE_EOT

R/W

0 = Normal operation

1 = Forces a bit-stuff error at the host

0 = Normal operation

1 = Forces an End-of-Transaction for the SIE

Status of RTAG signal from SIE RX FIFO

Status of TXOK from SIE

1

0

RTAG_IN

TXOK_IN

R

Note:

Bits 7:2 must be set to “0” for normal operation. Altering these bits will cause an abnormal USB behavior.

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Table 105 - SIE Configuration Register.

SIE_CONFIG

(0x7F98 - RESET=0x40)

NAME

SIE CONFIGURATION REGISTER

BIT

R/W

DESCRIPTION

7

FSEN

R/W

This bit indicates that the USB97c102 supports 12Mbps USB

must

data rates. This bit

be set to a one ‘1’ for normal

operation.

6

5

4

RST_SIE

RST_FRAME

EN_EXTFRAME

R/W

1 = Resets the SIE

1 = Clears FRAMEL and Bit 0 through 2 of FRAMEH

Extended Frame Count Enable. Expands the Frame count

from 11 bits to 16 bits for 8051 use.

0 = Bits 7-3 of FRAMEH are driven to 0.

1 = Bits 7-3 of FRAMEH count 1-0 transitions of bit 2 in

FRAMEH.

3

SIE_SUSPEND

R/W

1 = Forces the SIE into USB Suspend Mode. The MCU must

determine that Suspend must be entered.

2

1

SIE_RESUME

USB_RESUME

R/W

R

1 = Forces the SIE to transmit Resume signaling on the line.

1 = Indicates Resume signaling has been detected on the line

while in the Suspend State. This signal causes a Resume

Power Management interrupt).

0

USB_RESET

R

1 = Indicates that the USB line is being reset. Asserted when

SE0 is present on the bus for 32 or more 12 Mbps bit times.

This causes a USB_RESET Power management interrupt.

Table 106 - SIE Control Register 2

SIE_CTRL 2

(0x7FA9 – RESET=0x00)

NAME

SIE CONTROL REGISTER 2

DESCRIPTION

Reserved – This bit should always be cleared (0)

BIT

7

R/W

Reserved

6

5

4

3

Reserved

R/W Reserved – This bit should always be cleared (0)

2

SET_BUSY_ON_SETU R/W When set (1), a setup pckt rcvd on a control endpoint will

P

set that endpoint to busy in any direction it was not

disabled. When clear (0), a setup pckt will have no effect

on the endpoint’s control condition.

[1:0]

ISO_LIMIT

R/W ISO_Limit – Defines the maximum size of an isochronous

packet

1

0

1

0

1

PAYLOAD SIZE

1023 byte payload

248 byte payload total less 8 byte header = 240

byte Data payload

504 byte payload total less 8 byte header = 496

byte Data payload

0

1

248 byte payload total less 8 byte header = 240

byte Data payload

In conjunction with the Endpoint Control Registers defined above, the Endpoint Command Register allows the

dynamic modification and configuration of specific endpoints. This register which is new to the SMSC Family of USB

devices, allows the MCU to write each individual bit field within the existing register Endpoint set without having to do

read / modify / write operations. The Firmware can jam this register with a full constant, or could OR-in an EP

number.

SMSC DS – USB97C102

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This register allows the individual setting and clearing of the bits in the EP_CTRL registers.

Table 107 - Endpoint Command Register

EP_COMM

(0x7FAA- RESET=0x00)

ENDPOINT Command Register

BIT

NAME

R/W

DESCRIPTION

This bit, when set (1) will allow the command specified in bits 6-4

to control the TX endpoint. When this bit is cleared (0), the

command control the RX endpoint. In other words, if set (1), the

command will affect TX_ISO, TX_ENABLE, STALL_TXEP, and

TX_TOGGLE (defined in EPCTRL). If clear (0), the command will

affect RX_ISO, RX_ENABLE, STALL_RXEP, and RX_TOGGLE

(also defined in EPCTRL).

7

TX/RX

R/W

[6:4]

COMMAND

R/W

6

5

4

COMMAND BITS

0

Endpoint is disabled, and does not send handshakes.

0

1

Send a STALL handshake for an IN and/or OUT

transaction directed at this EP.

0

1

0

Normal Operation. ACK or NAK is sent depending on

whether data is in the EPXs TX_QUEUE or conversely for

EPX’s receive transactions.

0

1

Send a NAK handshake for an IN and/or OUT transaction

directed at this EP, regardless of TX_QUEUE status.

Clear Tx / Rx Toggle bit

1

0

1

0

1

0

1

Set Tx / Rx Toggle bit

Clear Tx / Rx ISO bit

Set Tx / Rx ISO bit

EP_COMM

(0x7FAA- RESET=0x00)

ENDPOINT Command Register

DESCRIPTION

BIT

NAME

EP_Select

R/W

[3:0]

3

0

1

2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

ENDPOINT SELECT

Endpoint 0

Endpoint 1

Endpoint 2

Endpoint 3

Endpoint 4

Endpoint 5

Endpoint 6

Endpoint 7

Endpoint 8

Endpoint 9

Endpoint 10

Endpoint 11

Endpoint 12

Endpoint 13

Endpoint 14

Endpoint 15

Section 8.4.5.4 of the USB Spec V1.1 states that “If a non-control endpoint receives a SETUP PID, it must ignore the

transaction and return no response.” In order for the hardware to do this correctly, it needs to know which endpoints

are non-control endpoints.

Each bit of the NonControl Endpoint registers will correspond to the associated Endpoint. Bits 0-7 of the NonControl

Endpoint 1 register will correspond to Endpoints 7-15. Bits 0-7 of the NonControl Endpoint 2 will correspond to

SMSC DS – USB97C102

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Endpoints 0-7. The MCU will write these registers, and set the corresponding bit=1 for each endpoint that is a non-

control endpoint. The hardware will not respond to a Setup PID for any endpoint whose corresponding bit is set (1).

Table 108 - NonControl Endpoint Register 1 (high endpoints)

NONCTRL_EP1

(0x7FAB – RESET=0x00)

NONCONTROL ENDPOINT REGISTER 1

BIT

NAME

R/W

DESCRIPTION

7

EP15

R/W When this bit is set (1), the Endpoint will not respond to a Setup PID.

When this bit is cleared (0), the Endpoint will respond to a setup PID