USB2533-1080AEN-TR [SMSC]
USB 2.0 Hi-Speed 3-Port Hub Controller; USB 2.0高速3端口集线器控制器
| 型号： | USB2533-1080AEN-TR |
| 厂家： | 
SMSC CORPORATION |
| 描述： | USB 2.0 Hi-Speed 3-Port Hub Controller |
| 文件： | 总61页 (文件大小：891K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
USB2533
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
PRODUCT FEATURES
Highlights
Additional Features
Hub Controller IC with 3 downstream ports
MultiTRAKTM
—
Dedicated Transaction Translator per port
USB-IF Battery Charger revision 1.2 support on up &
downstream ports (DCP, CDP, SDP)
PortMap
®
—
Configurable port mapping and disable sequencing
Battery charging support for Apple devices
PortSwap
FlexConnect: Downstream port 1 able to swap with
upstream port, allowing master capable devices to
control other devices on the hub
USB to I2CTM bridge endpoint support
—
Configurable differential intra-pair signal swapping
PHYBoostTM
—
Programmable USB transceiver drive strength for
recovering signal integrity
VariSenseTM
USB Link Power Management (LPM) support
SUSPEND pin for remote wakeup indication to host
Vendor Specific Messaging (VSM) support
—
Programmable USB receiver sensitivity
Low power operation
Enhanced OEM configuration options available
through a single serial I2CTM EEPROM, OTP, or
SMBus Slave Port
Full Power Management with individual or ganged
power control of each downstream port
Built-in Self-Powered or Bus-Powered internal default
settings provide flexibility in the quantity of USB
expansion ports utilized without redesign
36-pin (6x6mm) SQFN, RoHS compliant package
Footprint compatible with USB2513B
Supports “Quad Page” configuration OTP flash
Target Applications
—
Four consecutive 200 byte configuration pages
Fully integrated USB termination and Pull-up/Pull-
down resistors
LCD monitors and TVs
Multi-function USB peripherals
PC mother boards
On-chip Power On Reset (POR)
Internal 3.3V and 1.2V voltage regulators
Set-top boxes, DVD players, DVR/PVR
Printers and scanners
PC media drive bay
On Board 24MHz Crystal Driver, Resonator, or
External 24MHz clock input
Environmental
Portable hub boxes
—
Commercial temperature range support (0ºC to 70ºC)
—
Industrial temperature range support (-40ºC to 85ºC)
Mobile PC docking
Embedded systems
SMSC USB2533
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Order Number(s):
ORDER NUMBER
TEMPERATURE RANGE
0°C to +70°C
PACKAGE TYPE
36-pin SQFN
USB2533-1080AEN
USB2533-1080AEN-TR
USB2533i-1080AEN
USB2533i-1080AENTR
36-pin SQFN
(Tape & Reel)
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
36-pin SQFN
36-pin SQFN
(Tape & Reel)
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
The table above represents valid part numbers at the time of printing and may not represent parts that are currently
available. For the latest list of valid ordering numbers for this product, please contact the nearest sales office.
Copyright © 2013 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.0 (06-17-13)
2
SMSC USB2533
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table of Contents
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 Acronyms and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 Acronyms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 Reference Documents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Chapter 3 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.3 Buffer Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Chapter 4 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 Integrated Power Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Power Connection Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Chapter 5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1 Boot Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.1 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.2 Hardware Initialization Stage (HW_INIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.3 Software Initialization Stage (SW_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.4 SOC Configuration Stage (SOC_CFG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.5 Configuration Stage (CONFIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.6 Battery Charger Detection Stage (CHGDET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.7 Hub Connect Stage (Hub.Connect). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.8 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Chapter 6 Device Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 Configuration Method Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2 Customer Accessible Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.2.1 USB Accessible Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.2.2 SMBus Accessible Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3 Device Configuration Straps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.1 Non-Removable Device (NON_REM[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.2 Configuration Select (CFG_SEL[1:0]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.3 Downstream Battery Charging Enable (BC_EN[3:1]) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.4 Port Disable (PRT_DIS_Mx/PRT_DIS_Px) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Chapter 7 Device Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 I2C Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.1 I2C Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1.2 Pull-Up Resistors for I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2 SMBus Slave Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.1 SMBus Run Time Accessible Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.2.2 Run Time SMBus Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Chapter 8 Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
SMSC USB2533
3
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
8.1 Battery Charger Detection & Charging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1.1 Upstream Battery Charger Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.1.2 Downstream Battery Charging. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
8.2 Flex Connect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.2.1 Port Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3 Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.1 Power-On Reset (POR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.2 External Chip Reset (RESET_N). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
8.3.3 USB Bus Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.4 Link Power Management (LPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.5 Remote Wakeup Indicator (SUSP_IND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.5.1 Normal Resume Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.5.2 Modified Resume Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8.6 High Speed Indicator (HS_IND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Chapter 9 Operational Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.1 Absolute Maximum Ratings* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.2 Operating Conditions** . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.3 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3.1 Operational / Unconfigured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.3.2 Suspend / Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
9.4 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
9.5 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.5.1 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.5.2 Reset and Configuration Strap Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.5.3 USB Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.5.4 SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.5.5 I2C Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
9.6 Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.6.1 Oscillator/Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
9.6.2 External Reference Clock (REFCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Chapter 10 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Chapter 11 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Revision 1.0 (06-17-13)
4
SMSC USB2533
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
List of Figures
Figure 1.1 System Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3.1 36-SQFN Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4.1 Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 5.1 Hub Operational Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 7.1 I2C Sequential Access Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 7.2 I2C Sequential Access Read Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 8.1 Battery Charging External Power Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 9.1 Supply Rise Time Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 9.2 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 9.3 RESET_N Configuration Strap Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 10.1 36-SQFN Package Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 10.2 36-SQFN Package Recommended Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SMSC USB2533
5
Revision 1.0 (06-17-13)
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
List of Tables
Table 3.1 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 3.2 36-SQFN Package Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 3.3 Buffer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 6.1 Hub Configuration Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 6.2 NON_REM[1:0] Configuration Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6.3 PRT_DIS_Mx/PRT_DIS_Px Configuration Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7.1 SMBus Accessible Run Time Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 7.2 Upstream Battery Charging Detection Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 7.3 Upstream Custom Battery Charger Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 7.4 Upstream Custom Battery Charger Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.5 Port Power Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 7.6 OCS Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.7 Upstream Battery Charger Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 7.8 Charge Detect Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 7.9 Configure Portable Hub Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7.10 Port Select and Low-Power Suspend Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 7.11 Connect Configuration Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7.12 Upstream (Port 0) Battery Charging Control 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 7.13 Upstream (Port 0) Battery Charging Control 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 7.14 Upstream (Port 0) Battery Charging Run Time Control Register. . . . . . . . . . . . . . . . . . . . . . . 43
Table 7.15 Upstream (Port 0) Battery Charging Detect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 7.16 SMBus Page Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 8.1 Chargers Compatible with Upstream Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 8.2 Downstream Port Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 8.3 LPM State Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 9.1 Operational/Unconfigured Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 9.2 Suspend/Standby Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 9.3 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 9.4 Power-On Configuration Strap Valid Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9.5 RESET_N Configuration Strap Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 9.6 Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 10.1 36-SQFN Package Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11.1 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
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SMSC USB2533
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Chapter 1 General Description
The SMSC USB2533 is a low-power, OEM configurable, MTT (Multi-Transaction Translator) USB 2.0
hub controller with 3 downstream ports and advanced features for embedded USB applications. The
USB2533 is fully compliant with the USB 2.0 Specification, USB 2.0 Link Power Management
Addendum and will attach to an upstream port as a Full-Speed hub or as a Full-/Hi-Speed hub. The
3-port hub supports Low-Speed, Full-Speed, and Hi-Speed (if operating as a Hi-Speed hub)
downstream devices on all of the enabled downstream ports.
The USB2533 has been specifically optimized for embedded systems where high performance, and
minimal BOM costs are critical design requirements. Standby mode power has been minimized and
reference clock inputs can be aligned to the customer’s specific application. Additionally, all required
resistors on the USB ports are integrated into the hub, including all series termination and pull-up/pull-
down resistors on the D+ and D– pins.
The USB2533 supports both upstream battery charger detection and downstream battery charging.
The USB2533 integrated battery charger detection circuitry supports the USB-IF Battery Charging
(BC1.2) detection method and most Apple devices. These circuits are used to detect the attachment
and type of a USB charger and provide an interrupt output to indicate charger information is available
to be read from the device’s status registers via the serial interface. The USB2533 provides the battery
charging handshake and supports the following USB-IF BC1.2 charging profiles:
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
The USB2533 provides an additional USB endpoint dedicated for use as a USB to I2C interface,
allowing external circuits or devices to be monitored, controlled, or configured via the USB interface.
Additionally, the USB2533 includes many powerful and unique features such as:
FlexConnect, which provides flexible connectivity options. The USB2533’s downstream port 1 can be
swapped with the upstream port, allowing master capable devices to control other devices on the hub.
MultiTRAKTM Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain
consistent full-speed data throughput regardless of the number of active downstream connections.
MultiTRAKTM outperforms conventional USB 2.0 hubs with a single TT in USB full-speed data transfers.
PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a
USB2533 hub can be reordered or disabled in any sequence to support multiple platform designs with
minimum effort. For any port that is disabled, the USB2533 hub controllers automatically reorder the
remaining ports to match the USB host controller’s port numbering scheme.
PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows
direct alignment of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the
USB differential signals on the PCB.
PHYBoost, which provides programmable levels of Hi-Speed USB
signal drive strength in the downstream port transceivers. PHYBoost
attempts to restore USB signal integrity in a compromised system
environment. The graphic on the right shows an example of Hi-
Speed USB eye diagrams before and after PHYBoost signal integrity
restoration.
VariSense, which controls the USB receiver sensitivity enabling programmable levels of USB signal
receive sensitivity. This capability allows operation in a sub-optimal system environment, such as when
a captive USB cable is used.
The USB2533 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature
range versions.
SMSC USB2533
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
1.1
Block Diagram
Figure 1.1 details the internal block diagram of the USB2533.
Up or
Downstream
To I2C Master/Slave
SDA SCL
VDDA33
VDDA33
USB
RESET_N
VDDA33
VDDCR12
Serial
Interface
1.2V Reg
3.3V Reg
Flex PHY
Repeater
SIE
Controller
TT #1 TT #2 TT #3 TT #4
Port Controller
2KB
DP
SRAM
UDC
20
Port Power
OCS
Bridge
Routing & Port Re-Ordering Logic
GPIO
GPIO
256B
IRAM
8051
Controller
Swap PHY
PHY
PHY
2KB
OTP
4KB
SRAM ROM
32KB
USB
USB
USB
Down or Downstream Downstream
Upstream
Figure 1.1 System Block Diagram
Revision 1.0 (06-17-13)
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SMSC USB2533
DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Chapter 2 Acronyms and Definitions
2.1
Acronyms
EOP: End of Packet
EP:
FS:
Endpoint
Full-Speed
GPIO: General Purpose I/O (that is input/output to/from the device)
HS: Hi-Speed
HSOS: High Speed Over Sampling
I2C®: Inter-Integrated Circuit
LS:
Low-Speed
OTP: One Time Programmable
PCB: Printed Circuit Board
PCS: Physical Coding Sublayer
PHY: Physical Layer
SMBus: System Management Bus
UUID: Universally Unique IDentification
2.2
Reference Documents
1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th,
2004, http://www.usb.org
2. Universal Serial Bus Specification, Revision 2.0, April 27th, 2000, http://www.usb.org
3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org
4. I2C-Bus Specification, Version 1.1, http://www.nxp.com
5. System Management Bus Specification, Version 1.0, http://smbus.org/specs
SMSC MAKES NO WARRANTIES, EXPRESS, IMPLIED, OR STATUTORY, IN REGARD TO INFRINGEMENT OR
OTHER VIOLATION OF INTELLECTUAL PROPERTY RIGHTS. SMSC DISCLAIMS AND EXCLUDES ANY AND
ALL WARRANTIES AGAINST INFRINGEMENT AND THE LIKE.
No license is granted by SMSC expressly, by implication, by estoppel or otherwise, under any patent, trademark,
copyright, mask work right, trade secret, or other intellectual property right. **To obtain this software program the
appropriate SMSC Software License Agreement must be executed and in effect. Forms of these Software License
Agreements may be obtained by contacting SMSC.
SMSC USB2533
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Chapter 3 Pin Descriptions
SUSP_IND/LOCAL_PWR/NON_REM0
PRTPWR3/PRTCTL3/BC_EN3
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
VDDA33
FLEX_USBUP_DM
FLEX_USBUP_DP
XTAL2
OCS2_N
PRTPWR2/PRTCTL2/BC_EN2
VDD33
SMSC
USB2533
(Top View)
VDDCR12
XTAL1/REFCLK
NC
OCS1_N
PRTPWR1/PRTCTL1/BC_EN1
Ground Pad
(must be connected to VSS)
RBIAS
LED0
VDDA33
VDDA33
Indicates pins on the bottom of the device.
Figure 3.1 36-SQFN Pin Assignments
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DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
3.1
Pin Descriptions
This section provides a detailed description of each pin. The signals are arranged in functional groups
according to their associated interface.
The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal
is at a low voltage level. For example, RESET_N indicates that the reset signal is active low. When
“_N” is not present after the signal name, the signal is asserted when at the high voltage level.
The terms assertion and negation are used exclusively. This is done to avoid confusion when working
with a mixture of “active low” and “active high” signals. The term assert, or assertion, indicates that a
signal is active, independent of whether that level is represented by a high or low voltage. The term
negate, or negation, indicates that a signal is inactive.
Note: The buffer type for each signal is indicated in the BUFFER TYPE column of Table 3.1. A
description of the buffer types is provided in Section 3.3.
Note: Compatibility with the SMSC UCS100x family of USB port power controllers requires the
UCS100x be connected on Port 1 of the USB2533. Additionally, both PRTPWR1 and OCS1_N
must be pulled high at Power-On Reset (POR).
Table 3.1 Pin Descriptions
BUFFER
TYPE
NUM PINS
NAME
SYMBOL
DESCRIPTION
USB/HSIC INTERFACES
FLEX_USBUP_DP
FLEX_USBUP_DM
SWAP_USBDN1_DP
Upstream
USB D+
(Flex Port 0)
AIO
AIO
AIO
IS
Upstream USB Port 0 D+ data signal.
Note:
The upstream Port 0 signals can be
optionally swapped with the
downstream Port 1 signals.
1
1
Upstream
USB D-
(Flex Port 0)
Upstream USB Port 0 D- data signal.
Note:
The upstream Port 0 signals can be
optionally swapped with the
downstream Port 1 signals.
Downstream
USB D+
(Swap Port 1)
Downstream USB Port 1 D+ data signal.
Note:
The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
Port 1 D+
Disable
Configuration
Strap
PRT_DIS_P1
This strap is used in conjunction with
PRT_DIS_M1 to disable USB Port 1.
1
0 = Port 1 D+ Enabled
1 = Port 1 D+ Disabled
Note:
Both PRT_DIS_P1 and PRT_DIS_M1
must be tied to VDD33 at reset to
disable the associated port.
See Note 3.4 for more information on
configuration straps.
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
SWAP_USBDN1_DM
Downstream
USB D-
(Swap Port 1)
AIO
Downstream USB Port 1 D- data signal.
Note:
The downstream Port 1 signals can be
optionally swapped with the upstream
Port 0 signals.
Port 1 D-
Disable
Configuration
Strap
PRT_DIS_M1
IS
This strap is used in conjunction with
PRT_DIS_P1 to disable USB Port 1.
1
0 = Port 1 D- Enabled
1 = Port 1 D- Disabled
Note:
Both PRT_DIS_P1 and PRT_DIS_M1
must be tied to VDD33 at reset to
disable the associated port.
See Note 3.4 for more information on
configuration straps.
Downstream
USB D+
(Port 2)
USBDN2_DP
PRT_DIS_P2
AIO
IS
Downstream USB Port 2 D+ data signal.
Port 2 D+
Disable
This strap is used in conjunction with
PRT_DIS_M2 to disable USB Port 2.
Configuration
Strap
0 = Port 2 D+ Enabled
1 = Port 2 D+ Disabled
1
Note:
Both PRT_DIS_P2 and PRT_DIS_M2
must be tied to VDD33 at reset to
disable the associated port.
See Note 3.4 for more information on
configuration straps.
Downstream
USB D-
(Port 2)
USBDN2_DM
PRT_DIS_M2
AIO
IS
Downstream USB Port 2 D- data signal.
Port 2 D-
Disable
This strap is used in conjunction with
PRT_DIS_P2 to disable USB Port 2.
Configuration
0 = Port 2 D- Enabled
1 = Port 2 D- Disabled
1
Strap
Note:
Both PRT_DIS_P2 and PRT_DIS_M2
must be tied to VDD33 at reset to
disable the associated port.
See Note 3.4 for more information on
configuration straps.
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Downstream
USB D+
USBDN3_DP
AIO
Downstream USB Port 3 D+ data signal.
(Port 3)
Port 3 D+
Disable
PRT_DIS_P3
IS
This strap is used in conjunction with
PRT_DIS_M3 to disable USB Port 3.
Configuration
Strap
0 = Port 3 D+ Enabled
1 = Port 3 D+ Disabled
1
Note:
Both PRT_DIS_P3 and PRT_DIS_M3
must be tied to VDD33 at reset to
disable the associated port.
See Note 3.4 for more information on
configuration straps.
Downstream
USB D-
(Port 3)
USBDN3_DM
PRT_DIS_M3
AIO
IS
Downstream USB Port 3 D- data signal.
Port 3 D-
Disable
This strap is used in conjunction with
PRT_DIS_P3 to disable USB Port 3.
Configuration
0 = Port 3 D- Enabled
1 = Port 3 D- Disabled
1
Strap
Note:
Both PRT_DIS_P3 and PRT_DIS_M3
must be tied to VDD33 at reset to
disable the associated port.
See Note 3.4 for more information on
configuration straps.
I2C/SMBUS INTERFACE
I2C Serial
SCL
I_SMB
I2C serial clock input
Clock Input
SMBus Clock
SMBCLK
I_SMB
I_SMB
SMBus serial clock input
Configuration
Select 0
Configuration
CFG_SEL0
This strap is used in conjunction with CFG_SEL1
to set the hub configuration method. Refer to
Section 6.3.2, "Configuration Select
(CFG_SEL[1:0])," on page 29 for additional
information.
1
Strap
See Note 3.4 for more information on
configuration straps.
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
I2C Serial
Data
SDA
IS/OD8
I2C bidirectional serial data
SMBus Serial
Data
SMBDATA
IS/OD8
IS
SMBus bidirectional serial data
Non-
Removable
Device 1
Configuration
Strap
NON_REM1
(Note 3.3)
This strap is used in conjunction with
NON_REM0 to configure the downstream ports
as non-removable devices. Refer to Section
6.3.1, "Non-Removable Device
(NON_REM[1:0])," on page 29 for additional
information.
1
See Note 3.4 for more information on
configuration straps.
MISC.
Port 1 Over-
Current
Sense Input
OCS1_N
OCS2_N
UART_RX
IS
(PU)
This active-low signal is input from an external
current monitor to indicate an over-current
condition on USB Port 1.
1
1
Port 2 Over-
Current
Sense Input
IS
(PU)
This active-low signal is input from an external
current monitor to indicate an over-current
condition on USB Port 2.
UART
IS
Internal UART receive input
Receive Input
Note:
This is a 3.3V signal. For RS232
operation, an external 12V translator is
required.
1
Port 3 Over-
Current
Sense Input
OCS3_N
IS
(PU)
This active-low signal is input from an external
current monitor to indicate an over-current
condition on USB Port 3.
UART
Transmit
Output
UART_TX
O8
Internal UART transmit output
Note:
This is a 3.3V signal. For RS232
operation, an external 12V driver is
required.
1
1
SystemReset
Input
RESET_N
I_RST
This active-low signal allows external hardware to
reset the device.
Note:
The active-low pulse must be at least
5us wide. Refer to Section 8.3.2,
"External Chip Reset (RESET_N)," on
page 48 for additional information.
Crystal Input
XTAL1
ICLK
ICLK
External 24 MHz crystal input
Reference
Clock Input
REFCLK
Reference clock input. The device may be
alternatively driven by a single-ended clock
oscillator. When this method is used, XTAL2
should be left unconnected.
1
1
Crystal
Output
XTAL2
OCLK
External 24 MHz crystal output
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DATASHEET
USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
External USB
Transceiver
Bias Resistor
RBIAS
AI
A 12.0kΩ (+/- 1%) resistor is attached from
ground to this pin to set the transceiver’s internal
bias settings.
1
LED 0 Output
LED0
O8
IS
General purpose LED 0 output that is
configurable to blink or “breathe” at various rates.
1
Note:
LED0 must be enabled via the Protouch
configuration tool.
Detect
VBUS_DET
Detects state of upstream bus power.
Upstream
VBUS Power
When designing a detachable hub, this pin must
be connected to the VBUS power pin of the
upstream USB port through a resistor divider
(50kΩ by 100kΩ) to provide 3.3V.
For self-powered applications with a permanently
attached host, this pin must be connected to
either 3.3V or 5.0V through a resistor divider to
provide 3.3V.
1
In embedded applications, VBUS_DET may be
controlled (toggled) when the host desires to
renegotiate a connection without requiring a full
reset of the device.
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Remote
Wakeup
Indicator
SUSP_IND
OD8
Configurable sideband signal used to indicate
Suspend status (default) or Remote Wakeup
events to the Host.
Suspend Indicator (default configuration):
0 = Unconfigured, or configured and in USB
suspend mode
1 = Device is configured and is active
(i.e., not in suspend)
For Remote Wakeup Indicator mode:
Refer to Section 8.5, "Remote Wakeup Indicator
(SUSP_IND)," on page 49.
Refer to Section 6.3.1, "Non-Removable Device
(NON_REM[1:0])," on page 29 for information on
LED polarity when using this signal.
1
Local Power
Detect
LOCAL_PWR
IS
Detects the availability of a local self-power
source.
0 = Self/local power source is NOT available.
(i.e., device must obtain all power from upstream
USB VBUS)
1 = Self/local power source is available
See Note 3.2 for more information on this pin.
Non-
Removable
Device 0
Configuration
Strap
NON_REM0
(Note 3.3)
IS
This strap is used in conjunction with
NON_REM1 to configure the downstream ports
as non-removable devices. Refer to Section
6.3.1, "Non-Removable Device
(NON_REM[1:0])," on page 29 for additional
information.
See Note 3.4 for more information on
configuration straps.
High Speed
Indicator
HS_IND
O8
Indicates a high speed connection on the
upstream port. The active state of the LED will be
determined as follows:
If CFG_SEL1 = 0, HS_IND is active high.
If CFG_SEL1 = 1, HS_IND is active low.
Asserted = hub is connected at high speed
Negated = Hub is connected at full speed
1
Configuration
Select 1
Configuration
Strap
CFG_SEL1
IS
This strap is used in conjunction with CFG_SEL0
to set the hub configuration method. Refer to
Section 6.3.2, "Configuration Select
(CFG_SEL[1:0])," on page 29 for additional
information.
See Note 3.4 for more information on
configuration straps.
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SMSC USB2533
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Port 1 Power
Output
PRTPWR1
O8
Enables power to a downstream USB device
attached to Port 1.
0 = Power disabled on downstream Port 1
1 = Power enabled on downstream Port 1
Port 1 Control
PRTCTL1
BC_EN1
OD8/IS
(PU)
When configured as PRTCTL1, this pin functions
as both the Port 1 power enable output
(PRTPWR1) and the Port 1 over-current sense
input (OCS1_N). Refer to the PRTPWR1 and
OCS1_N descriptions for additional information.
1
Port 1 Battery
Charging
Configuration
IS
This strap is used to indicate support of the
battery charging protocol on Port 1. Enabling
battery charging support allows a device on the
port to draw currents per the USB battery
charging specification.
Strap
0 = Battery charging is not supported on Port 1
1 = Battery charging is supported on Port 1
See Note 3.4 for more information on
configuration straps.
Port 2 Power
Output
PRTPWR2
PRTCTL2
BC_EN2
O8
Enables power to a downstream USB device
attached to Port 2.
0 = Power disabled on downstream Port 2
1 = Power enabled on downstream Port 2
Port 2 Control
OD8/IS
(PU)
When configured as PRTCTL2, this pin functions
as both the Port 2 power enable output
(PRTPWR2) and the Port 2 over-current sense
input (OCS2_N). Refer to the PRTPWR2 and
OCS2_N descriptions for additional information.
1
Port 2 Battery
Charging
Configuration
IS
This strap is used to indicate support of the
battery charging protocol on Port 2. Enabling
battery charging support allows a device on the
port to draw currents per the USB battery
charging specification.
Strap
0 = Battery charging is not supported on Port 2
1 = Battery charging is supported on Port 2
See Note 3.4 for more information on
configuration straps.
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USB 2.0 Hi-Speed 3-Port Hub Controller
Datasheet
Table 3.1 Pin Descriptions (continued)
BUFFER
NUM PINS
NAME
SYMBOL
TYPE
DESCRIPTION
Port 3 Power
Output
PRTPWR3
O8
Enables power to a downstream USB device
attached to Port 3.
0 = Power disabled on downstream Port 3
1 = Power enabled on downstream Port 3
Port 3 Control
PRTCTL3
BC_EN3
OD8/IS
(PU)
When configured as PRTCTL3, this pin functions
as both the Port 3 power enable output
(PRTPWR3) and the Port 3 over-current sense
input (OCS3_N). Refer to the PRTPWR3 and
OCS3_N descriptions for additional information.
1
Port 3 Battery
Charging
Configuration
IS
This strap is used to indicate support of the
battery charging protocol on Port 3. Enabling
battery charging support allows a device on the
port to draw currents per the USB battery
charging specification.
Strap
0 = Battery charging is not supported on Port 3
1 = Battery charging is supported on Port 3
See Note 3.4 for more information on
configuration straps.
No Connect
NC
-
These pins must be left floating for normal device
operation.
5
POWER
+3.3V Analog
Power Supply
VDDA33
VDD33
P
+3.3V analog power supply. Refer to Chapter 4,
"Power Connections," on page 21 for power
connection information.
3
2
+3.3V Power
Supply
P
P
+3.3V power supply. These pins must be
connected to VDDA33. Refer to Chapter 4,
"Power Connections," on page 21 for power
connection information.
+1.2V Core
Power Supply
VDDCR12
+1.2V core power supply. A 1.0 μF (<1 Ω ESR)
capacitor to ground is required for regulator
stability. The capacitor should be placed as close
as possible to the device. Refer to Chapter 4,
"Power Connections," on page 21 for power
connection information.
1
Exposed
Pad on
Ground
VSS
P
Common ground. This exposed pad must be
connected to the ground plane with a via array.
package
bottom
(Figure 3.1)
Note 3.2 The LOCAL_PWR pin is sampled during the configuration state, immediately after negation
of reset, to determine whether the device is bus-powered or self-powered. When
configuration is complete, the latched value will not change until the next reset assertion.
To enable dynamic local power switching, the DYNAMIC_POWER register at location
0x4134 must be programmed with 0x41. If dynamic power switching is not required, the
DYNAMIC_POWER register should be left at the default value of 0xC1. Programming may
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be performed through the SMBus interface, or permanently via OTP. Refer to the Protouch
MPT User Manual for additional information.
Note 3.3 If using the local power detect function (LOCAL_PWR pin), the NON_REM[1:0]
configuration straps cannot be used to configure the non-removable state of the USB ports.
In this case, the non-removable state of the ports must be configured in internal device
registers via the Protouch tool or SMBus.
Note 3.4 Configuration strap values are latched on Power-On Reset (POR) and the rising edge of
RESET_N (external chip reset). Configuration straps are identified by an underlined
symbol name. Signals that function as configuration straps must be augmented with an
external resistor when connected to a load. Refer to Section 6.3, "Device Configuration
Straps," on page 29 for additional information.
3.2
Pin Assignments
Table 3.2 36-SQFN Package Pin Assignments
PIN
NUM
PIN
NUM
PIN NAME
PIN NAME
1
2
SWAP_USBDN1_DM/PRT_DIS_M1
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
UART_RX/OCS3_N
SWAP_USBDN1_DP/PRT_DIS_P1
3
USBDN2_DM/PRT_DIS_M2
UART_TX/
SDA/SMBDATA/NON_REM1
VDD33
4
USBDN2_DP/PRT_DIS_P2
5
NC
6
USBDN3_DM/PRT_DIS_M3
SCL/SMBCLK/CFG_SEL0
HS_IND/CFG_SEL1
RESET_N
7
USBDN3_DP/PRT_DIS_P3
8
NC
9
NC
VDDA33
VBUS_DET
10
11
12
13
14
15
16
17
18
SUSP_IND/LOCAL_PWR/NON_REM0
VDDA33
LED0
PRTPWR1/PRTCTL1/BC_EN1
OCS1_N
FLEX_USBUP_DM
FLEX_USBUP_DP
XTAL2
VDDCR12
VDD33
XTAL1/REFCLK
NC
PRTPWR2/PRTCTL2/BC_EN2
OCS2_N
RBIAS
PRTPWR3/PRTCTL3/BC_EN3
VDDA33
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3.3
Buffer Type Descriptions
Table 3.3 Buffer Types
DESCRIPTION
BUFFER TYPE
IS
I_RST
I_SMB
O8
Schmitt-triggered input
Reset Input
I2C/SMBus Clock Input
Output with 8 mA sink and 8 mA source
Open-drain output with 8 mA sink
Open-drain output with 12 mA sink
OD8
OD12
PU
50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-
ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD
50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal
pull-downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely
on internal resistors to drive signals external to the device. When connected to a
load that must be pulled low, an external resistor must be added.
AIO
ICLK
OCLK
P
Analog bi-directional
Crystal oscillator input pin
Crystal oscillator output pin
Power pin
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Chapter 4 Power Connections
4.1
Integrated Power Regulators
The integrated 3.3V and 1.2V power regulators allow the device to be supplied via a single 3.3V
external power supply.
The regulators are controlled by RESET_N. When RESET_N is brought high, the 3.3V regulator will
turn on. When RESET_N is brought low the 3.3V regulator will turn off.
4.2
Power Connection Diagrams
Figure 4.1 illustrates the power connections for the USB2533.
Single Supply Application
3.3V Internal
Logic
1.2V
Core Logic
3.3V I/O
+3.3V
Supply
1.2V Regulator
3.3V Regulator
VDDA33
VSS
(IN)
(OUT)
(IN)
(OUT)
(Bypass)
VDD33
USB2533
(2x)
VDDA33
VDDA33
VDDCR12
1.0uF
Figure 4.1 Power Connections
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Chapter 5 Modes of Operation
The device provides two main modes of operation: Standby Mode and Hub Mode. The operating mode
of the device is selected by setting values on primary inputs according to the table below.
Table 5.1 Controlling Modes of Operation
RESET_N
INPUT
RESULTING
MODE
SUMMARY
0
Standby
Lowest Power Mode: No functions are active other than monitoring the
RESET_N input. All port interfaces are high impedance. All regulators are
powered off.
1
Hub
Full Feature Mode: Device operates as a configurable USB hub with battery
charger detection. Power consumption is based on the number of active ports,
their speed, and amount of data transferred.
Note: Refer to Section 8.3.2, "External Chip Reset (RESET_N)," on page 48 for additional information
on RESET_N.
The flowchart in Figure 5.1 shows the modes of operation. It also shows how the device traverses
through the Hub mode stages (shown in bold.) The flow of control is dictated by control register bits
shown in italics as well as other events such as availability of a reference clock. The remaining sections
in this chapter provide more detail on each stage and mode of operation.
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(HW_INIT)
(SW_INIT)
Run from
Internal ROM
CFG_SEL[1:0] = 11b
NO
YES
YES
SMBus or I2C
Present?
NO
Config Load
From I2C
Do SMBus or I2C
Initialization
Config Load
From Internal ROM
NO
SOC Done?
YES
Combine OTP
Config Data
(SOC_CFG)
(CONFIG)
SW Upstream
BC detection
(CHGDET)
Hub Connect
(Hub.Connect)
Normal
operation
Figure 5.1 Hub Operational Mode Flowchart
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5.1
Boot Sequence
5.1.1
Standby Mode
If the external hardware reset is asserted, the hub will be in Standby Mode. This mode provides a very
low power state for maximum power efficiency when no signaling is required. This is the lowest power
state. In Standby Mode all internal regulators are powered off, the PLL is not running, and core logic
is powered down in order to minimize power consumption. Because core logic is powered off, no
configuration settings are retained in this mode and must be re-initialized after RESET_N is negated
high.
5.1.2
Hardware Initialization Stage (HW_INIT)
The first stage is the initialization stage and occurs on the negation of RESET_N. In this stage the
1.2V regulator is enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK
is supplied. Configuration registers are initialized to their default state and strap input values are
latched. The device will complete initialization and automatically enter the next stage. Because the
digital logic within the device is not yet stable, no communication with the device using the SMBus is
possible. Configuration registers are initialized to their default state.
If there is a REFCLK present, the next state is SW_INIT.
5.1.3
Software Initialization Stage (SW_INIT)
Once the hardware is initialized, the firmware can begin to execute from the internal ROM. The
firmware checks the CFG_SEL[1:0] configuration strap values to determine if it is configured for I2C
Master loading. If so, the configuration is loaded from an external I2C ROM in the device’s CONFIG
state.
For all other configurations, the firmware checks for the presence of an external I2C/SMBus. It does
this by asserting two pull down resistors on the data and clock lines of the bus. The pull downs are
typically 50Kohm. If there are 10Kohm pull-ups present, the device becomes aware of the presence
of an external SMBus/I2C bus. If a bus is detected, the firmware transitions to the SOC_CFG state.
5.1.4
5.1.5
SOC Configuration Stage (SOC_CFG)
In this stage, the SOC may modify any of the default configuration settings specified in the integrated
ROM such as USB device descriptors, or port electrical settings, and control features such as
upstream battery charging detection.
There is no time limit. In this stage the firmware will wait indefinitely for the SMBus/I2C configuration.
When the SOC has completed configuring the device, it must write to register 0xFF to end the
configuration.
Configuration Stage (CONFIG)
Once the SOC has indicated that it is done with configuration, then all the configuration data is
combined. The default data, the SOC configuration data, the OTP data are all combined in the firmware
and device is programmed.
After the device is fully configured, it will go idle and then into suspend if there is no VBUS or
Hub.Connect present. Once VBUS is present, and upstream battery charging is enabled, the device
will transition to the Battery Charger Detection Stage (CHGDET). If VBUS is present, and upstream
battery charging is not enabled, the device will transitions to the Connect (Hub.Connect) stage.
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5.1.6
Battery Charger Detection Stage (CHGDET)
After configuration, if enabled, the device enters the Battery Charger Detection Stage. If the battery
charger detection feature was disabled during the CONFIG stage, the device will immediately
transition to the Hub Connect (Hub.Connect) stage. If the battery charger detection feature remains
enabled, the battery charger detection sequence is started automatically.
If the charger detection remains enabled, the device will transition to the Hub.Connect stage if using
the hardware detection mechanism.
5.1.7
5.1.8
Hub Connect Stage (Hub.Connect)
Once the CHGDET stage is completed, the device enters the Hub.Connect stage.
Normal Mode
Lastly the SOC enters the Normal Mode of operation. In this stage, full USB operation is supported
under control of the USB Host on the upstream port. The device will remain in the normal mode until
the operating mode is changed by the system. The only device registers accessible to the SOC are
the run time registers described in Section 7.2.1, "SMBus Run Time Accessible Registers," on page 32.
If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any
of the designated Hub stages. Asserting the soft disconnect on the upstream port will cause the Hub
to return to the Hub.Connect stage until the soft disconnect is negated.
To save power, communication over the SMBus is not supported while in USB Suspend. The system
can prevent the device from going to sleep by asserting the ClkSusp control bit of the Configure
Portable Hub Register anytime before entering USB Suspend. While the device is kept awake during
USB Suspend, it will provide the SMBus functionality at the expense of not meeting USB requirements
for average suspend current consumption.
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Chapter 6 Device Configuration
The device supports a large number of features (some mutually exclusive), and must be configured in
order to correctly function when attached to a USB host controller. The hub can be configured either
internally or externally depending on the implemented interface.
SMSC provides a comprehensive software programming tool, Pro-Touch, for configuring the USB2533
functions, registers and OTP memory. All configuration is to be performed via the Pro-Touch
programming tool. For additional information on the Pro-Touch programming tool, contact your local
SMSC sales representative.
6.1
Configuration Method Selection
The CFG_SEL[1:0] configuration straps and the SDA pin are used to determine the hub configuration
method, as shown in Table 6.1. The software reads the SDA pin and the CFG_SEL[1:0] bits and
configures the system appropriately.
Table 6.1 Hub Configuration Selection
SDA
CFG_SEL1
CFG_SEL0
DESCRIPTION
X
0
0
Configuration is based on the configuration strap options and
internal OTP settings. This configuration sets the device Self
powered operation.
0
0
1
1
0
Invalid
X
Configuration based on the configuration strap options and
internal OTP settings. This configuration sets the device for Bus
powered operation.
0
1
1
1
1
Firmware performs a configuration load from 2-wire (I2C)
EEPROM. The device does not perform an SMBus Master
detection. Configuration is controlled by EEPROM values and
OTP settings. Strap options are disabled.
X
Firmware must wait for configuration from an SMBus Master.
Configuration is controlled by SMBus Master and OTP settings.
Strap options are disabled.
Note: Refer to Chapter 7, "Device Interfaces," on page 31 for detailed information on each device
configuration interface.
6.2
Customer Accessible Functions
The following USB or SMBus accessible functions are available to the customer via the SMSC Pro-
Touch Programming Tool.
Note: For additional programming details, refer to the SMSC Pro-Touch Programming Tool User
Manual.
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6.2.1
USB Accessible Functions
6.2.1.1
VSM commands over USB
By default, Vendor Specific Messaging (VSM) commands to the hub are enabled. The supported
commands are:
Enable Embedded Controller
Disable Embedded Controller
Enable Special Resume
Disable Special Resume
Reset Hub
2
6.2.1.2
6.2.1.3
6.2.1.4
I C Master Access over USB
Access to I2C devices is performed as a pass-through operation from the USB Host. The device
firmware has no knowledge of the operation of the attached I2C device. The supported commands are:
Enable I2C pass through mode
Disable I2C pass through mode
I2C write
I2C read
Send I2C start
Send I2C stop
OTP Access over USB
The OTP ROM in the device is accessible via the USB bus. All OTP parameters can modified via the
USB Host. The OTP operates in Single Ended mode. The supported commands are:
Enable OTP reset
Set OTP operating mode
Set OTP read mode
Program OTP
Get OTP status
Program OTP control parameters
Battery Charging Access over USB
The Battery charging behavior of the device can be dynamically changed by the USB Host when
something other than the preprogrammed or OTP programmed behavior is desired. The supported
commands are:
Enable/Disable battery charging
Upstream battery charging mode control
Downstream battery charging mode control
Battery charging timing parameters
Download custom battery charging algorithm
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6.2.1.5
Other Embedded Controller functions over USB
The following miscellaneous functions may be configured via USB:
Enable/Disable Embedded controller enumeration
Program Configuration parameters.
Program descriptor fields:
—Language ID
—Manufacturer string
—Product string
—idVendor
—idProduct
—bcdDevice
6.2.2
SMBus Accessible Functions
6.2.2.1
OTP Access over SMBus
The device’s OTP ROM is accessible over SMBus. All OTP parameters can modified via the SMbus
Host. The OTP can be programmed to operate in Single-Ended, Differential, Redundant, or Differential
Redundant mode, depending on the level of reliability required. The supported commands are:
Enable OTP reset
Set OTP operating mode
Set OTP read mode
Program OTP
Get OTP Status
Program OTP control parameters
6.2.2.2
Configuration Access over SMBus
The following functions are available over SMBus prior to the hub attaching to the USB host:
Program Configuration parameters.
Program descriptor fields:
—Language ID
—Manufacturer string
—Product string
—idVendor
—idProduct
—bcdDevice
Program Control Register
6.2.2.3
Run time Access over SMBus
There is a limited number of registers that are accessible via the SMBus during run time operation of
the device. Refer to Section 7.2.1, "SMBus Run Time Accessible Registers," on page 32 for details.
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6.3
Device Configuration Straps
Configuration straps are multi-function pins that are driven as outputs during normal operation. During
a Power-On Reset (POR) or an External Chip Reset (RESET_N), these outputs are tri-stated. The high
or low state of the signal is latched following de-assertion of the reset and is used to determine the
default configuration of a particular feature. Configuration straps are latched as a result of a Power-On
Reset (POR) or a External Chip Reset (RESET_N). Configuration strap signals are noted in Chapter 3,
"Pin Descriptions," on page 10 and are identified by an underlined symbol name. The following sub-
sections detail the various configuration straps.
Configuration straps include internal resistors in order to prevent the signal from floating when
unconnected. If a particular configuration strap is connected to a load, an external pull-up or pull-down
should be used to augment the internal resistor to ensure that it reaches the required voltage level
prior to latching. The internal resistor can also be overridden by the addition of an external resistor.
Note: The system designer must guarantee that configuration straps meet the timing requirements
specified in Section 9.5.2, "Reset and Configuration Strap Timing," on page 57 and Section
9.5.1, "Power-On Configuration Strap Valid Timing," on page 56. If configuration straps are not
at the correct voltage level prior to being latched, the device may capture incorrect strap
values.
Note: Configuration straps must never be driven as inputs. If required, configuration straps can be
augmented, or overridden with external resistors.
6.3.1
Non-Removable Device (NON_REM[1:0])
The NON_REM[1:0] configuration straps are sampled at RESET_N negation to determine if ports [3:1]
contain permanently attached (non-removable) devices as follows. Additionally, because the
SUSP_IND indicator functionality is shared with the NON_REM0 configuration strap, the active state
of the LED connected to SUSP_IND will be determined as follows:
Table 6.2 NON_REM[1:0] Configuration Definitions
NON_REM[1:0]
DEFINITION
‘00’
‘01’
‘10’
‘11’
All USB ports removable, SUSP_IND LED active high
Port 1 is non-removable, SUSP_IND LED active low
Ports 1 & 2 are non-removable, SUSP_IND LED active high
Ports 1, 2 & 3 are non-removable, SUSP_IND LED active low
Note: If using the local power detect function (LOCAL_PWR pin), the NON_REM[1:0] configuration
straps cannot be used to configure the non-removable state of the USB ports. In this case, the
non-removable state of the ports must be configured in internal device registers via the
Protouch tool or SMBus.
6.3.2
6.3.3
Configuration Select (CFG_SEL[1:0])
Refer to Section 6.1, "Configuration Method Selection," on page 26 for details on CFG_SEL[1:0].
Downstream Battery Charging Enable (BC_EN[3:1])
The battery charging enable configuration straps are used to enable battery charging on the
corresponding downstream port. For example, if BC_EN1 is driven high during the configuration strap
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latching time, downstream port 1 will indicate support of battery charging. Refer to Section 8.1.2,
"Downstream Battery Charging," on page 46 for additional information on battery charging.
6.3.4
Port Disable (PRT_DIS_Mx/PRT_DIS_Px)
These configuration straps disable the associated USB ports D- and D+ signals, respectively, where
“x” is the USB port number. Both the negative “M” and positive “P” port disable configuration straps for
a given USB port must be tied high at reset to disable the associated port.
Table 6.3 PRT_DIS_Mx/PRT_DIS_Px Configuration Definitions
PRT_DIS_MX/PRT_DIS_PX
DEFINITION
Port x D-/D+ Signal is Enabled (Default)
‘0’
‘1’
Port x D-/D+ Signal is Disabled
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Chapter 7 Device Interfaces
The USB2533 provides multiple interfaces for configuration and external memory access. This chapter
details the various device interfaces and their usage.
Note: For information on device configuration, refer to Chapter 6, "Device Configuration," on page 26.
7.1
I2C Master Interface
The I2C master interface implements a subset of the I2C Master Specification (Please refer to the
Philips Semiconductor Standard I2C-Bus Specification for details on I2C bus protocols). The device’s
I2C master interface is designed to attach to a single “dedicated” I2C EEPROM for loading
configuration data and conforms to the Standard-Mode I2C Specification (100 kbit/s transfer rate and
7-bit addressing) for protocol and electrical compatibility. The device acts as the master and generates
the serial clock SCL, controls the bus access (determines which device acts as the transmitter and
which device acts as the receiver), and generates the START and STOP conditions.
Note: Extensions to the I2C Specification are not supported.
Note: All device configuration must be performed via the SMSC Pro-Touch Programming Tool. For
additional information on the Pro-Touch programming tool, contact your local SMSC sales
representative.
2
7.1.1
I C Message Format
7.1.1.1
Sequential Access Writes
The I2C interface supports sequential writing of the device’s register address space. This mode is
useful for configuring contiguous blocks of registers. Figure 7.1 shows the format of the sequential
write operation. Where color is visible in the figure, blue indicates signaling from the I2C master, and
gray indicates signaling from the slave.
S
7-Bit Slave Address
0
A
xxxxxxxx
A
nnnnnnnn
A
...
nnnnnnnn
A
P
Register
Address
(bits 7-0)
Data value for
XXXXXX
Data value for
XXXXXX + y
Figure 7.1 I2C Sequential Access Write Format
In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for sequential write operation. Every subsequent access is a data write to a data register,
where the register address increments after each access and an ACK from the slave occurs.
Sequential write access is terminated by a Stop condition.
7.1.1.2
Sequential Access Reads
The I2C interface supports direct reading of the device registers. In order to read one or more register
addresses, the starting address must be set by using a write sequence followed by a read. The read
register interface supports auto-increment mode. The master must send a NACK instead of an ACK
when the last byte has been transferred.
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In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the
start address for the subsequent sequential read operation. In the read sequence, every data access
is a data read from a data register where the register address increments after each access. The write
sequence can end with optional Stop (P). If so, the read sequence must begin with a Start (S).
Otherwise, the read sequence must start with a Repeated Start (Sr).
Figure 7.2 shows the format of the read operation. Where color is visible in the figure, blue and gold
indicate signaling from the I2C master, and gray indicates signaling from the slave.
Optional. If present, Next
access must have Start(S),
otherwise Repeat Start (Sr)
S
7-Bit Slave Address
0
A
xxxxxxxx
A
P
Register
Address
(bits 7-0)
If previous write setting up
Register address ended with a
Stop (P), otherwise it will be
Repeated Start (Sr)
S
7-Bit Slave Address
1
ACK n n n n n n n n ACK n n n n n n n n ACK
...
n n n n n n n n NACK
P
Register value
for xxxxxxxx
Register value
for xxxxxxxx + 1
Register value
for xxxxxxxx + y
Figure 7.2 I2C Sequential Access Read Format
2
7.1.2
Pull-Up Resistors for I C
The circuit board designer is required to place external pull-up resistors (10 kΩ recommended) on the
SDA & SCL signals (per SMBus 1.0 Specification) to Vcc in order to assure proper operation.
7.2
SMBus Slave Interface
The USB2533 includes an integrated SMBus slave interface, which can be used to access internal
device run time registers or program the internal OTP memory. SMBus detection is accomplished by
detection of pull-up resistors (10 KΩ recommended) on both the SMBDATA and SMBCLK signals. To
disable the SMBus, a pull-down resistor of 10 KΩ must be applied to SMBDATA. The SMBus interface
can be used to configure the device as detailed in Section 6.1, "Configuration Method Selection," on
page 26.
Note: All device configuration must be performed via the SMSC Pro-Touch Programming Tool. For
additional information on the Pro-Touch programming tool, contact your local SMSC sales
representative.
7.2.1
SMBus Run Time Accessible Registers
Table 7.1 provides a summary of the SMBus accessible run time registers. Each register is detailed in
the subsequent tables.
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Note: The SMBus page register must be configured to allow the SOC to access the proper register
space. Refer to Section 7.2.2, "Run Time SMBus Page Register," on page 44 for details.
Table 7.1 SMBus Accessible Run Time Registers
XDATA
ADDR
NAME
UP_BC_DET
UP_CUST_BC_CTL
UP_CUST_BC_STAT
PORT_PWR_STAT
OCS_STAT
0x30E2
0x30E3
0x30E4
0x30E5
0x30E6
0x30EC
0x30ED
0x30EE
0x318B
0x318E
0x6100
0x6101
Table 7.2, "Upstream Battery Charging Detection Control Register"
Table 7.3, "Upstream Custom Battery Charger Control Register"
Table 7.4, "Upstream Custom Battery Charger Status Register"
Table 7.5, "Port Power Status Register"
Table 7.6, "OCS Status Register"
BC_CHG_MODE
CHG_DET_MSK
CFGP
Table 7.7, "Upstream Battery Charger Mode Register"
Table 7.8, "Charge Detect Mask Register"
Table 7.9, "Configure Portable Hub Register"
PSELSUSP
Table 7.10, "Port Select and Low-Power Suspend Register"
Table 7.11, "Connect Configuration Register"
CONNECT_CFG
BC_CTL_1 (Upstream)
Table 7.12, "Upstream (Port 0) Battery Charging Control 1 Register"
Table 7.13, "Upstream (Port 0) Battery Charging Control 2 Register"
BC_CTL_2
(Upstream)
BC_CTL_RUN_TIME
(Upstream)
0x6102
0x6103
Table 7.14, "Upstream (Port 0) Battery Charging Run Time Control
Register"
BC_CTL_DET
(Upstream)
Table 7.15, "Upstream (Port 0) Battery Charging Detect Register"
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Table 7.2 Upstream Battery Charging Detection Control Register
UPSTREAM BATTERY CHARGING REGISTER
UP_BC_DET
(0x30E2 - RESET= 0x02)
BIT
NAME
R/W
DESCRIPTION
7:5
CHARGER_TYPE
R/W
Read Only.
This field indicates the result of the automatic charger detection. Values
reported depend on EnhancedChrgDet bit setting in Upstream Battery
Charger Mode Register.
If EnhancedChrgDet = 1
000 = Charger Detection is not complete.
001 = DCP - Dedicated Charger Port
010 = CDP – Charging Downstream Port
011 = SDP – Standard Downstream Port
100 = Apple Low Current Charger
101 = Apple High Current Charger
110 = Apple Super High Current Charger
111 = Charger Detection Disabled
If EnhancedChrgDet = 0
000 = Charger Detection is not complete.
001 = DCP/CDP – Dedicated Charger or Charging Downstream Port
010 = Reserved
011 = SDP – Standard Downstream Port
100 = Apple Low Current Charger
101 = Apple High Current Charger
110 = Apple Super High Current Charger
111 = Charger Detection Disabled
4
CHGDET_COMPLETE
R
Indicates Charger Detection has been run and is completed. This bit is
negated when START_CHG_DET is asserted high.
3
Reserved
R/W
R
Reserved for debugging
2:1
CHG_DET[1:0]
Indicates encoded status of what chargers or status has been detected
according to the settings in the Charge Detect Mask Register. It can be
used to determine what current can be drawn from the upstream USB
port.
00 = No selected Chargers or Status identified
01 = 100ma (VBUS detect without enumeration)
10 = 500ma (Device enumerated, Set Config seen)
11 = 1000+ma (Charger detected)
The actual current amount for the charger will be system dependent
0
START_CHG_DET
R/W
Manually Initiates a USB battery charger detection sequence at the time
of assertion. This bit must not be set while hub is in operation. This bit
is cleared automatically when the manual battery charger detection
sequence is completed.
0 = Write: No Effect / Read: Battery Charger Detection Sequence
Completed or not run.
1 = Write: Start Battery Charger Detection / Read: Battery Charger
Detection Sequence is running
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Table 7.3 Upstream Custom Battery Charger Control Register
UP_CUST_BC_CTL
(0x30E3 - RESET= 0x00)
UPSTREAM CUSTOM BATTERY CHARGING CONTROL
BIT
NAME
R/W
DESCRIPTION
7
I2CControl
R/W
I2C control
0: I2C control disabled
1: I2C control enabled
6
5
4
3
DmPulldownEn
DpPulldownEn
IdatSinkEn
R/W
R/W
R/W
R/W
DM 15K pull down resistor control
0: DM 15K pull down resistor disabled
1: DM 15K pull down resistor enabled
DP 15K pull down resistor control
0: DP 15K pull down resistor disabled
1: DP 15K pull down resistor enabled
Idat current sink control
0: Idat current sink disabled
1: Idat current sink enabled
HostChrgEn
Host charger detection swap control
0: Charger detection connections of DP and DM are not swapped
(standard)
1: Charger detection connections of DP and DM are swapped. The USB
signal path is not reversed.
2
1
0
VdatSrcEn
R/W
R/W
R/W
Vdat voltage source control
0: Vdat voltage source disabled
1: Vdat voltage source enabled
ContactDetectEn
SeRxEn
Contact detect current source control
0: Contact detect current source disabled
1: Contact detect current source enabled
Single-ended receiver control
0: Single-ended receiver disabled
1: Single-ended receiver enabled
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Table 7.4 Upstream Custom Battery Charger Status Register
UPSTREAM CUSTOM BATTERY CHARGING STATUS
UP_CUST_BC_STAT
(0x30E4 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:4
3
Reserved
RxHiCurr
R
R
Reserved
DM high current Apple charger output
0: DM signal is not above the VSE_RXH threshold
1: DM signal is above the VSE_RXH threshold
2
1
0
DmSeRx
DpSeRx
VdatDet
R
R
R
DM Single Ended Receiver Status
DP Single Ended Receiver Status
Vdat detect
0: Vdat not detected
1: Vdat detect comparator output
Table 7.5 Port Power Status Register
PORT POWER STATUS
PORT_PWR_STAT
(0x30E5 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:5
4:1
Reserved
R
R
Reserved
PRTPWR[4:1]
Optional status to SOC indicating that power to the corresponding
downstream port was enabled by the USB Host for the specified port. Not
required for an embedded application.
This is a read-only status bit. Actual control over port power is
implemented by the USB Host, OCS Status Register and Downstream
Battery Charging logic, if enabled.
0: USB Host has not enabled port to be powered or in downstream battery
charging and corresponding OCS bit has been set
1: USB Host has enabled port to be powered
0
Reserved
R
Reserved
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Table 7.6 OCS Status Register
PORT POWER STATUS
OCS_STAT
(0x30E6 - RESET= 0x00)
BIT
NAME
R/W
DESCRIPTION
7:5
4:1
Reserved
OCS[4:1]
R
R
Reserved
Optional control from SOC that indicates an over-current condition on the
corresponding port for HUB status reporting to USB host. Also resets
corresponding PRTPWR status bit in the Port Power Status Register. Not
required for an embedded application.
0: No Over Current Condition
1: Over Current Condition
0
Reserved
R
Reserved
Table 7.7 Upstream Battery Charger Mode Register
UPSTREAM BATTERY CHARGER MODE
BC_CHG_MODE
(0x30EC - RESET= 0x00
BIT
NAME
R/W
DESCRIPTION
7:6
5
Reserved
HoldVdat
R
Reserved
R/W
Dead Battery Vdat Detect voltage source enable
0: The charger detection state machine will turn off the Vdat Source at the
end of the charger detection routine.
1: The charger detection state machine leave Vdat Source on during
Hub.Connect stage when a SDP has been detected.
4
3
Reserved
R
Reserved
SE1ChrgDet
R/W
Apple type charger detection control
0: The charger detection routine will not look for the attachment of an
Apple type charger.
1: The charger detection routine will look for the attachment of an Apple
type charger.
2
EnhancedChrgDet
Reserved
R/W
Enhanced charge detect control
0: The charger detection routine will not reverse Vdat SRC to differentiate
between a CDP and a DCP.
1: The charger detection routine will reverse Vdat SRC to differentiate
between a CDP and a DCP.
1:0
R
Reserved
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Table 7.8 Charge Detect Mask Register
CHARGE DETECT MASK
DESCRIPTION
CHG_DET_MSK
(0x30ED - RESET= 0x1F)
BIT
NAME
R/W
7
CONFIGURED
R/W
0: battChg.chgDet is not affected for this mask set when Hub is in a
session and has been configured by the USB Host
1: battChg.chgDet indicates status for this mask set met when Hub is in a
session and has been configured by the USB Host
6
5
4
3
2
1
CONNECTED
SUSPENDED
SE1SMask
SE1HMask
SE1LMask
CDPMask
R/W
R/W
R/W
R/W
R/W
R/W
0: battChg.chgDet is not affected for this mask set when Hub has
successfully connected with an upstream Host
1: battChg.chgDet indicates status for this mask set met when Hub has
successfully connected with an upstream host.
0: battChg.chgDet is not affected for this mask set when Hub is in a
session and has been suspended by the USB Host
1: battChg.chgDet indicates status for this mask set met when Hub is in a
session and has been suspended by the USB Host
0: battChg.chgDet is not affected for this mask set by detection of a Apple
Super High Current Charger
1: battChg.chgDet indicates status for this mask set met when a SE1
(Apple) Super High Current Charger is detected
0: battChg.chgDet is not affected for this mask set by detection of a Apple
High Current Charger
1: battChg.chgDet indicates status for this mask set met when a Apple
High Current Charger is detected
0: battChg.chgDet is not affected for this mask set by detection of a Apple
Low Current Charger
1: battChg.chgDet indicates status for this mask set met when a Apple
Low Current Charger is detected
0: battChg.chgDet is not affected for this mask set by detection of a CDP
Charger
1: battChg.chgDet indicates status for this mask set met when a CDP
Charger is detected
This mask bit should only be enabled if EnhancedChrgDet is asserted in
the Upstream Battery Charger Mode Register. Without it, the charger
detection is unable to identify a CDP.
0
DCPMask
R/W
0: battChg.chgDet is not affected for this mask set by detection of a DCP
Charger
1: battChg.chgDet indicates status for this mask set met when a DCP
Charger is detected
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Table 7.9 Configure Portable Hub Register
PORTABLE HUB CONFIGURATION REGISTER
CFGP
(0x30EE - RESET= 0x10)
BIT
NAME
R/W
DESCRIPTION
7
ClkSusp
R/W
0: Allow device to gate-off its internal clocks during suspend mode in order
to meet USB suspend current requirements.
1: Force device to run internal clock even during USB suspend (will cause
device to violate USB suspend current limit - intended for test or self-
powered applications which require use of SMBus during USB session.)
6
Reserved
R
Always read ‘0’
5:1
DIS_CHP_PHY_CL
K[5:1]
R/W
A ‘1’ disables the PHY clock of the corresponding port:
Bit 5 - Downstream port 5
Bit 4 - Downstream port 4
Bit 3 - Downstream port 3
Bit 2 - Downstream port 2
Bit 1 - Downstream port 1
0
Reserved
R
Always read ‘0’
Table 7.10 Port Select and Low-Power Suspend Register
PORT SELECT AND LOW POWER SUSPEND REGISTER
DESCRIPTION
PSELSUSP
(0x318B- RESET=0x00)
BIT
7:6
NAME
R/W
APortSel
R/W
Specifies which downstream USB port is associated with the
PRTPWRA pin function.
‘00’ - Port 1
‘01’ - Port 2
‘10’ - Port 3
‘11’ - Port 4
5:0
Note:
Reserved
R
Always read ‘0’
This register should be assigned during the Hub.Config or Hub.Connect stages, and should not be
dynamically updated during Hub.Communication stage or undefined behavior may result.
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Table 7.11 Connect Configuration Register
CONNECT CONFIGURATION REGISTER
CONNECT_CFG
(0x318E- RESET=0x00)
BIT
NAME
R/W
DESCRIPTION
7:2
1
Reserved
R
Reserved
EN_FLEX_MODE
R/W
Flex Connect mode enable
0: Flex Connect mode is disabled. (Normal hub operation with separate
port power and OCS control)
1: Flex Connect mode is enabled
0
FLEXCONNECT
R/W
FlexConnect Control. When asserted the device changes its hub
connections so that the Swap port (Physical Port 1) changes from it’s
default behavior of a downstream port to an upstream port. The Flex
Port (Physical port 0) transitions from an upstream port to a
downstream port.
‘0’ -
Flex Port = Upstream (Port 0)
Swap Port= Downstream (Port 1)
‘1’ -
Flex Port= Downstream (Port 1)
Swap Port= Upstream (Port 0)
This setting can be used to select whether the Flex Port is an upstream
or downstream port.
Another application for this setting is to allow a dual-role device on the
Swap Port to assume a host role and communicate directly with other
downstream hub ports, or to communicate through the Flex Port to a
exposed connector to an external device.
If a “private” communication channel is desired between embedded
devices, any externally exposed ports should be disabled.
Note: All port-specific settings such as VSNS, prtSp, sDiscon are
specific to the logic port 0, 1, 2, 3. When FLEXCONNECT is asserted,
these settings affect the newly assigned physical pins and PHY. Any
settings which are specific to the physical Flex Port and Swap Port
such as battery charger detection do not change with the setting of
FLEXCONNECT.
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Table 7.12 Upstream (Port 0) Battery Charging Control 1 Register
BC_CTL_1
(0x6100- RESET=0x00)
UPSTREAM (PORT 0) BATTERY CHARGING CONTROL 1
REGISTER
BIT
NAME
R/W
DESCRIPTION
7
USB2_IDP_SRC_EN
R/W
AFE 10uA IDP_SRC current source Enable
0: Disabled (Hi Z)
1: Enabled
6
5
USB2_VDAT_SRC_EN
R/W
AFE 0.6V VDATA_SRC voltage source Enable
0: Disabled (Hi Z)
1: Enabled
USB2_HOST_CHRG_EN R/W
Enable charging host port mode
0: Portable Device
1: Charging Host port.
When the charging host port is bit is set, the connections of
V
DATA_SRC, IDAT_SINK, IDP_SRC, VDAT_DET are reversed
between DP and DM
4
3
USB2_IDAT_SINK_EN
USB2_VDAT_DET
R/W
R
AFE 100uA current sink and the VDAT_DET comparator Enable
0: Disabled (Hi Z)
1: Enabled
V
DAT_DET comparator output
0: No voltage detected
1: Voltage detected (a possible charger or a
device)
2
1
0
USB2_BC_DP_RDIV_EN R/W
AFE Battery Charging Resistor Divider Enable – DP.
0: Disables resistor divider on DP.
1: Enables 2.7V voltage reference on DP through use of
9.7K/48.5K resistor divider.
USB2_BC_DM_RDIV_E
N
R/W
AFE Battery Charging Resistor Divider Enable – DM.
0: Disables resistor divider on DM.
1: Enables 2.0V voltage reference on DM through use of
29.1K/48.5K resistor divider.
USB2_DP_DM_SHORT_ R/W
EN
Sets the port into China battery charger mode.
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Table 7.13 Upstream (Port 0) Battery Charging Control 2 Register
BC_CTL_2
(0x6101- RESET=0x00)
UPSTREAM (PORT 0) BATTERY CHARGING CONTROL 2
REGISTER
BIT
NAME
R/W
DESCRIPTION
7
BC_10_125K_PU_DP
R/W
Setting this bit enables a 125K pull-up to VDD33 on DP. This
is used for USB battery charging in 1.0 mode detection only.
6
5
BC_10_125K_PU_DM
LINESTATE_DP
R/W
R
Setting this bit enables a 125K pull-up to VDD33 on DM. This
is used for USB battery charging in 1.0 mode detection only.
This is the direct value of the Full-Speed USB line state Data
Plus. It is used for battery charging detection. This line is not
valid in HS mode and should only be used in battery charging
detection.
4
LINESTATE_DM
R
This is the direct value of the Full-Speed USB line state Data
Minus. It is used for battery charging detection. This line is not
valid in HS mode and should only be used for battery charging
detection.
3
USB2_FS_DP
USB2_FS_DM
Reserved
R
R
R
This is the raw Full-Speed single ended receiver output for
Data Plus
2
This is the raw Full-Speed single ended receiver output for
Data Minus
1:0
Always read ‘0’
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Table 7.14 Upstream (Port 0) Battery Charging Run Time Control Register
BC_CTL_RUN_TIME
(0x6102- RESET=0x00)
UPSTREAM (PORT 0) BATTERY CHARGING RUN TIME
CONTROL REGISTER
BIT
NAME
R/W
DESCRIPTION
7
6
Reserved
R
Always read ‘0
SUSPENDN
R/W
Suspend enable. Forces upstream port into suspend
0: Suspend disabled
1: Suspend enabled
5
RESET
R/W
R/W
R/W
R/W
R/W
Reset enable. Forces upstream port into reset
0: Reset disabled
1: Reset enabled
4
USB2_FS_OEB
RPD_DP_EN
RPD_DM_EN
XCVRSELECT
Output Enable (OE). Forces upstream port into output enable
0: OE disabled
1: OE enabled
3
Data plus resistor pull-down enable
0: Data plus pull-down disabled
1: Data plus pull-down enabled
2
Data minus resistor pull-down enable
0: Data minus pull-down disabled
1: Data minus pull-down enabled
1:0
Transceiver Select. This field selects between the LS, FS and
HS transceivers.
2'b00: HS mode
2'b01: FS mode
2'b10: LS mode
2'b11: LS data-rate with FS rise/fall times (and EOP/IDLE)
Note:
Note: XCVRSELECT must change state only when
the device is not actively transmitting or receiving
Table 7.15 Upstream (Port 0) Battery Charging Detect Register
UPSTREAM (PORT 0) BATTERY CHARGING DETECT
BC_CTL_DET
(0x6103- RESET=0x00)
REGISTER
BIT
NAME
R/W
DESCRIPTION
7:3
2
Reserved
R
Always read ‘0
USB2_BC_RXHI_EN
R/W
Enable pin for the Apple high current battery charger
detection.
1
0
USB2_BC_RXHI_DET
USB2_BC_BIAS_EN
R
Output pin for the Apple high current battery charger detection.
When disabled this output will be low.
R/W
When enabling USB2_IDAT_SINK_EN or
USB2_VDAT_SRC_EN of the Upstream (Port 0) Battery
Charging Control 1 Register, this register bit must be set to
enable the required current source.
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7.2.2
Run Time SMBus Page Register
The following run time SMBus page register is located at 0xFF and must be programmed to allow the
SOC to page through different pages of the register space.
Table 7.16 SMBus Page Register
SMBUS_PAGE
(0xFF(I2C) - RESET= 0x00)
SMBUS PAGE REGISTER
BIT
NAME
R/W
DESCRIPTION
7:5
PAGE_SEL
R/W
From the I2C side, this field allows the I2C to select the accessible address
space:
000 = Select registers in the 3000 space (0x30e2 - 0x30ee)
010 = Select registers in the 3100 space (0x318b,0x318e)
110 = Select register in the 6100 space (0x6100,0x6101,0x6102)
5:0
Reserved
R
Reserved.
Note:
Software must never write a ‘1’ to these bits
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Chapter 8 Functional Descriptions
This chapter provides additional functional descriptions of key device features.
8.1
Battery Charger Detection & Charging
The USB2533 supports both upstream battery charger detection and downstream battery charging.
The integrated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2)
detection method and most Apple devices. These circuits are used to detect the attachment and type
of a USB charger and provide an interrupt output to indicate charger information is available to be read
from the device’s status registers via the serial interface. The USB2533 provides the battery charging
handshake and supports the following USB-IF BC1.2 charging profiles:
DCP: Dedicated Charging Port (Power brick with no data)
CDP: Charging Downstream Port (1.5A with data)
SDP: Standard Downstream Port (0.5A with data)
Custom profiles loaded via SMBus or OTP
The following sub-sections detail the upstream battery charger detection and downstream battery
charging features.
8.1.1
Upstream Battery Charger Detection
Battery charger detection is available on the upstream facing port. The detection sequence is intended
to identify chargers which conform to the Chinese battery charger specification, chargers which
conform to the USB-IF Battery Charger Specification 1.2, and most Apple devices.
In order to detect the charger, the device applies and monitors voltages on the upstream DP and DM
pins. If a voltage within the specified range is detected, the will be updated to reflect the proper status.
The device includes the circuitry required to implement battery charging detection using the Battery
Charging Specification. When enabled, the device will automatically perform charger detection upon
entering the Hub.ChgDet stage in Hub Mode. The device includes a state machine to provide the
detection of the USB chargers listed in the table below. The type of charger detected is returned in the
CHARGER_TYPE field of the .
Table 8.1 Chargers Compatible with Upstream Detection
USB ATTACH TYPE
DP/DM PROFILE
CHARGERTYPE
DCP (Dedicated Charging Port)
CDP (Charging Downstream Port)
Shorted < 200ohm
001
VDP reflected to VDM
010
(EnhancedChrgDet = 1)
SDP
15Kohm pull-down on DP and DM
011
(Standard Downstream Port)
USB Host or downstream hub port
Apple Low Current Charger
Apple High Current Charger
Apple Super High Current Charger
Apple
Apple
100
101
110
DP=2.7V
DM=2.0V
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Table 8.1 Chargers Compatible with Upstream Detection (continued)
USB ATTACH TYPE
DP/DM PROFILE
CHARGERTYPE
Apple Charger Low Current Charger (500mA)
DP=2.0V
DM=2.0V
100
Apple Charger High Current Charger (1000mA)
DP=2.0V
DM=2.7V
101
If a custom charger detection algorithm is desired, the SMBus registers can also be used to control
the charger detection block to implement a custom charger detection algorithm. In order to avoid
negative interactions with automatic battery charger detection or normal hub operation, the user should
only attempt Custom battery charger detection during the Hub.Config stage or Hub.Connect stage. No
logic is implemented to disable custom detection at other times - it is up to the user software to observe
this restriction.
There is a possibility that the system is not running the reference clock when battery charger detection
is required (for example if the battery is dead or missing). During the Hub.WaitRefClk stage the battery
charger detection sequence can be configured to be followed regardless of the activity of REFCLK by
relying on the operation of the internal oscillator.
8.1.2
Downstream Battery Charging
The device can be configured by an OEM to have any of the downstream ports to support battery
charging. The Hub's role in battery charging is to provide an acknowledge to a device's query as to if
the hub system supports USB battery charging. The hub silicon does not provide any current or power
FETs or any additional circuitry to actually charge the device. Those components must be provided as
externally by the OEM.
DC Power
SMSC
Hub
PRTPWR[n]
VBUS[n]
Figure 8.1 Battery Charging External Power Supply
If the OEM provides an external supply capable of supplying current per the battery charging
specification, the hub can be configured to indicate the presence of such a supply to the device. This
indication, via the PRTPWR[1:4] output pins, is on a per/port basis. For example, the OEM can
configure two ports to support battery charging through high current power FET's and leave the other
two ports as standard USB ports.
8.1.2.1
Downstream Battery Charging Modes
In the terminology of the USB Battery Charging Specification, if a port is configured to support battery
charging, the downstream port is a considered a CDP (Charging Downstream Port) if connected to a
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USB host, or a DCP (Dedicated Charging Port) if not connected to a USB host. If the port is not
configured to support battery charging, the port is considered an SDP (Standard Downstream Port).
All charging ports have electrical characteristics different from standard non-charging ports.
A downstream port will behave as a CDP, DCP, or SDP depending on the port’s configuration and
mode of operation. The port will not switch between a CDP/DCP or SDP at any time after initial power-
up and configuration. A downstream port can be in one of three modes shown in the table below.
Table 8.2 Downstream Port Types
USB ATTACH TYPE
DP/DM PROFILE
DCP
Apple charging mode or
China Mode (Shorted < 200ohm) or
SMSC custom mode
(Dedicated Charging Port)
CDP
VDP reflected to VDM
(Charging Downstream Port)
SDP
15Kohm pull-down on DP and DM
(Standard Downstream Port)
USB Host or downstream hub port
8.1.2.2
8.1.2.3
Downstream Battery Charging Configuration
Configuration of ports to support battery charging is performed via the BC_EN configuration straps,
USB configuration, SMBus configuration, or OTP. The Battery Charging Enable Register provides per
port battery charging configuration. Starting from bit 1, this register enables battery charging for each
down stream port when asserted. Bit 1 represents port 1 and so on. Each port with battery charging
enabled asserts the corresponding PRTPWR register bit.
Downstream Over-Current Management
It is the devices responsibility to manage over-current conditions. Over-Current Sense (OCS) is
handled according to the USB specification. For battery charging ports, PRTPWR is driven high
(asserted) after hardware initialization. If an OCS event occurs, the PRTPWR is negated. PRTPWR
will be negated for all ports in a ganged configuration. Only the respective PRTPWR will be negated
in the individual configuration.
If there is an over-current event in DCP mode, the port is turned off for one second and is then re-
enabled. If the OCS event persists, the cycle is repeated for a total or three times. If after three
attempts, the OCS still persists, the cycle is still repeated, but with a retry interval of ten seconds. This
retry persists for indefinitely. The indefinite retry prevents a defective device from permanently disabling
the port.
In CDP or SDP mode, the port power and over-current events are controlled by the USB host. The
OCS event does not have to be registered. When and if the hub is connected to a host, the host will
initialize the hub and enable its port power. If the over current still exists, it will be notified at that point.
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8.2
Flex Connect
This feature allows the upstream port to be swapped with downstream physical port 1. Only
downstream port 1 can be swapped physically. Using port remapping, any logical port (number
assignment) can be swapped with the upstream port (non-physical).
Flex Connect is enabled/disabled via two control bits in the Connect Configuration Register. The
FLEXCONNECT configuration bit switches the port, and EN_FLEX_MODE enables the mode.
8.2.1
Port Control
Once EN_FLEX_MODE bit is set, the functions of certain pins change, as outlined below.
If EN_FLEX_MODE is set and FLEXCONNECT is not set:
1. PRTPWR1 enters combined mode, becoming PRTPWR1/OCS1_N
2. OCS1_N becomes a don’t care
3. SUSPEND outputs ‘0’ to keep any upstream power controller off
If EN_FLEX_MODE is set and FLEXCONNECT is set:
1. The normal upstream VBUS pin becomes a don’t care
2. PRTPWR1 is forced to a ‘1’ in combined mode, keeping the port power on to the application
processor.
3. OCS1 becomes VBUS from the application processor through a GPIO
4. SUSPEND becomes PRTPWR1/OCS1_N for the port power controller for the connector port
8.3
Resets
The device has the following chip level reset sources:
Power-On Reset (POR)
External Chip Reset (RESET_N)
USB Bus Reset
8.3.1
8.3.2
Power-On Reset (POR)
A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and
reapplied to the device. A timer within the device will assert the internal reset per the specifications
listed in Section 9.5.1, "Power-On Configuration Strap Valid Timing," on page 56.
External Chip Reset (RESET_N)
A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within
operating range, per the specifications in Section 9.5.2, "Reset and Configuration Strap Timing," on
page 57. While reset is asserted, the device (and its associated external circuitry) enters Standby Mode
and consumes minimal current.
Assertion of RESET_N causes the following:
1. The PHY is disabled and the differential pairs will be in a high-impedance state.
2. All transactions immediately terminate; no states are saved.
3. All internal registers return to the default state.
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4. The external crystal oscillator is halted.
5. The PLL is halted.
Note: All power supplies must have reached the operating levels mandated in Section 9.2, "Operating
Conditions**," on page 53, prior to (or coincident with) the assertion of RESET_N.
8.3.3
USB Bus Reset
In response to the upstream port signaling a reset to the device, the device performs the following:
Note: The device does not propagate the upstream USB reset to downstream devices.
1. Sets default address to 0.
2. Sets configuration to: Unconfigured.
3. Moves device from suspended to active (if suspended).
4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the
reset sequence.
The host then configures the device in accordance with the USB Specification.
8.4
Link Power Management (LPM)
The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per
the USB 2.0 Link Power Management Addendum. These supported LPM states offer low transitional
latencies in the tens of microseconds versus the much longer latencies of the traditional USB
suspend/resume in the tens of milliseconds. The supported LPM states are detailed in Table 8.3. For
additional information, refer to the USB 2.0 Link Power Management Addendum.
Table 8.3 LPM State Definitions
STATE
DESCRIPTION
ENTRY/EXIT TIME TO L0
Entry: ~3 ms
L2
L1
L0
Suspend
Sleep
Exit: ~2 ms
Entry: ~65 us
Exit: ~100 us
Fully Enabled (On)
-
Note: State change timing is approximate and is measured by change in power consumption.
Note: System clocks are stopped only in suspend mode or when power is removed from the device.
8.5
Remote Wakeup Indicator (SUSP_IND)
The remote wakeup indicator feature uses the SUSP_IND as a side band signal to wake up the host
when in suspend. This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration
bit in the hub configuration space register CFG3. The only way to control the bit is by configuration
EEPROM, SMBus or internal ROM default setting. The state is only modified during a power on reset,
or hardware reset. No dynamic reconfiguring of this capability is possible.
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When HUB_RESUME_INHIBIT = ‘0’, Normal Resume Behavior per the USB 2.0 specification
When HUB_RESUME_INHIBIT = ‘1’, Modified Resume Behavior is enabled
Refer to the following subsections for additional details.
8.5.1
Normal Resume Behavior
VBUS_DET is used to detect presence of the Host. If VBUS_DET = ‘1’, then D+ pull-up is asserted
and normal USB functionality is enabled. The SUSP_IND provides an indication of the active or
suspended state of the hub.
The Hub will drive a ‘K’ on the upstream port if required to do so by USB protocol.
If VBUS_DET = ‘0’, then the D+ pull-up is negated. If battery charging is not enabled, the internal hub
logic will be reset, thus negating all downstream ports and associated downstream VBUS enable
signals. The hub will need to be re-enumerated to function, much like a new connect or after a
complete system reset.
8.5.2
Modified Resume Behavior
When the modified resume feature is enabled, the hub functions as follows:
VBUS_DET is used to detect presence of the Host. If VBUS_DET = ‘1’, then D+ pull-up is asserted
and normal USB functionality is enabled. SUSP_IND provides an indication of the active or suspended
state of the hub.
The device will drive a ‘K’ on the upstream port and downstream ports if required to do so by USB
protocol. The device will act as a controlling hub if required to do so by the USB protocol.
If VBUS_DET = ‘0’, then the D+ pull-up is negated, but the hub will not be internally reset. It will power-
on the downstream ports. The hub is able to continue to detect downstream remote wake events.
SUSP_IND provides an indication of the active or suspended state of the hub.
If a USB 2.0 specification compliant resume or wake event is detected by the device, the device is
remote wake enabled, and a port status change event occurs, SUSP_IND will be driven for the time
given in the GLOBAL_RESUME_TIME register.
If a remote wake event is detected on a downstream port:
1. Device disconnect
2. Device connect
3. A currently connected device requests remote wake-up.
Note: Downstream resume events are filtered for approximately 100uS by internal logic.
The device will not drive a ‘K’ on the upstream port. Instead, the SUSP_IND will be driven for
approximately 14 ms. The ‘K’ is not driven upstream because this would potentially back drive a
powered-down host. The device will drive RESUME to only the downstream ports which transmitted
the remote wake signal per the requirements of the USB 2.0 specification for controlling hub behavior.
Note: SUSP_IND is a one shot event. It will assert with each wake event detection. It will not
repeatedly assert in proxy for downstream devices.
For the case where the Host responds and turns on VBUS and can drive a ‘K’ downstream within the
14 ms time frame of a standard resume (measured from the SUSP_IND pin), then the hub detects the
‘K’. It will discontinue “Controlling Hub” activities, drive resume signaling on any other ports, and
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function as expected per the USB 2.0 Specification with respect to a resume event. It will permit the
host to take over resume signaling.
For the case where the host is not able to drive a ‘K’ within the 14 ms time frame, the hub will stop
sending a ‘K’ on the upstream and downstream ports. It must follow through as a controlling hub and
properly terminate the resume with either an EOP or with HS terminations as is currently implemented
in the selective resume case, per the USB specification.
8.6
High Speed Indicator (HS_IND)
The HS_IND pin can be used to drive an LED. The active state of the LED will be determined as
follows:
If CFG_SEL1 = ‘0’, HS_IND is active high.
If CFG_SEL1 = ‘1’, then HS_IND is active low.
Assertion of HS_IND indicates the device is connected at high speed. Negation of HS_IND indicates
the device is connected at full speed.
Note: This pin shares functionality with the CFG_SEL1 configuration strap. The logic state of this pin
is internally latched on the rising edge of RESET_N (RESET_N negation), and is used to
determine the hub configuration method. Refer to Section 6.3.2, "Configuration Select
(CFG_SEL[1:0])," on page 29 for additional information.
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Chapter 9 Operational Characteristics
9.1
Absolute Maximum Ratings*
+3.3 V Supply Voltage (VDD33, VDDA33) (Note 9.1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +3.6 V
Positive voltage on input signal pins, with respect to ground (Note 9.2) . . . . . . . . . . . . . . . . . . . . 3.6 V
Negative voltage on input signal pins, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V
Positive voltage on XTAL1/REFCLK, with respect to ground . . . . . . . . . . . . . . . . . . . . . . . . .VDDCR12
Positive voltage on USB DP/DM signals, with respect to ground (Note 9.3) . . . . . . . . . . . . . . . . . 5.5 V
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55oC to +150oC
Lead Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Refer to JEDEC Spec. J-STD-020
HBM ESD Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..JEDEC Class 3A
Note 9.1 When powering this device from laboratory or system power supplies, it is important that
the absolute maximum ratings not be exceeded or device failure can result. Some power
supplies exhibit voltage spikes on their outputs when AC power is switched on or off. In
addition, voltage transients on the AC power line may appear on the DC output. If this
possibility exists, it is suggested to use a clamp circuit.
Note 9.2 This rating does not apply to the following signals: All USB DM/DP pins, XTAL1/REFCLK,
XTAL2.
Note 9.3 This rating applies only when VDD33 is powered.
*Stresses exceeding those listed in this section could cause permanent damage to the device. This is
a stress rating only. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability. Functional operation of the device at any condition exceeding those indicated in
Section 9.2, "Operating Conditions**", Section 9.4, "DC Specifications", or any other applicable section
of this specification is not implied. Note, device signals are NOT 5 volt tolerant unless specified
otherwise.
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9.2
Operating Conditions**
+3.3 V Supply Voltage (VDD33, VDDA33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +3.0 V to 3.6 V
Power Supply Rise Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.4
Ambient Operating Temperature in Still Air (TA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Note 9.5
Note 9.4 The power supply rise time requirements vary dependent on the usage of the external
reset (RESET_N). If RESET_N is asserted at power-on, the power supply rise time must
be 10mS or less (tRT(max) = 10mS). If RESET_N is not used at power-on (tied high), the
power supply rise time must be 1mS or less (tRT(max) = 1mS). Figure 9.1 illustrates the
supply rise time requirements.
Note 9.5 0oC to +70oC for commercial version, -40oC to +85oC for industrial version.
**Proper operation of the device is guaranteed only within the ranges specified in this section.
Voltage
tRT
3.3V
100%
VDDA33
90%
10%
VSS
t90%
Time
t10%
Figure 9.1 Supply Rise Time Model
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9.3
Power Consumption
This section details the power consumption of the device as measured during various modes of
operation. Power dissipation is determined by temperature, supply voltage, and external source/sink
requirements.
9.3.1
Operational / Unconfigured
Table 9.1 Operational/Unconfigured Power Consumption
TYPICAL (mA)
VDD33
MAXIMUM (mA)
VDD33
HS Host / 1 HS Device
HS Host / 2 HS Devices
HS Host / 3 HS Devices
HS Host / 1 FS Device
HS Host / 2 FS Devices
HS Host / 3 FS Devices
Unconfigured
65
95
75
110
145
50
60
70
-
125
45
50
55
30
9.3.2
Suspend / Standby
Table 9.2 Suspend/Standby Power Consumption
MODE
SYMBOL
TYPICAL @ 25oC
COMMERCIAL
MAX
INDUSTRIAL
UNIT
MAX
Suspend
Standby
IVDD33
IVDD33
320
75
1250
130
1750
140
uA
uA
Note: Typical values measured with VDD33 = 3.3V. Maximum values measured with VDD33 = 3.6V.
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9.4
DC Specifications
Table 9.3 DC Electrical Characteristics
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
IS Type Input Buffer
Low Input Level
VIL
VIH
-0.3
2.0
0.8
3.6
V
V
High Input Level
I_RST Type Input Buffer
Low Input Level
VIL
VIH
-0.3
0.4
3.6
V
V
High Input Level
1.25
I_SMB Type Input Buffer
Low Input Level
VIL
VIH
-0.3
0.35
3.6
V
V
High Input Level
1.25
O8 Type Buffers
Low Output Level
High Output Level
OD8 Type Buffer
Low Output Level
OD12 Type Buffer
Low Output Level
VOL
VOH
0.4
V
V
IOL = 8 mA
IOH = -8 mA
VDD33 - 0.4
VOL
0.4
0.4
V
V
IOL = 8 mA
VOL
IOL = 12 mA
ICLK Type Buffer
(XTAL1/REFCLK Input)
Low Input Level
High Input Level
VIL
VIH
-0.3
0.8
0.35
V
V
VDDCR12
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9.5
AC Specifications
This section details the various AC timing specifications of the device.
9.5.1
Power-On Configuration Strap Valid Timing
Figure 9.2 illustrates the configuration strap timing requirements, in relation to power-on, for
applications where RESET_N is not used at power-on. The operational level (Vopp) for the external
power supply is detailed in Section 9.2, "Operating Conditions**," on page 53.
Note: For RESET_N configuration strap timing requirements, refer to Section 9.5.2, "Reset and
Configuration Strap Timing," on page 57.
External Power
Supply
Vopp
tcsh
Configuration
Straps
Figure 9.2 Power-On Configuration Strap Valid Timing
Table 9.4 Power-On Configuration Strap Valid Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
tcsh
Configuration strap hold after external power supply at
operational level
1
ms
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9.5.2
Reset and Configuration Strap Timing
Figure 9.3 illustrates the RESET_N timing requirements and its relation to the configuration strap
signals. Assertion of RESET_N is not a requirement. However, if used, it must be asserted for the
minimum period specified.
Refer to Section 8.3, "Resets," on page 48 for additional information on resets. Refer to Section 6.3,
"Device Configuration Straps," on page 29 for additional information on configuration straps.
trstia
RESET_N
tcsh
Configuration
Straps
Figure 9.3 RESET_N Configuration Strap Timing
Table 9.5 RESET_N Configuration Strap Timing
SYMBOL
DESCRIPTION
MIN
TYP
MAX
UNITS
trstia
tcsh
RESET_N input assertion time
5
1
us
Configuration strap hold after RESET_N deassertion
ms
9.5.3
USB Timing
All device USB signals conform to the voltage, power, and timing characteristics/specifications as set
forth in the Universal Serial Bus Specification. Please refer to the Universal Serial Bus Specification,
Revision 2.0, available at http://www.usb.org.
9.5.4
9.5.5
SMBus Timing
All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as
set forth in the System Management Bus Specification. Please refer to the System Management Bus
Specification, Version 1.0, available at http://smbus.org/specs.
2
I C Timing
All device I2C signals conform to the 100KHz Standard Mode (Sm) voltage, power, and timing
characteristics/specifications as set forth in the I2C-Bus Specification. Please refer to the I2C-Bus
Specification, available at http://www.nxp.com.
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9.6
Clock Specifications
The device can accept either a 24 MHz crystal or a 24 MHz single-ended clock oscillator input. If the
single-ended clock oscillator method is implemented, XTAL1 should be left unconnected and REFCLK
should be driven with a clock that adheres to the specifications outlined in Section 9.6.2, "External
Reference Clock (REFCLK)".
9.6.1
Oscillator/Crystal
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal
input/output signals (XTAL1I/XTAL2). See Table 9.6 for the recommended crystal specifications.
Table 9.6 Crystal Specifications
PARAMETER
SYMBOL
MIN
NOM
MAX
UNITS
NOTES
Crystal Cut
AT, typ
Fundamental Mode
Parallel Resonant Mode
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Ffund
-
24.000
-
MHz
PPM
oC
Total Allowable PPM Budget
Operating Temperature Range
-
-
-
+/-350
Note 9.7
Note 9.6
Note 9.6 0oC for commercial version, -40oC for industrial version.
Note 9.7 +70oC for commercial version, +85oC for industrial version.
9.6.2
External Reference Clock (REFCLK)
The following input clock specifications are suggested:
50% duty cycle 10%
24 MHz 350 PPM
Note: The external clock is recommended to conform to the signalling levels designated in the
JEDEC specification on 1.2V CMOS Logic. XTAL2 should be treated as a no connect when an
external clock is supplied.
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Chapter 10 Package Outline
Figure 10.1 36-SQFN Package Drawing
Table 10.1 36-SQFN Package Dimensions
MIN
NOMINAL
MAX
REMARKS
A
A1
D/E
D2/E2
L
b
k
ccc
e
0.80
0
0.90
0.02
6.00
3.70
0.60
0.25
0.55
-
1.00
0.05
6.10
3.80
0.75
0.30
-
Overall Package Height
Standoff
X/Y Body Size
X/Y Exposed Pad Size
Terminal Length
5.90
3.60
0.50
0.18
0.45
-
Terminal Width
Terminal to Exposed Pad Clearance
Coplanarity
0.08
0.50 BSC
Terminal Pitch
Notes:
1. All dimensions are in millimeters unless otherwise noted.
2. Dimension “b” applies to plated terminals and is measured between 0.15 and 0.30 mm from the terminal tip.
3. The pin 1 identifier may vary, but is always located within the zone indicated.
4. Coplanarity zone applies to exposed pad and terminals.
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Figure 10.2 36-SQFN Package Recommended Land Pattern
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Chapter 11 Datasheet Revision History
Table 11.1 Revision History
REVISION LEVEL
& DATE
SECTION/FIGURE/ENTRY
Initial Release
CORRECTION
Rev. 1.0
(06-17-13)
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