USB2534-1051AEN-TR_技术文档

USB2534

USB 2.0 Hi-Speed 4-Port Hub Controller

Highlights

Additional Features

• Hub Controller IC with 4 downstream ports

• MultiTRAK^™

• USB-IF Battery Charger revision 1.2 support on

up & downstream ports (DCP, CDP, SDP)

- Dedicated Transaction Translator per port

• PortMap



• Battery charging support for Apple devices

- Configurable port mapping and disable

sequencing

• FlexConnect: Downstream port 1 able to swap

with upstream port, allowing master capable

devices to control other devices on the hub

• USB to I²C bridge endpoint support

• PortSwap

- Configurable differential intra-pair signal

swapping

• PHYBoost^™

• USB Link Power Management (LPM) support

• SUSPEND pin for remote wakeup indication to

host

- Programmable USB transceiver drive

strength for recovering signal integrity

• VariSense^™

• Vendor Specific Messaging (VSM) support

• Enhanced OEM configuration options available

through a single serial I²C EEPROM, OTP, or

SMBus Slave Port

- Programmable USB receiver sensitivity

• Low power operation

• Full Power Management with individual or ganged

power control of each downstream port

• 36-pin (6x6mm) SQFN, RoHS compliant package

• Footprint compatible with USB2514B

• Built-in Self-Powered or Bus-Powered internal

default settings provide flexibility in the quantity of

USB expansion ports utilized without redesign

Target Applications

• Supports “Quad Page” configuration OTP flash

• LCD monitors and TVs

• Multi-function USB peripherals

• PC mother boards

- Four consecutive 200 byte configuration

pages

• Fully integrated USB termination and Pull-up/Pull-

down resistors

• Set-top boxes, DVD players, DVR/PVR

• Printers and scanners

• PC media drive bay

• On-chip Power On Reset (POR)

• Internal 3.3V and 1.2V voltage regulators

• Portable hub boxes

• On Board 24MHz Crystal Driver, Resonator, or

External 24MHz clock input

• Mobile PC docking

• Embedded systems

• Environmental

- Commercial temperature range support (0ºC

to 70ºC)

- Industrial temperature range support (-40ºC

to 85ºC)

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 1

USB2534

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-

rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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DS00001713B-page 2

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USB2534

Table of Contents

1.0 Introduction ..................................................................................................................................................................................... 4

2.0 Acronyms and Definitions ............................................................................................................................................................... 6

3.0 Pin Descriptions .............................................................................................................................................................................. 7

4.0 Power Connections ....................................................................................................................................................................... 17

5.0 Modes of Operation ...................................................................................................................................................................... 18

6.0 Device Configuration ..................................................................................................................................................................... 22

7.0 Device Interfaces .......................................................................................................................................................................... 26

8.0 Functional Descriptions ................................................................................................................................................................. 28

9.0 Operational Characteristics ........................................................................................................................................................... 33

10.0 Package Outline

................................................................................................................................................................................................... 39

Appendix A: Data sheet Revision History ........................................................................................................................................... 40

The Microchip Web Site ...................................................................................................................................................................... 41

Customer Change Notification Service ............................................................................................................................................... 41

Customer Support ............................................................................................................................................................................... 41

Product Identification System ............................................................................................................................................................. 42

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 3

USB2534

1.0

INTRODUCTION

The USB2534 is a low-power, OEM configurable, MTT (Multi-Transaction Translator) USB 2.0 hub controller with 4

downstream ports and advanced features for embedded USB applications. The USB2534 is fully compliant with the

USB 2.0 Specification, USB 2.0 Link Power Management Addendum and will attach to an upstream port as a Full-Speed

hub or as a Full-/Hi-Speed hub. The 4-port hub supports Low-Speed, Full-Speed, and Hi-Speed (if operating as a Hi-

Speed hub) downstream devices on all of the enabled downstream ports.

The USB2534 has been specifically optimized for embedded systems where high performance, and minimal BOM costs

are critical design requirements. Standby mode power has been minimized and reference clock inputs can be aligned

to the customer’s specific application. Additionally, all required resistors on the USB ports are integrated into the hub,

including all series termination and pull-up/pull-down resistors on the D+ and D– pins.

The USB2534 supports both upstream battery charger detection and downstream battery charging. The USB2534 inte-

grated battery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most

Apple devices. These circuits are used to detect the attachment and type of a USB charger and provide an interrupt

output to indicate charger information is available to be read from the device’s status registers via the serial interface.

The USB2534 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:

• DCP: Dedicated Charging Port (Power brick with no data)

• CDP: Charging Downstream Port (1.5A with data)

• SDP: Standard Downstream Port (0.5A with data)

• Custom profiles loaded via SMBus or OTP

The USB2534 provides an additional USB endpoint dedicated for use as a USB to I²C interface, allowing external cir-

cuits or devices to be monitored, controlled, or configured via the USB interface. Additionally, the USB2534 includes

many powerful and unique features such as:

FlexConnect, which provides flexible connectivity options. The USB2534’s downstream port 1 can be swapped with

the upstream port, allowing master capable devices to control other devices on the hub.

MultiTRAK^™Technology, which utilizes a dedicated Transaction Translator (TT) per port to maintain consistent full-

speed data throughput regardless of the number of active downstream connections. MultiTRAK^TMoutperforms conven-

tional USB 2.0 hubs with a single TT in USB full-speed data transfers.

PortMap, which provides flexible port mapping and disable sequences. The downstream ports of a USB2534 hub can

be reordered or disabled in any sequence to support multiple platform designs with minimum effort. For any port that is

disabled, the USB2534 hub controllers automatically reorder the remaining ports to match the USB host controller’s port

numbering scheme.

PortSwap, which adds per-port programmability to USB differential-pair pin locations. PortSwap allows direct alignment

of USB signals (D+/D-) to connectors to avoid uneven trace length or crossing of the USB differential signals on the

PCB.

PHYBoost, which provides programmable levels of Hi-Speed USB signal drive

strength in the downstream port transceivers. PHYBoost attempts to restore USB sig-

nal integrity in a compromised system environment. The graphic on the right shows

an example of Hi-Speed USB eye diagrams before and after PHYBoost signal integ-

rity restoration.

VariSense, which controls the USB receiver sensitivity enabling programmable lev-

els of USB signal receive sensitivity. This capability allows operation in a sub-optimal

system environment, such as when a captive USB cable is used.

The USB2534 is available in commercial (0°C to +70°C) and industrial (-40°C to +85°C) temperature range versions.

DS00001713B-page 4

 2012 - 2019 Microchip Technology Inc.

USB2534

1.1

Block Diagram

Figure 1-1 details the internal block diagram of the USB2534.

FIGURE 1-1:

SYSTEM BLOCK DIAGRAM

Up or

Downstream

To I²C Master/Slave

SDA SCL

VDDA33

RESET_N

USB

VDDCR12

Serial

Interface

1.2V Reg

3.3V Reg

Flex PHY

Repeater

Controller

SIE

TT #1 TT #2 TT #3 TT #4 TT #5 Port Controller

2KB

UDC

Port Power

OCS

Bridge

Routing & Port Re-Ordering Logic

DP

20

SRAM

GPIO

256B

IRAM

8051

Controller

Swap PHY

PHY

2KB

OTP

4KB

SRAM ROM

32KB

USB

Down or

Upstream

USB

Downstream Downstream Downstream

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DS00001713B-page 5

USB2534

2.0

2.1

ACRONYMS AND DEFINITIONS

Acronyms

EOP:

EP:

End of Packet

Endpoint

FS:

Full-Speed

GPIO: General Purpose I/O (that is input/output to/from the device)

HS: Hi-Speed

HSOS: High Speed Over Sampling

I²C:

Inter-Integrated Circuit

Low-Speed

LS:

OTP:

PCB:

PCS:

PHY:

One Time Programmable

Printed Circuit Board

Physical Coding Sublayer

Physical Layer

SMBus: System Management Bus

UUID: Universally Unique IDentification

2.2

Reference Documents

1. UNICODE UTF-16LE For String Descriptors USB Engineering Change Notice, December 29th, 2004, http://

www.usb.org

2. Universal Serial Bus Specification, Revision 2.0, April 27th, 2000, http://www.usb.org

3. Battery Charging Specification, Revision 1.2, Dec. 07, 2010, http://www.usb.org

4. I²C-Bus Specification, Version 1.1, http://www.nxp.com

5. System Management Bus Specification, Version 1.0, http://smbus.org/specs

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USB2534

3.0

PIN DESCRIPTIONS

FIGURE 3-1:

36-SQFN PIN ASSIGNMENTS

SUSP_IND/LOCAL_PWR/NON_REM0

28

29

30

31

32

33

34

35

36

18

17

16

15

14

13

12

11

10

PRTPWR3/PRTCTL3/BC_EN3

VDDA33

FLEX_USBUP_DM

FLEX_USBUP_DP

XTAL2

OCS2_N

PRTPWR2/PRTCTL2/BC_EN2

VDD33

USB2534

(Top View)

VDDCR12

XTAL1/REFCLK

NC

OCS1_N

PRTPWR1/PRTCTL1/BC_EN1

Ground Pad

(must be connected to VSS)

RBIAS

LED0

VDDA33

Indicates pins on the bottom of the device.

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 7

USB2534

3.1

Pin Descriptions

This section provides a detailed description of each pin. The signals are arranged in functional groups according to their

associated interface.

The “_N” symbol in the signal name indicates that the active, or asserted, state occurs when the signal is at a low voltage

level. For example, RESET_N indicates that the reset signal is active low. When “_N” is not present after the signal

name, the signal is asserted when at the high voltage level.

The terms assertion and negation are used exclusively. This is done to avoid confusion when working with a mixture of

“active low” and “active high” signals. The term assert, or assertion, indicates that a signal is active, independent of

whether that level is represented by a high or low voltage. The term negate, or negation, indicates that a signal is inac-

tive.

Note:

The buffer type for each signal is indicated in the BUFFER TYPE column of Table 3-1. A description of the

buffer types is provided in Section 3.3.

Note:

Compatibility with the UCS100x family of USB port power controllers requires the UCS100x be connected

on Port 1 of the USB2534. Additionally, both PRTPWR1 and OCS1_N must be pulled high at Power-On

Reset (POR).

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS

Buffer

Type

Name

Symbol

Description

USB/HSIC INTERFACES

FLEX_USBUP_DP

Upstream USB

D+

(Flex Port 0)

AIO

IS

Upstream USB Port 0 D+ data signal.

Note:

The upstream Port 0 signals can be

1

optionally swapped with the down-

stream Port 1 signals.

FLEX_USBUP_DM

SWAP_USBDN1_DP

Upstream USB

D-

(Flex Port 0)

Upstream USB Port 0 D- data signal.

Note: The upstream Port 0 signals can be

optionally swapped with the down-

stream Port 1 signals.

Downstream

USB D+

(Swap Port 1)

Downstream USB Port 1 D+ data signal.

Note:

The downstream Port 1 signals can be

optionally swapped with the upstream

Port 0 signals.

Port 1 D+

Disable

PRT_DIS_P1

This strap is used in conjunction with

PRT_DIS_M1 to disable USB Port 1.

Configuration

Strap

1

0 = Port 1 D+ Enabled

1 = Port 1 D+ Disabled

Note:

Both PRT_DIS_P1 and PRT_DIS_M1

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

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USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

SWAP_USBDN1_DM

Downstream

USB D-

(Swap Port 1)

AIO

Downstream USB Port 1 D- data signal.

Note: The downstream Port 1 signals can be

optionally swapped with the upstream

Port 0 signals.

Port 1 D-

Disable

PRT_DIS_M1

IS

This strap is used in conjunction with PRT_DIS_P1

to disable USB Port 1.

Configuration

Strap

1

0 = Port 1 D- Enabled

1 = Port 1 D- Disabled

Note:

Both PRT_DIS_P1 and PRT_DIS_M1

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

Downstream

USB D+

(Port 2)

USBDN2_DP

PRT_DIS_P2

AIO

IS

Downstream USB Port 2 D+ data signal.

Port 2 D+

Disable

This strap is used in conjunction with

PRT_DIS_M2 to disable USB Port 2.

Configuration

Strap

0 = Port 2 D+ Enabled

1 = Port 2 D+ Disabled

1

Note:

Both PRT_DIS_P2 and PRT_DIS_M2

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

Downstream

USB D-

(Port 2)

USBDN2_DM

PRT_DIS_M2

AIO

IS

Downstream USB Port 2 D- data signal.

Port 2 D-

Disable

Configuration

Strap

This strap is used in conjunction with PRT_DIS_P2

to disable USB Port 2.

0 = Port 2 D- Enabled

1 = Port 2 D- Disabled

Note:

Both PRT_DIS_P2 and PRT_DIS_M2

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

Downstream

USB D+

(Port 3)

USBDN3_DP

PRT_DIS_P3

AIO

IS

Downstream USB Port 3 D+ data signal.

Port 3 D+

Disable

Configuration

Strap

This strap is used in conjunction with

PRT_DIS_M3 to disable USB Port 3.

0 = Port 3 D+ Enabled

1 = Port 3 D+ Disabled

Note:

Both PRT_DIS_P3 and PRT_DIS_M3

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 9

USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

Downstream

USB D-

USBDN3_DM

AIO

Downstream USB Port 3 D- data signal.

(Port 3)

Port 3 D-

Disable

PRT_DIS_M3

IS

This strap is used in conjunction with PRT_DIS_P3

to disable USB Port 3.

Configuration

Strap

0 = Port 3 D- Enabled

1 = Port 3 D- Disabled

1

Note:

Both PRT_DIS_P3 and PRT_DIS_M3

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

Downstream

USB D+

(Port 4)

USBDN4_DP

PRT_DIS_P4

AIO

IS

Downstream USB Port 4 D+ data signal.

Port 4 D+

Disable

Configuration

Strap

This strap is used in conjunction with

PRT_DIS_M4 to disable USB Port 4.

0 = Port 4 D+ Enabled

1 = Port 4 D+ Disabled

Note:

Both PRT_DIS_P4 and PRT_DIS_M4

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

Downstream

USB D-

(Port 4)

USBDN4_DM

PRT_DIS_M4

AIO

IS

Downstream USB Port 4 D- data signal.

Port 4 D-

Disable

Configuration

Strap

This strap is used in conjunction with PRT_DIS_P4

to disable USB Port 4.

0 = Port 4 D- Enabled

1 = Port 4 D- Disabled

Note:

Both PRT_DIS_P4 and PRT_DIS_M4

must be tied to VDD33 at reset to dis-

able the associated port.

See Note 3-3 for more information on configuration

straps.

I²C/SMBUS INTERFACE

I²C Serial

Clock Input

SCL

I_SMB

I²C serial clock input

SMBus Clock

SMBCLK

I_SMB

SMBus serial clock input

Configuration

Select 0

Configuration

Strap

CFG_SEL0

This strap is used in conjunction with CFG_SEL1

to set the hub configuration method. Refer to

Section 6.3.2, "Configuration Select

(CFG_SEL[1:0])," on page 25 for additional

information.

See Note 3-3 for more information on configuration

straps.

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USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

I²C bidirectional serial data

I²C Serial Data

SDA

IS/OD8

SMBus Serial

Data

SMBDATA

SMBus bidirectional serial data

Non-

Removable

Device 1

Configuration

Strap

NON_REM1

(Note 3-2)

IS

This strap is used in conjunction with NON_REM0

to configure the downstream ports as non-

removable devices. Refer to Section 6.3.1, "Non-

Removable Device (NON_REM[1:0])," on page 24

for additional information.

1

See Note 3-3 for more information on configuration

straps.

MISC.

Port 1 Over-

Current Sense

Input

OCS1_N

OCS2_N

UART_RX

IS

(PU)

This active-low signal is input from an external

current monitor to indicate an over-current

condition on USB Port 1.

1

Port 2 Over-

Current Sense

Input

IS

(PU)

This active-low signal is input from an external

current monitor to indicate an over-current

condition on USB Port 2.

UART Receive

Input

IS

Internal UART receive input

Note:

This is a 3.3V signal. For RS232 opera-

tion, an external 12V translator is

required.

1

Port 3 Over-

Current Sense

Input

OCS3_N

IS

(PU)

This active-low signal is input from an external

current monitor to indicate an over-current

condition on USB Port 3.

UARTTransmit

Output

UART_TX

O8

Internal UART transmit output

Note:

This is a 3.3V signal. For RS232 opera-

tion, an external 12V driver is required.

Port 4 Over-

Current Sense

Input

OCS4_N

IS

(PU)

This active-low signal is input from an external

current monitor to indicate an over-current

condition on USB Port 4.

System Reset

Input

RESET_N

I_RST

This active-low signal allows external hardware to

reset the device.

Note:

The active-low pulse must be at least

5us wide. Refer to Section 8.3.2, "Exter-

nal Chip Reset (RESET_N)," on

page 30 for additional information.

1

Crystal Input

XTAL1

ICLK

External 24 MHz crystal input

Reference

Clock Input

REFCLK

Reference clock input. The device may be

alternatively driven by a single-ended clock

oscillator. When this method is used, XTAL2

should be left unconnected.

1

Crystal Output

XTAL2

RBIAS

OCLK

AI

External 24 MHz crystal output

External USB

Transceiver

Bias Resistor

A 12.0k (+/- 1%) resistor is attached from ground

to this pin to set the transceiver’s internal bias

settings.

LED 0 Output

LED0

O8

General purpose LED 0 output that is configurable

to blink or “breathe” at various rates.

1

Note:

LED0 must be enabled via the Protouch

configuration tool.

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DS00001713B-page 11

USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

Detect

VBUS_DET

IS

Detects state of upstream bus power.

Upstream

VBUS Power

When designing a detachable hub, this pin must

be connected to the VBUS power pin of the

upstream USB port through a resistor divider

(50k by 100k) to provide 3.3V.

For self-powered applications with a permanently

attached host, this pin must be connected to either

3.3V or 5.0V through a resistor divider to provide

3.3V.

1

In embedded applications, VBUS_DET may be

controlled (toggled) when the host desires to

renegotiate a connection without requiring a full

reset of the device.

Remote

Wakeup

Indicator

SUSP_IND

OD8

Configurable sideband signal used to indicate

Suspend status (default) or Remote Wakeup

events to the Host.

Suspend Indicator (default configuration):

0 = Unconfigured, or configured and in USB

suspend mode

1 = Device is configured and is active

(i.e., not in suspend)

For Remote Wakeup Indicator mode:

Refer to Section 8.5, "Remote Wakeup Indicator

(SUSP_IND)," on page 31.

Refer to Section 6.3.1, "Non-Removable Device

(NON_REM[1:0])," on page 24 for information on

LED polarity when using this signal.

1

Local Power

Detect

LOCAL_PWR

IS

Detects the availability of a local self-power

source.

0 = Self/local power source is NOT available. (i.e.,

device must obtain all power from upstream USB

VBUS)

1 = Self/local power source is available

See Note 3-1 for more information on this pin.

Non-

Removable

Device 0

Configuration

Strap

NON_REM0

(Note 3-2)

This strap is used in conjunction with NON_REM1

to configure the downstream ports as non-

removable devices. Refer to Section 6.3.1, "Non-

Removable Device (NON_REM[1:0])," on page 24

for additional information.

See Note 3-3 for more information on configuration

straps.

DS00001713B-page 12

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USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

High Speed

Indicator

HS_IND

O8

Indicates a high speed connection on the upstream

port. The active state of the LED will be

determined as follows:

If CFG_SEL1 = 0, HS_IND is active high.

If CFG_SEL1 = 1, HS_IND is active low.

Asserted = hub is connected at high speed

Negated = Hub is connected at full speed

1

Configuration

Select 1

Configuration

Strap

CFG_SEL1

IS

This strap is used in conjunction with CFG_SEL0

to set the hub configuration method. Refer to

Section 6.3.2, "Configuration Select

(CFG_SEL[1:0])," on page 25 for additional

information.

See Note 3-3 for more information on configuration

straps.

Port 1 Power

Output

PRTPWR1

PRTCTL1

BC_EN1

O8

Enables power to a downstream USB device

attached to Port 1.

0 = Power disabled on downstream Port 1

1 = Power enabled on downstream Port 1

Port 1 Control

OD8/IS

(PU)

When configured as PRTCTL1, this pin functions

as both the Port 1 power enable output

(PRTPWR1) and the Port 1 over-current sense

input (OCS1_N). Refer to the PRTPWR1 and

OCS1_N descriptions for additional information.

1

Port 1 Battery

Charging

Configuration

Strap

IS

This strap is used to indicate support of the battery

charging protocol on Port 1. Enabling battery

charging support allows a device on the port to

draw currents per the USB battery charging

specification.

0 = Battery charging is not supported on Port 1

1 = Battery charging is supported on Port 1

See Note 3-3 for more information on configuration

straps.

Port 2 Power

Output

PRTPWR2

PRTCTL2

BC_EN2

O8

Enables power to a downstream USB device

attached to Port 2.

0 = Power disabled on downstream Port 2

1 = Power enabled on downstream Port 2

Port 2 Control

OD8/IS

(PU)

When configured as PRTCTL2, this pin functions

as both the Port 2 power enable output

(PRTPWR2) and the Port 2 over-current sense

input (OCS2_N). Refer to the PRTPWR2 and

OCS2_N descriptions for additional information.

1

Port 2 Battery

Charging

Configuration

Strap

IS

This strap is used to indicate support of the battery

charging protocol on Port 2. Enabling battery

charging support allows a device on the port to

draw currents per the USB battery charging

specification.

0 = Battery charging is not supported on Port 2

1 = Battery charging is supported on Port 2

See Note 3-3 for more information on configuration

straps.

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 13

USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

Port 3 Power

Output

PRTPWR3

O8

Enables power to a downstream USB device

attached to Port 3.

0 = Power disabled on downstream Port 3

1 = Power enabled on downstream Port 3

Port 3 Control

PRTCTL3

BC_EN3

OD8/IS

(PU)

When configured as PRTCTL3, this pin functions

as both the Port 3 power enable output

(PRTPWR3) and the Port 3 over-current sense

input (OCS3_N). Refer to the PRTPWR3 and

OCS3_N descriptions for additional information.

1

Port 3 Battery

Charging

Configuration

Strap

IS

This strap is used to indicate support of the battery

charging protocol on Port 3. Enabling battery

charging support allows a device on the port to

draw currents per the USB battery charging

specification.

0 = Battery charging is not supported on Port 3

1 = Battery charging is supported on Port 3

See Note 3-3 for more information on configuration

straps.

Port 4 Power

Output

PRTPWR4

PRTCTL4

BC_EN4

O8

Enables power to a downstream USB device

attached to Port 4.

0 = Power disabled on downstream Port 4

1 = Power enabled on downstream Port 4

Port 4 Control

OD8/IS

(PU)

When configured as PRTCTL4, this pin functions

as both the Port 4 power enable output

(PRTPWR4) and the Port 4 over-current sense

input (OCS4_N). Refer to the PRTPWR4 and

OCS4_N descriptions for additional information.

1

Port 4 Battery

Charging

Configuration

Strap

IS

This strap is used to indicate support of the battery

charging protocol on Port 4. Enabling battery

charging support allows a device on the port to

draw currents per the USB battery charging

specification.

0 = Battery charging is not supported on Port 4

1 = Battery charging is supported on Port 4

See Note 3-3 for more information on configuration

straps.

No Connect

NC

-

These pins must be left floating for normal device

operation.

2

POWER

+3.3V Analog

Power Supply

VDDA33

VDD33

P

+3.3V analog power supply. Refer to Section 4.0,

"Power Connections," on page 17 for power

connection information.

3

2

+3.3V Power

Supply

P

+3.3V power supply. These pins must be

connected to VDDA33. Refer to Section 4.0,

"Power Connections," on page 17 for power

connection information.

+1.2V Core

Power Supply

VDDCR12

+1.2V core power supply. A 1.0 F (<1  ESR)

capacitor to ground is required for regulator

stability. The capacitor should be placed as close

as possible to the device. Refer to Section 4.0,

"Power Connections," on page 17 for power

connection information.

1

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USB2534

TABLE 3-1:

Num Pins

PIN DESCRIPTIONS (CONTINUED)

Buffer

Type

Name

Symbol

Description

Exposed

Pad on

Ground

VSS

P

Common ground. This exposed pad must be

connected to the ground plane with a via array.

package

bottom

(Figure 3-1)

Note 3-1

The LOCAL_PWR pin is sampled during the configuration state, immediately after negation of reset,

to determine whether the device is bus-powered or self-powered. When configuration is complete,

the latched value will not change until the next reset assertion. To enable dynamic local power

switching, the DYNAMIC_POWER register at location 0x4134 must be programmed with 0x41. If

dynamic power switching is not required, the DYNAMIC_POWER register should be left at the default

value of 0xC1. Programming may be performed through the SMBus interface, or permanently via

OTP. Refer to the Protouch MPT User Manual for additional information.

Note 3-2

Note 3-3

If using the local power detect function (LOCAL_PWR pin), the NON_REM[1:0] configuration straps

cannot be used to configure the non-removable state of the USB ports. In this case, the non-

removable state of the ports must be configured in internal device registers via the Protouch tool or

SMBus.

Configuration strap values are latched on Power-On Reset (POR) and the rising edge of RESET_N

(external chip reset). Configuration straps are identified by an underlined symbol name. Signals that

function as configuration straps must be augmented with an external resistor when connected to a

load. Refer to Section 6.3, "Device Configuration Straps," on page 24 for additional information.

3.2

Pin Assignments

TABLE 3-2:

Pin Num

36-SQFN PACKAGE PIN ASSIGNMENTS

Pin Name

Pin Num

Pin Name

1

2

SWAP_USBDN1_DM/PRT_DIS_M1

SWAP_USBDN1_DP/PRT_DIS_P1

USBDN2_DM/PRT_DIS_M2

USBDN2_DP/PRT_DIS_P2

NC

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

UART_RX/OCS3_N

PRTPWR4/PRTCTL4/BC_EN4NC

UART_TX/OCS4_N

SDA/SMBDATA/NON_REM1

VDD33

3

4

5

6

USBDN3_DM/PRT_DIS_M3

USBDN3_DP/PRT_DIS_P3

USBDN4_DM/PRT_DIS_M4

USBDN4_DP/PRT_DIS_P4

VDDA33

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

RESET_N

7

8

9

VBUS_DET

10

11

12

13

14

15

16

17

18

SUSP_IND/LOCAL_PWR/NON_REM0

VDDA33

LED0

PRTPWR1/PRTCTL1/BC_EN1

OCS1_N

FLEX_USBUP_DM

FLEX_USBUP_DP

XTAL2

VDDCR12

VDD33

XTAL1/REFCLK

NC

PRTPWR2/PRTCTL2/BC_EN2

OCS2_N

RBIAS

PRTPWR3/PRTCTL3/BC_EN3

VDDA33

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DS00001713B-page 15

USB2534

3.3

Buffer Type Descriptions

TABLE 3-3:

BUFFER TYPES

Buffer Type

Description

IS

Schmitt-triggered input

I_RST

I_SMB

O8

Reset Input

I²C/SMBus Clock Input

Output with 8 mA sink and 8 mA source

Open-drain output with 8 mA sink

Open-drain output with 12 mA sink

OD8

OD12

PU

50 µA (typical) internal pull-up. Unless otherwise noted in the pin description, internal pull-

ups are always enabled.

Note:

Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on

internal resistors to drive signals external to the device. When connected to a load

that must be pulled high, an external resistor must be added.

PD

50 µA (typical) internal pull-down. Unless otherwise noted in the pin description, internal pull-

downs are always enabled.

Note:

Internal pull-down resistors prevent unconnected inputs from floating. Do not rely

on internal resistors to drive signals external to the device. When connected to a

load that must be pulled low, an external resistor must be added.

AIO

ICLK

OCLK

P

Analog bi-directional

Crystal oscillator input pin

Crystal oscillator output pin

Power pin

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USB2534

4.0

4.1

POWER CONNECTIONS

Integrated Power Regulators

The integrated 3.3V and 1.2V power regulators allow the device to be supplied via a single 3.3V external power supply.

The regulators are controlled by RESET_N. When RESET_N is brought high, the 3.3V regulator will turn on. When

RESET_N is brought low the 3.3V regulator will turn off.

4.2

Power Connection Diagrams

Figure 4-1 illustrates the power connections for the USB2534.

FIGURE 4-1:

POWER CONNECTIONS

Single Supply Application

3.3V Internal

Logic

1.2V

Core Logic

3.3V I/O

+3.3V

Supply

1.2V Regulator

3.3V Regulator

VDDA33

VSS

(IN)

(OUT)

(IN)

(OUT)

(Bypass)

VDD33

USB2534

(2x)

VDDA33

VDDCR12

1.0uF

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DS00001713B-page 17

USB2534

5.0

MODES OF OPERATION

The device provides two main modes of operation: Standby Mode and Hub Mode. The operating mode of the device is

selected by setting values on primary inputs according to the table below.

TABLE 5-1:

CONTROLLING MODES OF OPERATION

RESET_N

Input

Resulting

Mode

Summary

0

Standby

Lowest Power Mode: No functions are active other than monitoring the

RESET_N input. All port interfaces are high impedance. All regulators are

powered off.

1

Hub

Full Feature Mode: Device operates as a configurable USB hub with battery

charger detection. Power consumption is based on the number of active ports,

their speed, and amount of data transferred.

Note:

Refer to Section 8.3.2, "External Chip Reset (RESET_N)," on page 30 for additional information on

RESET_N.

The flowchart in Figure 5-1 shows the modes of operation. It also shows how the device traverses through the Hub

mode stages (shown in bold.) The flow of control is dictated by control register bits shown in italics as well as other

events such as availability of a reference clock. The remaining sections in this chapter provide more detail on each stage

and mode of operation.

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USB2534

FIGURE 5-1:

HUB OPERATIONAL MODE FLOWCHART

(HW_INIT)

(SW_INIT)

Run from

Internal ROM

CFG_SEL[1:0] = 11b

NO

YES

SMBus or I2C

Present?

NO

Config Load

From I²C

Do SMBus or I2C

Initialization

Config Load

From Internal ROM

NO

SOC Done?

YES

Combine OTP

Config Data

(SOC_CFG)

(CONFIG)

SW Upstream

BC detection

(CHGDET)

Hub Connect

(Hub.Connect)

Normal

operation

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DS00001713B-page 19

USB2534

5.1

Boot Sequence

5.1.1

STANDBY MODE

If the external hardware reset is asserted, the hub will be in Standby Mode. This mode provides a very low power state

for maximum power efficiency when no signaling is required. This is the lowest power state. In Standby Mode all internal

regulators are powered off, the PLL is not running, and core logic is powered down in order to minimize power consump-

tion. Because core logic is powered off, no configuration settings are retained in this mode and must be re-initialized

after RESET_N is negated high.

5.1.2

HARDWARE INITIALIZATION STAGE (HW_INIT)

The first stage is the initialization stage and occurs on the negation of RESET_N. In this stage the 1.2V regulator is

enabled and stabilizes, internal logic is reset, and the PLL locks if a valid REFCLK is supplied. Configuration registers

are initialized to their default state and strap input values are latched. The device will complete initialization and auto-

matically enter the next stage. Because the digital logic within the device is not yet stable, no communication with the

device using the SMBus is possible. Configuration registers are initialized to their default state.

If there is a REFCLK present, the next state is SW_INIT.

5.1.3

SOFTWARE INITIALIZATION STAGE (SW_INIT)

Once the hardware is initialized, the firmware can begin to execute from the internal ROM. The firmware checks the

CFG_SEL[1:0] configuration strap values to determine if it is configured for I²C Master loading. If so, the configuration

is loaded from an external I²C ROM in the device’s CONFIG state.

For all other configurations, the firmware checks for the presence of an external I²C/SMBus. It does this by asserting

two pull down resistors on the data and clock lines of the bus. The pull downs are typically 50Kohm. If there are 10Kohm

pull-ups present, the device becomes aware of the presence of an external SMBus/I²C bus. If a bus is detected, the

firmware transitions to the SOC_CFG state.

5.1.4

SOC CONFIGURATION STAGE (SOC_CFG)

In this stage, the SOC may modify any of the default configuration settings specified in the integrated ROM such as USB

device descriptors, or port electrical settings, and control features such as upstream battery charging detection.

There is no time limit. In this stage the firmware will wait indefinitely for the SMBus/I²C configuration. When the SOC

has completed configuring the device, it must write to register 0xFF to end the configuration.

5.1.5

CONFIGURATION STAGE (CONFIG)

Once the SOC has indicated that it is done with configuration, then all the configuration data is combined. The default

data, the SOC configuration data, the OTP data are all combined in the firmware and device is programmed.

After the device is fully configured, it will go idle and then into suspend if there is no VBUS or Hub.Connect present.

Once VBUS is present, and upstream battery charging is enabled, the device will transition to the Battery Charger

Detection Stage (CHGDET). If VBUS is present, and upstream battery charging is not enabled, the device will transitions

to the Connect (Hub.Connect) stage.

5.1.6

BATTERY CHARGER DETECTION STAGE (CHGDET)

After configuration, if enabled, the device enters the Battery Charger Detection Stage. If the battery charger detection

feature was disabled during the CONFIG stage, the device will immediately transition to the Hub Connect (Hub.Con-

nect) stage. If the battery charger detection feature remains enabled, the battery charger detection sequence is started

automatically.

If the charger detection remains enabled, the device will transition to the Hub.Connect stage if using the hardware detec-

tion mechanism.

5.1.7

HUB CONNECT STAGE (HUB.CONNECT)

Once the CHGDET stage is completed, the device enters the Hub.Connect stage.

5.1.8

NORMAL MODE

Lastly the SOC enters the Normal Mode of operation. In this stage, full USB operation is supported under control of the

USB Host on the upstream port. The device will remain in the normal mode until the operating mode is changed by the

system.

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USB2534

If RESET_N is asserted low, then Standby Mode is entered. The device may then be placed into any of the designated

Hub stages. Asserting the soft disconnect on the upstream port will cause the Hub to return to the Hub.Connect stage

until the soft disconnect is negated.

To save power, communication over the SMBus is not supported while in USB Suspend. The system can prevent the

device from going to sleep by asserting the ClkSusp control bit of the Configure Portable Hub Register anytime before

entering USB Suspend. While the device is kept awake during USB Suspend, it will provide the SMBus functionality at

the expense of not meeting USB requirements for average suspend current consumption.

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DS00001713B-page 21

USB2534

6.0

DEVICE CONFIGURATION

The device supports a large number of features (some mutually exclusive), and must be configured in order to correctly

function when attached to a USB host controller. The hub can be configured either internally or externally depending on

the implemented interface.

Microchip provides a comprehensive software programming tool, Pro-Touch, for configuring the USB2534 functions,

registers and OTP memory. All configuration is to be performed via the Pro-Touch programming tool. For additional infor-

mation on the Pro-Touch programming tool, contact your local Microchip sales representative.

6.1

Configuration Method Selection

The CFG_SEL[1:0] configuration straps and the SDApin are used to determine the hub configuration method, as shown

in Table 6-1. The software reads the SDA pin and the CFG_SEL[1:0] bits and configures the system appropriately.

TABLE 6-1:

HUB CONFIGURATION SELECTION

SDA

CFG_SEL1

CFG_SEL0

Description

X

0

Configuration is based on the configuration strap options and

internal OTP settings. This configuration sets the device Self

powered operation.

0

1

0

Invalid

X

Configuration based on the configuration strap options and internal

OTP settings. This configuration sets the device for Bus powered

operation.

1

0

1

Firmware performs a configuration load from 2-wire (I²C) EEPROM.

The device does not perform an SMBus Master detection.

Configuration is controlled by EEPROM values and OTP settings.

Strap options are disabled.

Firmware must wait for configuration from an SMBus Master.

Configuration is controlled by SMBus Master and OTP settings.

Strap options are disabled.

Note:

Refer to Section 7.0, "Device Interfaces," on page 26 for detailed information on each device configuration

interface.

6.2

Customer Accessible Functions

The following USB or SMBus accessible functions are available to the customer via the Pro-Touch Programming Tool.

Note:

For additional programming details, refer to the Pro-Touch Programming Tool User Manual.

6.2.1

6.2.1.1

USB ACCESSIBLE FUNCTIONS

VSM commands over USB

By default, Vendor Specific Messaging (VSM) commands to the hub are enabled. The supported commands are:

• Enable Embedded Controller

• Disable Embedded Controller

• Enable Special Resume

• Disable Special Resume

• Reset Hub

6.2.1.2

I²C Master Access over USB

Access to I²C devices is performed as a pass-through operation from the USB Host. The device firmware has no knowl-

edge of the operation of the attached I²C device. The supported commands are:

• Enable I²C pass through mode

• Disable I²C pass through mode

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USB2534

• I²C write

• I²C read

• Send I²C start

• Send I²C stop

6.2.1.3

OTP Access over USB

The OTP ROM in the device is accessible via the USB bus. All OTP parameters can modified via the USB Host. The

OTP operates in Single Ended mode. The supported commands are:

• Enable OTP reset

• Set OTP operating mode

• Set OTP read mode

• Program OTP

• Get OTP status

• Program OTP control parameters

6.2.1.4

Battery Charging Access over USB

The Battery charging behavior of the device can be dynamically changed by the USB Host when something other than

the preprogrammed or OTP programmed behavior is desired. The supported commands are:

• Enable/Disable battery charging

• Upstream battery charging mode control

• Downstream battery charging mode control

• Battery charging timing parameters

• Download custom battery charging algorithm

6.2.1.5

Other Embedded Controller functions over USB

The following miscellaneous functions may be configured via USB:

• Enable/Disable Embedded controller enumeration

• Program Configuration parameters.

• Program descriptor fields:

- Language ID

- Manufacturer string

- Product string

- idVendor

- idProduct

- bcdDevice

6.2.2

SMBUS ACCESSIBLE FUNCTIONS

OTP Access over SMBus

6.2.2.1

The device’s OTP ROM is accessible over SMBus. All OTP parameters can modified via the SMbus Host. The OTP can

be programmed to operate in Single-Ended, Differential, Redundant, or Differential Redundant mode, depending on the

level of reliability required. The supported commands are:

• Enable OTP reset

• Set OTP operating mode

• Set OTP read mode

• Program OTP

• Get OTP Status

• Program OTP control parameters

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DS00001713B-page 23

USB2534

6.2.2.2

Configuration Access over SMBus

The following functions are available over SMBus prior to the hub attaching to the USB host:

• Program Configuration parameters.

• Program descriptor fields:

- Language ID

- Manufacturer string

- Product string

- idVendor

- idProduct

- bcdDevice

• Program Control Register

6.3

Device Configuration Straps

Configuration straps are multi-function pins that are driven as outputs during normal operation. During a Power-On

Reset (POR) or an External Chip Reset (RESET_N), these outputs are tri-stated. The high or low state of the signal is

latched following de-assertion of the reset and is used to determine the default configuration of a particular feature. Con-

figuration straps are latched as a result of a Power-On Reset (POR) or a External Chip Reset (RESET_N). Configuration

strap signals are noted in Section 3.0, "Pin Descriptions," on page 7 and are identified by an underlined symbol name.

The following sub-sections detail the various configuration straps.

Configuration straps include internal resistors in order to prevent the signal from floating when unconnected. If a partic-

ular configuration strap is connected to a load, an external pull-up or pull-down should be used to augment the internal

resistor to ensure that it reaches the required voltage level prior to latching. The internal resistor can also be overridden

by the addition of an external resistor.

Note:

• The system designer must ensure that configuration straps meet the timing requirements specified in Section

9.6.2, "Reset and Configuration Strap Timing," on page 37 and Section 9.6.1, "Power-On Configuration Strap

Valid Timing," on page 37. If configuration straps are not at the correct voltage level prior to being latched, the

device may capture incorrect strap values.

• Configuration straps must never be driven as inputs. If required, configuration straps can be augmented, or over-

ridden with external resistors.

6.3.1

NON-REMOVABLE DEVICE (NON_REM[1:0])

The NON_REM[1:0] configuration straps are sampled at RESET_N negation to determine if ports [3:1] contain perma-

nently attached (non-removable) devices as follows. Additionally, because the SUSP_IND indicator functionality is

shared with the NON_REM0 configuration strap, the active state of the LED connected to SUSP_IND will be determined

as follows:

TABLE 6-2:

NON_REM[1:0] CONFIGURATION DEFINITIONS

NON_REM[1:0]

Definition

‘00’

‘01’

‘10’

‘11’

All USB ports removable, SUSP_IND LED active high

Port 1 is non-removable, SUSP_IND LED active low

Ports 1 & 2 are non-removable, SUSP_IND LED active high

Ports 1, 2 & 3 are non-removable, SUSP_IND LED active low

Note:

If using the local power detect function (LOCAL_PWR pin), the NON_REM[1:0] configuration straps cannot

be used to configure the non-removable state of the USB ports. In this case, the non-removable state of

the ports must be configured in internal device registers via the Protouch tool or SMBus.

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USB2534

6.3.2

CONFIGURATION SELECT (CFG_SEL[1:0])

Refer to Section 6.1, "Configuration Method Selection," on page 22 for details on CFG_SEL[1:0].

6.3.3

DOWNSTREAM BATTERY CHARGING ENABLE (BC_EN[4:1])

The battery charging enable configuration straps are used to enable battery charging on the corresponding downstream

port. For example, if BC_EN1 is driven high during the configuration strap latching time, downstream port 1 will indicate

support of battery charging. Refer to Section 8.1.2, "Downstream Battery Charging," on page 29 for additional informa-

tion on battery charging.

6.3.4

PORT DISABLE (PRT_DIS_MX/PRT_DIS_PX)

These configuration straps disable the associated USB ports D- and D+ signals, respectively, where “x” is the USB port

number. Both the negative “M” and positive “P” port disable configuration straps for a given USB port must be tied high

at reset to disable the associated port.

TABLE 6-3:

PRT_DIS_MX/PRT_DIS_PX CONFIGURATION DEFINITIONS

PRT_DIS_MX/PRT_DIS_PX

Definition

Port x D-/D+ Signal is Enabled (Default)

Port x D-/D+ Signal is Disabled

‘0’

‘1’

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DS00001713B-page 25

USB2534

7.0

DEVICE INTERFACES

The USB2534 provides multiple interfaces for configuration and external memory access. This chapter details the var-

ious device interfaces and their usage.

Note:

For information on device configuration, refer to Section 6.0, "Device Configuration," on page 22.

7.1

I²C Master Interface

The I²C master interface implements a subset of the I²C Master Specification (Please refer to the Philips Semiconductor

Standard I²C-Bus Specification for details on I²C bus protocols). The device’s I²C master interface is designed to attach

to a single “dedicated” I²C EEPROM for loading configuration data and conforms to the Standard-Mode I²C Specification

(100 kbit/s transfer rate and 7-bit addressing) for protocol and electrical compatibility. The device acts as the master and

generates the serial clock SCL, controls the bus access (determines which device acts as the transmitter and which

device acts as the receiver), and generates the START and STOP conditions.

Note:

• Extensions to the I²C Specification are not supported.

• All device configuration must be performed via the Pro-Touch Programming Tool. For additional information on

the Pro-Touch programming tool, contact your local sales representative.

7.1.1

I²C MESSAGE FORMAT

Sequential Access Writes

7.1.1.1

The I²C interface supports sequential writing of the device’s register address space. This mode is useful for configuring

contiguous blocks of registers. Figure 7-1 shows the format of the sequential write operation. Where color is visible in

the figure, blue indicates signaling from the I²C master, and gray indicates signaling from the slave.

FIGURE 7-1:

I²C SEQUENTIAL ACCESS WRITE FORMAT

S

7-Bit Slave Address

0

A

xxxxxxxx

A

nnnnnnnn

A

...

nnnnnnnn

A

P

Register

Address

(bits 7-0)

Data value for

XXXXXX

Data value for

XXXXXX + y

In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the start address for

sequential write operation. Every subsequent access is a data write to a data register, where the register address incre-

ments after each access and an ACK from the slave occurs. Sequential write access is terminated by a Stop condition.

7.1.1.2

Sequential Access Reads

The I²C interface supports direct reading of the device registers. In order to read one or more register addresses, the

starting address must be set by using a write sequence followed by a read. The read register interface supports auto-

increment mode. The master must send a NACK instead of an ACK when the last byte has been transferred.

In this operation, following the 7-bit slave address, the 8-bit register address is written indicating the start address for

the subsequent sequential read operation. In the read sequence, every data access is a data read from a data register

where the register address increments after each access. The write sequence can end with optional Stop (P). If so, the

read sequence must begin with a Start (S). Otherwise, the read sequence must start with a Repeated Start (Sr).

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USB2534

Figure 7-2 shows the format of the read operation. Where color is visible in the figure, blue and gold indicate signaling

from the I²C master, and gray indicates signaling from the slave.

FIGURE 7-2:

I²C SEQUENTIAL ACCESS READ FORMAT

Optional. If present, Next

access must have Start(S),

otherwise Repeat Start (Sr)

S

7-Bit Slave Address

0

A

xxxxxxxx

A

P

Register

Address

(bits 7-0)

If previous write setting up

Register address ended with a

Stop (P), otherwise it will be

Repeated Start (Sr)

S

7-Bit Slave Address

1

ACK n n n n n n n n ACK n n n n n n n n ACK

...

n n n n n n n n NACK

P

Register value

for xxxxxxxx

Register value

for xxxxxxxx + 1

Register value

for xxxxxxxx + y

7.1.2

PULL-UP RESISTORS FOR I²C

The circuit board designer is required to place external pull-up resistors (10 k recommended) on the SDA & SCL sig-

nals (per SMBus 1.0 Specification) to Vcc in order to assure proper operation.

7.2

SMBus Slave Interface

The USB2534 includes an integrated SMBus slave interface, which can be used to access internal device run time reg-

isters or program the internal OTP memory. SMBus detection is accomplished by detection of pull-up resistors (10 K

recommended) on both the SMBDATA and SMBCLK signals. To disable the SMBus, a pull-down resistor of 10 K must

be applied to SMBDATA. The SMBus interface can be used to configure the device as detailed in Section 6.1, "Config-

uration Method Selection," on page 22.

Note:

All device configuration must be performed via the Pro-Touch Programming Tool. For additional information

on the Pro-Touch programming tool, contact your local Microchip sales representative.

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 27

USB2534

8.0

FUNCTIONAL DESCRIPTIONS

This chapter provides additional functional descriptions of key device features.

8.1

Battery Charger Detection & Charging

The USB2534 supports both upstream battery charger detection and downstream battery charging. The integrated bat-

tery charger detection circuitry supports the USB-IF Battery Charging (BC1.2) detection method and most Apple

devices. These circuits are used to detect the attachment and type of a USB charger and provide an interrupt output to

indicate charger information is available to be read from the device’s status registers via the serial interface. The

USB2534 provides the battery charging handshake and supports the following USB-IF BC1.2 charging profiles:

• DCP: Dedicated Charging Port (Power brick with no data)

• CDP: Charging Downstream Port (1.5A with data)

• SDP: Standard Downstream Port (0.5A with data)

• Custom profiles loaded via SMBus or OTP

The following sub-sections detail the upstream battery charger detection and downstream battery charging features.

8.1.1

UPSTREAM BATTERY CHARGER DETECTION

Battery charger detection is available on the upstream facing port. The detection sequence is intended to identify char-

gers which conform to the Chinese battery charger specification, chargers which conform to the USB-IF Battery Charger

Specification 1.2, and most Apple devices.

In order to detect the charger, the device applies and monitors voltages on the upstream DP and DM pins. If a voltage

within the specified range is detected, the device will be updated to reflect the proper status.

The device includes the circuitry required to implement battery charging detection using the Battery Charging Specifi-

cation. When enabled, the device will automatically perform charger detection upon entering the Hub.ChgDet stage in

Hub Mode. The device includes a state machine to provide the detection of the USB chargers listed in the table below.

TABLE 8-1:

CHARGERS COMPATIBLE WITH UPSTREAM DETECTION

USB Attach TypeE

DP/DM Profile

Charger Type

DCP (Dedicated Charging Port)

CDP (Charging Downstream Port)

Shorted < 200ohm

001

VDP reflected to VDM

010

(EnhancedChrgDet = 1)

SDP

15Kohm pull-down on DP and DM

011

(Standard Downstream Port)

USB Host or downstream hub port

Apple Low Current Charger

Apple High Current Charger

Apple Super High Current Charger

Apple

100

101

110

DP=2.7V

DM=2.0V

Apple Charger Low Current Charger (500mA)

Apple Charger High Current Charger (1000mA)

DP=2.0V

DM=2.0V

100

101

DP=2.0V

DM=2.7V

If a custom charger detection algorithm is desired, the SMBus registers can also be used to control the charger detection

block to implement a custom charger detection algorithm. In order to avoid negative interactions with automatic battery

charger detection or normal hub operation, the user should only attempt Custom battery charger detection during the

Hub.Config stage or Hub.Connect stage. No logic is implemented to disable custom detection at other times - it is up to

the user software to observe this restriction.

There is a possibility that the system is not running the reference clock when battery charger detection is required (for

example if the battery is dead or missing). During the Hub.WaitRefClk stage the battery charger detection sequence can

be configured to be followed regardless of the activity of REFCLK by relying on the operation of the internal oscillator.

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8.1.2

DOWNSTREAM BATTERY CHARGING

The device can be configured by an OEM to have any of the downstream ports to support battery charging. The Hub's

role in battery charging is to provide an acknowledge to a device's query as to if the hub system supports USB battery

charging. The hub silicon does not provide any current or power FETs or any additional circuitry to actually charge the

device. Those components must be provided as externally by the OEM.

FIGURE 8-1:

BATTERY CHARGING EXTERNAL POWER SUPPLY

DC Power

INT

SCL

Microchip

SOC

SDA

Hub

PRTPWR[n]

VBUS[n]

If the OEM provides an external supply capable of supplying current per the battery charging specification, the hub can

be configured to indicate the presence of such a supply to the device. This indication, via the PRTPWR[1:4] output pins,

is on a per/port basis. For example, the OEM can configure two ports to support battery charging through high current

power FET's and leave the other two ports as standard USB ports.

8.1.2.1

Downstream Battery Charging Modes

In the terminology of the USB Battery Charging Specification, if a port is configured to support battery charging, the

downstream port is a considered a CDP (Charging Downstream Port) if connected to a USB host, or a DCP (Dedicated

Charging Port) if not connected to a USB host. If the port is not configured to support battery charging, the port is con-

sidered an SDP (Standard Downstream Port). All charging ports have electrical characteristics different from standard

non-charging ports.

A downstream port will behave as a CDP, DCP, or SDP depending on the port’s configuration and mode of operation.

The port will not switch between a CDP/DCP or SDP at any time after initial power-up and configuration. A downstream

port can be in one of three modes shown in the table below.

TABLE 8-2:

DOWNSTREAM PORT TYPES

USB Attach Type

DP/DM Profile

DCP

Apple charging mode or

China Mode (Shorted < 200ohm) or

MCHP custom mode

(Dedicated Charging Port)

CDP

VDP reflected to VDM

(Charging Downstream Port)

SDP

15Kohm pull-down on DP and DM

(Standard Downstream Port)

USB Host or downstream hub port

8.1.2.2

Downstream Battery Charging Configuration

Configuration of ports to support battery charging is performed via the BC_EN configuration straps, USB configuration,

SMBus configuration, or OTP. The Battery Charging Enable Register provides per port battery charging configuration.

Starting from bit 1, this register enables battery charging for each down stream port when asserted. Bit 1 represents port

1 and so on. Each port with battery charging enabled asserts the corresponding PRTPWR register bit.

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USB2534

8.1.2.3

Downstream Over-Current Management

It is the devices responsibility to manage over-current conditions. Over-Current Sense (OCS) is handled according to

the USB specification. For battery charging ports, PRTPWR is driven high (asserted) after hardware initialization. If an

OCS event occurs, the PRTPWR is negated. PRTPWR will be negated for all ports in a ganged configuration. Only the

respective PRTPWR will be negated in the individual configuration.

If there is an over-current event in DCP mode, the port is turned off for one second and is then re-enabled. If the OCS

event persists, the cycle is repeated for a total or three times. If after three attempts, the OCS still persists, the cycle is

still repeated, but with a retry interval of ten seconds. This retry persists for indefinitely. The indefinite retry prevents a

defective device from permanently disabling the port.

In CDP or SDP mode, the port power and over-current events are controlled by the USB host. The OCS event does not

have to be registered. When and if the hub is connected to a host, the host will initialize the hub and enable its port

power. If the over current still exists, it will be notified at that point.

8.2

Flex Connect

This feature allows the upstream port to be swapped with downstream physical port 1. Only downstream port 1 can be

swapped physically. Using port remapping, any logical port (number assignment) can be swapped with the upstream

port (non-physical).

Flex Connect is enabled/disabled via two control bits in the Connect Configuration Register. The FLEXCONNECT con-

figuration bit switches the port, and EN_FLEX_MODE enables the mode.

8.2.1

PORT CONTROL

Once EN_FLEX_MODE bit is set, the functions of certain pins change, as outlined below.

If EN_FLEX_MODE is set and FLEXCONNECT is not set:

1. PRTPWR1 enters combined mode, becoming PRTPWR1/OCS1_N

2. OCS1_N becomes a don’t care

3. SUSPEND outputs ‘0’ to keep any upstream power controller off

If EN_FLEX_MODE is set and FLEXCONNECT is set:

1. The normal upstream VBUS pin becomes a don’t care

2. PRTPWR1 is forced to a ‘1’ in combined mode, keeping the port power on to the application processor.

3. OCS1 becomes VBUS from the application processor through a GPIO

4. SUSPEND becomes PRTPWR1/OCS1_N for the port power controller for the connector port

8.3

Resets

The device has the following chip level reset sources:

• Power-On Reset (POR)

• External Chip Reset (RESET_N)

• USB Bus Reset

8.3.1

POWER-ON RESET (POR)

A power-on reset occurs whenever power is initially supplied to the device, or if power is removed and reapplied to the

device. A timer within the device will assert the internal reset per the specifications listed in Section 9.6.1, "Power-On

Configuration Strap Valid Timing," on page 37.

8.3.2

EXTERNAL CHIP RESET (RESET_N)

A valid hardware reset is defined as assertion of RESET_N, after all power supplies are within operating range, per the

specifications in Section 9.6.2, "Reset and Configuration Strap Timing," on page 37. While reset is asserted, the device

(and its associated external circuitry) enters Standby Mode and consumes minimal current.

Assertion of RESET_N causes the following:

1. The PHY is disabled and the differential pairs will be in a high-impedance state.

2. All transactions immediately terminate; no states are saved.

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USB2534

3. All internal registers return to the default state.

4. The external crystal oscillator is halted.

5. The PLL is halted.

Note:

All power supplies must have reached the operating levels mandated in Section 9.2, "Operating Condi-

tions**," on page 34, prior to (or coincident with) the assertion of RESET_N.

8.3.3

USB BUS RESET

In response to the upstream port signaling a reset to the device, the device performs the following:

Note: The device does not propagate the upstream USB reset to downstream devices.

1. Sets default address to 0.

2. Sets configuration to: Unconfigured.

3. Moves device from suspended to active (if suspended).

4. Complies with Section 11.10 of the USB 2.0 Specification for behavior after completion of the reset sequence.

The host then configures the device in accordance with the USB Specification.

8.4

Link Power Management (LPM)

The device supports the L0 (On), L1 (Sleep), and L2 (Suspend) link power management states per the USB 2.0 Link

Power Management Addendum. These supported LPM states offer low transitional latencies in the tens of microsec-

onds versus the much longer latencies of the traditional USB suspend/resume in the tens of milliseconds. The supported

LPM states are detailed in Table 8-3. For additional information, refer to the USB 2.0 Link Power Management Adden-

dum.

TABLE 8-3:

State

LPM STATE DEFINITIONS

Description

Entry/Exit Time to L0

L2

Suspend

Entry: ~3 ms

Exit: ~2 ms

L1

L0

Sleep

Entry: ~65 us

Exit: ~100 us

Fully Enabled (On)

-

Note:

• State change timing is approximate and is measured by change in power consumption.

• System clocks are stopped only in suspend mode or when power is removed from the device.

8.5

Remote Wakeup Indicator (SUSP_IND)

The remote wakeup indicator feature uses the SUSP_IND as a side band signal to wake up the host when in suspend.

This feature is enabled and disabled via the HUB_RESUME_INHIBIT configuration bit in the hub configuration space

register CFG3. The only way to control the bit is by configuration EEPROM, SMBus or internal ROM default setting. The

state is only modified during a power on reset, or hardware reset. No dynamic reconfiguring of this capability is possible.

When HUB_RESUME_INHIBIT = ‘0’, Normal Resume Behavior per the USB 2.0 specification

When HUB_RESUME_INHIBIT = ‘1’, Modified Resume Behavior is enabled

Refer to the following subsections for additional details.

8.5.1

NORMAL RESUME BEHAVIOR

VBUS_DET is used to detect presence of the Host. If VBUS_DET = ‘1’, then D+ pull-up is asserted and normal USB

functionality is enabled. The SUSP_IND provides an indication of the active or suspended state of the hub.

The Hub will drive a ‘K’ on the upstream port if required to do so by USB protocol.

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If VBUS_DET = ‘0’, then the D+ pull-up is negated. If battery charging is not enabled, the internal hub logic will be reset,

thus negating all downstream ports and associated downstream VBUS enable signals. The hub will need to be re-enu-

merated to function, much like a new connect or after a complete system reset.

8.5.2

MODIFIED RESUME BEHAVIOR

When the modified resume feature is enabled, the hub functions as follows:

VBUS_DET is used to detect presence of the Host. If VBUS_DET = ‘1’, then D+ pull-up is asserted and normal USB

functionality is enabled. SUSP_IND provides an indication of the active or suspended state of the hub.

The device will drive a ‘K’ on the upstream port and downstream ports if required to do so by USB protocol. The device

will act as a controlling hub if required to do so by the USB protocol.

If VBUS_DET = ‘0’, then the D+ pull-up is negated, but the hub will not be internally reset. It will power-on the down-

stream ports. The hub is able to continue to detect downstream remote wake events.

SUSP_IND provides an indication of the active or suspended state of the hub.

If a USB 2.0 specification compliant resume or wake event is detected by the device, the device is remote wake enabled,

and a port status change event occurs, SUSP_IND will be driven for the time given in the GLOBAL_RESUME_TIME

register.

If a remote wake event is detected on a downstream port:

1. Device disconnect

2. Device connect

3. A currently connected device requests remote wake-up.

Note:

Downstream resume events are filtered for approximately 100uS by internal logic.

The device will not drive a ‘K’ on the upstream port. Instead, the SUSP_IND will be driven for approximately 14 ms. The

‘K’ is not driven upstream because this would potentially back drive a powered-down host. The device will drive

RESUME to only the downstream ports which transmitted the remote wake signal per the requirements of the USB 2.0

specification for controlling hub behavior.

Note:

SUSP_IND is a one shot event. It will assert with each wake event detection. It will not repeatedly assert

in proxy for downstream devices.

For the case where the Host responds and turns on VBUS and can drive a ‘K’ downstream within the 14 ms time frame

of a standard resume (measured from the SUSP_IND pin), then the hub detects the ‘K’. It will discontinue “Controlling

Hub” activities, drive resume signaling on any other ports, and function as expected per the USB 2.0 Specification with

respect to a resume event. It will permit the host to take over resume signaling.

For the case where the host is not able to drive a ‘K’ within the 14 ms time frame, the hub will stop sending a ‘K’ on the

upstream and downstream ports. It must follow through as a controlling hub and properly terminate the resume with

either an EOP or with HS terminations as is currently implemented in the selective resume case, per the USB specifi-

cation.

8.6

High Speed Indicator (HS_IND)

The HS_IND pin can be used to drive an LED. The active state of the LED will be determined as follows:

• If CFG_SEL1 = ‘0’, HS_IND is active high.

• If CFG_SEL1 = ‘1’, then HS_IND is active low.

Assertion of HS_IND indicates the device is connected at high speed. Negation of HS_IND indicates the device is con-

nected at full speed.

Note:

This pin shares functionality with the CFG_SEL1 configuration strap. The logic state of this pin is internally

latched on the rising edge of RESET_N (RESET_N negation), and is used to determine the hub configu-

ration method. Refer to Section 6.3.2, "Configuration Select (CFG_SEL[1:0])," on page 25 for additional

information.

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9.0

9.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Ratings*

+3.3 V Supply Voltage (VDD33, VDDA33) (Note 9-1) .................................................................................... 0 V to +3.6 V

Positive voltage on input signal pins, with respect to ground (Note 9-2)...................................................................3.6 V

Negative voltage on input signal pins, with respect to ground ................................................................................-0.5 V

Positive voltage on XTAL1/REFCLK, with respect to ground........................................................................... VDDCR12

Positive voltage on USB DP/DM signals, with respect to ground (Note 9-3) ............................................................5.5 V

Storage Temperature ..............................................................................................................................-55^oC to +150^oC

Lead Temperature Range ...........................................................................................Refer to JEDEC Spec. J-STD-020

HBM ESD Performance.........................................................................................................................JEDEC Class 3A

Note 9-1

When powering this device from laboratory or system power supplies, it is important that the absolute

maximum ratings not be exceeded or device failure can result. Some power supplies exhibit voltage

spikes on their outputs when AC power is switched on or off. In addition, voltage transients on the

AC power line may appear on the DC output. If this possibility exists, it is suggested to use a clamp

circuit.

Note 9-2

Note 9-3

This rating does not apply to the following signals: All USB DM/DP pins, XTAL1/REFCLK, XTAL2.

This rating applies only when VDD33 is powered.

*Stresses exceeding those listed in this section could cause permanent damage to the device. This is a stress rating

only. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Functional

operation of the device at any condition exceeding those indicated in Section 9.2, "Operating Conditions**", Section 9.5,

"DC Specifications", or any other applicable section of this specification is not implied. Note, device signals are NOT 5

volt tolerant unless specified otherwise.

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USB2534

9.2

Operating Conditions**

+3.3 V Supply Voltage (VDD33, VDDA33)...................................................................................................+3.0 V to 3.6 V

Power Supply Rise Time ..................................................................................................................................... Note 9-4

Ambient Operating Temperature in Still Air (T_A)................................................................................................. Note 9-5

Note 9-4

The power supply rise time requirements vary dependent on the usage of the external reset

(RESET_N). If RESET_N is asserted at power-on, the power supply rise time must be 10mS or less

(t_RT(max)= 10mS). If RESET_N is not used at power-on (tied high), the power supply rise time must

be 1mS or less (t_RT(max)= 1mS). Figure 9-1 illustrates the supply rise time requirements.

Note 9-5

0^oC to +70^oC for commercial version, -40^oC to +85^oC for industrial version.

**Proper operation of the device is ensured only within the ranges specified in this section.

FIGURE 9-1:

SUPPLY RISE TIME MODEL

Voltage

t_RT

3.3V

100%

VDDA33

90%

10%

VSS

t_90%

Time

t_10%

9.3

Power Consumption

This section details the power consumption of the device as measured during various modes of operation. Power dis-

sipation is determined by temperature, supply voltage, and external source/sink requirements.

9.3.1

OPERATIONAL / UNCONFIGURED

TABLE 9-1:

OPERATIONAL/UNCONFIGURED POWER CONSUMPTION

Typical (mA)

Maximum (mA)

VDD33

HS Host / 1 HS Device

HS Host / 2 HS Devices

HS Host / 3 HS Devices

HS Host / 4 HS Devices

HS Host / 1 FS Device

HS Host / 2 FS Devices

HS Host / 3 FS Devices

HS Host / 4 FS Devices

Unconfigured

65

95

75

110

145

175

50

125

155

45

50

60

55

70

65

80

30

-

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9.3.2

SUSPEND / STANDBY

TABLE 9-2:

Mode

SUSPEND/STANDBY POWER CONSUMPTION

Symbol

Typical @ 25^oC

Commercial MAX

Industrial MAX

Unit

Suspend

Standby

I_VDD33

320

75

1250

130

1750

140

uA

Note:

Typical values measured with VDD33 = 3.3V. Maximum values measured with VDD33 = 3.6V.

9.4

Package Thermal Specifications

Thermal parameters are measured or estimated for devices with the ground soldered to thermal vias in a multilayer

2S2P PCB per JESD51. Thermal resistance is measured from the die to the ambient air. The values provided are based

on the package body, die size, maximum power consumption, 85°C ambient temperature, and 125°C junction tempera-

ture of the die.

Symbol

°C/W

Velocity (Meter/s)

35

30

27

20

3.4

0.3

19

0

1

_JA

2.5

-

_JB

_JC

_JT

_JB

-

0

Use the following formulas to calculate the junction temperature:

T_J= P x _JA+ T_A

T_J= P x _JT+ T_T

T_J= P x _JC+ T_C

TABLE 9-3:

Symbol

PACKAGE THERMALS LEGEND

Description

T_J

Junction temperature

P

Power dissipated

_JA

_JC

_JT

T_A

T_C

T_T

Junction-to-ambient-temperature

Junction-to-top-of-package

Junction-to-bottom-of-case

Ambient temperature

Temperature of the bottom of the case

Temperature of the top of the case

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USB2534

9.5

DC Specifications

TABLE 9-4:

DC ELECTRICAL CHARACTERISTICS

Parameter

Symbol

MIN

TYP

MAX

Units

Notes

IS Type Input Buffer

Low Input Level

V_IL

V_IH

-0.3

2.0

0.8

3.6

V

High Input Level

I_RST Type Input Buffer

Low Input Level

V_IL

V_IH

-0.3

0.4

3.6

V

High Input Level

1.25

I_SMB Type Input Buffer

Low Input Level

V_IL

V_IH

-0.3

0.35

3.6

V

High Input Level

1.25

O8 Type Buffers

Low Output Level

V_OL

V_OH

0.4

V

I_OL= 8 mA

I_OH= -8 mA

VDD33 - 0.4

High Output Level

OD8 Type Buffer

Low Output Level

V_OL

0.4

V

I_OL= 8 mA

OD12 Type Buffer

Low Output Level

V_OL

I_OL= 12 mA

ICLK Type Buffer

(XTAL1/REFCLK Input)

Low Input Level

High Input Level

V_IL

V_IH

-0.3

0.8

0.35

3.6

V

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9.6

AC Specifications

This section details the various AC timing specifications of the device.

9.6.1

POWER-ON CONFIGURATION STRAP VALID TIMING

Figure 9-2 illustrates the configuration strap timing requirements, in relation to power-on, for applications where

RESET_N is not used at power-on. The operational level (V_opp) for the external power supply is detailed in Section 9.2,

"Operating Conditions**," on page 34.

Note:

For RESET_N configuration strap timing requirements, refer to Section 9.6.2, "Reset and Configuration

Strap Timing," on page 37.

FIGURE 9-2:

POWER-ON CONFIGURATION STRAP VALID TIMING

External Power

Supply

V_opp

t_csh

Configuration

Straps

TABLE 9-5:

Symbol

t_csh

POWER-ON CONFIGURATION STRAP VALID TIMING

Description

MIN

TYP

MAX

Units

Configuration strap hold after external power supply at

operational level

1

ms

9.6.2

RESET AND CONFIGURATION STRAP TIMING

Figure 9-3 illustrates the RESET_N timing requirements and its relation to the configuration strap signals. Assertion of

RESET_N is not a requirement. However, if used, it must be asserted for the minimum period specified.

Refer to Section 8.3, "Resets," on page 30 for additional information on resets. Refer to Section 6.3, "Device Configu-

ration Straps," on page 24 for additional information on configuration straps.

FIGURE 9-3:

RESET_N CONFIGURATION STRAP TIMING

t_rstia

RESET_N

t_csh

Configuration

Straps

TABLE 9-6:

Symbol

RESET_N CONFIGURATION STRAP TIMING

Description

MIN

TYP

MAX

Units

t_rstia

t_csh

RESET_N input assertion time

5

1

us

Configuration strap hold after RESET_N deassertion

ms

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USB2534

9.6.3

USB TIMING

All device USB signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Uni-

versal Serial Bus Specification. Please refer to the Universal Serial Bus Specification, Revision 2.0, available at http://

www.usb.org.

9.6.4

SMBUS TIMING

All device SMBus signals conform to the voltage, power, and timing characteristics/specifications as set forth in the Sys-

tem Management Bus Specification. Please refer to the System Management Bus Specification, Version 1.0, available

at http://smbus.org/specs.

9.6.5

I²C TIMING

All device I²C signals conform to the 100KHz Standard Mode (Sm) voltage, power, and timing characteristics/specifica-

tions as set forth in the I²C-Bus Specification. Please refer to the I²C-Bus Specification, available at http://www.nxp.com.

9.7

Clock Specifications

The device can accept either a 24 MHz crystal or a 24 MHz single-ended clock oscillator input. If the single-ended clock

oscillator method is implemented, XTAL1 should be left unconnected and REFCLK should be driven with a clock that

adheres to the specifications outlined in Section 9.7.2, "External Reference Clock (REFCLK)".

9.7.1

OSCILLATOR/CRYSTAL

It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals

(XTAL1I/XTAL2). See Table 9-7 for the recommended crystal specifications.

TABLE 9-7:

CRYSTAL SPECIFICATIONS

Parameter

Symbol

MIN

NOM

AT, typ

Fundamental Mode

Parallel Resonant Mode

MAX

Units

Notes

Crystal Cut

Crystal Oscillation Mode

Crystal Calibration Mode

Frequency

F_fund

-

24.000

-

MHz

PPM

^oC

Total Allowable PPM Budget

Operating Temperature Range

-

+/-350

Note 9-7

Note 9-6

Note 9-7

0^oC for commercial version, -40^oC for industrial version.

+70^oC for commercial version, +85^oC for industrial version.

9.7.2

EXTERNAL REFERENCE CLOCK (REFCLK)

The following input clock specifications are suggested:

• 24 MHz  350 PPM

Note:

The external clock is recommended to conform to the signalling levels designated in the JEDEC specifica-

tion on 1.2V CMOS Logic. XTAL2 should be treated as a no connect when an external clock is supplied.

DS00001713B-page 38

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USB2534

10.0 PACKAGE OUTLINE

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

FIGURE 10-1:

36-SQFN PACKAGE DRAWING

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USB2534

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

REVISION LEVEL

& DATE

SECTION/FIGURE/ENTRY

CORRECTION

DS00001713B

(7-26-19)

Product Identification System

Added “Direction of Unreeling”, pin 1 drawing.

Section 9.4, "Package Thermal

Specifications"

Updated Table 9-3, "Package Thermal Resistance

Parameters"

DS00001713A Revision A replaces the previous SMSC version, revision 1.1

Rev. 1.1

(12-06-13)

SMBus Runtime Registers

Register definitions removed. These definitions are

provided in application note AN 26.18 “SMBus Slave

Interface for the USB253x/USB3x13/USB46x4”.

Rev. 1.1

(09-24-13)

Table 9-4, “DC Electrical

Characteristics,” on page 36

Updated ICLK V_IHmax from “VDDCR12” to “3.6”

Section 9.7.2, "External Reference

Clock (REFCLK)," on page 38

Removed 50% duty cycle requirement.

Table 6-1, “Hub Configuration

Selection,” on page 22

Corrected SDA and CFG_SEL1 values for last two

entries in the table.

Rev. 1.0

Initial Release

(06-17-13)

DS00001713B-page 40

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USB2534

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tains the following information:

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To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://www.microchip.com/support

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 41

USB2534

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

[X]

XXX

[X]⁽¹⁾

-

Examples:

a) USB2534-1080AEN, Commercial Temp

36-pin SQFN Pkg., Tray

Temperature

Range

Package

Tape and Reel

Option

b) USB2534-1050AEN, Commercial Temp

36-pin SQFN Pkg., Tray

Device:

USB2534, USB2534i

c) USB2534-1080AEN-TR, Commercial Temp

36-pin SQFN Pkg., Tape & Reel

d) USB2534-1050AEN-TR, Commercial Temp

36-pin SQFN Pkg., Tape & Reel

Temperature

Range:

Blank

i

=

0C to +70C Commercial

-40C to+85C Industrial

e) USB2534i-1080AEN, Industrial Temp

36-pin SQFN Pkg., Tray

Package:

1080AEN = 36-pin SQFN (Battery Charging disabled

f)

USB2534i-1050AEN-TR, Industrial Temp

36-pin SQFN Pkg., Tray

by default)

1050AEN = 36-pin SQFN (Battery Charging enabled

by default)

g) USB2534i-1080AEN-TR, Industrial Temp

36-pin SQFN Pkg., Tape & Reel

h) USB2534i-1050AEN-TR, Industrial Temp

36-pin SQFN Pkg., Tape & Reel

Tape and Reel

Option:

Blank

TR

=

Standard packaging (tray)

Tape and Reel(1)

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This identifier

is used for ordering purposes and is not printed

on the device package. Check with your

Microchip Sales Office for package availability

with the Tape and Reel option.

Reel size is 4,000.

DS00001713B-page 42

 2012 - 2019 Microchip Technology Inc.

USB2534

PREVIOUS VERSION ORDERING INFORMATION:

ORDER NUMBER

TEMPERATURE

RANGE

PACKAGE TYPE

36-pin SQFN

USB2534-1080AEN (Battery Charging disabled by default)

USB2534-1050AEN (Battery Charging enabled by default)

0°C to +70°C

-40°C to +85°C

36-pin SQFN

(Tape & Reel)

USB2534-1080AEN-TR (Battery Charging disabled by default)

USB2534-1050AEN-TR (Battery Charging enabled by default)

USB2534i-1080AEN (Battery Charging disabled by default)

USB2534i-1050AEN (Battery Charging enabled by default)

36-pin SQFN

(Tape & Reel)

USB2534i-1080AEN-TR (Battery Charging disabled by default)

USB2534i-1050AEN-TR (Battery Charging enabled by default)

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 43

USB2534

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be super-

seded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REP-

RESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-

chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold

harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory,

CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,

MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST

Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other

countries.

ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision

Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication,

CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN,

In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,

PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are

trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other

countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 9781522445111

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

and India. The Company’s quality system processes and procedures

CERTIFIEDꢀBYꢀDNVꢀ

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TSꢀ16949ꢀ==ꢀ

DS00001713B-page 44

 2012 - 2019 Microchip Technology Inc.

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-67-3636

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

08/15/18

 2012 - 2019 Microchip Technology Inc.

DS00001713B-page 45


型号：	USB2534-1051AEN-TR
厂家：	MICROCHIP
描述：	USB Bus Controller, CMOS 时钟外围集成电路
文件：	总45页 (文件大小：1763K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

USB2534-1051AEN-TR [MICROCHIP]

相关型号：

USB2534-1080AEN

USB2534-1080AEN-TR

USB2534-1081AEN

USB2534I-1050AEN

USB2534I-1050AEN-TR

USB2534I-1080AEN

USB2534I-1080AEN-TR

USB2534I-1080AENTR

USB2534I-1081AEN

USB260

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