HC4052 [SLS]
Analog Multiplexer/Demultiplexer(High-Performance Silicon-Gate CMOS); 模拟多路复用器/多路解复用器（高性能硅栅CMOS ）
| 型号： | HC4052 |
| 厂家： | 
SYSTEM LOGIC SEMICONDUCTOR |
| 描述： | Analog Multiplexer/Demultiplexer(High-Performance Silicon-Gate CMOS) |
| 文件： | 总9页 (文件大小：90K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SL74HC4052
Analog Multiplexer/Demultiplexer
High-Performance Silicon-Gate CMOS
The SL74HC4052 utilize silicon-gate CMOS technology to achieve
fast propagation delays, low ON resistances, and low OFF leakage
currents. These analog multiplexers/demultiplexers control analog
voltages that may vary across the complete power supply range (from
VCC to VEE).
The Channel-Select inputs determine which one of the Analog
Inputs/Outputs is to be connected, by means of an analog switch, to
the Common Output/Input.When the Enable pin is high, all analog
switches are turned off.
The Channel-Select and Enable inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with LS/ALS
TTLoutputs.
ORDERING INFORMATION
SL74HC4052N Plastic
SL74HC4052D SOIC
TA = -55° to 125° C for all packages
·
·
·
·
·
·
Fast Switching and Propagation Speeds
Low Crosstalk Between Switches
Diode Protection on All Inputs/Outputs
Analog Power Supply Range (VCC-VEE)=2.0 to 12.0 V
Digital (Control) Power Supply Range (VCC-GND)=2.0 to 6.0 V
Low Noise
PIN ASSIGNMENT
LOGIC DIAGRAM
Double-Pole, 4-Position
Plus Commo n Off
FUNCTION TABLE
Control Inputs
Enable Select
ON
Channels
B
L
A
L
L
L
L
L
H
Y0
X0
X1
X2
X3
L
H
L
Y1
Y2
Y3
H
H
X
H
X
PIN 16 =VCC
PIN 7 = VEE
PIN 8 = GND
None
X = don’ t care
System Logic
SLS
SL74HC4052
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V
VCC
Positive DC Supply Voltage (Referenced to GND)
(Referenced to VEE)
-0.5 to +7.0
-0.5 to +14.0
VEE
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
-7.0 to +0.5
VEE - 0.5 to VCC+0.5
-1.5 to VCC +1.5
±25
V
V
V
IS
V
IN
Digital Input Voltage (Referenced to GND)
DC Input Current Into or Out of Any Pin
V
I
mA
mW
PD
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
750
500
Tstg
TL
Storage Temperature
-65 to +150
260
°C
°C
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Max
Unit
Positive Supply Voltage (Referenced to GND)
(Referenced to VEE)
2.0
2.0
6.0
12.0
V
VEE
Negative DC Supply Voltage (Referenced to GND)
Analog Input Voltage
- 6.0
VEE
GND
-
GND
VCC
V
V
V
IS
V
Digital Input Voltage (Referenced to GND)
Static or Dynamic Voltage Across Switch
Operating Temperature, All Package Types
VCC
V
IN
*
V
IO
1.2
V
TA
-55
+125
°C
ns
tr, tf
Input Rise and Fall Time (Channel Select
or Enable Inputs)
VCC =2.0 V
VCC =4.5 V
VCC =6.0 V
0
0
0
1000
500
400
*
For voltage drops across the switch greater than 1.2 V (switch on), excessive V current may be drawn;
CC
i. e., the current out of the switch may contain both V and switch input components. The reliability of the
CC
device will be unaffected unless the Maximum Ratings are exceeded.
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V and VOUT should be constrained to the range
IN
indicated in the Recommended Operating Conditions..
Unused digital input pins must be tied to an appropriate logic voltage level (e.g., either GND or VCC).
Unused Analog I/O pins may be left open or terminated.
System Logic
SLS
Semiconductor
SL74HC4052
DC ELECTRICAL CHARACTERISTICS Digital Section (Voltages Referenced to GND) VEE=GND,
Except Where Noted
VCC
V
Guaranteed Limit
Symbol
Parameter
Test Conditions
RON = Per Spec
25 °C to
-55°C
£85
°C
£125
Unit
V
°C
V
IH
Minimum High-Level
Input Voltage, Channel-
Select or Enable Inputs
2.0
4.5
6.0
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
IL
Maximum Low -Level
Input Voltage, Channel-
Select or Enable Inputs
RON = Per Spec
2.0
4.5
6.0
0.3
0.9
1.2
0.3
0.9
1.2
0.3
0.9
1.2
V
IIN
Maximum Input
Leakage Current,
Channel-Select or
Enable Inputs
V =VCC or GND,
VEE=-6.0 V
6.0
±0.1
±1.0
±1.0
mA
IN
ICC
Maximum Quiescent
Supply Current
(per Package)
Channel Select = VCC or GND
Enable = VCC or GND
V = VCC or GND
IS
mA
V = 0 V
IO
V
EE = GND
6.0
6.0
2
8
20
80
40
160
VEE = -6.0
DC ELECTRICAL CHARACTERISTICS Analog Section
VCC
V
VEE
Guaranteed Limit
25 °C £85 £125 Unit
Symbol
RON
Parameter
Test Conditions
V
to
°C
°C
-55°C
Maximum “ON” Resistance
V =V or V
IH
4.5
4.5
6.0
0.0
-4.5
-6.0
190
120
100
240 280
150 170
125 140
W
IN
IL
V = VCC or VEE
IS £ 2.0 mA(Figure 1)
IS
V =V or V
IH
V = VCC or VEE
IS
4.5
4.5
0.0
-4.5
150
100
190 230
125 140
IN
IL
(Endpoints)
IS £ 2.0 mA(Figure 1)
6.0
-6.0
80
100 115
DRON
Maximum Difference in
“ON” Resistance Between
Any Two Channels in the
Same Package
V =V or V
IH
4.5
4.5
6.0
0.0
-4.5
-6.0
30
12
10
35
15
12
40
18
14
W
IN
IL
V = 1/2 (VCC- VEE)
IS
IS £ 2.0 mA
IOFF
Maximum Off- Channel
Leakage Current, Any One
Channel
V =V or V
IH
6.0
6.0
6.0
-6.0
-6.0
-6.0
0.1
0.1
0.1
0.5
1.0
1.0
1.0
2.0
2.0
mA
IN
IL
V = VCC- VEE
IO
Switch Off (Figure 2)
Maximum Off- Channel
Leakage Current, Common
Channel
V =V or V
IN
IL
IH
V = VCC- VEE
IO
Switch Off (Figure 3)
ION
Maximum On- Channel
Leakage Current, Channel to
Channel
V =V or V
mA
IN
IL
IH
Switch to Switch =
VCC- VEE (Figure 4)
System Logic
Semiconductor
SLS
SL74HC4052
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Guaranteed Limit
Symbol
Parameter
V
25 °C to £85°C
-55°C
£125°C
Unit
ns
tPLH, tPHL Maximum Propagation Delay, Channel-Select to
Analog Output (Figures 8 and 9)
2.0
4.5
6.0
370
74
465
93
550
110
94
63
79
tPLH, tPHL Maximum Propagation Delay , Analog Input to
Analog Output (Figures 10 and 11)
2.0
4.5
6.0
60
12
10
75
15
13
90
18
15
ns
ns
ns
tPLZ, tPHZ Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
2.0
4.5
6.0
290
58
49
364
73
62
430
86
73
tPZL, tPZH Maximum Propagation Delay , Enable to Analog
Output (Figures 12 and 13)
2.0
4.5
6.0
345
69
59
435
87
74
515
103
87
CIN
Maximum Input Capacitance, Channel-Select or
Enable Inputs
-
10
10
10
pF
pF
CI/O
Maximum Capacitance
-
35
35
35
Analog I/O
Common O/I
Feedthrough
All Switches Off
-
-
80
80
80
1.0
1.0
1.0
Power Dissipation Capacitance (Per Package)
(Figure 15)
Typical @25°C,VCC=5.0 V, V =0 V
EE
CPD
Used to determine the no-load dynamic power
consumption:
80
pF
PD=CPDVCC2f+ICCVCC
System Logic
Semiconductor
SLS
SL74HC4052
ADDITIONAL APPLICATION CHARACTERISTICS (GND = 0.0 V)
VCC
VEE
V
Limit*
Symbol
BW
Parameter
Test Conditions
fin=1 MHz Sine Wave
Adjust fin Voltage to Obtain 0 dBm at VOS
Increase fin Frequence Until dB Meter
Reads -3 dB
V
25 °C
Unit
Maximum On-
Channel
Bandwidth or
Minimum
Frequency
Response
(Figure 5)
MHz
2.25
4.50
6.00
-2.25
-4.50
-6.00
95
95
95
RL =50 W, CL=10 pF
-
-
Off-Channel
Feedthrough
Isolation
fin= Sine Wave
Adjust fin Voltage to Obtain 0 dBm at V
fin = 10 kHz, RL =600 W, CL=50 pF
dB
2.25
4.50
6.00
-2.25
-4.50
-6.00
-50
-50
-50
IS
(Figure 6)
fin = 1.0 MHz, RL =50 W, CL=10 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
-40
-40
-40
Feedthrough
Noise, Channel
Select Input to
Common O/I
(Figure 7)
V £ 1 MHz Square Wave (tr = tf = 6 ns)
mVpp
IN
Adjust RL at Setup so that IS= 0 A Enable =
GND
RL =600 W, CL=50 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
25
105
135
RL =10 W, CL=10 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
35
145
190
-
Crosstalk
fin= Sine Wave
dB
Between Any
Two Switches
(Figure 14)
Adjust fin Voltage to Obtain 0 dBm at V
fin = 10 kHz, RL =600 W, CL=50 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
-50
-50
-50
IS
fin = 1 MHz, RL =50 W, CL=10 pF
2.25
4.50
6.00
-2.25
-4.50
-6.00
-60
-60
-60
THD
Total Harmonic
Distortion
fin= 1 kHz, RL =10 kW, CL=50 pF
THD = THDMeasured - THDSource
%
(Figure 16)
V =4.0 VPP sine wave
2.25
4.50
6.00
-2.25
-4.50
-6.00
0.10
0.08
0.05
IS
V =8.0 VPP sine wave
IS
V =11.0 VPP sine wave
IS
* Limits not tested. Determined by design and verified by qualification.
System Logic
SLS
Semiconductor
SL74HC4052
Figure 1. On Resistance Test Set-Up
Figure 2. Maximum Off Channel Leakage
Current, Any One Channel, Test Set-UP
Figure 3. Maximum Off Channel Leakage Current,
Common Channel, Test Set-UP
* Includes all probe and jig capacitance.
Figure 5. Maximum On Channel Bandwidth,
Test Set-UP
Figure 4. Maximum On Channel Leakage
Current, Channel to Channel, Test Set-UP
* Includes all probe and jig capacitance.
* Includes all probe and jig capacitance.
Figure 6. Off Channel Feedthrough Isolation,
Test Set-UP
Figure 7.Feedthrough Noise, Channel Select to Common
Out, Test Set-UP
System Logic
SLS
Semiconductor
SL74HC4052
System Logic
Semiconductor
SLS
SL74HC4052
* Includes all probe and jig capacitance.
Figure 8. Switching Weveforms
Figure 9. Test Set-UP, Channel Select to Analog Out
* Includes all probe and jig capacitance.
Figure 10. Switching Weveforms
Figure 11. Test Set-UP, Analog In to Analog Out
Figure 12. Switching Weveforms
Figure 13. Test Set-UP, Enable to Analog Out
System Logic
SLS
Semiconductor
SL74HC4052
* Includes all probe and jig capacitance.
Figure 14. Crosstalk Between Any Two Switches,
Figure 15. Power Dissipation Capacitance, Test Set-U
p
Test Set-U
p
Figure 16. Total Harmonic Distortion, Test Set-UP
EXPANDED LOGIC DIAGRAM
System Logic
Semiconductor
SLS
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