Si8238BD-D-IS [SILICON]
0.5 and 4.0 Amp ISOdrivers (2.5 and 5 kVRMS);型号: | Si8238BD-D-IS |
厂家: | SILICON |
描述: | 0.5 and 4.0 Amp ISOdrivers (2.5 and 5 kVRMS) 驱动 双极性晶体管 接口集成电路 |
文件: | 总59页 (文件大小:1005K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Si823x Data Sheet
0.5 and 4.0 Amp ISOdrivers (2.5 and 5 kV
)
RMS
KEY FEATURES
The Si823x isolated driver family combines two independent, isolated drivers into a sin-
gle package. The Si8230/1/3/4 are high-side/low-side drivers, while the Si8232/5/7/8 are
dual drivers. Versions with peak output currents of 0.5 A (Si8230/1/2/7) and 4.0 A
(Si8233/4/5/8) are available. All drivers operate with a maximum supply voltage of 24 V.
• Two completely isolated drivers in one
package
• Up to 5 kV
input-to-output isolation
RMS
• Up to 1500 V peak driver-to-driver
differential voltage
DC
The Si823x drivers utilize Silicon Labs' proprietary silicon isolation technology, which
provides up to 5 kVRMS withstand voltage per UL1577 and fast 45 ns propagation times.
Driver outputs can be grounded to the same or separate grounds or connected to a pos-
itive or negative voltage. The TTL level compatible inputs with >400 mV hysteresis are
available in individual control input (Si8230/2/3/5/7/8) or PWM input (Si8231/4) configu-
rations. High integration, low propagation delay, small installed size, flexibility, and cost-
effectiveness make the Si823x family ideal for a wide range of isolated MOSFET/IGBT
gate drive applications.
• HS/LS and dual driver versions
• Up to 8 MHz switching frequency
• 0.5 A peak output (Si8230/1/2/7)
• 4.0 A peak output (Si8233/4/5/8)
• High electromagnetic immunity
• RoHS-compliant packages:
• SOIC-14/16 wide body
Automotive Grade is available for certain part numbers. These products are built using
automotive-specific flows at all steps in the manufacturing process to ensure the robust-
ness and low defectivity required for automotive applications.
• SOIC-16 narrow body
• LGA-14
• QFN-14 (pin to pin compatible with
LGA-14 packages)
Automotive Applications
Industrial Applications
• On-board chargers
• Power delivery systems
• AEC-Q100 qualification
• Battery management systems
• Automotive-grade OPNs available
• AIAG compliant PPAP documentation
support
• Motor control systems
• Charging stations
• Isolated dc-dc power supplies
• Traction inverters
• Lighting control systems
• IMDS and CAMDS listing support
• Hybrid Electric Vehicles
• Plasma displays
• Battery Electric Vehicles
• Solar and industrial inverters
Safety Regulatory Approvals
• UL 1577 recognized
• Up to 5000 VRMS for 1 minute
• CSA component notice 5A approval
• IEC 60950-1, 62368-1, 60601-1 (re-
inforced insulation)
• VDE certification conformity
• VDE 0884-10
• EN60950-1 (reinforced insulation)
• CQC certification approval
• GB4943.1
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Rev. 2.1.1
Si823x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si823x Ordering Guide 1, 2, 3
Legacy
Ordering
Part Number
(OPN)
Ordering Part
Number (OPN)
Peak
Current
UVLO
Voltage Rating
Isolation
Inputs
Configuration
Temp Range Package Type
2.5 kV Only
Wide Body (WB) Package Options
High Side/
Si8230BB-D-IS VIA, VIB
Si8230-A-IS
Low Side
High Side/
Low Side
0.5 A
8 V
Si8231BB-D-IS
Si8232BB-D-IS
Si8234CB-D-IS
PWM
VIA,VIB
PWM
Si8231-A-IS
Si8232-A-IS
N/A
Dual Driver
High Side/
Low Side
SOIC-16
Wide Body
10 V
8 V
2.5 kVrms –40 to +125 °C
High Side/
Low Side
Si8233BB-D-IS
VIA,VIB
Si8233-B-IS
Si8234-B-IS
4.0 A
High Side/
Low Side
Si8234BB-D-IS
Si8235BB-D-IS
PWM
VIA,VIB
Dual Driver
Si8235-B-IS
N/A
Si8230AB-D-IS VIA, VIB
High Side/
Low Side
Si8231AB-D-IS
Si8232AB-D-IS
Si8233AB-D-IS
Si8234AB-D-IS
Si8235AB-D-IS
PWM
VIA,VIB
VIA,VIB
PWM
0.5 A
4.0 A
5 V
5 V
N/A
Dual Driver
N/A
SOIC-16
Wide Body
2.5 kVrms –40 to +125 °C
N/A
High Side/
Low Side
N/A
VIA,VIB
Dual Driver
N/A
Narrow Body (NB) Package Options
High Side/
Low Side
Si8230BB-D-IS1 VIA,VIB
High Side/
Low Side
0.5 A
8 V
Si8231BB-D-IS1
PWM
Si8232BB-D-IS1 VIA,VIB
Si8233BB-D-IS1 VIA,VIB
Dual Driver
2.5 kVrms
SOIC-16
Narrow Body
High Side/
Low Side
–40 to +125 °C
N/A
High Side/
Low Side
Si8234BB-D-IS1
PWM
4.0 A
8 V
Si8235BB-D-IS1 VIA,VIB
Si8235BA-D-IS1 VIA,VIB
Dual Driver
Dual Driver
1.0 kVrms
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Si823x Data Sheet
Ordering Guide
Legacy
Ordering
Part Number
(OPN)
Ordering Part
Number (OPN)
Peak
Current
UVLO
Voltage Rating
Isolation
Inputs
Configuration
Temp Range Package Type
2.5 kV Only
Si8230AB-D-IS1 VIA,VIB
Si8231AB-D-IS1 PWM
N/A
N/A
N/A
N/A
N/A
N/A
High Side/
Low Side
0.5 A
4.0 A
5 V
5 V
Si8232AB-D-IS1 VIA,VIB
Si8233AB-D-IS1 VIA,VIB
Dual Driver
SOIC-16
Narrow Body
2.5 kVrms –40 to +125 °C
High Side/
Low Side
Si8234AB-D-IS1
PWM
Si8235AB-D-IS1 VIA,VIB
LGA Package Options
Si8233CB-D-IM
Dual Driver
10 V
8 V
N/A
Si8233-B-IM
N/A
Si8233BB-D-IM VIA,VIB
Si8233AB-D-IM
High Side/
Low Side
5 V
LGA-14 5x5
mm
Si8234BB-D-IM
PWM
Si8234AB-D-IM
4.0 A
8 V
5 V
8 V
5 V
2.5 kVrms –40 to +125 °C
Si8234-B-IM
N/A
Si8235BB-D-IM
VIA,VIB
Si8235AB-D-IM
Si8235-B-IM
N/A
Dual Driver
QFN Package Options
SI8233AB-D-IM1
VIA,VIB
5 V
8 V
5 V
8 V
5 V
8 V
N/A
N/A
N/A
N/A
N/A
N/A
SI8233BB-D-IM1
High Side/
Low Side
SI8234AB-D-IM1
PWM
SI8234BB-D-IM1
4.0 A
2.5 kVrms –40 to +125 °C
QFN-14
SI8235AB-D-IM1
VIA,VIB
SI8235BB-D-IM1
Dual Driver
5 kV Ordering Options
High Side/
Low Side
Si8230BD-D-IS VIA, VIB
High Side/
Low Side
0.5 A
4.0 A
Si8231BD-D-IS
PWM
Si8232BD-D-IS VIA, VIB
Si8233BD-D-IS VIA, VIB
Dual Driver
SOIC-16
Wide Body
8 V
5.0 kVrms –40 to +125 °C
N/A
High Side/
Low Side
High Side/
Low Side
Si8234BD-D-IS
PWM
Si8235BD-D-IS VIA, VIB
Dual Driver
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Si823x Data Sheet
Ordering Guide
Legacy
Ordering
Part Number
(OPN)
Ordering Part
Number (OPN)
Peak
Current
UVLO
Voltage Rating
Isolation
Inputs
Configuration
Temp Range Package Type
2.5 kV Only
Si8230AD-D-IS VIA, VIB
Si8231AD-D-IS PWM
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
High Side/
Low Side
0.5 A
5 V
Si8232AD-D-IS VIA, VIB
Si8233AD-D-IS VIA, VIB
Dual Driver
SOIC-16
Wide Body
High Side/
Low Side
Si8234AD-D-IS
PWM
4.0 A
0.5 A
4.0 A
5 V
Si8235AD-D-IS VIA, VIB
SI8230AD-D-IS3 VIA, VIB
SI8230BD-D-IS3 VIA, VIB
SI8233AD-D-IS3 VIA, VIB
SI8233BD-D-IS3 VIA, VIB
SI8235AD-D-IS3 VIA, VIB
SI8235BD-D-IS3 VIA, VIB
3 V VDDI Ordering Options
Si8237AB-D-IS1 VIA, VIB
Si8237BB-D-IS1 VIA, VIB
Si8238AB-D-IS1 VIA, VIB
Si8238BB-D-IS1 VIA, VIB
Si8237AD-D-IS VIA, VIB
Si8237BD-D-IS VIA, VIB
Si8238AD-D-IS VIA, VIB
Si8238BD-D-IS VIA, VIB
SI8238AD-D-IS3 VIA, VIB
SI8238BD-D-IS3 VIA, VIB
Dual Driver
5.0 kVrms –40 to +125 °C
High Side/
Low Side
SOIC-14 Wide
Body with
8 V
5 V
8 V
5 V
8 V
increased
creepage
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
Dual Driver
5 V
8 V
0.5 A
4.0 A
0.5 A
SOIC-16
Narrow Body
2.5 kVrms
5 V
8 V
5 V
8 V
5 V
8 V
5 V
8 V
SOIC-16
Wide Body
–40 to +125 °C
N/A
5.0 kVrms
SOIC-14 Wide
Body with
4.0 A
increased
creepage
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
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Si823x Data Sheet
Ordering Guide
Automotive Grade OPNs
Automotive-grade devices are built using automotive-specific flows at all steps in the manufacturing process to ensure robustness and
low defectivity. These devices are supported with AIAG-compliant Production Part Approval Process (PPAP) documentation, and fea-
ture International Material Data System (IMDS) and China Automotive Material Data System (CAMDS) listing. Qualifications are compli-
ant with AEC-Q100, and a zero-defect methodology is maintained throughout definition, design, evaluation, qualification, and mass pro-
duction steps.
Table 1.2. Ordering Guide for Automotive Grade OPNs1, 2, 4, 5
Ordering Part Num-
ber (OPN)
Peak Cur-
rent
UVLO
Voltage
Isolation
Rating
Inputs
Configuration
Temp Range
Package Type
Wide Body (WB) Package Options
Si8233BB-AS VIA, VIB High Side/Low Side
4.0 A
8 V
2.5 kVrms
–40 to +125 °C
SOIC-16 Wide
Body
Narrow Body (NB) Package Options
Si8230BB-AS1
Si8233BB-AS1
Si8235BB-AS1
Si8233AB-AS1
VIA, VIB High Side/Low Side
0.5 A
4.0 A
4.0 A
4.0 A
8 V
8 V
8 V
5 V
2.5 kVrms
2.5 kVrms
2.5 kVrms
2.5 kVrms
–40 to +125 °C
–40 to +125 °C
–40 to +125 °C
–40 to +125 °C
SOIC-16 Narrow
Body
VIA, VIB High Side/Low Side
VIA, VIB High Side/Low Side
VIA, VIB High Side/Low Side
SOIC-16 Narrow
Body
SOIC-16 Narrow
Body
SOIC-16 Narrow
Body
LGA Package Option
Si8235BB-AM
VIA, VIB
Dual Driver
4.0 A
8 V
2.5 kVrms
–40 to +125 °C
LGA-14
5x5 mm
5 kV Ordering Options
Si8233BD-AS
VIA, VIB High Side/Low Side
4.0 A
4.0 A
8 V
8 V
5.0
5.0
–40 to +125 °C
–40 to +125 °C
SOIC-16 Wide
Body
Si8235BD-AS
VIA, VIB
Dual Driver
SOIC-16 Wide
Body
3 V VDDI Ordering Options
Si8238BB-AS1
VIA, VIB
Dual Driver
Dual Driver
4.0 A
4.0 A
8 V
8 V
2.5 kVrms
5.0 kVrms
–40 to +125 °C
–40 to +125 °C
SOIC-16 Narrow
Body
Si8238BD-AS
VIA, VIB
SOIC-16 Wide
Body
Note:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions.
2. “Si” and “SI” are used interchangeably.
3. An "R" at the end of the part number denotes tape and reel packaging option.
4. Automotive-Grade devices (with an "–A" suffix) are identical in construction materials, topside marking, and electrical parameters
to their Industrial-Grade (with a "–I" suffix) version counterparts. Automotive-Grade products are produced utilizing full automotive
process flows and additional statistical process controls throughout the manufacturing flow. The Automotive-Grade part number is
included on shipping labels.
5. Additional Ordering Part Numbers may be available in Automotive-Grade. Please contact your local Silicon Labs sales represen-
tative for further information.
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Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Top Level Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.3 Typical Operating Characteristics (0.5 Amp). . . . . . . . . . . . . . . . . . . .11
2.4 Typical Operating Characteristics (4.0 Amp). . . . . . . . . . . . . . . . . . . .14
2.5 Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . .16
2.5.1 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
2.5.2 Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.6 Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . .18
2.7 Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . .19
2.8 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.9 Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . .21
2.9.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . .21
2.9.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . .21
2.9.3 Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . .21
2.9.4 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.9.5 Disable Input . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
2.10 Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . .23
3. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1 Test Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4.1 High-Side/Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . .34
4.2 Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
5. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6. Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . .42
6.2 Package Outline: 14-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . .44
6.3 Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . .46
6.4 Package Outline: 14 LD LGA (5 x 5 mm) . . . . . . . . . . . . . . . . . . . . .47
6.5 Package Outline: 14 LD QFN. . . . . . . . . . . . . . . . . . . . . . . . .48
7. Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
7.1 Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .49
7.2 Land Pattern: 14-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . .50
7.3 Land Pattern: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . .51
7.4 Land Pattern: 14 LD LGA/QFN . . . . . . . . . . . . . . . . . . . . . . . .52
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8. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
8.1 Si823x Top Marking (14/16-Pin Wide Body SOIC). . . . . . . . . . . . . . . . . .53
8.2 Si823x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . . .54
8.3 Si823x Top Marking (14 LD LGA/QFN) . . . . . . . . . . . . . . . . . . . . .55
9. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Si823x Data Sheet
System Overview
2. System Overview
2.1 Top Level Block Diagrams
VDDI
VDDA
VIA
VOA
UVLO
GNDA
DT CONTROL &
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
VIB
GNDI
Si8230/3
Figure 2.1. Si8230/3 Two-Input High-Side/Low-Side Isolated Drivers
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Si823x Data Sheet
System Overview
VDDI
VDDA
PWM
LPWM
VOA
UVLO
GNDA
DT CONTROL
&
OVERLAP
PROTECTION
DT
VDDI
VDDI
VDDB
VDDI
UVLO
VOB
UVLO
DISABLE
GNDB
LPWM
GNDI
Si8231/4
Figure 2.2. Si8231/4 Single-Input High-Side/Low-Side Isolated Drivers
VDDI
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
UVLO
VDDI
VDDB
DISABLE
VOB
UVLO
GNDB
VIB
GNDI
Si8232/5/7/8
Figure 2.3. Si8232/5/7/8 Dual Isolated Drivers
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Si823x Data Sheet
System Overview
2.2 Functional Description
The operation of an Si823x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead of
light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up. A
simplified block diagram for a single Si823x channel is shown in the figure below.
Transmitter
Receiver
Driver
VDD
RF OSCILLATOR
MODULATOR
Semiconductor-
Based Isolation
Barrier
Dead
time
control
B
DEMODULATOR
A
0.5 to 4 A
peak
Gnd
Figure 2.4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the figure below for more details.
Input Signal
Modulation Signal
Output Signal
Figure 2.5. Modulation Scheme
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Si823x Data Sheet
System Overview
2.3 Typical Operating Characteristics (0.5 Amp)
The typical performance characteristics depicted in Figure 2.6 Rise/Fall Time vs. Supply Voltage on page 11 through Figure
2.15 Output Source Current vs. Temperature on page 12 are for information purposes only. Refer to Table 3.1 Electrical Characteris-
tics1 on page 25 for actual specification limits.
10
8
30
25
20
15
10
Tfall
H-L
L-H
6
4
Trise
2
25 °C
CL = 100 pF
25 °C
CL = 100 pF
0
9
12
15
18
21
24
9
12
15
18
21
24
VDDA Supply (V)
VDDA Supply (V)
Figure 2.6. Rise/Fall Time vs. Supply Voltage
Figure 2.7. Propagation Delay vs. Supply Voltage
50
45
40
40
35
Trise
30
25
L- H
35
Tfall
30
20
H-L
25
20
15
10
15
5
VDD=12 V, 25°C
VDD=12 V, 25 °C
0
10
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Load (nF)
Load (nF)
Figure 2.8. Rise/Fall Time vs. Load
Figure 2.9. Propagation Delay vs. Load
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Si823x Data Sheet
System Overview
30
25
20
15
10
5
4
3
2
1
L-H
H-L
VDDA = 15 V,
f = 250 kHz, CL = 0 pF
Duty Cycle = 50%
2 Channels Switching
VDD=12 V, Load = 200 pF
-45
-20
5
30
55
80
105
130
-45
-20
5
30
55
80
105
130
Temperature (° C)
Temperature (°C)
Figure 2.10. Propagation Delay vs. Temperature
Figure 2.11. Supply Current vs. Temperature
3.5
7
Duty Cycle = 50%
Duty Cycle = 50%
1 MHz
CL = 100 pF
1 Channel Switching
= 0 pF
CL
1 Channel Switching
3
2.5
2
6
1 MHz
5
500 kHz
100 kHz
4
500 kHz
3
1.5
1
100 kHz
50 kHz
2
50 kHz
1
0.5
0
0
9
14
19
24
9
14
19
VDDA Supply Voltage (V)
24
VDDA Supply Voltage (V)
Figure 2.12. Supply Current vs. Supply Voltage
Figure 2.13. Supply Current vs. Supply Voltage
500
450
400
350
425
400
375
350
325
300
300
VDD=12 V, Vout=VDD -5 V
275
Vout=VDD-5 V
250
250
-45
-20
5
30
55
80
105
130
9
14
19
Supply Voltage (V)
24
Temperature (°C)
Figure 2.14. Output Source Current vs. Supply Voltage
Figure 2.15. Output Source Current vs. Temperature
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Si823x Data Sheet
System Overview
1125
1000
875
900
800
700
600
500
750
VDD=12 V, Vout=5 V
625
Vout=5 V
500
-45
-20
5
30
55
80
105
130
9
14
19
24
Temperature (°C)
Supply Voltage (V)
Figure 2.16. Output Sink Current vs. Supply Voltage
Figure 2.17. Output Sink Current vs. Temperature
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Si823x Data Sheet
System Overview
2.4 Typical Operating Characteristics (4.0 Amp)
The typical performance characteristics depicted in Figure 2.18 Rise/Fall Time vs. Supply Voltage on page 14 through Figure
2.27 Output Source Current vs. Temperature on page 15 are for information purposes only. Refer to Table 3.1 Electrical Characteris-
tics1 on page 25 for actual specification limits.
10
8
30
25
20
15
10
25° C
25°C
CL= 100 pF
C = 100 pF
L
Tfall
L-H
6
Trise
4
H -L
2
0
9
12
15
18
21
24
9
12
15
18
21
24
VDDA Supply (V)
VDDA Supply (V)
Figure 2.18. Rise/Fall Time vs. Supply Voltage
Figure 2.19. Propagation Delay vs. Supply Voltage
40
50
VDD=12V,
25°C
VDD=12V
°
C
, 25
H-L
30
20
10
0
40
Trise
L-H
Tfall
30
20
10
0
2
4
6
8
10
0
2
4
6
8
10
Load (nF)
Load (nF)
Figure 2.20. Rise/Fall Time vs. Load
Figure 2.21. Propagation Delay vs. Load
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Si823x Data Sheet
System Overview
10
8
30
25
20
15
10
VDDA = 15V,
f = 250kHz,C= 0 pF
VDD=12V,
L
Load = 200pF
Duty Cycle = 50%
2 Channels Switching
H-L
6
L-H
4
2
0
-45
-20
5
30
55
80
105
130
-45
-20
5
30
55
80
105
130
Temperature (°C)
Temperature ( °C)
Figure 2.22. Propagation Delay vs. Temperature
Figure 2.23. Supply Current vs. Temperature
Duty Cycle = 50%
Duty Cycle = 50%
14
14
= 0 pF
1 Channel Switching
CL
CL = 100 pF
1 Channel Switching
1MHz
12
10
8
12
10
8
1MHz
500kHz
500kHz
6
6
4
4
100kHz
50 kHz
100kHz
50 kHz
2
2
0
0
9
12
15
18
21
24
9
12
15
18
21
24
VDDA Supply Voltage (V)
VDDA Supply Voltage (V)
Figure 2.24. Supply Current vs. Supply Voltage
Figure 2.25. Supply Current vs. Supply Voltage
4
3.5
VDD=12V,
Vout=VDD 5V
Vout=VDD-5V
-
3.75
3.25
3
3.5
3.25
3
2.75
2.5
2.25
2
2.75
2.5
2.25
2
9
12
15
18
21
24
-45
-20
5
30
55
80
105
130
Temperature (°C)
Supply Voltage (V)
Figure 2.26. Output Source Current vs. Supply Voltage
Figure 2.27. Output Source Current vs. Temperature
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Rev. 2.1.1 | 15
Si823x Data Sheet
System Overview
9
8
7
6
5
4
7
6.75
6.5
6.25
6
VDD=12V,
Vout=5V
Vout=5V
5.75
5.5
5.25
5
4.75
4.5
4.25
4
9
12
15
18
21
24
-45
-20
5
30
55
80
105
130
Supply Voltage (V)
Temperature (°C)
Figure 2.28. Output Sink Current vs. Supply Voltage
Figure 2.29. Output Sink Current vs. Temperature
2.5 Family Overview and Logic Operation During Startup
The Si823x family of isolated drivers consists of high-side, low-side, and dual driver configurations.
2.5.1 Products
The table below shows the configuration and functional overview for each product in this family.
Table 2.1. Si823x Family Overview
Part Number
Configuration
Overlap Protection
Programmable
Dead Time
Inputs
Peak Output Cur-
rent (A)
Si8230
Si8231
Si8232/7
Si8233
Si8234
Si8235/8
High-Side/Low-Side
High-Side/Low-Side
Dual Driver
√
√
√
√
VIA, VIB
PWM
0.5
0.5
0.5
4.0
4.0
4.0
—
√
—
√
VIA, VIB
VIA, VIB
PWM
High-Side/Low-Side
High-Side/Low-Side
Dual Driver
√
√
—
—
VIA, VIB
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Si823x Data Sheet
System Overview
2.5.2 Device Behavior
The table below consists of truth tables for the Si8230/3, Si8231/4, and Si8232/5/7/8 families.
Table 2.2. Si823x Family Truth Table1
Si8230/3 (High-Side/Low-Side) Truth Table
Inputs
VIA
VDDI State Disable
Output
Notes
VIB
L
VOA
VOB
L
L
Powered
Powered
Powered
Powered
L
L
L
L
L
L
L
H
L
Output transition occurs after internal dead time expires.
Output transition occurs after internal dead time expires.
Output transition occurs after internal dead time expires.
H
H
H
L
H
L
H
L
Invalid state. Output transition occurs after internal dead
time expires.
X2
X2
Unpowered
Powered
X
H
L
L
L
L
Output returns to input state within 7 µs of VDDI power re-
storation.
X
X
Device is disabled.
Si8231/4 (PWM Input High-Side/Low-Side) Truth Table
PWM Input
VDDI State Disable
Output
Notes
VOA
VOB
H
L
Powered
Powered
L
L
X
H
L
L
L
H
L
Output transition occurs after internal dead time expires.
Output transition occurs after internal dead time expires.
X2
Unpowered
Output returns to input state within 7 µs of VDDI power re-
storation.
X
Powered
H
L
L
Device is disabled.
Si8232/5/7/8 (Dual Driver) Truth Table
Inputs VDDI State Disable
Output
Notes
VIA
VIB
VOA
VOB
L
L
Powered
Powered
Powered
Powered
Unpowered
Powered
L
L
L
L
Output transition occurs immediately
(no internal dead time).
L
H
L
L
H
H
L
H
L
Output transition occurs immediately
(no internal dead time).
H
H
L
Output transition occurs immediately
(no internal dead time).
H
L
H
L
Output transition occurs immediately
(no internal dead time).
X2
X2
X
X
H
Output returns to input state within 7 µs of VDDI power re-
storation.
X
L
L
Device is disabled.
Notes:
1. This truth table assumes VDDA and VDDB are powered. If VDDA and VDDB are below UVLO, see 2.9 Undervoltage
Lockout Operation for more information.
2. Note that an input can power the input die through an internal diode if its source has adequate current.
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Rev. 2.1.1 | 17
Si823x Data Sheet
System Overview
2.6 Power Supply Connections
Isolation requirements mandate individual supplies for VDDI, VDDA, and VDDB. The decoupling caps for these supplies must be
placed as close to the VDD and GND pins of the Si823x as possible. The optimum values for these capacitors depend on load current
and the distance between the chip and the regulator that powers it. Low effective series resistance (ESR) capacitors, such as Tantalum,
are recommended.
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Rev. 2.1.1 | 18
Si823x Data Sheet
System Overview
2.7 Power Dissipation Considerations
Proper system design must assure that the Si823x operates within safe thermal limits across the entire load range.The Si823x total
power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by
the series gate resistor and load. Equation 1 shows total Si823x power dissipation.
R
R
p
p
2
P
= V
I
+ 2 I
V
+ f Q
( )(
V
+ f Q
( )(
V
+ 2fCintV
DD2
(
)(
)
(
)(
)
D
DDI DDI
DD2
DD2
TL
DD2
TL
DD2
)(
)
)(
)
R + R
R + R
p
g
p g
where:
PD is the total Si823x device power dissipation (W)
IDDI is the input-side maximum bias current (3 mA)
IDD2 is the driver die maximum bias current (2.5 mA)
Cint is the internal parasitic capacitance (75 pF for the 0.5 A driver and 370 pF for the 4.0 A driver)
VDDI is the input-side VDD supply voltage (2.7 to 5.5 V)
VDD2 is the driver-side supply voltage (10 to 24 V)
f is the switching frequency (Hz)
QTL is the gate charge of the FET being driven
RG is the external gate resistor
RP is the RDS(ON) of the driver pull-up switch: (Rp = 15 Ω for the 0.5 A driver; Rp = 2.7 Ω for the 4.0 A driver)
Rn is the RDS(ON) of the driver pull-down switch: (Rn = 5 Ω for the 0.5 A driver and 1 Ω for the 4.0 A driver)
Equation 1
Power dissipation example for 0.5 A driver using Equation 1 with the following givens:
VDDI = 5.0 V
VDD2 = 12 V
f = 350 kHz
RG = 22 Ω
QTL = 25 nC
5
3
)
−9
3
−12
(
)
(
)(
)
Pd = 0.015 + 0.060 + 350 × 10 25 × 10
12
+ 2 350 × 10 75 × 10
(144) = 145 mW
(
(
)
5 + 22
From which the driver junction temperature is calculated using Equation 2, where:
Pd is the total Si823x device power dissipation (W)
θja is the thermal resistance from junction to air (105 °C/W in this example)
TA is the ambient temperature
o
(
)(
)
T = P × Θ × T = 0.145 105 + 20 = 35.2 C
j
d
ja
A
The maximum power dissipation allowable for the Si823x is a function of the package thermal resistance, ambient temperature, and
maximum allowable junction temperature, as shown in Equation 2:
T
− T
A
Θja
jmax
P
≤
Dmax
where:
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Rev. 2.1.1 | 19
Si823x Data Sheet
System Overview
PDmax = Maximum Si823x power dissipation (W)
Tjmax = Si823x maximum junction temperature (150 °C)
TA = Ambient temperature (°C)
Θja = Si823x junction-to-air thermal resistance (105 °C/W)
f = Si823x switching frequency (Hz)
Equation 2
Substituting values for PDmax Tjmax, TA, and θja into Equation 2 results in a maximum allowable total power dissipation of 1.19 W. Maxi-
mum allowable load is found by substituting this limit and the appropriate data sheet values from Table 3.1 Electrical Characteristics1
on page 25 into Equation 1 and simplifying. The result is Equation 3 (0.5 A driver) and Equation 4 (4.0 A driver), both of which as-
sume VDDI = 5 V and VDDA = VDDB = 18 V.
−3
1.4 × 10
f
−11
−10
C
C
=
=
− 7.5 × 10
− 3.7 × 10
L(MAX)
L(MAX)
Equation 3
−3
1.4 × 10
f
Equation 4
Equation 3 and Equation 4 are graphed in the figure below, where the points along the load line represent the package dissipation-
limited value of CL for the corresponding switching frequency.
2.8 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si823x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si823x as close to the device it is driving as possible. In addition, the VDD supply and ground
trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground plane sys-
tem having separate ground and VDD planes for power devices and small signal components provides the best overall noise perform-
ance.
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Rev. 2.1.1 | 20
Si823x Data Sheet
System Overview
2.9 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 2.30 Device Behavior during Normal Operation and
Shutdown on page 21, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respectively. Note that outputs
VOA and VOB default low when input side power supply (VDDI) is not present.
2.9.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs VIA and VIB.
2.9.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors.
The Si823x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and VOB,
remain low when the input side of the Si823x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance. Each
driver output can enter or exit UVLO independently. For example, VOA unconditionally enters UVLO when VDDA falls below VDDAUV–
and exits UVLO when VDDA rises above VDDAUV+
.
UVLO+
VDDHYS
UVLO-
VDDI
UVLO+
VDDHYS
UVLO-
VDDA
VIA
DISABLE
tSD
tRESTART
tPHL
tPLH
tSD
tSTART
tSTART
tSTART
VOA
Figure 2.30. Device Behavior during Normal Operation and Shutdown
2.9.3 Undervoltage Lockout (UVLO)
The UVLO circuit unconditionally drives VO low when VDD is below the lockout threshold. Upon power up, the Si823x is maintained in
UVLO until VDD rises above VDDUV+. During power down, the Si823x enters UVLO when VDD falls below the UVLO threshold plus
hysteresis (i.e., VDD < VDDUV+ – VDDHYS).
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Rev. 2.1.1 | 21
Si823x Data Sheet
System Overview
2.9.4 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si8231/4), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.9.5 Disable Input
When brought high, the DISABLE input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device opera-
tion terminates within tSD after DISABLE =VIH and resumes within tRESTART after DISABLE = VIL. The DISABLE input has no effect if
VDDI is below its UVLO level (i.e., VOA, VOB remain low).
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Rev. 2.1.1 | 22
Si823x Data Sheet
System Overview
2.10 Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si8230/1/3/4) include programmable overlap protection to prevent outputs VOA and VOB from being high
at the same time. These devices also include programmable dead time, which adds a user-programmable delay between transitions of
VOA and VOB. When enabled, dead time is present on all transitions, even after overlap recovery. The amount of dead time delay (DT)
is programmed by a single resistor (RDT) connected from the DT input to ground per Equation 5. Note that the dead time pin can be
tied to VDDI or left floating to provide a nominal dead time at approximately 400 ps.
DT ≈ 10 × RDT
where:
DT = dead time (ns) and
RDT = dead time programing resistor (kΩ)
Equation 5
The device driving VIA and VIB should provide a minimum dead time of TDD to avoid activating overlap protection. Input/output timing
waveforms for the two-input drivers are shown in Figure 2.31 Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers on
page 23, and dead time waveforms are shown in Figure 2.32 Dead Time Waveforms for High-Side / Low-Side Two-input Drivers on
page 24.
Figure 2.31. Input / Output Waveforms for High-Side / Low-Side Two-Input Drivers
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Rev. 2.1.1 | 23
Si823x Data Sheet
System Overview
OVERLAP
OVERLAP
VOB
VIA/
PWM
VIA/
PWM
VIB
50%
VIB
DT
DT
DT
DT
90%
VOA
VOA
VOB
10%
DT
DT
90%
VOB
10%
B. Dead Time Operation During Overlap
A. Typical Dead Time Operation
Figure 2.32. Dead Time Waveforms for High-Side / Low-Side Two-input Drivers
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Rev. 2.1.1 | 24
Si823x Data Sheet
Electrical Specifications
3. Electrical Specifications
Table 3.1. Electrical Characteristics1
2.7 V < VDDI < 5.5 V, VDDA = VDDB = 12 V or 15 V, TA = –40 to +125 °C, Typical specs at 25 °C, TJ = -40 to +150 °C
Parameter
Symbol
VDDI
Test Condition
Min
Typ
Max
Unit
V
DC Specifications
Input-side Power Supply
Voltage
Si8230/1/2/3/4/5
Si8237/8
4.5
2.7
6.5
—
—
—
5.5
5.5
24
Driver Supply Voltage
VDDA, VDDB
Voltage between VDDA and
GNDA, and VDDB and GNDB
(See 1. Ordering Guide)
V
Input Supply Quiescent
Current
IDDI(Q)
Si8230/2/3/5/7/8
Si8231/4
—
—
—
2
3
5
mA
mA
mA
3.5
—
Output Supply Quiescent
Current
IDDA(Q), IDDB(Q)
Current per channel
3.0
Input Supply Active Current
Output Supply Active Current
IDDI
IDDA
Input freq = 500 kHz, no load
Current per channel with
—
—
3.5
6
—
—
mA
mA
IDDB
Input freq = 500 kHz, no load
Input Pin Leakage Current
IVIA, IVIB, IPWM
IDISABLE
–10
–10
—
—
+10
+10
µA dc
µA dc
Input Pin Leakage Current
(Si8230/1/2/3/4/5)
Input Pin Leakage Current
(Si8237/8)
-1000
+1000
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
VIH
VIL
2.0
—
—
—
—
0.8
—
V
V
VIHYST
Si8230/1/2/3/4/5/7/8
IOA, IOB = –1 mA
400
450
—
mV
V
Logic High Output Voltage
VOAH, VOBH
(VDDA /
VDDB)
— 0.04
—
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
—
—
—
0.04
—
V
A
Output Short-Circuit Pulsed
Sink Current
IOA(SCL), IOB(SCL)
Si8230/1/2/7, Figure 3.1 IOL
Sink Current Test Circuit on
page 28
0.5
Si8233/4/5/8, Figure 3.1 IOL
Sink Current Test Circuit on
page 28
—
—
—
4.0
0.25
2.0
—
—
—
A
A
A
Output Short-Circuit Pulsed
Source Current
IOA(SCH),
IOB(SCH)
Si8230/1/2/7, Figure 3.2 IOH
Source Current Test Circuit on
page 28
Si8233/4/5/8, Figure 3.2 IOH
Source Current Test Circuit on
page 28
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Rev. 2.1.1 | 25
Si823x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Si8230/1/2/7
Min
—
Typ
5.0
1.0
15
Max
—
Unit
Ω
Output Sink Resistance
RON(SINK)
Si8233/4/5/8
—
—
Ω
Output Source Resistance
RON(SOURCE)
Si8230/1/2/7
—
—
Ω
Si8233/4/5/8
—
2.7
4.0
3.70
—
Ω
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDIUV+
VDDIUV–
VDDI rising (Si8230/1/2/3/4/5)
VDDI falling
3.60
3.30
4.45
4.15
V
V
(Si8230/1/2/3/4/5)
(Si8230/1/2/3/4/5)
VDDI rising (Si8237/8)
VDDI falling (Si8237/8)
(Si8237/8)
VDDI Lockout Hysteresis
VDDIHYS
VDDIUV+
—
2.15
2.10
—
250
2.3
—
2.5
2.40
—
mV
V
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
VDDIUV–
2.22
75
V
VDDIHYS
mV
VDDA, VDDB Undervoltage
Threshold
VDDAUV+, VDDBUV+
VDDA, VDDB rising
5 V Threshold
8 V Threshold
10 V Threshold
12.5 V Threshold
5.20
7.50
9.60
12.4
5.80
8.60
11.1
13.8
6.30
9.40
12.2
14.8
V
V
V
V
VDDA, VDDB Undervoltage
Threshold
VDDAUV–, VDDBUV–
VDDA, VDDB falling
5 V Threshold
8 V Threshold
10 V Threshold
12.5 V Threshold
4.90
7.20
9.40
11.6
—
5.52
8.10
10.1
12.8
280
6.0
8.70
10.9
13.8
—
V
V
V
V
VDDA, VDDB
Lockout Hysteresis
VDDAHYS
VDDBHYS
,
UVLO voltage = 5 V
UVLO voltage = 8 V
mV
VDDA, VDDB
Lockout Hysteresis
VDDAHYS
VDDBHYS
,
—
—
600
—
—
mV
mV
VDDA, VDDB
VDDAHYS
,
UVLO voltage = 10 V or 12.5 V
1000
Lockout Hysteresis
VDDBHYS
AC Specifications
Minimum Pulse Width
Propagation Delay
—
—
—
10
30
—
—
45
ns
ns
ns
tPHL, tPLH
PWD
CL = 200 pF
Pulse Width Distortion
5.60
|tPLH - tPHL
|
Minimum Overlap Time2
TDD
DT = VDDI, No-Connect
—
0.4
—
ns
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Rev. 2.1.1 | 26
Si823x Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Programmed Dead Time3
DT
Figure 2.32 Dead Time Wave-
forms for High-Side / Low-Side
Two-input Drivers on page 24,
RDT = 100 k
730
900
1170
ns
Figure 2.32 Dead Time Wave-
forms for High-Side / Low-Side
Two-input Drivers on page 24,
RDT = 6 k
55
70
75
ns
Output Rise and Fall Time
tR,tF
CL = 200 pF (Si8230/1/2/7)
CL = 200 pF (Si8233/4/5/8)
—
—
—
—
—
—
20
12
60
ns
ns
ns
Shutdown Time from
Disable True
tSD
Restart Time from
Disable False
tRESTART
tSTART
CMTI
—
—
20
—
—
45
60
40
—
ns
µs
Device Start-up Time
Time from VDD_ = VDD_UV+ to
VOA, VOB = VIA, VIB
Common Mode
VIA, VIB, PWM = VDDI or 0 V
VCM = 1500 V
kV/µs
Transient Immunity
(see Figure 3.3 Common Mode
Transient Immunity Test Circuit
on page 29)
Notes:
1. VDDA = VDDB = 12 V for 5, 8, and 10 V UVLO devices; VDDA = VDDB = 15 V for 12.5 V UVLO devices.
2. TDD is the minimum overlap time without triggering overlap protection (Si8230/1/3/4 only).
3. The largest RDT resistor that can be used is 220 kΩ.
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Rev. 2.1.1 | 27
Si823x Data Sheet
Electrical Specifications
3.1 Test Circuits
Figures Figure 3.1 IOL Sink Current Test Circuit on page 28, Figure 3.2 IOH Source Current Test Circuit on page 28, and Figure
3.3 Common Mode Transient Immunity Test Circuit on page 29 depict sink current, source current, and common-mode transient im-
munity test circuits, respectively.
VDDA = VDDB = 15 V
VDDI
VDD
10
IN
OUT
Si823x
INPUT
SCHOTTKY
+
_
8 V
VSS
100 µF
1 µF
1 µF
CER
10 µF
EL
Measure
50 ns
RSNS
0.1
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 3.1. IOL Sink Current Test Circuit
VDDA = VDDB = 15 V
VDDI
VDD
10
IN
OUT
Si823x
INPUT
SCHOTTKY
+
5.5 V
VSS
100 µF
1 µF
_
1 µF
CER
10 µF
EL
Measure
RSNS
0.1
50 ns
VDDI
GND
200 ns
INPUT WAVEFORM
Figure 3.2. IOH Source Current Test Circuit
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Rev. 2.1.1 | 28
Si823x Data Sheet
Electrical Specifications
12 V
Supply
Si823x
VDDI
VDDA
Input Signal
Switch
INPUT
VOA
5V
DISABLE GNDA
Isolated
Supply
DT
VDDB
VOB
Oscilloscope
100k
GNDI
GNDB
Isolated
Ground
High Voltage
Differential
Probe
Output
Input
Vcm Surge
Output
High Voltage
Surge Generator
Figure 3.3. Common Mode Transient Immunity Test Circuit
Table 3.2. Regulatory Information1
CSA
The Si823x is certified under CSA Component Acceptance Notice 5A. For more details, see Master Contract Number 232873.
60950-1, 62368-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 250 VRMS working voltage and 2 MOPP (Means of Patient Protection).
VDE
The Si823x is certified according to VDE 0884-10 and EN 60950-1. For more details, see certificates 40018443, 40030763.
0884-10: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si823x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si823x is certified under GB4943.1-2011. For more details, see certificates CQC13001096106, CQC13001096108, and CQC
17001178087.
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
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Rev. 2.1.1 | 29
Si823x Data Sheet
Electrical Specifications
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec. Regulatory Certifi-
cations apply to 3.75 kVRMS rated devices which are production tested to 4.5 kVRMS for 1 sec. Regulatory Certifications apply to
5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see 1. Ordering Guide.
Table 3.3. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WBSOIC-14/16
5 kVRMS
WBSOIC-14/16
NBSOIC-16
2.5 kVRMS
14 LD LGA
/QFN
2.5 kVRMS
Nominal External Air
Gap
(Clearance)1
CLR
8.0
8.0/4.01
3.5
mm
Nominal External Track-
ing (Creepage)1
CPG
DTI
8.0
8.0/4.01
0.014
3.5
mm
mm
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
Erosion Depth
0.014
0.014
CTI or PTI
ED
IEC60112
f = 1 ΜΗz
600
600
600
V
mm
Ω
0.019/0.122
0.019/0.122
0.021
1012
1012
1012
Resistance
(Input-Output)2
RIO
Capacitance
(Input-Output)2
CIO
CI
1.4
1.4
1.4
pF
pF
Input Capacitance3
4.0
4.0
4.0
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in 6.1 Package Outline: 16-Pin
Wide Body SOIC, 6.2 Package Outline: 14-Pin Wide Body SOIC, 6.3 Package Outline: 16-Pin Narrow Body SOIC, 6.4 Package
Outline: 14 LD LGA (5 x 5 mm), 6.5 Package Outline: 14 LD QFN. VDE certifies the clearance and creepage limits as 4.7 mm
minimum for the NB SOIC and 8.5 mm minimum for the WB SOIC package. UL does not impose a clearance and creepage mini-
mum for component level certifications. CSA certifies the clearance and creepage of the WB SOIC package with designation
"IS3" as 8 mm minimum. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SOIC and 7.6 mm mini-
mum for the WB SOIC package with package designation "IS" as listed in the data sheet.
2. To determine resistance and capacitance, the Si823x is converted into a 2-terminal device. Pins 1–8 (1–7, 14 LD LGA/QFN) are
shorted together to form the first terminal and pins 9–16 (8–14, 14 LD LGA/QFN) are shorted together to form the second termi-
nal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
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Rev. 2.1.1 | 30
Si823x Data Sheet
Electrical Specifications
Table 3.4. IEC 60664-1 Ratings
Test Condition
Parameter
Specification
WB SOIC-14/16 NB SOIC-16
14 LD
LGA/QFN
Basic Isolation Group
Material Group
I
I
I
Installation Classification
Rated Mains Voltages < 150 VRMS
Rated Mains Voltages < 300 VRMS
Rated Mains Voltages < 400 VRMS
Rated Mains Voltages < 600 VRMS
I-IV
I-IV
I-III
I-III
I-IV
I-III
I-II
I-II
I-IV
I-III
I-II
I-II
Table 3.5. VDE 0884-10 Insulation Characteristics1
Parameter
Symbol
Test Condition
Characteristic
Unit
WB
SOIC-14/16
NB SOIC-16
14 LD
LGA/QFN
Maximum Working Insu-
lation Voltage
VIORM
891
560
V peak
V peak
Input to Output Test Volt-
age
VPR
Method b1
(VIORM x 1.875 = VPR
100%
1671
1050
,
Production Test, tm = 1
sec,
Partial Discharge < 5 pC)
Transient Overvoltage
Surge Voltage
VIOTM
t = 60 s
6000
4000
V peak
Tested per IEC 60065
with surge voltage of 1.2
µs/50 µs
VIOSM
Vpeak
Si823xxB/C/D tested with
4000 V
3077
2
3077
2
3077
Ω
Pollution Degree (DIN
VDE 0110, Table 1)
>109
>109
Insulation Resistance at
TS, VIO = 500 V
RS
*Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si823x provides a climate classification of
40/125/21.
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Rev. 2.1.1 | 31
Si823x Data Sheet
Electrical Specifications
Table 3.6. VDE 0884-10 Safety Limiting Values1
Parameter
Symbol
Test
WB SOIC-14/16
NB SOIC-16
14 LD
Unit
LGA/QFN
Condition
Case
Temperature
TS
150
50
150
50
150
50
°C
Safety Input Current
ΙS
θJA = 100 °C/W (WB SO-
IC-14/16),
mA
105 °C/W (NB SOIC-16,
14 LD LGA/QFN)
VDDI = 5.5 V,
VDDA = VDDB = 24 V,
TJ = 150 °C, TA = 25 °C
Device Power Dissipa-
tion2
PD
1.2
1.2
1.2
W
Notes:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figures Figure 3.4 WB SOIC, NB SOIC,
14 LD LGA/QFN Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on
page 32.
2. The Si82xx is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square wave.
Table 3.7. Thermal Characteristics
Parameter
Symbol
WB
NB
14 LD LGA/QFN
Unit
SOIC-14/16
SOIC-16
IC Junction-to-Air
θJA
100
105
105
°C/W
Thermal Resistance
60
50
40
30
20
10
0
VDDI = 5.5 V
VDDA, VDDB = 24 V
0
50
100
Case Temperature (ºC)
150
200
Figure 3.4. WB SOIC, NB SOIC, 14 LD LGA/QFN Thermal Derating Curve, Dependence of Safety Limiting Values with Case
Temperature per VDE 0884-10
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Rev. 2.1.1 | 32
Si823x Data Sheet
Electrical Specifications
Table 3.8. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
Storage Temperature2
TSTG
–65
+150
°C
Ambient Temperature under Bias
Junction Temperature
TA
TJ
–40
—
+125
+150
°C
°C
V
Input-side Supply Voltage
Driver-side Supply Voltage
VDDI
–0.6
–0.6
–0.5
6.0
VDDA, VDDB
VIO
30
V
Voltage on any Pin with respect to
Ground
VDD + 0.5
V
Peak Output Current (tPW = 10 µs,
duty cycle = 0.2%)
IOPK
—
0.5
4.0
A
A
(0.5 Amp versions)
Peak Output Current (tPW = 10 µs,
duty cycle = 0.2%)
IOPK
—
(4.0 Amp versions)
Lead Solder Temperature (10 s)
—
—
260
°C
Maximum Isolation (Input to Out-
put) (1 s)
6500
VRMS
WB SOIC
Maximum Isolation (Output to Out-
put) (1 s)
WB SOIC
—
—
—
—
—
2500
4500
2500
3850
650
VRMS
VRMS
VRMS
VRMS
VRMS
Maximum Isolation (Input to Out-
put) (1 s)
NB SOIC
Maximum Isolation (Output to Out-
put) (1 s)
NB SOIC
Maximum Isolation (Input to Out-
put) (1 s)
14 LD LGA/QFN
Maximum Isolation (Output to Out-
put) (1 s)
14 LD LGA/QFN
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
2. VDE certifies storage temperature from –40 to 150 °C.
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Rev. 2.1.1 | 33
Si823x Data Sheet
Applications
4. Applications
The following examples illustrate typical circuit configurations using the Si823x.
4.1 High-Side/Low-Side Driver
The Figure A in the drawing below shows the Si8230/3 controlled using the VIA and VIB input signals, and Figure B shows the Si8231/4
controlled by a single PWM signal.
VDD2
VDD2
D1
D1
C3
1 µF
C3
1 µF
VDDI
VDDI
VDDI
GNDI
VDDI
GNDI
C1
1 µF
C2
0.1 µF
1500 V max
1500 V max
Q1
C1
1 µF
C2
0.1 µF
VDDA
VDDA
CB
CB
Q1
OUT1
OUT2
VIA
VIB
PWMOUT
PWM
DT
VOA
VOA
GNDA
GNDA
DT
RDT
RDT
CONTROLLER
CONTROLLER
Si8230/3
Si8231/4
VDDB
VDDB
C4
0.1 µF
C5
10 µF
C4
0.1 µF
C5
10 µF
I/O
DISABLE
I/O
DISABLE
GNDB
VOB
GNDB
VOB
VDDB
Q2
Q2
A
B
Figure 4.1. Si823x in Half-Bridge Application
For both cases, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has a
maximum drain voltage of 1500 V. The boot-strap start up time will depend on the CB cap chosen. See application note, “AN486: High-
Side Bootstrap Design Using Si823x ISODrivers in Power Delivery Systems”. VOB is connected as a conventional low-side driver, and,
in most cases, VDD2 is the same as VDDB. Note that the input side of the Si823x requires VDD in the range of 4.5 to 5.5 V (2.7 to 5.5
V for Si8237/8), while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to their respective
grounds. It is recommended that bypass capacitors of 0.1 and 1 µF value be used on the Si823x input side and that they be located as
close to the chip as possible. Moreover, it is recommended that 0.1 and 10 µF bypass capacitors, located as close to the chip as possi-
ble, be used on the Si823x output side to reduce high-frequency noise and maximize performance.
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Rev. 2.1.1 | 34
Si823x Data Sheet
Applications
4.2 Dual Driver
The figure below shows the Si823x configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be referenced to a com-
mon ground or to different grounds with as much as 1500 V dc between them.
VDDI
VDDI
Q1
C1
C2
VOA
1 µF
0.1 µF
GNDI
VDDA
VDDA
GNDA
VIA
VIB
PH1
PH2
C3
0.1 µF
C4
10 µF
Si8232/5/7/8
CONTROLLER
VDDB
VDDB
GNDB
C5
0.1 µF
C6
10 µF
I/O
DISABLE
Q2
VOB
Figure 4.2. Si8232/5/7/8 in a Dual Driver Application
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. That is, the voltage at VOA can be higher or lower than that of VOB by VDD without damaging the driver. Therefore, a dual
driver in a low-side high side/low side drive application can use either VOA or VOB as the high side driver. Similarly, a dual driver can
operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity changes.
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Rev. 2.1.1 | 35
Si823x Data Sheet
Pin Descriptions
5. Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
2
16
15
14
13
12
11
10
9
1
2
16
15
14
13
12
11
10
9
VIA
VIB
VIA
VIB
VDDA
VOA
GNDA
NC
VDDA
VOA
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
DISABLE
DT
VDDI
GNDI
DISABLE
DT
GNDA
NC
Si8230
Si8233
Si8230
Si8233
NC
NC
VDDB
VOB
VDDB
VOB
GNDB
NC
NC
VDDI
VDDI
GNDB
Table 5.1. Si8230/3 Two-Input HS/LS Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13
missing
Pin
1
Name
VIA
Description
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Input-side ground terminal.
2
VIB
3
VDDI
4
GNDI
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection).
7
NC
VDDI
GNDB
VOB
VDDB
NC
No connection.
8
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
9
10
11
12
13
14
15
16
Driver B output (low-side driver).
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
NC
No connection.
GNDA
VOA
VDDA
Ground terminal for Driver A.
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Rev. 2.1.1 | 36
Si823x Data Sheet
Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
2
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
1
2
PWM
NC
PWM
NC
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
VDDI
GNDI
DISABLE
DT
Si8231
Si8234
Si8231
Si8234
DISABLE
DT
NC
NC
VDDB
VOB
VDDB
VOB
GNDB
NC
NC
VDDI
VDDI
GNDB
Table 5.2. Si8231/4 PWM Input HS/LS Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13
missing
Pin
1
Name
PWM
Description
PWM input.
2
NC
No connection.
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Input-side ground terminal.
4
GNDI
DISABLE
5
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
6
DT
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection).
7
NC
VDDI
GNDB
VOB
VDDB
NC
No connection.
8
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
9
10
11
12
13
14
15
16
Driver B output (low-side driver).
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
NC
No connection.
GNDA
VOA
VDDA
Ground terminal for Driver A.
Driver A output (high-side driver).
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Rev. 2.1.1 | 37
Si823x Data Sheet
Pin Descriptions
SOIC-16 (Narrow)
SOIC-16 (Wide)
1
2
16
15
14
13
12
11
10
9
1
2
16
15
14
13
12
11
10
9
VIA
VIB
VIA
VIB
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
3
4
5
6
7
8
3
4
5
6
7
8
VDDI
GNDI
VDDI
Si8232
Si8235
Si8237
Si8238
Si8232
Si8235
Si8237
Si8238
GNDI
DISABLE
DISABLE
NC
NC
VDDB
VOB
VDDB
VOB
NC
NC
NC
NC
VDDI
VDDI
GNDB
GNDB
Table 5.3. Si8232/5/7/8 Dual Isolated Driver (SOIC-16). WB SOIC-14 with IS3 package designation, has pins 12 & 13 missing
Pin
1
Name
VIA
Description
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
2
VIB
3
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for
Si8237/8).
4
5
GNDI
Input-side ground terminal.
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
6
7
8
NC
NC
No connection.
No connection.
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V, (2.7 to 5.5 V for
Si8237/8).
9
GNDB
VOB
VDDB
NC
Ground terminal for Driver B.
10
11
12
13
14
15
16
Driver B output.
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
NC
No connection.
GNDA
VOA
VDDA
Ground terminal for Driver A.
Driver A output.
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Rev. 2.1.1 | 38
Si823x Data Sheet
Pin Descriptions
LGA-14 and QFN-14 (5 x 5 mm)
1
2
3
4
5
14
13
12
11
10
GNDI
VIA
VDDA
VOA
GNDA
NC
VIB
VDDI
Si8233
DISABLE
VDDB
6
7
9
8
DT
VOB
VDDI
GNDB
Table 5.4. Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA and QFN)
Pin
GNDI
VIA
Name
Description
1
2
3
4
5
Input-side ground terminal.
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
VIB
VDDI
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see2.10 Programmable Dead Time and
Overlap Protection).
VDDI
GNDB
VOB
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Rev. 2.1.1 | 39
Si823x Data Sheet
Pin Descriptions
LGA-14 and QFN-14 (5 x 5 mm)
1
2
3
4
5
14
13
12
11
10
GNDI
PWM
NC
VDDA
VOA
GNDA
NC
VDDI
Si8234
DISABLE
VDDB
6
7
9
8
DT
VOB
VDDI
GNDB
Table 5.5. Si8234 PWM Input HS/LS Isolated Driver (14 LD LGA and QFN)
Pin
GNDI
PWM
NC
Name
Description
1
2
3
4
5
Input-side ground terminal.
PWM input.
No connection.
VDDI
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
DT
6
Dead time programming input. The value of the resistor connected from DT to ground
sets the dead time between output transitions of VOA and VOB. Defaults to 400 ps dead
time when connected to VDDI or left open (see 2.10 Programmable Dead Time and
Overlap Protection).
VDDI
GNDB
VOB
7
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Rev. 2.1.1 | 40
Si823x Data Sheet
Pin Descriptions
LGA-14 and QFN-14 (5 x 5 mm)
1
2
3
4
5
14
13
12
11
10
GNDI
VIA
VDDA
VOA
GNDA
NC
VIB
Si8235
VDDI
DISABLE
VDDB
6
7
9
8
NC
VOB
VDDI
GNDB
Table 5.6. Si8235 Dual Isolated Driver (14 LD LGA and QFN)
Pin
GNDI
VIA
Name
Description
1
2
3
4
5
Input-side ground terminal.
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
VIB
VDDI
DISABLE
Device Disable. When high, this input unconditionally drives outputs VOA, VOB LOW. It
is strongly recommended that this input be connected to external logic level to avoid er-
roneous operation due to capacitive noise coupling.
NC
6
7
No connection.
VDDI
GNDB
VOB
Input-side power supply terminal; connect to a source of 4.5 to 5.5 V.
Ground terminal for Driver B.
8
9
Driver B output (low-side driver).
VDDB
NC
10
11
12
13
14
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
No connection.
GNDA
VOA
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Rev. 2.1.1 | 41
Si823x Data Sheet
Package Outlines
6. Package Outlines
6.1 Package Outline: 16-Pin Wide Body SOIC
Figure 6.1 16-Pin Wide Body SOIC on page 42 illustrates the package details for the Si823x in a 16-Pin Wide Body SOIC. Table
6.1 Package Diagram Dimensions on page 42 lists the values for the dimensions shown in the illustration.
Figure 6.1. 16-Pin Wide Body SOIC
Table 6.1. Package Diagram Dimensions
Dimension
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
E
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
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Rev. 2.1.1 | 42
Si823x Data Sheet
Package Outlines
Dimension
ααα
Min
—
Max
0.10
0.33
0.10
0.25
0.10
0.20
bbb
—
ccc
—
ddd
—
eee
—
fff
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Rev. 2.1.1 | 43
Si823x Data Sheet
Package Outlines
6.2 Package Outline: 14-Pin Wide Body SOIC
Figure 6.2 Si823x 14-pin WB SOIC Outline on page 44 illustrates the package details for the Si823x in a 14-Pin Wide Body SOIC.
Table 6.2 Package Diagram Dimensions on page 44 lists the values for the dimensions shown in the illustration.
Figure 6.2. Si823x 14-pin WB SOIC Outline
Table 6.2. Package Diagram Dimensions
Dimension
MIN
—
MAX
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
E
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E1
e
L
0.40
0.25
1.27
0.75
h
ͦ
ͦ
Θ
0
8
aaa
bbb
ccc
ddd
eee
fff
—
—
—
—
—
—
0.10
0.33
0.10
0.25
0.10
0.20
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Rev. 2.1.1 | 44
Si823x Data Sheet
Package Outlines
Dimension
MIN
MAX
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020 specification for small body, lead-free components.
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Rev. 2.1.1 | 45
Si823x Data Sheet
Package Outlines
6.3 Package Outline: 16-Pin Narrow Body SOIC
Figure 6.3 16-pin Small Outline Integrated Circuit (SOIC) Package on page 46 illustrates the package details for the Si823x in a 16-
pin narrow-body SOIC. Table 6.3 Package Diagram Dimensions on page 46 lists the values for the dimensions shown in the illustra-
tion.
Figure 6.3. 16-pin Small Outline Integrated Circuit (SOIC) Package
Table 6.3. Package Diagram Dimensions
Dimension
Min
Max
1.75
0.25
—
Dimension
Min
Max
A
—
L
0.40
0.25 BSC
0.25
0°
1.27
A1
0.10
L2
h
A2
1.25
0.50
8°
b
0.31
0.51
0.25
θ
c
0.17
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 2.1.1 | 46
Si823x Data Sheet
Package Outlines
6.4 Package Outline: 14 LD LGA (5 x 5 mm)
Figure 6.4 Si823x LGA Outline on page 47 illustrates the package details for the Si823x in an LGA outline. Table 6.4 Package Dia-
gram Dimensions on page 47 lists the values for the dimensions shown in the illustration.
Figure 6.4. Si823x LGA Outline
Table 6.4. Package Diagram Dimensions
Dimension
MIN
0.74
0.25
NOM
0.84
MAX
0.94
0.35
A
b
0.30
D
5.00 BSC
4.15 BSC
0.65 BSC
5.00 BSC
3.90 BSC
0.75
D1
e
E
E1
L
0.70
0.05
—
0.80
0.15
0.10
0.10
0.08
0.15
0.08
L1
aaa
bbb
ccc
ddd
eee
0.10
—
—
—
—
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
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Rev. 2.1.1 | 47
Si823x Data Sheet
Package Outlines
6.5 Package Outline: 14 LD QFN
Figure 6.5 Si823x 14-pin LD QFN Outline on page 48 illustrates the package details for the Si823x in an QFN outline. Table
6.5 Package Diagram Dimensions on page 48 lists the values for the dimensions shown in the illustration.
Figure 6.5. Si823x 14-pin LD QFN Outline
Table 6.5. Package Diagram Dimensions
Dimension
MIN
0.74
0
NOM
0.85
MAX
0.90
0.05
0.35
A
A1
b
0.025
0.25
0.30
D
5.00 BSC
0.65 BSC
5.00 BSC
3.60 BSC
0.60
e
E
E1
L
0.50
—
0.70
—
L13
ccc
ddd
0.10 BSC
—
—
—
—
0.08
0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. L1 shall not be less than 0.01 mm.
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Rev. 2.1.1 | 48
Si823x Data Sheet
Land Patterns
7. Land Patterns
7.1 Land Pattern: 16-Pin Wide Body SOIC
Figure 7.1 16-Pin SOIC Land Pattern on page 49 illustrates the recommended land pattern details for the Si823x in a 16-pin wide-
body SOIC. Table 7.1 16-Pin Wide Body SOIC Land Pattern Dimensions on page 49 lists the values for the dimensions shown in the
illustration.
Figure 7.1. 16-Pin SOIC Land Pattern
Table 7.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.1.1 | 49
Si823x Data Sheet
Land Patterns
7.2 Land Pattern: 14-Pin Wide Body SOIC
Figure 7.2 14-Pin WB SOIC Land Pattern on page 50 illustrates the recommended land pattern details for the Si823x in a 14-pin Wide
Body SOIC. Table 7.2 14-Pin WB SOIC Land Pattern Dimensions on page 50 lists the values for the dimensions shown in the
illustration.
Figure 7.2. 14-Pin WB SOIC Land Pattern
Table 7.2. 14-Pin WB SOIC Land Pattern Dimensions
Dimension
Feature
(mm)
4.20
1.50
4.25
0.65
C1
E
Pad Column Spacing
Pad Row Pitch
Pad Width
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.1.1 | 50
Si823x Data Sheet
Land Patterns
7.3 Land Pattern: 16-Pin Narrow Body SOIC
Figure 7.3 16-Pin Narrow Body SOIC PCB Land Pattern on page 51 illustrates the recommended land pattern details for the Si823x in
a 16-pin narrow-body SOIC. Table 7.3 16-Pin Narrow Body SOIC Land Pattern Dimensions on page 51 lists the values for the dimen-
sions shown in the illustration.
Figure 7.3. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 7.3. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Rev. 2.1.1 | 51
Si823x Data Sheet
Land Patterns
7.4 Land Pattern: 14 LD LGA/QFN
Figure 7.4 14-Pin LGA/QFN Land Pattern on page 52 illustrates the recommended land pattern details for the Si823x in a 14-pin LGA/
QFN. Table 7.4 14-Pin LGA/QFN Land Pattern Dimensions on page 52 lists the values for the dimensions shown in the illustration.
Figure 7.4. 14-Pin LGA/QFN Land Pattern
Table 7.4. 14-Pin LGA/QFN Land Pattern Dimensions
Dimension
(mm)
4.20
0.65
0.80
0.40
C1
E
X1
Y1
Notes:
General
1. All dimensions shown are in millimeters (mm).
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabri-
cation Allowance of 0.05 mm.
Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
2. The stencil thickness should be 0.125 mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Rev. 2.1.1 | 52
Si823x Data Sheet
Top Markings
8. Top Markings
8.1 Si823x Top Marking (14/16-Pin Wide Body SOIC)
Table 8.1. Top Marking Explanation (14/16-Pin Wide Body SOIC)
Line 1 Marking: Base Part Number
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
Ordering Options
See Ordering Guide for more information.
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
B = 2.5 kV; C = 3.75 kV; D = 5.0 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
TTTTTT = Mfg Code
Line 3 Marking: Circle = 1.5 mm Diameter
(Center Justified)
Manufacturing Code from Assembly Purchase Order form.
“e4” Pb-Free Symbol
Country of Origin
TW = Taiwan (as shown), TH = Thailand
ISO Code Abbreviation
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Rev. 2.1.1 | 53
Si823x Data Sheet
Top Markings
8.2 Si823x Top Marking (16-Pin Narrow Body SOIC)
Line 1 Marking: Base Part Number
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2, 7 = 0.5 A
Ordering Options
See Ordering Guide for more information.
3, 4, 5, 8 = 4.0 A
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV
Line 2 Marking: YY = Year
WW = Workweek
Assigned by the Assembly House. Corresponds to the year and
workweek of the mold date.
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
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Rev. 2.1.1 | 54
Si823x Data Sheet
Top Markings
8.3 Si823x Top Marking (14 LD LGA/QFN)
Line 1 Marking: Base Part Number
Si823 = ISOdriver product series
Y = Peak output current
0, 1, 2 = 0.5 A
Ordering Options
See Ordering Guide for more information.
3, 4, 5 = 4.0 A
Line 2 Marking: Ordering options
U = UVLO level
A = 5 V; B = 8 V; C = 10 V; D = 12.5 V
V = Isolation rating
A = 1.0 kV; B = 2.5 kV; C = 3.75 kV
I = –40 to +125 °C ambient temperature range
M = LGA package type
M1 = QFN package type
Manufacturing Code from Assembly
Pin 1 identifier
Line 3 Marking: TTTTTT
Line 4 Marking: Circle = 1.5 mm diameter
YYWW
Manufacturing date code
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Rev. 2.1.1 | 55
Si823x Data Sheet
Revision History
9. Revision History
Revision 2.1.1
January 2018
• Added new table to Ordering Guide for Automotive-Grade OPN options.
Revision 2.1
October 2017
• Added IS3 and IM1 packaging options
• Added IEC 62368-1 references throughout
• Changed max propagation delay spec from 60 ns to 45 ns based on new test limits
• Removed references to IEC 61010
• Removed references to IEC 60747, replaced with references to VDE 0884-10
Revision 2.0
August 7, 2017
Revision 1.9
July 7, 2017
• Updated 1. Ordering Guide to designate tape and reel packaging option.
Revision 1.8
May 17, 2016
• Converted document from Framemaker to DITA.
Revision 1.7
• Updated 3.1 Test Circuits
• Added CQC certificate numbers.
• Updated Table 3.3 Insulation and Safety-Related Specifications on page 30
• Updated Erosion Depth.
Updated Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31
• Updated VPR for WBSOIC-16.
•
Updated Table 3.8 Absolute Maximum Ratings1 on page 33
• Removed Io and added Peak Output Current specifications.
•
• Updated Equation 1.
• Updated Figure 4.1 Si823x in Half-Bridge Application on page 34.
• Updated Figure 4.2 Si8232/5/7/8 in a Dual Driver Application on page 35.
Updated Ordering Guide Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2
•
Revision 1.6
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2, Ordering Part Numbers.
•
• Added Revision D Ordering Part Numbers.
• Removed all Ordering Part Numbers of previous revisions.
Revision 1.5
Updated Table 3.1 Electrical Characteristics1 on page 25, input and output supply current.
•
• Added references to AEC-Q100 qualified throughout.
• Changed all 60747-5-2 references to 60747-5-5.
• Added references to CQC throughout.
• Updated pin descriptions throughout.
• Corrected dead time default to 400 ps from 1 ns.
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2, Ordering Part Numbers.
• Removed moisture sensitivity level table notes.
•
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Rev. 2.1.1 | 56
Si823x Data Sheet
Revision History
Revision 1.4
• Updated 1. Ordering Guide.
• Updated "3 V VDDI Ordering Options".
Revision 1.3
• Added Si8237/8 throughout.
Updated Table 3.1 Electrical Characteristics1 on page 25.
•
• Updated Figure 3.1 IOL Sink Current Test Circuit on page 28.
• UpdatedFigure 3.2 IOH Source Current Test Circuit on page 28.
• Added Figure 3.3 Common Mode Transient Immunity Test Circuit on page 29.
• Updated Si823x Family Truth Table to include notes 1 and 2.
• Updated 2.10 Programmable Dead Time and Overlap Protection.
• Removed references to Figures 26A and 26B.
Updated Table 1.1 Si823x Ordering Guide 1, 2, 3 on page 2.
•
• Added Si8235-BA-C-IS1 ordering part number.
• Added table note.
Revision 1.2
• Updated 1. Ordering Guide.
• Updated moisture sensitivity level (MSL) for all package types.
Updated Table 3.8 Absolute Maximum Ratings1 on page 33.
• Added junction temperature spec.
•
• Updated 3.1 Test Circuits with new notes.
• Updated Figures Figure 2.16 Output Sink Current vs. Supply Voltage on page 13, Figure 2.14 Output Source Current vs. Supply
Voltage on page 12, Figure 2.17 Output Sink Current vs. Temperature on page 13, and Figure 2.15 Output Source Current vs. Tem-
perature on page 12 to reflect correct y-axis scaling.
• Updated Figure 4.2 Si8232/5/7/8 in a Dual Driver Application on page 35.
• Updated .
• Updated 6.1 Package Outline: 16-Pin Wide Body SOIC.
• Updated Table 6.1 Package Diagram Dimensions on page 42.
• Change references to 1.5 kVRMS rated devices to 1.0 kVRMS throughout.
• Updated 2.7 Power Dissipation Considerations.
Revision 1.1
• Updated .
• Updated CMTI specification.
Updated Table 3.1 Electrical Characteristics1 on page 25.
• Updated CMTI specification.
Updated Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
•
•
• Updated 4.2 Dual Driver.
• Updated 1. Ordering Guide.
• Replaced pin descriptions on page 1 with chip graphics.
Revision 1.0
• Updated Tables 3.1 Test Circuits, Table 3.3 Insulation and Safety-Related Specifications on page 30, Table 3.4 IEC 60664-1 Rat-
ings on page 31, and Table 3.5 VDE 0884-10 Insulation Characteristics1 on page 31.
• Updated 1. Ordering Guide.
• Added 5 V UVLO ordering options
• Added Device Marking sections.
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Rev. 2.1.1 | 57
Si823x Data Sheet
Revision History
Revision 0.3
• Moved Sections 2, 3, and 4 to after Section 5.
• Updated Tables Table 5.4 Si8233 Two-Input HS/LS Isolated Driver (14 LD LGA and QFN) on page 39, Table 5.5 Si8234 PWM Input
HS/LS Isolated Driver (14 LD LGA and QFN) on page 40.
• Removed Si8230, Si8231, and Si8232 from pinout and from title.
• Updated and added Ordering Guide footnotes.
Updated UVLO specifications in Table 3.1 Electrical Characteristics1 on page 25.
Added PWD and Output Supply Active Current specifications in Table 3.1 Electrical Characteristics1 on page 25.
•
•
• Updated and added typical operating condition graphs in 2.3 Typical Operating Characteristics (0.5 Amp) and 2.4 Typical Operating
Characteristics (4.0 Amp).
Revision 0.2
• Updated all specs to reflect latest silicon revision.
Updated Table 3.1 Electrical Characteristics1 on page 25 to include new UVLO options.
Updated Table 3.8 Absolute Maximum Ratings1 on page 33 to reflect new maximum package isolation ratings
•
•
• Added Figures 34, 35, and 36.
• Updated Ordering Guide to reflect new package offerings.
• Added "Undervoltage Lockout (UVLO)" section to describe UVLO operation.
Revision 0.11
• Initial release.
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Rev. 2.1.1 | 58
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Disclaimer
Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or
intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes
without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included
information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted
hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of
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