SI82390AD-IS [SILICON]
Buffer/Inverter Based Peripheral Driver,;
| 型号： | SI82390AD-IS |
| 厂家： | 
SILICON |
| 描述： | Buffer/Inverter Based Peripheral Driver, 驱动 光电二极管 接口集成电路 |
| 文件： | 总38页 (文件大小：1152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si8239x Data Sheet
4.0 A ISODrivers with 2.5 V VDDI and Safety Features
KEY FEATURES
The Si8239x combines two isolated drivers with either an independent input control or a
single input into a single package for high power applications. All drivers operate with a
2.5 V input VDD and a maximum drive supply voltage of 24 V.
• Two isolated drivers in one package
• Up to 5 kVRMS isolation
• Up to 1500 VDC peak driver-to-driver
differential voltage
The Si8239x isolators are ideal for driving power MOSFETs and IGBTs used in a wide
variety of switched power and motor control applications. These drivers utilize Silicon
Laboratories' proprietary silicon isolation technology, supporting up to 5 kVRMS with-
stand voltage. This technology enables high CMTI (100 kV/µs), lower prop delays and
skew, reduced variation with temperature and age and tighter part-to-part matching.
• Enhanced output UVLO safety
• Status feedback to controller
• Both outputs drive low on UVLO
• EN pin for enhanced safety
• Extended VDDI: 2.5 V – 5.5 V
• PWM and dual driver versions
• 4.0 A peak output
It also offers some unique features such as an output UVLO fault detection and feed-
back, and automatic shutdown for both drivers, an EN (active high) pin, a safe delayed
start-up time of 1 ms, fail-safe drivers with default low in case of VDDI power-down, and
dead time programmability. The Si8239x family offers longer service life and dramatically
higher reliability compared to opto-coupled gate drivers.
• High electromagnetic immunity
• Extended start-up time (1ms) for safe
initialization sequence
Applications
• 30 ns propagation delay
• Power Delivery Systems
• Motor Control Systems
• Isolated DC-DC Power Supplies
• Lighting Control Systems
• Solar and Industrial Inverters
• Transient immunity: 100 kV/µs
• Programmable dead time
• 10–200 ns
• 40–600 ns
• Deglitch option for filtering noise
• Wide operating range
• –40 to +125 °C
Safety Approvals (Pending)
• UL 1577 recognized
• RoHS-compliant packages
• SOIC-16 wide body
• Up to 5000 Vrms for 1 minute
• CSA component notice 5A approval
• IEC 60950-1
• SOIC-16 narrow body
• AEC-Q100 qualified
• VDE certification conformity
• VDE 0884-10
• EN 60950-1 (reinforced insulation)
• CQC certification approval
• GB4943.1
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Rev. 1.0
Si8239x Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Si8239x Ordering Guide
Ordering Part
Number
Configuration Output Enhanced
UVLO
Status
Pin
Delayed Dead-Time Deglitch
Package
Type
Isolation
Rating
UVLO
UVLO
Startup
Time
Setting
Available Now
Si82390AD-IS
Si82390BD-IS
Si82390CD-IS
Si82395AD-IS
Si82395BD-IS
Si82395CD-IS
Si82397AD-IS
Si82397BD-IS
Si82397CD-IS
Si82391AD-IS
Si82391BD-IS
Si82391CD-IS
Si82393CD-IS
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
6 V
8 V
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
No
No
No
No
No
No
No
No
No
No
No
No
Yes
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
12 V
6 V
8 V
No
12 V
6 V
No
No
8 V
No
No
12 V
6 V
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
8 V
No
12 V
12 V
No
HS/LS,
No
VIA/VIB
Si82396AD-IS
Si82396BD-IS
Si82396CD-IS
Si82394AD-IS
Si82394BD-IS
Si82394CD-IS
Si82398AD-IS
Si82398BD-IS
Si82398CD-IS
Si82390AB-IS1
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
HS/LS, PWM
HS/LS, PWM
HS/LS, PWM
HS/LS, PWM
HS/LS, PWM
HS/LS, PWM
Dual, VIA, VIB
6 V
8 V
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
N/A
No
No
No
No
No
No
No
No
No
No
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
N/A
12 V
6 V
No
N/A
Yes
Yes
Yes
No
10–200 ns
10–200 ns
10–200 ns
10–200 ns
10–200 ns
10–200 ns
N/A
8 V
12 V
6 V
8 V
No
12 V
6 V
No
Yes
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
2.5
kVrms
Si82390BB-IS1
Si82390CB-IS1
Si82392BB-IS1
Si82395AB-IS1
Si82395BB-IS1
Dual, VIA, VIB
Dual, VIA, VIB
8 V
12 V
8 V
Yes
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
N/A
N/A
N/A
N/A
N/A
No
No
No
No
No
2.5
kVrms
2.5
kVrms
HS/LS,
VIA/VIB
2.5
kVrms
Dual, VIA, VIB
6 V
No
Yes
Yes
2.5
kVrms
Dual, VIA, VIB
8 V
No
2.5
kVrms
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Si8239x Data Sheet
Ordering Guide
Ordering Part
Number
Configuration Output Enhanced
UVLO
Status
Pin
Delayed Dead-Time Deglitch
Package
Type
Isolation
Rating
UVLO
12 V
6 V
UVLO
Startup
Time
Setting
Si82395CB-IS1
Si82394AB4-IS1
Si82394BB4-IS1
Dual, VIA, VIB
HS/LS, PWM
HS/LS, PWM
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
N/A
No
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
2.5
kVrms
No
40–600 ns
40–600 ns
40–600 ns
Yes
Yes
Yes
2.5
kVrms
8 V
No
2.5
kVrms
Si82394CB4-IS1 HS/LS, PWM
12 V
No
2.5
kVrms
Si82394AD4-IS
Si82394BD4-IS
Si82394CD4-IS
Si82391AB-IS1
HS/LS, PWM
HS/LS, PWM
HS/LS, PWM
Dual, VIA, VIB
6 V
8 V
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
40–600 ns
40–600 ns
40–600 ns
N/A
Yes
Yes
Yes
No
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
12 V
6 V
No
Yes
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
SOIC-16 NB
2.5
kVrms
Si82391BB-IS1
Si82391CB-IS1
Si82396AB-IS1
Si82396BB-IS1
Si82396CB-IS1
Si82398AB4-IS1
Si82398BB4-IS1
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
Dual, VIA, VIB
HS/LS, PWM
HS/LS, PWM
8 V
12 V
6 V
Yes
Yes
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
N/A
N/A
No
No
2.5
kVrms
2.5
kVrms
N/A
No
2.5
kVrms
8 V
N/A
No
2.5
kVrms
12 V
6 V
N/A
No
2.5
kVrms
40–600 ns
40–600 ns
40–600 ns
Yes
Yes
Yes
2.5
kVrms
8 V
2.5
kVrms
Si82398CB4-IS1 HS/LS, PWM
12 V
2.5
kVrms
Si82398AD4-IS
Si82398BD4-IS
Si82398CD4-IS
HS/LS, PWM
HS/LS, PWM
HS/LS, PWM
6 V
8 V
No
No
No
Yes
Yes
Yes
No
No
No
40–600 ns
40–600 ns
40–600 ns
Yes
Yes
Yes
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
SOIC-16 WB 5 kVrms
12 V
Note:
1. All products are rated at 4 A output drive current max, VDDI = 2.5 V – 5.5 V, EN (active high).
2. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifica-
tions and peak solder temperatures.
3. “Si” and “SI” are used interchangeably.
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Rev. 1.0 | 2
Si8239x Data Sheet
System Overview
2. System Overview
The operation of an Si8239x channel is analogous to that of an optocoupler and gate driver, except an RF carrier is modulated instead
of light. This simple architecture provides a robust isolated data path and requires no special considerations or initialization at start-up.
A simplified block diagram for a single Si8239x channel is shown in the following figure.
Figure 2.1. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier. Referring to the
Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The Receiver contains a demodulator that
decodes the input state according to its RF energy content and applies the result to output B via the output driver. This RF on/off keying
scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consumption, and better immunity to
magnetic fields. See the following figure for more details.
Figure 2.2. Modulation Scheme
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Si8239x Data Sheet
System Overview
2.1 Typical Performance Characteristics
The typical performance characteristics depicted in the following figures are for information purposes only. Refer to the Electrical Char-
acteristics table for actual specification limits.
Figure 2.4. Propagation Delay vs. Supply Voltage
Figure 2.3. Rise/Fall Time vs. Supply Voltage
Figure 2.5. Rise/Fall Time vs. Load
Figure 2.6. Propagation Delay vs. Load
Figure 2.7. Propagation Delay vs. Temperature
Figure 2.8. Supply Current vs. Supply Voltage
Figure 2.9. Supply Current vs. Supply Voltage
Figure 2.10. Supply Current vs. Temperature
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Si8239x Data Sheet
System Overview
Figure 2.11. Output Sink Current vs. Supply Voltage
Figure 2.12. Output Source Current vs. Supply Voltage
Figure 2.13. Output Sink Current vs. Temperature
Figure 2.14. Output Source Current vs. Temperature
2.2 Family Overview and Logic Operation During Startup
The Si8239x family of isolated drivers consists of high-side/low-side and dual driver configurations.
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Si8239x Data Sheet
System Overview
2.2.1 Device Behavior
The following are truth tables for the Si8239x families.
Table 2.1. Si82390/1/3 Drivers Enhanced UVLO and Status
EN1
VIA
VIB
VDDI
VDDA
VDDB
VOA
H
VOB
L
RDY
Notes
P2
P
H
L
H
P
P
H
L
H
H
H
H
P
P
P
P
L
H
H
H
H / L4
H / L4
H
P
L
X
X
L
X
X
H
L/NC
X
P
P
P
P
P
P
P
P
L
L
L
L
L
L
H
H
Device disabled
UP2
UD3
Fail-safe output when
VDDI unpowered
X
X
X
X
H
H
P
P
P
UP
P
L
UD
L
L
L
VOA, VOB are actively
driven low if either
VDDA or VDDB is UP
UP
UD
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
4. VOA = VOB = L for Si82393 only
Table 2.2. Si82392/5/6 Drivers with UVLO Status
EN1
H
VIA
VIB
VDDI
VDDA
VDDB
VOA
VOB
RDY
Notes
H
L
L
H
H
P
P
P
P
P
P
P
P
P
H
L
L
H
H
H
H
H
H / L4
H / L4
H
H
L
X
X
L
X
X
H
L/NC
X
P
P
P
P
P
P
P
P
L
L
L
L
L
L
H
H
Device disabled
UP2
UD3
Fail-safe output when
VDDI unpowered
H
L
X
X
H
L
H
H
H
H
P
P
P
P
P
P
UP
UP
P
H
L
UD
UD
H
L
L
L
L
VOA depends on
VDDA state
X
X
UP
UP
UD
UD
VOB depends on
VDDB state
P
L
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
4. VOA = VOB = L for Si82392 only
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Si8239x Data Sheet
System Overview
Table 2.3. Si82397 Dual Drivers with No UVLO Status
EN1
H
VIA
VIB
VDDI
VDDA
VDDB
VOA
VOB
Notes
H
L
L
H
H
L
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
H
L
H
L
L
L
L
H
H
L
H
H
L
H
H
X
X
X
X
L/NC
X
L
Device disabled
UP2
L
Fail-safe output when
VDDI is unpowered
UD3
UD
H
H
X
H
P
P
UP
H
VOA depends on VDDA
state
L
X
X
X
H
L
H
H
H
P
P
P
P
UP
P
L
UP
UP
UD
UD
VOB depends on VDDB
state
P
L
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the VIA,VIB input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
Table 2.4. Si82394/8 PWM Input HS/LS Drivers with UVLO Status
EN1
PWM
VDDI
VDDA
VDDB
VOA
VOB
RDY
Notes
H
H
P
P
P
H
L
H
See Dead-time note and
Figure 2.18 Dead Time
Waveforms for High-
Side/Low-Side Drivers on
page 13 for timing
L
X
X
H
L/NC
X
P
P
P
P
P
P
P
P
L
L
L
H
L
L
H
H
Device disabled
UP2
UD3
Fail-safe output when
VDDI unpowered
H
L
H
H
H
H
P
P
P
P
P
P
UP
UP
P
H
L
UD
UD
L
L
L
L
L
VOA depends on VDDA
state
H
L
UP
UP
UD
UD
VOB depends on VDDB
state
P
H
Note:
1. The EN pin needs to be pulled down with a 100 kΩ resistor externally to GND.
2. The chip can be powered through the PWM input ESD diodes even if VDDI is unpowered. It is recommended that inputs be left
unpowered when VDDI is unpowered. The EN pin has a special ESD circuit that prevents the IC from powering up through the
EN pin.
3. UD = undetermined if same side power is UP.
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Si8239x Data Sheet
System Overview
2.3 Power Supply Connections
Isolation requirements mandate separating VDDI from the driver supplies. The decoupling caps for these supplies must be placed as
close to the VDD and GND pins of the Si8239x as possible. The optimum values for these capacitors are 1 μF and 0.1 μF for VDDI and
10 μF and 0.1 μF for each driver supply. Low effective series resistance (ESR) capacitors, such as Tantalum, are recommended.
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Si8239x Data Sheet
System Overview
2.4 Power Dissipation Considerations
Proper system design must assure that the Si8239x operates within safe thermal limits across the entire load range. The Si8239x total
power dissipation is the sum of the power dissipated by bias supply current, internal parasitic switching losses, and power dissipated by
the series gate resistor and load. Equation 1 shows Si8239x power dissipation.
R
R
n
p
2
DD2
2
DD2
2
DD2
P
= V
* I
+ 2 * V
* I
+ f * C *V
*
+ f * C * V
*
+ 2* f * C * V
D
DDI DDI
DD2 DD2
L
L
int
(
)
(
)
R + R
R + R
p
g
n
g
Equation 1.
Note: Where:
• PD is the total Si8239x device power dissipation (W)
• IDDI is the input side maximum bias current (from table 4.1, 3.8 mA)
• IDD2 is the driver side maximum bias current (from table 4.1, 6.5 mA)
• Cint is the internal parasitic capacitance (370 pf)
• VDDI is the input side VDD supply voltage (2.5 V to 5. 5V)
• VDD2 is the driver side supply voltage (10 V to 24 V)
• f is the switching frequency (Hz)
• CL is the load capacitance (F)
• RG is the external gate resistor (Ω)
• RP is the RDS(ON) of the driver pull-up device (2.7 Ω)
• Rn is the RDS(ON) of the driver pull-down device (1 Ω)
Example calculation (using IDDx values from Table 4.1 for Si82397)
VDDI = 5 V
VDD2 = 12 V
f = 350 kHz
RG = 22 Ω
CL = 2 nF
2.7
2.7 + 22
1
−9
)
−9
)
−12
P
= 5 * .0021 + 2 * 12 *.0025 + 350000 * 2 *10
(
* 144 *
+ 350000 * 2 * 10
(
* 144 *
+ 2 * 350000 * 370 *10
(
* 144
(
)
(
)
)
D
1 + 22
PD = 0.123 W is the total dissipated power by the Si8239x package.
From this, the driver junction temperature can be calculated using Equation 2.
T = T + P * θ
ja
j
A
D
Equation 2.
Note: Where:
• Tj is the junction temperature (°C)
• TA is the ambient temperature (°C)
• PD is the power dissipated in the package (W)
• Θja is the thermal resistance of the package (100 °C/W from table 4.7)
For this example, assume that TA is 25 °C.
T = 25 + 0.123 * 100
j
Tj is 37.3 °C.
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Si8239x Data Sheet
System Overview
Equation 2 can be rearranged to determine the maximum package power dissipation for a given ambient temperature.
T
− T
A
jmax
P
=
Dmax
(
)
θ
ja
Note: Where:
• PDmax is the maximum allowed power dissipation (W)
• Tjmax is the maximum allowed junction temperature (150 °C from table 4.8)
• TA is the ambient temperature (25 °C in this example)
• Θja is the thermal resistance of the package (100 °C/W from table 4.7)
PDmax = 1.25 W
Substituting values used in this example back into Equation 1, establishes a relationship between the maximum capacitive load and
switching frequency.
The following figure shows the relationship between the capacitive load and the switching frequency for four different driver supply vol-
tages. In the figure, the points along the load line represent the package dissipation-limited value of CL as a function of switching fre-
quency.
Figure 2.15. Max Load vs. Switching Frequency
2.5 Layout Considerations
It is most important to minimize ringing in the drive path and noise on the Si8239x VDD lines. Care must be taken to minimize parasitic
inductance in these paths by locating the Si8239x as close to the device it is driving as possible. In addition, the VDD supply and
ground trace paths must be kept short. For this reason, the use of power and ground planes is highly recommended. A split ground
plane system having separate ground and VDD planes for power devices and small signal components provides the best overall noise
performance.
2.6 Undervoltage Lockout Operation
Device behavior during start-up, normal operation and shutdown is shown in Figure 2.16 Si82391/2/3/6/8 Device Behavior during Nor-
mal Operation and Shutdown on page 11, where UVLO+ and UVLO- are the positive-going and negative-going thresholds respective-
ly. Note that outputs VOA and VOB default low when input side power supply (VDDI) is not present.
2.6.1 Device Startup
Outputs VOA and VOB are held low during power-up until VDD is above the UVLO threshold for time period tSTART. Following this,
the outputs follow the states of inputs VIA and VIB.
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Si8239x Data Sheet
System Overview
2.6.2 Undervoltage Lockout
Undervoltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or when VDD is below its
specified operating circuits range. The input (control) side, Driver A and Driver B, each have their own undervoltage lockout monitors.
The Si8239x input side enters UVLO when VDDI < VDDIUV–, and exits UVLO when VDDI > VDDIUV+. The driver outputs, VOA and
VOB, remain low when the input side of the Si8239x is in UVLO and their respective VDD supply (VDDA, VDDB) is within tolerance.
Each driver output can enter or exit UVLO independently for the Si82394/5/6/7/8 products. For example, VOA unconditionally enters
UVLO when VDDA falls below VDDAUV– and exits UVLO when VDDA rises above VDDAUV+. For the Si82390/1/3 products, when
either VDDA or VDDB falls under VDDxUV–, this information is fed back through the isolation barrier to the input side logic which forces
VOB or VOA to be driven low respectively under these conditions. If the application is driving a transformer for an isolated power con-
verter, for example, this behavior is useful to prevent flux imbalances in the transformer. Please note that this feature implies that it can
only be implemented when the VDDA and VDDB power supplies are independent from each other. If a bootstrap circuit is used for
Si82390/1/3, it will prevent the IC from powering up. Do not use the Si82390/1/3 in conjunction with a bootstrap circuit for driver power.
Figure 2.16. Si82391/2/3/6/8 Device Behavior during Normal Operation and Shutdown
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Si8239x Data Sheet
System Overview
Figure 2.17. Si82390/4/5/7 Device Behavior during Normal Operation and Shutdown
2.6.3 Control Inputs
VIA, VIB, and PWM inputs are high-true, TTL level-compatible logic inputs. A logic high signal on VIA or VIB causes the corresponding
output to go high. For PWM input versions (Si82394/8), VOA is high and VOB is low when the PWM input is high, and VOA is low and
VOB is high when the PWM input is low.
2.6.4 Enable Input
When brought low, the EN input unconditionally drives VOA and VOB low regardless of the states of VIA and VIB. Device operation
terminates within tSD after EN = VIL and resumes within tRESTART after EN = VIH. The EN input has no effect if VDDI is below its
UVLO level (i.e., VOA, VOB remain low). The EN pin should be connected to GNDI through a 100 kΩ pull-down resistor.
2.6.5 Delayed Startup Time
Product options Si82390/4/5/7 have a safe startup time (tSTARTUP_SAFE) of 1ms typical from input power valid to output showing
valid data. This feature allows users to proceed through a safe initialization sequence with a monotonic output behavior.
2.6.6 RDY Pin
This is a digital output pin available on all options except the Si82397. The RDY pin is “H” if all the UVLO circuits monitoring VDDI,
VDDA, and VDDB are above UVLO threshold. It indicates that device is ready for operation. An “L” status indicates that one of the
power supplies (VDDI, VDDA, or VDDB) is in an unpowered state.
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Si8239x Data Sheet
System Overview
2.7 Programmable Dead Time and Overlap Protection
All high-side/low-side drivers (Si82394/8) include programmable dead time, which adds a user-programmable delay between transitions
of VOA and VOB. When enabled, dead time is present on all transitions. The amount of dead time delay (DT) is programmed by a
single resistor (RDT) connected from the DT input to ground per the equation below. Note that the dead time pin should be connected
to GND1 through a resistor between the values of 6 kΩ and 100 kΩ and a filter capacitor of 100 pF in parallel as shown in Figure
3.1 Si82394/8 Application Diagram on page 14. It is highly recommended it not be tied to VDDI. See Figure 2.18 Dead Time Wave-
forms for High-Side/Low-Side Drivers on page 13 below.
Figure 2.18. Dead Time Waveforms for High-Side/Low-Side Drivers
2.8 De-glitch Feature
A de-glitch feature is provided on some options, as defined in the Ordering Guide. The de-glitch basically provides an internal time de-
lay during which any noise is ignored and will not pass through the IC. It is about 30 ns; so, for these product options, the prop delay will
be extended by 30 ns.
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Si8239x Data Sheet
Applications
3. Applications
The following examples illustrate typical circuit configurations using the Si8239x.
3.1 High-Side/Low-Side Driver
The following figure shows the Si82394/8 controlled by a single PWM signal.
Figure 3.1. Si82394/8 Application Diagram
In the above figure, D1 and CB form a conventional bootstrap circuit that allows VOA to operate as a high-side driver for Q1, which has
a maximum drain voltage of 1500 V. VOB is connected as a conventional low-side driver. Note that the input side of the Si8239x re-
quires VDDI in the range of 2.5 to 5.5 V, while the VDDA and VDDB output side supplies must be between 6.5 and 24 V with respect to
their respective grounds. The boot-strap start up time will depend on the CB cap chosen. Also note that the bypass capacitors on the
Si8239x should be located as close to the chip as possible.
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Si8239x Data Sheet
Applications
3.2 Dual Driver
The following figure shows the Si82390/1/5/6/7 configured as a dual driver. Note that the drain voltages of Q1 and Q2 can be refer-
enced to a common ground or to different grounds with as much as 1500 Vdc between them.
VDDB
C3
D1
1 µF
VDDI
VDDI
GNDI
C2
0.1 µF
C1
1 µF
VDDA
1500 V max
Q1
CB
VOA
VIA
VIB
OUT 1
OUT 2
GNDA
Si82392/5/6/7
CONTROLLER
VDDB
VDDB
GNDB
C4
0.1 µF
C5
10 µF
I/O
I/O
EN
RPD
RDY
Q2
(Not present
on Si82397)
VOB
Figure 3.2. Si82392/5/6/7 Application Diagram
VDDI
VDDI
Q1
C2
0.1 µF
C1
1 µF
VOA
GNDI
VDDA
VIA
VIB
OUT 1
OUT 2
VDDA
C3
0.1 µF
C4
10 µF
Si82390/1/3
CONTROLLER
VDDB
VDDB
GNDB
C5
0.1 µF
C6
10 µF
I/O
I/O
EN
RPD
RDY
Q2
VOB
Figure 3.3. Si82390/1/3 with Enhanced UVLO Feature Application Diagram
Because each output driver resides on its own die, the relative voltage polarities of VOA and VOB can reverse without damaging the
driver. A dual driver can operate as a dual low-side or dual high-side driver and is unaffected by static or dynamic voltage polarity
changes. The Si82390/1/3 come equipped with an enhanced UVLO feature as described in 2.6.2 Undervoltage Lockout. This feature is
intended for systems which provide VDDA and VDDB as independent isolated power supplies. Si82390/1/3 are not recommended for
use with bootstrap configuration for driver supply since the driver output will not be asserted unless both VDDA and VDDB are above
the UVLO threshold.
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Si8239x Data Sheet
Electrical Characteristics
4. Electrical Characteristics
Table 4.1. Electrical Characteristics1,2
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
DC Specifications
Input-side Power Supply Voltage
Driver Supply Voltage
VDDI
2.5
6.5
3.3
—
5.5
24
V
V
VDDA, VDDB
Voltage between VDDA and
GNDA, and VDDB and
GNDB
Input Supply Quiescent Current EN = 0
IDDI(Q)
Si82390/1/2/3/4/5/6/8
Si82397
—
—
—
2.8
1.5
4.2
3.8
2.1
6.5
mA
mA
mA
Output Supply Quiescent Current, per
channel EN = 0
IDDA(Q),
IDDB(Q)
Si82390/1/2/3/4/5/6/8
Si82397
—
—
1.5
5.0
2.5
7.2
mA
mA
Input Supply Active Current
IDDI
Si82390/1/2/3/5/6 VIA, VIB
freq = 1 MHz
Si82394/8: PWM freq = 1
MHz
—
—
5.2
3.7
7.1
4.4
—
7.3
5.6
Si82397: VIA, VIB freq = 1
MHz
Output Supply Active Current, per
channel
IDDA/B
Si82390/1/2/3/4/5/6/8: Input
freq = 1 MHz, no load
—
16.0
12.4
+10
mA
µA
Si82397: Input freq = 1 MHz,
no load
—
Input Pin Leakage Current, VIA, VIB,
PWM
IVIA, IVIB, IPWM
–10
Input Pin Leakage Current, EN
Logic High Input Threshold
Logic Low Input Threshold
Input Hysteresis
IENABLE
VIH
–10
2.0
—
—
—
+10
—
µA
V
TTL Levels
TTL Levels
VIL
—
0.8
—
V
VIHYST
400
450
—
mV
V
Logic High Output Voltage
VOAH, VOBH
IOA, IOB = –1 mA
VDDA,
VDDB –
0.04
—
Logic Low Output Voltage
VOAL, VOBL
IOA, IOB = 1 mA
—
—
—
0.04
—
V
A
Output Short-Circuit Pulsed Source
Current
IOA(SCL),
IOB(SCL)
See Figure 4.1 IOL Sink Cur-
rent Test on page 19
4.0
Output Short-Circuit Pulsed Source
Current
IOA(SCH),
IOB(SCH)
See Figure 4.2 IOH Source
Current Test on page 19
—
2.0
—
A
Output Sink Resistance
RON(SINK)
RON(SOURCE)
VDDIUV+
—
—
1.0
2.7
2.3
2.2
100
—
—
Ω
Ω
Output Source Resistance
VDDI Undervoltage Threshold
VDDI Undervoltage Threshold
VDDI Lockout Hysteresis
VDDI rising
VDDI falling
2.15
2.1
80
2.5
2.4
—
V
VDDIUV–
V
VDDIHYS
mV
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Si8239x Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDDA, VDDB Undervoltage Threshold
VDDAUV+
,
VDDA, VDDB rising
V
VDDBUV+
6 V
5.0
7.2
9.2
6.0
8.6
7.0
8 V
10.0
12.8
12 V
11.1
VDDA, VDDB Undervoltage Threshold
VDDAUV–
,
VDDA, VDDB falling
V
VDDBUV–
6 V
4.7
6.6
5.8
8.0
6.7
9.3
11.6
—
8 V
12 V
8.7
10.1
280
600
1000
VDDA, VDDB Lockout Hysteresis
VDDAHYS
VDDBHYS
,
UVLO = 6 V
UVLO = 8 V
UVLO = 12 V
200
450
600
mV
—
—
AC Specifications
UVLO Fault Shutdown Time Enhanced
Mode
VDDAUV– to VOB low
VDDBUV– to VOA low
—
—
120
10
—
—
ns
ns
Si82390/1/3 only
UVLO Fault Shutdown Time
VDDAUV– to VOA low
VDDBUV– to VOB low
UVLO fault to RDY
Minimum Pulse Width
Propagation Delay
t_FLT
—
—
20
92
30
30
—
—
40
ns
ns
ns
tpHL, tpLH
Si82390/1/2/3/5/6/7 (with no
de-glitch)
VDDA/B = 12 V
CL = 0 pF
tpHL
tpLH
Si82394/8 (with no de-glitch)
20
35
30
45
40
55
ns
ns
Si82394/8 (with no de-glitch;
measured with 6 kΩ RDT re-
sistor; includes minimum
dead time)
tpHL
Si82394xx4/8xx4 (have de-
glitch)
60
99
77
95
ns
ns
tpLH
Si82394xx4/8xx4 (have de-
glitch and measured with 6
kΩ RDT resistor; includes
minimum dead time and de-
glitch delay)
116
135
Pulse Width Distortion |tPLH – tPHL
|
PWD
DT
VDDA/B = 12 V
CL = 0 pF
—
2.7
5.60
ns
ns
Programmed Dead Time for product
options with 40–600 ns dead time set-
ting range
RDT = 6 kΩ
RDT = 15 kΩ
RDT = 100 kΩ
CL = 200 pF
27
70
38
90
57
130
750
12
450
—
590
—
Output Rise and Fall Time
tR,tF
ns
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Si8239x Data Sheet
Electrical Characteristics
Parameter
Symbol
Test Condition
Min
—
Typ
—
Max
60
Unit
Shutdown Time from Enable False
tSD
All options with no de-glitch
All options with de-glitch
All options with no de-glitch
All options with de-glitch
ns
—
—
113
60
Restart Time from Enable True
Device Start-up Time Input
tRESTART
—
—
ns
—
—
95
Time from VDDI_ =
VDDI_UV+ to VOA, VOB =
VIA, VIB
—
—
Si82390/4/5/7
Si82391/2/3/6/8
Device Start-up Time
Output
tSTART_SAFE
tSTART
1
ms
µs
µs
40
60
tSTART_OUT
Time from VDDA/B = VDDA/
B_UV+ to VOA, VOB = VIA,
VIB
—
—
—
Common Mode Transient Immunity
CMTI
VIA, VIB, PWM = VDDI or 0
V
35
100
kV/µs
VCM = 1500 V
Note:
1. 2.5 V < VDDI < 5.5 V; 6.5 V < VDDA, VDDB < 24 V; TA = –40 to +125 °C.
2. Typical specs at 25 °C, VDDA = VDDB = 12 V for 5 V and 8 V UVLO devices, otherwise 15 V.
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Si8239x Data Sheet
Electrical Characteristics
The following figures depict sink current, source current, and common-mode transient immunity test circuits, respectively.
Figure 4.1. IOL Sink Current Test
Figure 4.2. IOH Source Current Test
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Si8239x Data Sheet
Electrical Characteristics
Figure 4.3. CMTI Test Circuit
Table 4.2. Regulatory Information1,2,3
CSA
The Si8239x is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
VDE
The Si8239x is certified according to VDE 0884-10. For more details, see File 5006301-4880-0001.
VDE 0884-10: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si8239x is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
CQC
The Si8239x is certified under GB4943.1-2011. For more details, see certificates CQCxxx (TBD).
Rated up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
Note:
1. Regulatory Certifications apply to 2.5 kVRMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
2. Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
3. For more information, see Ordering Guide.
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Si8239x Data Sheet
Electrical Characteristics
Table 4.3. Insulation and Safety-Related Specifications
Parameter
Symbol
Test Condition
Value
Unit
WBSOIC-16
NBSOIC-16
Nominal Air Gap
(Clearance)1
L(1O1)
L(1O2)
8.0
4.01
mm
Nominal External
Tracking (Creepage)
8.0
4.01
mm
mm
Minimum Internal
Gap (Internal Clear-
ance)
0.014
0.014
Tracking Resistance
(Proof Tracking In-
dex)
PTI
IEC60112
600
600
V
Erosion Depth
ED
0.019
1012
0.019
1012
mm
Ω
Resistance (Input-
Output)2
RIO
Capacitance (Input-
Output)2
CIO
CI
f = 1 MHz
1.4
4.0
1.4
4.0
pF
pF
Input Capacitance3
Note:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in 7. Package Outline: 16-Pin Wide
Body SOIC and 9. Package Outline: 16-Pin Narrow Body SOIC. VDE certifies the clearance and creepage limits as 4.7 mm mini-
mum for the NB SOIC-16 and 8.5 mm minimum for the WB SOIC-16 package. UL does not impose a clearance and creepage
minimum for component level certifications. CSA certifies the clearance and creepage limits as 3.9 mm minimum for the NB SO-
IC16 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si8239x is converted into a 2-terminal device. Pins 1–8 are shorted together to
form the first terminal,and pins 9–16 are shorted together to form the second terminal. The parameters are then measured be-
tween these two terminals.
3. Measured from input pin to ground.
Table 4.4. IEC 60664-1 (VDE 0884) Ratings
Parameter
Test Condition
Specification
WB SOIC-16
NB SOIC-16
Basic Isolation Group
Material Group
I
I
Installation Classification
Rated Mains Voltages < 150 VRMS
Rated Mains Voltages < 300 VRMS
Rated Mains Voltages < 400 VRMS
Rated Mains Voltages < 600 VRMS
I-IV
I-IV
I-III
I-III
I-IV
I-III
I-II
I-II
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Si8239x Data Sheet
Electrical Characteristics
Table 4.5. IEC 60747-5-5 Insulation Characteristics
Parameter
Symbol
Test Condition
Characteristic
Unit
WB SOIC-16
NB SOIC-16
Maximum Working
Insulation Voltage
VIORM
891
560
V peak
V peak
Input to Output Test
Voltage
VPR
Method b1 (VIORM
x
1671
1050
1.875 = VPR, 100%
Production Test, tm
= 1 sec, Partial Dis-
charge < 5 pC)
Transient Overvolt-
age
VIOTM
t = 60 sec
6000
2
4000
2
V peak
Pollution Degree
(DIN VDE 0110, See
Table 4.1 Electrical
Characteristics1,2 on
page 16)
>109
>109
Insulation Resist-
RS
Ω
ance at TS, VIO
=
500 V
Note:
1. Maintenance of the safety data is ensured by protective circuits. The Si8239x provides a climate classification of 40/125/21.
Table 4.6. IEC Safety Limiting Values1
Parameter
Symbol
Test Condition
WB SOIC-16
NB SOIC-16
Unit
°C
Safety Temperature
Safety Input Current
TS
IS
150
50
150
50
θJA = 100 °C/W (WB
SOIC-16), 105 °C/W
(NB SOIC-16)
mA
VDDI = 5.5 V,
VDDA = VDDB = 24 V,
TJ = 150 °C, TA = 25 °C
Device Power Dissi-
pation2
PD
1.2
1.2
W
Note:
1. Maximum value allowed in the event of a failure. Refer to the thermal derating curve in Figure 4.4 WB SOIC-16, NB SOIC-16
Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature per VDE 0884-10 on page 24.
2. The Si8239x is tested with VDDI = 5.5 V, VDDA = VDDB = 24 V, TJ = 150 ºC, CL = 100 pF, input 2 MHz 50% duty cycle square
wave.
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Si8239x Data Sheet
Electrical Characteristics
Table 4.7. Thermal Characteristics
Parameter
Symbol
WB SOIC-16
NB SOIC-16
Unit
IC Junction-to-Air Ther-
mal Resistance
θJA
100
105
°C/W
Table 4.8. Absolute Maximum Ratings1
Parameter
Symbol
Min
Max
Unit
Ambient Temperature
under Bias
TA
–40
+125
°C
Storage Temperature
Junction Temperature
TSTG
TJ
–65
—
+150
+150
6.0
°C
°C
V
Input-side Supply Volt-
age
VDDI
–0.6
Driver-side Supply Volt-
age
VDDA, VDDB
VIO
–0.6
–0.5
—
30
VDD + 0.5
4.0
V
V
A
Voltage on any Pin with
respect to Ground
Peak Output Current
(tPW = 10 µs, duty cycle
= 0.2%)
IOPK
Lead Solder Tempera-
ture (10 s)
—
260
°C
ESD per AEC-Q100
HBM
CDM
—
—
—
4
2
kV
kV
Maximum Isolation (Input
to Output) (1 s) WB SO-
IC-16
6500
VRMS
Maximum Isolation (Out-
put to Output) (1 s) WB
SOIC-16
—
—
—
2500
4500
2500
VRMS
VRMS
VRMS
Maximum Isolation (Input
to Output) (1 s) NB SO-
IC-16
Maximum Isolation (Out-
put to Output) (1 s) NB
SOIC-16
Note:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to
the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for ex-
tended periods may affect device reliability.
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Si8239x Data Sheet
Electrical Characteristics
Figure 4.4. WB SOIC-16, NB SOIC-16 Thermal Derating Curve, Dependence of Safety Limiting Values with Case Temperature
per VDE 0884-10
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Si8239x Data Sheet
Top-Level Block Diagrams
5. Top-Level Block Diagrams
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
UVLO
VDDB
EN
VOB
UVLO
GNDB
VIB
RDY
GNDI
Si82390/1/3
Figure 5.1. Si82390/1/3 Dual Isolated Drivers with Enhanced UVLO Safety
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Si8239x Data Sheet
Top-Level Block Diagrams
VDDA
VIA
VOA
UVLO
GNDA
VDDI
VDDI
UVLO
VDDB
EN
VOB
UVLO
GNDB
VIB
RDY
GNDI
Si82392/5/6
Figure 5.2. Si82392/5/6 Dual Isolated Drivers with RDY Pin
Figure 5.3. Si82394/98 Single-Input High-Side/Low-Side Isolated Drivers
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Si8239x Data Sheet
Top-Level Block Diagrams
Figure 5.4. Si82397 Dual Isolated Drivers
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Si8239x Data Sheet
Pin Descriptions
6. Pin Descriptions
VDDA
VOA
GNDA
NC
VDDA
VOA
GNDA
NC
VIA
1
2
3
4
5
16
15
14
13
12
PWM
1
2
3
4
5
16
15
14
13
12
VIB
NC
VDDI
VDDI
GNDI
EN
GNDI
EN
Si82390/91/3
Si82392/5/96
Si82394/8
NC
NC
NC
RDY
DT
RDY
6
7
8
11
10
9
VDDB
VOB
6
7
8
11
10
9
VDDB
VOB
GNDB
GNDB
VDDI
VDDI
VDDA
VOA
GNDA
NC
VIA
1
2
3
4
5
16
15
14
13
12
VIB
VDDI
GNDI
EN
Si82397
NC
NC
NC
6
7
8
11
10
9
VDDB
VOB
GNDB
VDDI
Figure 6.1. Si8239x SOIC-16
Table 6.1. Pin Descriptions
Description
Pin Name
PWM
VIA
PWM input
Non-inverting logic input terminal for Driver A.
Non-inverting logic input terminal for Driver B.
Input-side power supply terminal; connect to a source of 2.5 to 5.5 V.
Input-side ground terminal.
VIB
VDDI
GNDI
EN
Device ENABLE. When low or NC, this input unconditionally drives outputs VOA, VOB LOW. When high, device is ena-
bled to perform in normal operating mode. It is strongly recommended that this input be connected to external logic level
to avoid erroneous operation due to capacitive noise coupling.
DT
Dead time programming input. The value of the resistor connected from DT to ground sets the dead time between output
transitions of VOA and VOB.
RDY
Power ready on secondary side for Driver A and Driver B (both UVLO thresholds for VDDA and VDDB need to be
crossed). High state indicates UVLO thresholds crossed, low state indicates UVLO low condition. No reset is necessary.
NC
No connection.
GNDB
VOB
Ground terminal for Driver B.
Driver B output (low-side driver).
VDDB
GNDA
VOA
Driver B power supply voltage terminal; connect to a source of 6.5 to 24 V.
Ground terminal for Driver A.
Driver A output (high-side driver).
VDDA
Driver A power supply voltage terminal; connect to a source of 6.5 to 24 V.
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Si8239x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
7. Package Outline: 16-Pin Wide Body SOIC
The following figure illustrates the package details for the Si8239x in a 16-Pin Wide Body SOIC. The table lists the values for the dimen-
sions shown in the illustration.
Figure 7.1. 16-Pin Wide Body SOIC
Table 7.1. Package Diagram Dimensions
Symbol
Millimeters
Min
—
Max
2.65
0.30
—
A
A1
A2
b
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
1.27
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Si8239x Data Sheet
Package Outline: 16-Pin Wide Body SOIC
Symbol
Millimeters
Min
0.25
0°
Max
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification for small body, lead-free components.
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Si8239x Data Sheet
Land Pattern: 16-Pin Wide Body SOIC
8. Land Pattern: 16-Pin Wide Body SOIC
The following figure illustrates the recommended land pattern details for the Si8239x in a 16-Pin Wide-Body SOIC. The table lists the
values for the dimensions shown in the illustration.
Figure 8.1. 16-Pin Wide Body SOIC PCB Land Pattern
Table 8.1. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN for Density Level B (Median Land Protru-
sion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8239x Data Sheet
Package Outline: 16-Pin Narrow Body SOIC
9. Package Outline: 16-Pin Narrow Body SOIC
The following figure illustrates the package details for the Si8239x in a 16-Pin Narrow-Body SOIC. The table lists the values for the
dimensions shown in the illustration.
Figure 9.1. 16-Pin Narrow Body SOIC
Table 9.1. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
Dimension
Min
Max
A
A1
A2
b
L
0.40
1.27
0.10
1.25
0.31
0.17
L2
0.25 BSC
h
0.25
0°
0.50
8°
0.51
0.25
θ
c
aaa
bbb
ccc
ddd
0.10
0.20
0.10
0.25
D
9.90 BSC
6.00 BSC
3.90 BSC
1.27 BSC
E
E1
e
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
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Si8239x Data Sheet
Land Pattern: 16-Pin Narrow Body SOIC
10. Land Pattern: 16-Pin Narrow Body SOIC
The following figure illustrates the recommended land pattern details for the Si8239x in a 16-Pin Narrow-Body SOIC. The table lists the
values for the dimensions shown in the illustration.
Figure 10.1. 16-Pin Narrow Body SOIC PCB Land Pattern
Table 10.1. 16-Pin Narrow Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Note:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0.05 mm is assumed.
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Si8239x Data Sheet
Top Markings
11. Top Markings
11.1 Si8239x Top Marking (16-Pin Wide Body SOIC)
11.2 Top Marking Explanation (16-Pin Wide Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si8239 = ISOdriver product series
Y = Output configuration: 0, 1, 3, 4, 5, 6, 7, 8
0, 1, 5, 6, 7 = Dual drivers
See Ordering Guide for more informa-
tion.
3 = Dual input (VIA, VIB) High Side/Low Side drivers
4, 8 = PWM input High side/Low side drivers
U = UVLO level: A, B, C
A = 6 V; B = 8 V; C = 12 V
V = Isolation rating: B, D
B = 2.5 kV; D = 5.0 kV
D = Dead time setting range: none, 4
none = 10–200 ns; 4 = 40–600 ns
Line 2 Marking:
Line 3 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the year
and workweek of the mold date.
WW = Workweek
TTTTTT = Mfg Code
Circle = 1.5 mm Diameter
(Center Justified)
Country of Origin
ISO Code Abbreviation
Manufacturing Code from Assembly Purchase Order form.
“e4” Pb-Free Symbol
TW = Taiwan
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Si8239x Data Sheet
Top Markings
11.3 Si8239x Top Marking (16-Pin Narrow Body SOIC)
11.4 Top Marking Explanation (16-Pin Narrow Body SOIC)
Line 1 Marking:
Base Part Number
Ordering Options
Si8239 = ISOdriver product series
Y = Output configuration: 0, 1, 2, 4, 5, 6, 7, 8
0, 1, 5, 6, 7 = Dual drivers
See Ordering Guide for more informa-
tion.
2 = Dual input (VIA, VIB) High side/Low side drivers
4, 8 = PWM input High side/Low side drivers
U = UVLO level: A, B, C
A = 6 V; B = 8 V; C = 12 V
V = Isolation rating: B, D
B = 2.5 kV; D = 5.0 kV
D = Dead time setting range: none, 4
none = 10–200; 4 = 40–600
Line 2 Marking:
YY = Year
Assigned by the Assembly House. Corresponds to the year
and workweek of the mold date.
WW = Workweek
TTTTTT = Mfg Code
Manufacturing Code from Assembly Purchase Order form.
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Table of Contents
1. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1 Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . 4
2.2 Family Overview and Logic Operation During Startup . . . . . . . . . . . . . . . . 5
2.2.1 Device Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Power Supply Connections . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.6 Undervoltage Lockout Operation . . . . . . . . . . . . . . . . . . . . . . .10
2.6.1 Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.6.2 Undervoltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.6.3 Control Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.6.4 Enable Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.6.5 Delayed Startup Time . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.6.6 RDY Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.7 Programmable Dead Time and Overlap Protection . . . . . . . . . . . . . . . . .13
2.8 De-glitch Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3. Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 High-Side/Low-Side Driver . . . . . . . . . . . . . . . . . . . . . . . . .14
3.2 Dual Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. Top-Level Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 25
6. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7. Package Outline: 16-Pin Wide Body SOIC. . . . . . . . . . . . . . . . . . . . 29
8. Land Pattern: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . 31
9. Package Outline: 16-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . 32
10. Land Pattern: 16-Pin Narrow Body SOIC. . . . . . . . . . . . . . . . . . . . 33
11. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11.1 Si8239x Top Marking (16-Pin Wide Body SOIC) . . . . . . . . . . . . . . . . . .34
11.2 Top Marking Explanation (16-Pin Wide Body SOIC). . . . . . . . . . . . . . . . .34
11.3 Si8239x Top Marking (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . . .35
11.4 Top Marking Explanation (16-Pin Narrow Body SOIC) . . . . . . . . . . . . . . . .35
Table of Contents 36
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intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"
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