SI3000-KSR [SILICON]
Programmable Codec, 1-Func, PDSO16, SOIC-16;
| 型号： | SI3000-KSR |
| 厂家： | 
SILICON |
| 描述： | Programmable Codec, 1-Func, PDSO16, SOIC-16 放大器 电动机控制 |
| 文件： | 总34页 (文件大小：816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Si3000
VOICEBAND CODEC WITH MICROPHONE/SPEAKER DRIVE
Features
Complete voice codec solution includes the following:
84 dB ADC Dynamic Range
84 dB DAC Dynamic Range
4–12 kHz Sample Rates
30 dB Microphone Pre-Amp
Support for 32 Headphones
3:1 Analog Input Mixer
3.3–5.0 V Power Supply
Direct Serial Interface to DSPs
Programmable Input Gain/
Direct Connection to Si303x/44/56,
Ordering Information:
Attenuation: –34.5 dB to 12 dB
serial interface DAA chipsets
See page 29.
Programmable Output Gain/
Low profile 16-Pin SOIC Package
Attenuation: –34.5 dB to 12 dB
RoHS-compliant package
available
Pin Assignments
Si3000
Applications
Modem Voice Channel (DSVD) Speech Processing
1
2
3
4
5
6
7
8
SPKRL
Telephony
General Purpose Analog I/O
SPKRR
MBIAS
HDST
SDI
16
15
14
13
12
11
10
9
LINEO
GND
VA
Companion chip for FDX
ISOmodems with voice features
SDO
VD
Description
FSYNC
MCLK
SCLK
LINEI
MIC
The Si3000 is a complete voice band audio codec solution that offers high
integration by incorporating programmable input and output gain/
attenuation, a microphone bias circuit, handset hybrid circuit, and an
output drive for 32 headphones. The Si3000 can be connected directly
to the Si3034, Si3035, Si3044, and Si3056 North American and
international DAA chipsets through their daisy-chaining serial interface. It
also serves as a companion chip to a FAT ISOmodem chipset with voice
features, providing hardware support for a handset and speaker phone.
The device operates from a single 3.3 to 5 V power supply and is
available in a 16-pin small outline package (SOIC).
RESET
Functional Block Diagram
Si3000
MBIAS
0/+10/+20/+30 dB
MIC
MCLK
Prog Gain/
Attenuator
ADC
SCLK
LINEI
0/+10/+20 dB
FSYNC
Digital
SDI
Handset
Hybrid
Interface
HDST
SDO
0/–6/–12/–18 dB
SPKRR
Headphone
Driver
Prog Gain/
Attenuator
DAC
SPKRL
LINEO
0/–6/–12/–18 dB
RESET
Rev. 1.4 12/10
Copyright © 2010 by Silicon Laboratories
Si3000
Si3000
2
Rev. 1.4
Si3000
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.2. Pre-amp/Microphone Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.3. Programmable Input Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.4. Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.5. Programmable Output Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.6. Line Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.7. Speaker Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.8. Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
2.9. Clock Generation Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.10. Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.11. Loopback Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2.12. Reducing Power-on Pop Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4. Pin Descriptions: Si3000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Package Outline: 16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
7. 16-Pin SOIC Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
8. Package Markings (Top Markings) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.1. Si3000-C-GS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
8.2. Si3000-C-FS Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Rev. 1.4
3
Si3000
1. Electrical Specifications
Table 1. Recommended Operating Conditions
1
1
Parameter
Symbol
Test Condition
Typ
Unit
Min
0
Max
Ambient Temperature
TA
VA
VD
F and K-grade
25
70
°C
V
Si3000 Supply Voltage, Analog2
Si3000 Supply Voltage, Digital2,3
3.0
3.0
3.3/5.0
3.3/5.0
5.25
5.25
V
Notes:
1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated.
2. The digital supply, VD, and analog supply, VA, can operate from either 3.3 V or 5.0 V. The Si3000 supports interface to
3.3 V logic when operating from 3.3 V. VD must be within 0.6 V of VA.
3. The Si3000 specifications are guaranteed using the typical application circuit (including component tolerance) of
Figure 13.
Table 2. DC Characteristics, VA/VD = 5 V
(VA = 5 V ±5%, VD = 5 V ±5%, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
VIL
VOH
VOL
IL
3.5
—
—
—
—
—
—
6.5
10
—
—
0.8
—
V
V
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
Power Supply Current, Analog1
Power Supply Current, Digital2
Total Supply Current, Sleep Mode3
IO = –2 mA
IO = 2 mA
3.5
—
V
0.4
10
10
15
1.5
V
–10
—
µA
mA
mA
mA
IA
VA pin
VD pin
ID
—
—
Notes:
1. No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz.
2. Slave mode operation, Fs = 12.5 kHz.
3. All inputs, except MCLK, are held static, and all outputs are unloaded.
Table 3. DC Characteristics, VA/VD = 3.3 V
(VA = 3.3 V ±10%, VD = 3.3 V ±10%, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
High Level Input Voltage
VIH
VIL
VOH
VOL
IL
2.4
—
—
—
—
—
—
6
—
0.8
—
V
V
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Input Leakage Current
IO = –2 mA
IO = 2 mA
2.4
—
V
0.35
10
V
–10
—
µA
mA
mA
mA
Power Supply Current, Analog
Power Supply Current, Digital2
Total Supply Current, Sleep Mode3
IA
VA pin
VD pin
10
ID
—
6
10
—
—
1.5
Notes:
1. No loads at DAC outputs, no load at MBIAS, Fs=12.5 kHz.
2. Slave mode operation, Fs = 12.5 kHz.
3. All inputs, except MCLK, are held static, and all outputs are unloaded.
4
Rev. 1.4
Si3000
Table 4. AC Characteristics
(VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Min
—
Typ
16
Max
—
Unit
Bits
dB
ADC Resolution
ADC Dynamic Range1,2
ADC Total Harmonic Distortion3
VA, VD = 3.3 V ±10%
ADCDR
VIN = 1 kHz, –3 dB
80
84
—
ADCTHD VIN = 1 kHz, –3 dB, MIC/LINEI
VIN = 1 kHz, –3 dB, HDST
—
–80
–80
–80
–80
1
–62
–62
–76
–71
—
dB
—
ADC Total Harmonic Distortion3
VA, VD = 5 V ±5%
ADCTHD VIN = 1 kHz, –3 dB, MIC/LINEI
VIN = 1 kHz, –3 dB, HDST
—
dB
—
ADC Full Scale Level (0 dB gain)4
ADC Programmable Input Gain
ADC Input Gain Step Size
ADC Freq Response5
ADC Freq Response5
ADC Freq Response
VRX
Vin = 1 kHz
—
Vrms
dB
dB
Hz
dB
dB
dB
dB
–34.5
—
—
12
—
1.5
33
FRR
FRR
FRR
Low –3 dB corner
300 Hz
—
—
–0.1
–0.2
—
—
0
3400 Hz
—
0
Line In Preamp Gain
0/10/20
—
Mic In Preamp Gain
—
0/10/20/
30
—
ADC Input Resistance
ADC Input Capacitance
ADC Gain Drift
0 dB Preamp Gain
VIN = 1 kHz
—
—
20
15
—
—
k
pF
AT
—
0.002
16
—
dB/°C
Bits
dB
DAC Resolution
—
—
DAC Dynamic Range1,2
DAC Total Harmonic Distortion3
VA, VD = 3.3 V ±10%
DACDR
VIN = 1 kHz, –6 dB
80
—
84
—
DACTHD VIN=1 kHz,–6 dB,LINEO,600
VIN=1 kHz,–6 dB, SPKR, 60
VIN=1 kHz,–6 dB, HDST, 600
DACTHD VIN=1 kHz,–3 dB,LINEO,600
VIN=1 kHz,–3 dB, SPKR, 60
VIN=1 kHz,–3 dB, HDST, 600
VRX
–76
–72
–80
–76
–72
–80
1
–60
–60
–70
–65
–65
–76
—
dB
—
—
DAC Total Harmonic Distortion3
VA, VD = 5 V ±5%
—
dB
—
—
DAC Full Scale Level (0 dB gain)
DAC Programmable Output Gain
Notes:
—
Vrms
dB
–34.5
—
12
1. DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges
between 4000 and 12000 Hz.
2. 0 dB setting for analog and digital attenuation/gain.
3. THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz.
4. At 0 dB gain setting, 1 Vrms input corresponds to –1.5 dB of full scale digital output code.
5. These characteristics are determined by external components. See Figure 13.
6. With a 600 load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 Vrms output.
Rev. 1.4
5
Si3000
Table 4. AC Characteristics (Continued)
(VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C)
Parameter
Symbol
Test Condition
Min
—
Typ
1.5
33
Max
—
—
0
Unit
dB
DAC Output Gain Step Size
DAC Freq Response5
FRR
FRR
FRR
Low –3 dB corner
300 Hz
—
Hz
DAC Freq Response5
–0.01
–0.2
600
—
—
dB
DAC Freq Response
3400 Hz
—
0
dB
DAC Line Output Load Resistance
DAC Line Output Load Capacitance
DAC SPKR Output Load Resistance
DAC Gain Drift
—
—
40
—
—
—
—
—
—
—
—
—
pF
—
60
AT
VIN = 1 kHz
—
0.002
90
dB/°C
dB
Interchannel Isolation (Crosstalk)
HDST Full Scale Level Input
HDST Full Scale Level Output6
HDST Output Resistance
MIC Bias Voltage
—
—
0.5
1.0
600
2.5
40
Vrms
Vrms
—
Rout
Vmbias
PSRR
DC
—
—
V
MIC Power Supply Rejection Ratio
Notes:
—
dB
1. DR = VIN + 20 log (RMS signal/RMS noise). Measurement bandwidth is 300 to 3400 Hz. Valid sample rate ranges
between 4000 and 12000 Hz.
2. 0 dB setting for analog and digital attenuation/gain.
3. THD = 20 log (RMS distortion/RMS signal). Valid sample rate ranges between 4000 and 12000 Hz.
4. At 0 dB gain setting, 1 Vrms input corresponds to –1.5 dB of full scale digital output code.
5. These characteristics are determined by external components. See Figure 13.
6. With a 600 load. Output starts clipping with half of full scale digital input, which corresponds to a 0.5 Vrms output.
Table 5. Absolute Maximum Ratings
Parameter
Symbol
V , V
Value
–0.5 to 6.0
±10
Unit
V
DC Supply Voltage
D
A
Input Current, Si3000 Digital Input Pins
Digital Input Voltage
I
mA
V
IN
V
–0.3 to (V + 0.3)
IND
D
Operating Temperature Range
Storage Temperature Range
T
–10 to 100
–40 to 150
°C
°C
A
T
STG
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
6
Rev. 1.4
Si3000
Table 6. Switching Characteristics—General Inputs
(VA, VD = 5 V ±5% or 3.3 V ±10%,TA = 0 to 70°C, CL = 20 pF)
1
Symbol
Test Condition
Min
Typ
Max
Unit
Parameter
Cycle Time, MCLK
MCLK Duty Cycle
Rise Time, MCLK
Fall Time, MCLK
RESET Pulse Width
Rise Time, RESET
Notes:
t
t
16.67
40
—
50
—
—
—
1
—
60
5
ns
%
mc
dty
t
—
ns
ns
ns
µs
r
t
—
5
f
2
t
250
—
—
—
rl
t
Rr
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VD –
0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width is the greater of 5 s or 10 MCLK cycle times.
tmc
tr
tf
VIH
VIL
MCLK
tRr
RESET
trl
Figure 1. General Inputs Timing Diagram
Rev. 1.4
7
Si3000
Table 7. Switching Characteristics—Serial Interface
(VA, VD = 5 V ±5% or 3.3 V ±10%, TA = 0 to 70°C, CL = 20 pF)
Parameter
Symbol
Test Condition
Min
354
—
Typ
Max
—
Unit
ns
%
Cycle Time, SCLK
t
1/256 Fs
c
SCLK Duty Cycle
t
50
—
—
—
—
—
—
—
dty
Delay Time, SCLK to FSYNC
Delay Time, SCLK to SDO Valid
Delay Time, SCLK to FSYNC
Setup Time, SDI, before SCLK
Hold Time, SDI, after SCLK
t
—
10
20
10
—
ns
ns
ns
ns
ns
ns
d1
d2
d3
t
—
t
—
t
25
20
25
su
t
—
h
Setup Time, FSYNC (mode 2) before
t
—
su
MCLK
Hold Time, FSYNC (mode 2) after
t
20
—
—
ns
h
MCLK
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VD – 0.4 V, VIL = 0.4 V
tc
VOH
VOL
SCLK
td3
td1
FSYNC
(mode 0)
td3
FSYNC
(mode 1)
FSYNC
(mode 2)
td2
16 Bit
SDO
High-Z
High-Z
D15
D14
D14
... D2
D1
D1
D0
tsu
th
16 Bit
SDI
D15
... D2
D0
Figure 2. Serial Interface Timing Diagram
8
Rev. 1.4
Si3000
Table 8. Digital FIR Filter Characteristics—Transmit and Receive
(VA, VD = 5 V ±5% or 3.3 V ±10%, Sample Rate = 8 kHz, TA = 0 to 70°C)
Parameter
Symbol
Min
0
Typ
—
Max
3.6
3.6
0.1
—
Unit
kHz
kHz
dB
F
Passband (3 dB, HPFD = 1)
Passband (3 dB, HPFD = 0)
Passband Ripple Peak-to-Peak
Stopband
(3 dB)
F
0.01
–0.1
—
—
(3 dB)
—
4.4
—
kHz
dB
–74
—
—
Stopband Attenuation
Group Delay
t
12/Fs
—
sec
gd
Note: Typical FIR filter characteristics for Fs = 8000 Hz are shown in Figures 3, 4, 5, and 6.
Table 9. Digital IIR Filter Characteristics—Transmit and Receive
(VA, VD = 5 V ±5% or 3.3 V ±10%, Sample Rate = 8 kHz, TA = 70°C)
Parameter
Symbol
Min
0
Typ
—
Max
3.6
3.6
0.2
—
Unit
kHz
kHz
dB
F
Passband (3 dB, HPFD = 1)
Passband (3 dB, HPFD = 0)
Passband Ripple Peak-to-Peak
Stopband
(3 dB)
F
0.01
–0.2
—
—
(3 dB)
—
4.4
—
kHz
dB
–40
—
—
Stopband Attenuation
Group Delay
t
1.6/Fs
—
sec
gd
Note: Typical IIR filter characteristics for Fs = 8000 Hz are shown in Figures 7, 8, 9, and 10. Figures 11 and 12 show group
delay versus input frequency.
Rev. 1.4
9
Si3000
Input Frequency - Hz
Input Frequency - Hz
Figure 3. FIR Receive Filter Response
Figure 5. FIR Transmit Filter Response
Input Frequency - Hz
Input Frequency - Hz
Figure 6. FIR Transmit Filter Passband Ripple
Figure 4. FIR Receive Filter Passband Ripple
For Figures 3–6, all filter plots apply to a sample rate of
Fs = 8 kHz. The filters scale with the sample rate as follows:
= 0.4125 Fs
F
(0.1 dB)
F
= 0.45 Fs
(– 3 dB)
where Fs is the sample frequency.
10
Rev. 1.4
Si3000
Input Frequency - Hz
Input Frequency - Hz
Figure 7. IIR Receive Filter Response
Figure 10. IIR Transmit Filter Passband Ripple
Input Frequency - Hz
Input Frequency - Hz
Figure 8. IIR Receive Filter Passband Ripple
Figure 11. IIR Receive Group Delay
Input Frequency - Hz
Input Frequency - Hz
Figure 9. IIR Transmit Filter Response
Figure 12. IIR Transmit Group Delay
Rev. 1.4
11
Si3000
12
Rev. 1.4
Si3000
‘
Table 10. Component Values—Typical Application
Symbol
Value
C1,C3,C6,C8
0.1 µF, 16 V, ±20%
10 µF, 16 V, ±20%
Motorola MMBD914L
Phonejack Stereo
4 Header
C2,C4,C5,C7,C9,C10
D1
J1,J2
JP1
K1
Relay DPDT
L1,L2
R1
Ferrite Bead
0 , 1/4 W ±5%
51 , 1/4 W ±5%
10 k, 1/4 W ±5%
2.2 k, 1/4 W, ±5%
10 , 1/16 W, ±5%
30 , 1/16 W, ±5%
LM317LZ
R2
R4
R8
R9
R11,R12
U2
Q1
PNP Transistor
Rev. 1.4
13
Si3000
2.2. Pre-amp/Microphone Bias Circuit
2. Functional Description
An internal amplifier with a selectable gain of 0 dB,
10 dB, 20 dB, or 30 dB is provided for the MIC input and
an internal amplifier with a selectable gain of 0 dB,
10 dB, or 20 dB, is provided for the LINEI input. AC
coupling is required for both inputs because any DC
offset on the input will be amplified if gain is selected.
Gain settings for the LINEI and MIC inputs are achieved
by writing the RX Gain Control 1 register 5. When gain
is disabled, these inputs become line level inputs with a
full-scale input of 1 Vrms.
The Si3000 is a highly integrated voice bandwidth audio
codec which contains a single 16-bit A/D converter and
D/A converter. The analog input path contains a
microphone input with selectable gain, a line level input
with selectable gain, and a handset input. Each of the
inputs go through a mixer prior to A/D conversion. The
result of this A/D conversion is a 16-bit 2s complement
signed number. Following the A/D converter is a digital
programmable gain amplifier. The analog output path
contains a digital programmable gain amplifier feeding a
single 16-bit D/A converter. The DAC output is provided
to a line output, a headphone drive output, and a
handset output. Control for the various functions
available on the Si3000 as well as the audio data are
communicated to the device over a serial interface.
A microphone bias circuit is provided on-chip which
consists of a 2.5 V reference output capable of sourcing
up to 5 mA of current. This circuit can be used for active
microphones requiring a bias source.
2.3. Programmable Input Gain/Attenuation
The Si3000 can be connected directly to the Si3035,
Si3034, Si3044, or Si3056 in modem applications
requiring a voice channel, or the device can be used as
a stand-alone codec in other voice band applications.
The Si3000 offers high integration, and it needs only a
few low-cost, discrete components as shown in
Figure 13.
The signals from the microphone, line, or handset inputs
are mixed and then routed to the A/D converter and a
digital programmable gain circuit which provides up to
12 dB of gain or –34.5 dB of attenuation in 1.5 dB steps.
Level changes only take effect on zero crossings to
minimize audible artifacts. The requested level change
is implemented if no zero crossing is found after 256
frames. Write the ADC Volume Control register 6 to set
digital input gain/attenuation.
2.1. Analog Inputs
The typical connection diagram (Figure 13) shows the
recommended external analog circuitry for the Si3000.
The device supports three mono analog inputs—line
level, microphone level, and a handset input. Each of
these inputs is provided to a mixer circuit prior to A/D
conversion. Each analog input may also be muted by
writing the appropriate bits in the control registers.
Unused analog inputs should be tied to GND through a
0.1 F capacitor. This prevents any DC current flow.
2.4. Analog Outputs
The analog outputs of the D/A converter are routed to a
line level output (LINEO), a pair of speaker outputs
(SPKRL and SPKRR), and a handset. Each analog
output can be independently muted.
Si3034/35/44/56 Chipsets
DAA
Line-Side
Device
DAA
System-Side
Device
TIP
Discretes
RING
DSP
SPKR
Line
Si3000
Voice Codec
Handset
Mic
Figure 14. Si3000 with Silicon Labs DAA System Diagram
14
Rev. 1.4
Si3000
frequency and the value of the sample rate control
registers 3 and 4 determine the sample rate (Fs). The
serial port clock, SCLK, runs at 256 bits per frame,
where the frame rate is equivalent to the sample rate.
Digital information is transferred between the DSP and
the Si3000 in the form of 16-bit Primary Frames and 16-
bit Secondary Frames. There are separate pins for
receive (SDO) and transmit (SDI) functions, providing
simultaneous receive/transmit operation within each
frame.
2.5. Programmable Output Gain/Attenuation
Prior to D/A conversion, the Si3000 contains a digital
programmable gain/attenuator which provides up to
12 dB of gain or –34.5 dB of attenuation in 1.5 dB steps.
Level changes only take effect on zero crossings to
minimize audible artifacts. The requested level change
is implemented if no zero crossing is found after 256
frames. Write the DAC Volume Control (register 7) to
set digital input gain/attenuation.
2.6. Line Output
Primary Frames are used for digital audio data samples.
Primary Frames occur at the frame rate and are always
present.
Secondary Frames are used for accessing internal
Si3000 registers. Secondary Frames are not always
present and are requested on-demand. When
Secondary Frames are present, they occur mid-point
between Primary Frames. Hence, no Primary Frames
are dropped.
On Primary Frame transmits (DSP to Si3000), the
Si3000 treats the LSB (16th bit) as a flag to request a
Secondary Frame. Set the primary frame LSB = 1 to
request a secondary frame; otherwise, set the primary
frame LSB = 0. Therefore, out of 16-bits of transmit data
on SDI, only 15-bits represent actual audio data. When
secondary frames are not present, no transmission
occurs during this time slot.
On Primary Frames receives (Si3000 to DSP), the
Si3000 drives SDO with 16-bits of audio data, if the
Si3000 is in either Serial Mode 0 or 1. However, if the
Si3000 is in SLAVE mode (Mode 2), the Si3000
supplies 15-bits of Audio Data to the DSP and always
drives the LSB zero. This feature is designed to work
with the Si3021 register 14 SSEL set to 10. In this
system configuration, when the DSP receives Primary
Frames, it can check the LSB to determine whether the
receive data is from the Si3021 or from the Si3000.
On Secondary Frame receives and transmits; the
Si3000 treats the input and output serial stream as 16-
bits of data. Figure 15 shows the relative timing of the
serial frames.
LINEO is a line level analog output signal centered
around a common mode voltage. The minimum
recommended load impedance is 600 . This output is
a fully filtered output with a 1 Vrms full scale range. The
only external component required is the 10 F DC
blocking capacitor shown in Figure 13 on page 12. This
output may be muted through the LOM bit in register 6
or attenuated by setting the analog attenuation bits in
register 9.
2.7. Speaker Output
The SPKRL and SPKRR are mono, in-phase, analog
outputs capable of driving a small loudspeaker whose
impedance is typically 32 (see Figure 13 on page 12).
The speaker outputs may be muted through the SLM
and SRM bits in the DAC Gain Control register 7 or
attenuated by setting the analog attenuation bits in
register 9.
2.8. Digital Interface
The Si3000 has two serial interface modes that support
most standard modem DSPs. These modes are
selected by the addition of a 50 k pull-down/up resistor
on the SDO and SCLK pins as shown in Figure 13 on
page 12. The key difference between these two serial
modes is the operation of the FSYNC signal. Table 11
summarizes the serial mode definitions.
Table 11. Serial Modes
Mode SCLK* SDO*
Description
FSYNC frames data
FSYNC pulse starts data frame
Slave mode
0
1
2
3
0
0
1
1
0
1
0
1
Figure 16 and Figure 17 illustrate the secondary frame
write cycle and read cycle, respectively. During a read
cycle, the R/W bit is high and the 5-bit address field
contains the address of the register to be read. The
contents of the 8-bit control register are placed on the
SDO signal. During a write cycle, the R/W bit is low and
the 5-bit address field contains the address of the
register to be written. The 8-bit data to be written
immediately follows the address on SDI. Only one
register can be read or written during each secondary
frame. See "3. Control Registers" on page 19 for the
register addresses and functions.
Reserved
*Note: Pull-up/pull-down states
The digital interface consists of a single synchronous
serial link which communicates audio and control data.
In slave mode, SCLK is connected only to the pullup/
pulldown resistor, and MCLK is a 256 Fs input which is
internally multiplied using the on-chip phase-locked loop
(PLL) to clock the A/D converter and D/A converter. In
master mode, the master clock (MCLK) is an input and
the serial data clock (SCLK) is an output. The MCLK
Rev. 1.4
15
Si3000
Primary
Secondary
Primary
FSYNC
D15 – D1 D0 = 0 (Software FC Bit)
Secondary
Update
XMT Data
XMT Data
RCV Data
SDI
Secondary
Update
RCV Data
SDO
16 SCLKs
128 SCLKs
256 SCLKs
Figure 15. Secondary Request
FSYNC
(mode 0)
FSYNC
(mode 1)
D15 D14 D13 D12 D11 D10 D9 D8
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
A
A
A
A
A
D
D
D
D
D
D
D
D
SDI
R/W
SDO
Figure 16. Secondary Communication Data Format—Write Cycle
FSYNC
(mode 0)
FSYNC
(mode 1)
D0
D15 D14 D13 D12 D11 D10 D9 D8 D7
0
0
1
A
A
A
A
A
SDI
D7 D6 D5 D4 D3 D2 D1 D0
R/W
D
D
D
D
D
D
D
D
High Z
SDO
High Z
Figure 17. Secondary Frame Format—Read Cycle
16
Rev. 1.4
Si3000
FUP1
FPLL1
MCLK
÷ N1
P
÷ 5 or
÷ 10*
VCO1
1024·Fs
D
*Note: See PLL bit in Register 2.
÷ M1
8 bits
Figure 18. Clock Generation Subsystem (PLL)
2.9. Clock Generation Subsystem
Table 12. MCLK Examples for 8 kHz
The Si3000 contains an on-chip clock generator. Using
a single MCLK input frequency, the Si3000 can
generate all the desired standard modem sample rates,
as well as the common 11.025 kHz rate for audio
playback.
MCLK (MHz)
1.8432
N1
9
M1
200
256
10
4.0000
25
1
4.0960
The clock generator consists of a phase-locked loop
(PLL1) that achieves the desired sample frequency.
Figure 18 illustrates the clock generator. The
architecture of the PLL allows for fast lock time on initial
start-up, fast lock time when changing modem sample
rates and high noise immunity. A large number of MCLK
frequencies between 1 MHz and 60 MHz are supported.
5.2800
33
9
256
64
5.7600
6.1440
3
20
8.1920
1
5
9.2160
9
40
2.9.1. Programming the Clock Generator
10.0800
10.5600
11.0592
12.288
63
33
27
3
256
128
100
10
As noted in Figure 18, the clock generator must output a
clock equal to 1024*Fs, where Fs is the desired sample
rate. The 1024*Fs clock is determined through
programming of the following registers:
Register 3 - N1 divider, 8 bits.
14.7456
16.0000
18.4320
24.5760
25.8048
33.7600
44.2368
46.0800
47.9232
48.0000
56.0000
59.200
9
25
Register 4 - M1 divider, 8 bits
25
9
64
N1 (register 3) and M1 (register 4) are 8-bit unsigned
20
values. F
is the clock provided to the MCLK pin.
MCLK
Table 12 lists several standard crystal rates that could
be supplied to MCLK.
3
5
63
211
27
9
100
256
25
When programming the registers of the clock generator,
the order of register writes is important. For PLL
updates, N1 (register 3) must always be written first,
immediately followed by a write to M1 (register 4).
8
Note: The values shown in Table 12 satisfy the equations
above. However, when programming the registers for
N1 and M1, the value placed in these registers must be
one less than the value calculated from the equations.
117
75
175
185
100
64
128
128
Rev. 1.4
17
Si3000
3. Restore MCLK before initiating the power up sequence.
2.9.2. PLL Lock Times
4. Reset the Si3000 using the RESET pin (after MCLK is
present).
The Si3000 changes sample rates very quickly.
However, lock time will vary based on the programming
of the clock generator. The following relationship
describes the boundaries on PLL locking time:
5. Program the registers to desired settings.
2.11. Loopback Operation
PLL lock time < 1 ms
The Si3000 advanced design provides the
manufacturer with increased ability to determine system
functionality during production line tests, as well as
support for end-user diagnostics. Two loopback modes
exist for this purpose, allowing increased coverage of
system components.
It is recommended that the PLL be programmed during
initialization.
The final design consideration for the clock generator is
the update rate of PLL. The following criteria must be
satisfied in order for the PLL to remain stable:
F
= F
N1 144kHz
The digital loopback1 mode allows an external device to
send audio data to the SDI input pin and receive the
signal through the SDO output pin. In this mode, the
group delay of the digital filters is present. This mode
UP1
MCLK
Where F
is shown in Figure 18.
UP1
2.9.3. Setting Generic Sample Rates
The above clock generation description focuses on allows testing of the digital filters, DAC, and ADC. To
common modem sample rates. The restrictions and enable this mode, set the DL1 bit of register 2, and clear
equations above still apply; however, a more generic DL2.
relationship between MCLK and Fs (the desired sample
rate) is needed. The following equation describes this
send audio data to the SDI input pin and receive the
relationship:
The digital loopback2 mode allows an external device to
signal through the SDO output pin. This mode allows
M1
5 1024 Fs
testing of the digital filters, but not the ADC and DAC. To
enable this mode, set the DL2 bit of register 2, and clear
DL1.
------- = --------------------------------
N1 MCLK
where Fs is the sample frequency, and all other symbols
are shown in Figure 18.
2.12. Reducing Power-on Pop Noise
Knowing the MCLK frequency and desired sample rate
the values for the M1 and N1 registers can be
determined. When determining these values, remember
to consider the range for each register as well as the
minimum update rate for the first PLL.
To minimize power-on pop during initialization, a waiting
period is recommended before powering up the analog
output drivers. The waiting period starts when the reset
signal to the Si3000 is negated. The wait time required
is dependent on the external load. Typically, the load
consists of an AC coupling capacitor in series with an
equivalent load resistor to ground. The equivalent load
resistor can either be a speaker load, or the input
resistance of an external amplifier. The rule-of-thumb for
the waiting period in msec is derived by C*(12+R). For
example, in the case of a 10 F AC coupling capacitor
and resistive load of 1.0 k the recommended waiting
period is 10*(12+1) = 130 msec.
The values determined for M1 and N1 must be adjusted
by minus one when determining the value written to the
respective registers. This is due to internal logic, which
adds one to the value stored in the register. This
addition allows the user to write a zero value in any of
the registers and the effective divide-by is one. A
special case occurs when both M1 and N1 are
programmed with a zero value. When M1 and N1 are
both zero, the PLL is bypassed.
If the analog outputs drive external amplifiers, another
factor to consider is the voltage division ratio
determined by R/(R+12), where R represents the input
resistance of the external amplifier. This ratio must be
kept as small as possible. A good target value is R = 1
k. If needed, add a load resistor in parallel with the
amplifier input to lower the effective input resistance of
the amplifier stage.
2.10. Sleep Mode
The Si3000 supports a low-power sleep mode. Sleep
mode is activated by setting the Chip Power Down
(CPD) bit in register 1. When the Si3000 is in sleep
mode, the MCLK signal may be stopped or remain
active, but it must be active before waking up the
Si3000. To take the Si3000 out of sleep mode, pulse the
reset pin (RESET) low. In summary, the power down/up
sequence is as follows:
1. Set the Power Down bit (PDN, register 6, bit 3).
2. MCLK may stay active or stop.
18
Rev. 1.4
Si3000
3. Control Registers
Note: Any register not listed here is reserved and should not be written. Any register bit labelled reserved should be written to
zero during writes to the register. Register 0 can be read (always returns 0) and written safely.
Table 13. Register Summary
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
SPD
Bit 3
LPD
PLL
Bit 2
HPD
DL1
Bit 1
MPD
DL2
Bit 0
1
2
3
4
5
6
7
8
9
Control 1
SR
CPD
Control 2
HPFD
PLL1 Divide N1
PLL1 Multiply M1
RX Gain Control 1
ADC Volume Control
DAC Volume Control
Status Report
Divider N1
Multiplier M1
MCG
LIG
LIM
MCM
HIM
LOM
SLM
IIR
RXG
TXG
HOM
SRM
SLSC
SRSC
LOSC
Analog Attenuation
LOT
SOT
Rev. 1.4
19
Si3000
Register 1. Control 1
Bit
D7
SR
D6
D5
D4
D3
D2
D1
D0
Name
Type
SPD
R/W
LPD
R/W
HPD
R/W
MPD
R/W
CPD
R/W
R/W
Reset settings = 0000_0000
Bit
Name
Function
7
SR
Software Reset.
1 = Sets all registers to their reset value.
0 = Enables chip for normal operation.
Note: Bit will automatically clear after being set.
6:5 Reserved Read returns zero.
4
3
2
1
0
SPD
LPD
HPD
MPD
CPD
Speaker Drive Power Down.
1= Normal operation
0 = Power down left and right speaker drive.
Line Drive Power Down.
1 = Normal operation
0 = Power down line driver.
Handset Drive Power Down.
1 = Normal operation
0 = Power down handset driver.
MIC Bias Power Down.
1 = Power down MIC bias buffer.
0 = Normal operation
Chip Power Down.
1 = Puts Si3000 into power down mode.
0 = Normal operation
20
Rev. 1.4
Si3000
Register 2. Control 2
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
HPFD
R/W
PLL
R/W
DL1
R/W
DL2
R/W
Reset Settings = 0000_0000
Bit
7:5
4
Name
Reserved
HPFD
Function
Read returns zero.
High Pass Filter (HPF) Disable.
1 = HPF disabled
0 = HPF enabled
3
2
1
0
PLL
DL1
PLL Divide by 10.
1 = Sets final stage of PLL to divide by 10.
0 = Sets final stage of PLL to divide by 5.
Digital Loopback.
1 = Enables digital loopback (DAC analog out ADC analog in).
0 = Normal operation
DL2
Digital Loopback.
1 = Enables digital loopback (DAC one bit ADC one bit).
0 = Normal operation
Reserved
Read returns zero.
Rev. 1.4
21
Si3000
Register 3. PLL1 Divide N1
Bit
D7
D6
D5
D4
Divider N1
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
N1
N1.
Contains the (value – 1) for determining the output frequency on PLL.
Register 4. PLL1 Multiply M1
Bit
D7
D6
D5
D4
Multiplier M1
R/W
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7:0
M1
M1.
Contains the (value – 1) for determining the output frequency on PLL.
22
Rev. 1.4
Si3000
Register 5. RX Gain Control 1
Bit
D7
D6
D5
LIM
R/W
D4
D3
D2
D1
D0
IIR
Name
Type
LIG
MCG
R/W
MCM
R/W
HIM
R/W
R/W
R/W
Reset settings = 0100_0111
Bit
Name
Function
7:6
LIG
Line in Gain.
11 = 20 dB gain
10 = 10 dB gain
01 = 0 dB gain
00 = Reserved
5
LIM
Line in Mute.
1 = Line input muted
0 = Line input goes to mixer
4:3
MCG
MIC Input Gain.
11 = 30 dB gain
10 = 20 dB gain
01 = 10 dB gain
00 = 0 dB gain
2
1
0
MCM
HIM
IIR
MIC Input Mute.
1 = Mute MIC input
0 = MIC input goes into mixer.
Handset Input Mute.
1 = Mute handset input
0 = Handset input goes into mixer.
IIR Enable.
1 = Enables IIR filter
0 = Enables FIR filter
Rev. 1.4
23
Si3000
Register 6. ADC Volume Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
RXG
R/W
LOM
R/W
HOM
R/W
Reset settings = 0101_1100
Bit
7
Name
Reserved
RXG
Function
Read returns zero.
6:2
RX PGA Gain Control.
11111 = 12 dB
10111 = 0 dB
00000 = –34.5 dB
LSB = 1.5 dB
1
0
LOM
HOM
Line Out Mute.
0 = Mute
1 = Active
Handset Out Mute.
0 = Mute
1 = Active
24
Rev. 1.4
Si3000
Register 7. DAC Volume Control
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
TXG
R/W
SLM
R/W
SRM
R/W
Reset settings = 0101_1100
Bit
7
Name
Reserved
TXG
Function
Read returns zero.
6:2
TX PGA Gain Control.
11111 = 12 dB
10111 = 0 dB
00000 = –34.5 dB
LSB = 1.5 dB
1
0
SLM
SRM
SPKR_L Mute.
0 = Mute
1 = Active
SPKR_R Mute.
0 = Mute
1 = Active
Rev. 1.4
25
Si3000
Register 8. Status Report
Bit
D7
SLSC
R
D6
SRSC
R
D5
LOSC
R
D4
D3
D2
D1
D0
Name
Type
Reset settings = 0000_0000
Bit
Name
Function
7
SLSC
SPK_L Short Circuit.
1 = Indicate short circuit status is detected at left speaker.
0 = Normal mode
6
5
SRSC
LOSC
SPK_R Short Circuit.
1 = Indicate short circuit status is detected at right speaker.
0 = Normal mode
Line Out Short Circuit.
1 = Indicate short circuit status is detected at line out.
0 = Normal mode
4:0
Reserved
Read returns zero.
Register 9. Analog Attenuation
Bit
D7
D6
D5
D4
D3
D2
D1
D0
Name
Type
LOT
R/W
SOT
R/W
Reset settings = 0000_0000
Bit
7:4
3:2
Name
Reserved
LOT
Type
Read returns zero.
Line Out Attenuation.
11 = –18 dB analog attenuation on Line Output.
10 = –12 dB analog attenuation on Line Output.
01 = –6 dB analog attenuation on Line Output.
00 = 0 dB analog attenuation on Line Output.
Speaker Out Attenuation.
2:0
SOT
11 = –18 dB analog attenuation on Speaker Output.
10 = –12 dB analog attenuation on Speaker Output.
01 = –6 dB analog attenuation on Speaker Output.
00 = 0 dB analog attenuation on Speaker Output.
26
Rev. 1.4
Si3000
4. Pin Descriptions: Si3000
1
2
3
4
5
6
7
8
SPKRL
LINEO
GND
VA
SPKRR
16
15
14
13
12
11
10
9
MBIAS
HDST
SDI
SDO
VD
FSYNC
MCLK
SCLK
LINEI
MIC
RESET
Pin #
Pin Name
Description
1
SPKRR
Speaker Right Output.
Analog output capable of driving a 60 load.
2
3
MBIAS
HDST
Microphone bias output.
Handset Input/Output.
Handset analog input/output.
4
SDI
Serial Port Data In.
Serial communication and control data that is generated by the System DSP to the
Si3000.
5
6
SDO
Serial Port Data Out.
Serial communication data that is provided by the Si3000 to the system DSP.
FSYNC
Frame Sync Output.
Data framing signal that is used to indicate the start and stop of a communication data
frame.
7
8
MCLK
SCLK
Master Clock Input.
High speed master clock input. Generally supplied by the system crystal clock or DSP.
Serial Port Bit Clock Input/Output.
Controls the serial data on SDO and latches the data on SDI. This pin is an input in
slave mode and an output in master mode.
9
RESET
Reset.
An active low input that is used to reset all control registers to a defined initialized
state. Also used to bring the Si3000 out of sleep mode.
10
11
12
MIC
MIC Input.
Microphone level or line level input. This input contains selectable gain of 0, 10, 20, or
30 dB with a full scale input level of 1 V
.
RMS
LINEI
Line Input.
Line level input with selectable gain of 0, 10, or 20 dB. The full scale input level is
1 V
.
RMS
V
Digital Supply Voltage.
D
Provides the digital supply voltage to the Si3000. Nominally either 5 or 3.3 V and
within 0.6 V of V .
A
Rev. 1.4
27
Si3000
Pin #
Pin Name
Description
13
V
Analog Supply Voltage.
Provides the analog supply voltage to the Si3000. Nominally either 5 or 3.3 V and
A
within 0.6 V of V .
D
14
15
GND
Ground.
Connects to the system digital ground.
LINEO
Line Output.
Line level analog output with a 1 V
full scale output level.
RMS
16
SPKRL
Speaker Left Output.
Analog output capable of driving a 60 load.
28
Rev. 1.4
Si3000
5. Ordering Guide
Table 14. Ordering Guide
Part Number
Si3000-C-FS
Si3000-C-GS
Package
SOIC-16
SOIC-16
Lead-Free
Yes
Temp. Range
0 to 70 °C
Yes
–40 to 85 °C
*Note: Add an “R” at the end of the device to denote tape and reel option.
Rev. 1.4
29
Si3000
6. Package Outline: 16-Pin SOIC
Figure 19 illustrates the package details for the Si3000. Table 15 lists the values for the dimensions shown in the
illustration.
Figure 19. 16-Pin Small Outline Integrated Circuit (SOIC) Package
Table 15. Package Diagram Dimensions
Dimension
Min
—
Max
1.75
0.25
—
Dimension
Min
Max
A
A1
A2
b
L
L2
h
0.40
1.27
0.10
1.25
0.31
0.17
0.25 BSC
0.25
0°
0.50
8°
0.51
0.25
θ
c
aaa
bbb
0.10
0.20
D
9.90 BSC
6.00 BSC
3.90 BSC
E
ccc
0.10
0.25
E1
ddd
e
1.27 BSC
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
30
Rev. 1.4
Si3000
7. 16-Pin SOIC Land Pattern
Figure illustrates the recommended land pattern for the Si3000 16-pin SOIC. Table 16 lists the values for the
dimensions shown in the illustration.
Figure 20. 16-Pin SOIC Land Pattern Diagram
Table 16. 16-Pin MSOP Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
mm
5.40
1.27
0.60
1.55
C1
E
X1
Y1
Pad Length
Notes:
General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ASME Y14.5M-1994.
3. This Land Pattern Design is based on the IPC-7351 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a
Fabrication Allowance of 0.05 mm.
Solder Mask Design
5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
Stencil Design
6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
7. The stencil thickness should be 0.125 mm (5 mils).
8. The ratio of stencil aperture to land pad size should be 1:1.
Card Assembly
9. A No-Clean, Type-3 solder paste is recommended.
10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
Rev. 1.4
31
Si3000
8. Package Markings (Top Markings)
Codes for the Si3000-C-GS and Si3000-C-FS top marks are as follows:
YY = Current Year
WW = Work Week
R = Die Revision
TTTTT = Trace Code
8.1. Si3000-C-GS Top Marking
8.2. Si3000-C-FS Top Marking
32
Rev. 1.4
Si3000
DOCUMENT CHANGE LIST
Revision 1.0 to Revision 1.1
Updated Functional Block Diagram.
Removed all B-grade references.
Updated Table 4 (AC Characteristics).
Updated Figure 14.
Removed analog loopback feature description.
Revision 1.1 to Revision 1.2
Updated " Features" on page 1 and "5. Ordering
Guide" on page 29 to add updated support for lead-
free, RoHS-compliant packages.
Updated document for compatibility with Silicon
Laboratories 3rd generation serial interface DAA, the
Si3056.
Updated Figure 13 on page 12.
Updated MIC and MICBIAS pin number labels.
Changed standardized minimum input/output
attenuation level to –34.5 dB. In some instances, this
level was incorrectly specified at –36 dB.
Updated SOIC package outline drawing and
dimensions table.
Revision 1.2 to Revision 1.3
Updated Table 6 on page 7.
Updated Figure 1 on page 7.
Updated Figure 2 on page 8.
Updated Figure 13 on page 12.
Updated "2.8. Digital Interface" on page 15.
Updated "2.11. Loopback Operation" on page 18.
Updated "4. Pin Descriptions: Si3000" on page 27.
Revision 1.3 to Revision 1.4
Added extended temperature Si3000-C-GS to Table
14 ordering guide.
Added Section 7, 16-Pin SOIC Land Pattern.
Added Section 8, Package Top Markings.
Rev. 1.4
33
Si3000
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34
Rev. 1.4
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