EFM32G210 [SILICON]
Wake-up Interrupt Controller;型号: | EFM32G210 |
厂家: | SILICON |
描述: | Wake-up Interrupt Controller |
文件: | 总68页 (文件大小:1797K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
EFM32G210 DATASHEET
EFM32G210F128
• ARM Cortex-M3 CPU platform
• Communication interfaces
• High Performance 32-bit processor @ up to 32 MHz
• Memory Protection Unit
• 2× Universal Synchronous/Asynchronous Receiv-
er/Transmitter
• UART/SPI/SmartCard (ISO 7816)/IrDA
• Triple buffered full/half-duplex operation
• Low Energy UART
• Wake-up Interrupt Controller
• Flexible Energy Management System
• 20 nA @ 3 V Shutoff Mode
• Autonomous operation with DMA in Deep Sleep
Mode
• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out
Detector, RAM and CPU retention
• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz
oscillator, Power-on Reset, Brown-out Detector, RAM and CPU
retention
• 45 µA/MHz @ 3 V Sleep Mode
• 180 µA/MHz @ 3 V Run Mode, with code executed from flash
• 128 KB Flash
• I2C Interface with SMBus support
• Address recognition in Stop Mode
• Ultra low power precision analog peripherals
• 12-bit 1 Msamples/s Analog to Digital Converter
• 4 single ended channels/2 differential channels
• On-chip temperature sensor
• 16 KB RAM
• 24 General Purpose I/O pins
• 12-bit 500 ksamples/s Digital to Analog Converter
• 2× Analog Comparator
• Configurable push-pull, open-drain, pull-up/down, input filter, drive
strength
• Capacitive sensing with up to 5 inputs
• Supply Voltage Comparator
• Configurable peripheral I/O locations
• 14 asynchronous external interrupts
• Output state retention and wake-up from Shutoff Mode
• 8 Channel DMA Controller
• Ultra efficient Power-on Reset and Brown-Out Detec-
tor
• 2-pin Serial Wire Debug interface
• 1-pin Serial Wire Viewer
• 8 Channel Peripheral Reflex System (PRS) for autonomous in-
ter-peripheral signaling
• Hardware AES with 128/256-bit keys in 54/75 cycles
• Timers/Counters
• Pre-Programmed UART Bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.98 to 3.8 V
• QFN32 package
• 2× 16-bit Timer/Counter
• 2×3 Compare/Capture/PWM channels
• Dead-Time Insertion on TIMER0
• 16-bit Low Energy Timer
• 1× 24-bit Real-Time Counter
• 1× 8-bit Pulse Counter
• Watchdog Timer with dedicated RC oscillator @ 50 nA
32-bit ARM Cortex-M0+, Cortex-M3 and Cortex-M4 microcontrollers for:
• Energy, gas, water and smart metering
• Health and fitness applications
• Smart accessories
• Alarm and security systems
• Industrial and home automation
...the world's most energy friendly microcontrollers
1 Ordering Information
Table 1.1 (p. 2) shows the available EFM32G210 devices.
Table 1.1. Ordering Information
Ordering Code
Flash (kB) RAM (kB)
Max
Speed
(MHz)
Supply
Voltage
(V)
Temperature
(ºC)
Package
EFM32G210F128-QFN32
128
16
32
1.98 - 3.8
-40 - 85
QFN32
Adding the suffix 'T' to the part number (e.g. EFM32G210F128-QFN32T) denotes tray.
Visit www.silabs.com for information on global distributors and representatives.
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2 System Summary
2.1 System Introduction
The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of
the powerful 32-bit ARM Cortex-M3, innovative low energy techniques, short wake-up time from energy
saving modes, and a wide selection of peripherals, the EFM32G microcontroller is well suited for any
battery operated application as well as other systems requiring high performance and low-energy con-
sumption. This section gives a short introduction to each of the modules in general terms and also shows
a summary of the configuration for the EFM32G210 devices. For a complete feature set and in-depth
information on the modules, the reader is referred to the EFM32G Reference Manual.
A block diagram of the EFM32G210 is shown in Figure 2.1 (p. 3) .
Figure 2.1. Block Diagram
G210F128
Core andMemory
Clock Management
Energy Management
High Frequency
Crystal
High Frequency
RC
Oscillator
Memory
Protection
Unit
Voltage
Regulator
Voltage
Comparator
Oscillator
ARM Cortex™- M3 processor
Low Frequency
RC
Aux High Freq
RC
Oscillator
Oscillator
Flash
Program
Memory
RAM
Memory
Debug
Interface
DMA
Controller
Power-on
Reset
Brown-out
Detector
Low Frequency
Crystal
Oscillator
Watchdog
Oscillator
128 KB
16 KB
32-bit bus
Peripheral Reflex System
Serial Interfaces
I/O Ports
Timers andTriggers
Analog Interfaces
Security
Timer/
Counter
Peripheral
Reflex
System
General
Purpose
I/ O
USART
2x
ADC
DAC
AES
2x
24 pins
Low Energy Real Time
Timer™
Counter
Low
Analog
Comparator
Energy
UART™
External
Interrupts
Pin
Reset
I2C
Pulse
Counter
Watchdog
Timer
2x
2.1.1 ARM Cortex-M3 Core
The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone
MIPS/MHz. A Memory Protection Unit with support for up to 8 memory segments is included, as well
as a Wake-up Interrupt Controller handling interrupts triggered while the CPU is asleep. The EFM32
implementation of the Cortex-M3 is described in detail in EFM32G Cortex-M3 Reference Manual.
2.1.2 Debug Interface (DBG)
This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition
there is also a 1-wire Serial Wire Viewer pin which can be used to output profiling information, data trace
and software-generated messages.
2.1.3 Memory System Controller (MSC)
The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The
flash memory is readable and writable from both the Cortex-M3 and DMA. The flash memory is divided
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into two blocks; the main block and the information block. Program code is normally written to the main
block. Additionally, the information block is available for special user data and flash lock bits. There is
also a read-only page in the information block containing system and device calibration data. Read and
write operations are supported in the energy modes EM0 and EM1.
2.1.4 Direct Memory Access Controller (DMA)
The Direct Memory Access (DMA) controller performs memory operations independently of the CPU.
This has the benefit of reducing the energy consumption and the workload of the CPU, and enables
the system to stay in low energy modes when moving for instance data from the USART to RAM or
from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230 µDMA
controller licensed from ARM.
2.1.5 Reset Management Unit (RMU)
The RMU is responsible for handling the reset functionality of the EFM32G.
2.1.6 Energy Management Unit (EMU)
The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcon-
trollers. Each energy mode manages if the CPU and the various peripherals are available. The EMU
can also be used to turn off the power to unused SRAM blocks.
2.1.7 Clock Management Unit (CMU)
The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board
the EFM32G. The CMU provides the capability to turn on and off the clock on an individual basis to all
peripheral modules in addition to enable/disable and configure the available oscillators. The high degree
of flexibility enables software to minimize energy consumption in any specific application by not wasting
power on peripherals and oscillators that are inactive.
2.1.8 Watchdog (WDOG)
The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase appli-
cation reliability. The failure may e.g. be caused by an external event, such as an ESD pulse, or by a
software failure.
2.1.9 Peripheral Reflex System (PRS)
The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module
communicate directly with each other without involving the CPU. Peripheral modules which send out
Reflex signals are called producers. The PRS routes these reflex signals to consumer peripherals which
apply actions depending on the data received. The format for the Reflex signals is not given, but edge
triggers and other functionality can be applied by the PRS.
2.1.10 Inter-Integrated Circuit Interface (I2C)
The I2C module provides an interface between the MCU and a serial I2C-bus. It is capable of acting as
both a master and a slave, and supports multi-master buses. Both standard-mode, fast-mode and fast-
mode plus speeds are supported, allowing transmission rates all the way from 10 kbit/s up to 1 Mbit/s.
Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant system.
The interface provided to software by the I2C module, allows both fine-grained control of the transmission
process and close to automatic transfers. Automatic recognition of slave addresses is provided in all
energy modes.
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2.1.11 Universal Synchronous/Asynchronous Receiver/Transmitter (US-
ART)
The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible
serial I/O module. It supports full duplex asynchronous UART communication as well as RS-485, SPI,
MicroWire and 3-wire. It can also interface with ISO7816 SmartCards, and IrDA devices.
2.1.12 Pre-Programmed UART Bootloader
The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Auto-
baud and destructive write are supported. The autobaud feature, interface and commands are described
further in the application note.
2.1.13 Low Energy Universal Asynchronous Receiver/Transmitter
(LEUART)
The unique LEUARTTM, the Low Energy UART, is a UART that allows two-way UART communication on
a strict power budget. Only a 32.768 kHz clock is needed to allow UART communication up to 9600 baud/
s. The LEUART includes all necessary hardware support to make asynchronous serial communication
possible with minimum of software intervention and energy consumption.
2.1.14 Timer/Counter (TIMER)
The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-
Width Modulation (PWM) output. TIMER0 also includes a Dead-Time Insertion module suitable for motor
control applications.
2.1.15 Real Time Counter (RTC)
The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal
oscillator, or a 32.768 kHz RC oscillator. In addition to energy modes EM0 and EM1, the RTC is also
available in EM2. This makes it ideal for keeping track of time since the RTC is enabled in EM2 where
most of the device is powered down.
2.1.16 Low Energy Timer (LETIMER)
The unique LETIMERTM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2
in addition to EM1 and EM0. Because of this, it can be used for timing and output generation when most
of the device is powered down, allowing simple tasks to be performed while the power consumption of
the system is kept at an absolute minimum. The LETIMER can be used to output a variety of waveforms
with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be
configured to start counting on compare matches from the RTC.
2.1.17 Pulse Counter (PCNT)
The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature
encoded inputs. It runs off either the internal LFACLK or the PCNTn_S0IN pin as external clock source.
The module may operate in energy mode EM0 - EM3.
2.1.18 Analog Comparator (ACMP)
The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indi-
cating which input voltage is higher. Inputs can either be one of the selectable internal references or from
external pins. Response time and thereby also the current consumption can be configured by altering
the current supply to the comparator.
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2.1.19 Voltage Comparator (VCMP)
The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can
be generated when the supply falls below or rises above a programmable threshold. Response time and
thereby also the current consumption can be configured by altering the current supply to the comparator.
2.1.20 Analog to Digital Converter (ADC)
The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits
at up to one million samples per second. The integrated input mux can select inputs from 4 external
pins and 6 internal signals.
2.1.21 Digital to Analog Converter (DAC)
The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC
is fully differential rail-to-rail, with 12-bit resolution. It has one single ended output buffer connected to
channel 0. The DAC may be used for a number of different applications such as sensor interfaces or
sound output.
2.1.22 Advanced Encryption Standard Accelerator (AES)
The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or
decrypting one 128-bit data block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK
cycles with 256-bit keys. The AES module is an AHB slave which enables efficient access to the data
and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or 16-bit
operations are not supported.
2.1.23 General Purpose Input/Output (GPIO)
In the EFM32G210, there are 24 General Purpose Input/Output (GPIO) pins, which are divided into ports
with up to 16 pins each. These pins can individually be configured as either an output or input. More
advanced configurations like open-drain, filtering and drive strength can also be configured individually
for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM
outputs or USART communication, which can be routed to several locations on the device. The GPIO
supports up to 14 asynchronous external pin interrupts, which enables interrupts from any pin on the
device. Also, the input value of a pin can be routed through the Peripheral Reflex System to other
peripherals.
2.2 Configuration Summary
The features of the EFM32G210 is a subset of the feature set described in the EFM32G Reference
Manual. Table 2.1 (p. 6) describes device specific implementation of the features.
Table 2.1. Configuration Summary
Module
Cortex-M3
DBG
Configuration
Pin Connections
Full configuration
Full configuration
NA
DBG_SWCLK, DBG_SWDIO,
DBG_SWO
MSC
DMA
RMU
Full configuration
Full configuration
Full configuration
NA
NA
NA
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Module
EMU
Configuration
Pin Connections
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration with IrDA
Full configuration
Full configuration
Full configuration with DTI
Full configuration
Full configuration
Full configuration
Full configuration, 8-bit count register
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
Full configuration
24 pins
NA
CMU
CMU_OUT0, CMU_OUT1
WDOG
PRS
NA
NA
I2C0
I2C0_SDA, I2C0_SCL
US0_TX, US0_RX. US0_CLK, US0_CS
US1_TX, US1_RX, US1_CLK, US1_CS
LEU0_TX, LEU0_RX
TIM0_CC[2:0], TIM0_CDTI[2:0]
TIM1_CC[2:0]
USART0
USART1
LEUART0
TIMER0
TIMER1
RTC
NA
LETIMER0
PCNT0
ACMP0
ACMP1
VCMP
ADC0
LET0_O[1:0]
PCNT0_S[1:0]
ACMP0_CH[1:0], ACMP0_O
ACMP1_CH[7:5], ACMP1_O
NA
ADC0_CH[7:4]
DAC0
DAC0_OUT[0]
AES
NA
GPIO
Available pins are shown in
Table 4.3 (p. 51)
2.3 Memory Map
The EFM32G210 memory map is shown in Figure 2.2 (p. 8), with RAM and Flash sizes for the
largest memory configuration.
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Figure 2.2. EFM32G210 Memory Map with largest RAM and Flash sizes
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3 Electrical Characteristics
3.1 Test Conditions
3.1.1 Typical Values
The typical data are based on TAMB=25°C and VDD=3.0 V, as defined in Table 3.2 (p. 9), by simu-
lation and/or technology characterisation unless otherwise specified.
3.1.2 Minimum and Maximum Values
The minimum and maximum values represent the worst conditions of ambient temperature, supply volt-
age and frequencies, as defined in Table 3.2 (p. 9), by simulation and/or technology characterisa-
tion unless otherwise specified.
3.2 Absolute Maximum Ratings
The absolute maximum ratings are stress ratings, and functional operation under such conditions are
not guaranteed. Stress beyond the limits specified in Table 3.1 (p. 9) may affect the device reliability
or cause permanent damage to the device. Functional operating conditions are given in Table 3.2 (p.
9) .
Table 3.1. Absolute Maximum Ratings
Symbol
Parameter
Condition
Min
Typ
Max
Unit
1501 °C
TSTG
Storage tempera-
ture range
-40
TS
Maximum soldering Latest IPC/JEDEC J-STD-020
260 °C
temperature
Standard
VDDMAX
External main sup-
ply voltage
0
3.8
V
V
VIOPIN
Voltage on any I/O
pin
-0.3
VDD+0.3
Current per I/O pin
(sink)
100 mA
-100 mA
IIOMAX
Current per I/O pin
(source)
1Based on programmed devices tested for 10000 hours at 150°C. Storage temperature affects retention of preprogrammed cal-
ibration values stored in flash. Please refer to the Flash section in the Electrical Characteristics for information on flash data re-
tention for different temperatures.
3.3 General Operating Conditions
3.3.1 General Operating Conditions
Table 3.2. General Operating Conditions
Symbol
TAMB
VDDOP
fAPB
Parameter
Min
Typ
Max
Unit
85 °C
3.8
Ambient temperature range
Operating supply voltage
Internal APB clock frequency
Internal AHB clock frequency
-40
1.98
V
32 MHz
32 MHz
fAHB
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3.4 Current Consumption
Table 3.3. Current Consumption
Symbol
Parameter
Condition
Min
Typ
Max
Unit
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
180
181
183
185
186
191
220
45
µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
206 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
207 µA/
MHz
EM0 current. No
prescaling. Running
prime number cal-
culation code from
Flash. (Production
test condition = 14
MHz)
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
211 µA/
MHz
IEM0
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
215 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
218 µA/
MHz
1.2 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
µA/
MHz
32 MHz HFXO, all peripheral
clocks disabled, VDD= 3.0 V
µA/
MHz
28 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
47
62 µA/
MHz
21 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
48
64 µA/
MHz
EM1 current (Pro-
duction test condi-
tion = 14 MHz)
14 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
50
69 µA/
MHz
IEM1
11 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
51
72 µA/
MHz
6.6 MHz HFRCO, all peripheral
clocks disabled, VDD= 3.0 V
56
83 µA/
MHz
1.2 MHz HFRCO. all peripheral
clocks disabled, VDD= 3.0 V
103
0.9
µA/
MHz
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=25°C
1.5 µA
IEM2
EM2 current
EM2 current with RTC
prescaled to 1 Hz, 32.768
kHz LFRCO, VDD= 3.0 V,
TAMB=85°C
3.0
6.0 µA
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
VDD= 3.0 V, TAMB=25°C
VDD= 3.0 V, TAMB=85°C
0.59
2.75
0.02
0.25
1.0 µA
5.8 µA
IEM3
EM3 current
EM4 current
0.045 µA
0.7 µA
IEM4
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3.4.1 EM0 Current Consumption
Figure 3.1. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 28 MHz
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.2. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 21 MHz
4.0
3.9
3.8
3.7
3.6
3.5
4.0
3.9
3.8
3.7
3.6
3.5
85.0°C
65.0°C
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.3. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 14 MHz
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
2.75
2.70
2.65
2.60
2.55
2.50
2.45
2.40
2.35
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.4. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 11 MHz
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
2.20
2.15
2.10
2.05
2.00
1.95
1.90
1.85
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.5. EM0 Current consumption while executing prime number calculation code from flash
with HFRCO running at 7 MHz
1.45
1.40
1.35
1.30
1.25
1.20
1.45
1.40
1.35
1.30
1.25
1.20
Vdd= 2.0V
Vdd= 2.2V
Vdd= 2.4V
Vdd= 2.6V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.2V
Vdd= 3.4V
Vdd= 3.6V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.4.2 EM1 Current Consumption
Figure 3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 28 MHz
1.40
1.35
1.30
1.25
1.20
1.15
1.40
1.35
1.30
1.25
1.20
1.15
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 21 MHz
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
1.08
1.06
1.04
1.02
1.00
0.98
0.96
0.94
0.92
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 14 MHz
0.76
0.74
0.72
0.70
0.68
0.66
0.64
0.76
0.74
0.72
0.70
0.68
0.66
0.64
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
85.0°C
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 11 MHz
0.62
0.60
0.58
0.56
0.54
0.52
0.62
0.60
0.58
0.56
0.54
0.52
85.0°C
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running
at 7 MHz
0.44
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.36
0.44
0.43
0.42
0.41
0.40
0.39
0.38
0.37
0.36
85.0°C
Vdd= 2.0V
Vdd= 2.4V
Vdd= 2.8V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
65.0°C
45.0°C
25.0°C
5.0°C
- 15.0°C
- 40.0°C
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.4.3 EM2 Current Consumption
Figure 3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
3.5
3.0
2.5
2.0
1.5
1.0
0.5
- 40.0°C
- 15.0°C
5.0°C
Vdd= 1.8V
Vdd= 2.2V
Vdd= 2.6V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
25.0°C
45.0°C
65.0°C
85.0°C
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.4.4 EM3 Current Consumption
Figure 3.12. EM3 current consumption.
3.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
- 40.0°C
Vdd= 1.8V
Vdd= 2.2V
Vdd= 2.6V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
- 15.0°C
5.0°C
25.0°C
45.0°C
65.0°C
85.0°C
2.5
2.0
1.5
1.0
0.5
0.0
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.4.5 EM4 Current Consumption
Figure 3.13. EM4 current consumption.
0.45
0.45
- 40.0°C
Vdd= 1.8V
- 15.0°C
Vdd= 2.2V
5.0°C
Vdd= 2.6V
Vdd= 3.0V
Vdd= 3.4V
Vdd= 3.8V
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
25.0°C
45.0°C
65.0°C
85.0°C
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.5 Transition between Energy Modes
The transition times are measured from the trigger to the first clock edge in the CPU.
Table 3.4. Energy Modes Transitions
Symbol
Parameter
Min
Typ
Max
Unit
tEM10
Transition time from EM1 to EM0
0
HF-
CORE-
CLK
cycles
tEM20
tEM30
tEM40
Transition time from EM2 to EM0
Transition time from EM3 to EM0
Transition time from EM4 to EM0
2
2
µs
µs
µs
163
3.6 Power Management
The EFM32G requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with
optional filter) at the PCB level. For practical schematic recommendations, please see the application
note, "AN0002 EFM32 Hardware Design Considerations".
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Table 3.5. Power Management
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VBODextthr-
BOD threshold on
falling external sup-
ply voltage
1.74
1.96
1.98
V
VBODextthr+
BOD threshold on
rising external sup-
ply voltage
1.85
V
V
VPORthr+
Power-on Reset
(POR) threshold on
rising external sup-
ply voltage
tRESETdly
Delay from reset
is released until
program execution
starts
Applies to Power-on Reset,
Brown-out Reset and pin reset.
163
µs
ns
µF
tRESET
negative pulse
length to ensure
complete reset of
device
50
CDECOUPLE
Voltage regulator
decoupling capaci-
tor.
X5R capacitor recommended.
Apply between DECOUPLE pin
and GROUND
1
3.7 Flash
Table 3.6. Flash
Symbol
Parameter
Condition
Min
Typ
Max
Unit
ECFLASH
Flash erase cycles
before failure
20000
cycles
TAMB<150°C
10000
10
h
RETFLASH
Flash data retention TAMB<85°C
TAMB<70°C
years
years
µs
20
tW_PROG
Word (32-bit) pro-
gramming time
20
tP_ERASE
tD_ERASE
IERASE
Page erase time
Device erase time
Erase current
20
40
20.4
40.8
20.8 ms
41.6 ms
71 mA
IWRITE
Write current
71 mA
VFLASH
Supply voltage dur-
ing flash erase and
write
1.98
3.8
V
1Measured at 25°C
3.8 General Purpose Input Output
Table 3.7. GPIO
Symbol
Parameter
Condition
Min
Typ
Max
0.30VDD
Unit
1
VIOIL
Input low voltage
V
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Symbol
Parameter
Condition
Min
0.70VDD
Typ
Max
Unit
V
1
VIOIH
Input high voltage
Sourcing 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.80VDD
0.90VDD
0.85VDD
0.90VDD
V
Sourcing 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Sourcing 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Sourcing 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output high volt-
age (Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
VIOOH
Sourcing 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.75VDD
0.85VDD
0.60VDD
0.80VDD
Sourcing 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
Sourcing 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sourcing 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sinking 0.1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
0.20VDD
0.10VDD
0.10VDD
0.05VDD
Sinking 0.1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOWEST
Sinking 1 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Sinking 1 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= LOW
Output low voltage
(Production test
condition = 3.0V,
DRIVEMODE =
STANDARD)
VIOOL
Sinking 6 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.30VDD
Sinking 6 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= STANDARD
0.20VDD
0.35VDD
0.25VDD
Sinking 20 mA, VDD=1.98 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
Sinking 20 mA, VDD=3.0 V,
GPIO_Px_CTRL DRIVEMODE
= HIGH
IIOLEAK
Input leakage cur-
rent
High Impedance IO connected
to GROUND or VDD
±0.1
±40 nA
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
RPU
I/O pin pull-up resis-
tor
40
40
kOhm
RPD
I/O pin pull-down re-
sistor
kOhm
Ohm
RIOESD
Internal ESD series
resistor
200
tIOGLITCH
Pulse width of puls-
es to be removed
by the glitch sup-
pression filter
10
50 ns
GPIO_Px_CTRL DRIVEMODE
= LOWEST and load capaci-
tance CL=12.5-25pF.
20+0.1CL
20+0.1CL
0.1VDD
250 ns
250 ns
V
tIOOF
Output fall time
GPIO_Px_CTRL DRIVEMODE
= LOW and load capacitance
CL=350-600pF
VIOHYST
I/O pin hysteresis
VDD = 1.98 - 3.8 V
(VIOTHR+ - VIOTHR-
)
1If the GPIO input voltage is between 0.3VDD and 0.7VDD, the current consumption will increase.
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Figure 3.14. Typical Low-Level Output Current, 2V Supply Voltage
0.20
0.15
0.10
0.05
0.00
5
4
3
2
1
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
20
45
40
35
30
25
20
15
10
5
15
10
5
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.15. Typical High-Level Output Current, 2V Supply Voltage
0.00
–0.05
–0.10
–0.15
–0.20
0.0
–0.5
–1.0
–1.5
–2.0
–2.5
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–5
–10
–15
–20
0.0
0.5
1.0
1.5
2.0
0.0
0.5
1.0
1.5
2.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.16. Typical Low-Level Output Current, 3V Supply Voltage
0.5
0.4
0.3
0.2
0.1
0.0
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
40
35
30
25
20
15
10
50
40
30
20
10
0
5
- 40°C
- 40°C
25°C
85°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.17. Typical High-Level Output Current, 3V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.18. Typical Low-Level Output Current, 3.8V Supply Voltage
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
14
12
10
8
6
4
2
- 40°C
25°C
85°C
- 40°C
25°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
50
40
30
20
10
50
40
30
20
10
0
- 40°C
25°C
- 40°C
25°C
85°C
85°C
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
Low- Level Output Voltage [V]
Low- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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Figure 3.19. Typical High-Level Output Current, 3.8V Supply Voltage
0.0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
0
- 40°C
25°C
85°C
- 40°C
25°C
85°C
–1
–2
–3
–4
–5
–6
–7
–8
–9
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = LOWEST
GPIO_Px_CTRL DRIVEMODE = LOW
0
0
- 40°C
- 40°C
25°C
85°C
25°C
85°C
–10
–20
–30
–40
–50
–10
–20
–30
–40
–50
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
High- Level Output Voltage [V]
High- Level Output Voltage [V]
GPIO_Px_CTRL DRIVEMODE = STANDARD
GPIO_Px_CTRL DRIVEMODE = HIGH
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3.9 Oscillators
3.9.1 LFXO
Table 3.8. LFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFXO
Supported nominal
crystal frequency
32.768
30
kHz
ESRLFXO
Supported crystal
equivalent series re-
sistance (ESR)
120 kOhm
CLFXOL
Supported crystal
external load range
X1
25 pF
nA
ILFXO
Current consump-
tion for core and
buffer after startup.
ESR=30 kOhm, CL=10 pF,
LFXOBOOST in CMU_CTRL is
1
190
400
tLFXO
Start- up time.
ESR=30 kOhm, CL=10 pF,
40% - 60% duty cycle has
been reached, LFXOBOOST in
CMU_CTRL is 1
ms
1See Minimum Load Capacitance (CLFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio
For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help
users configure both load capacitance and software settings for using the LFXO. For details regarding
the crystal configuration, the reader is referred to application note "AN0016 EFM32 Oscillator Design
Consideration".
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3.9.2 HFXO
Table 3.9. HFXO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fHFXO
Supported nominal
crystal Frequency
4
32 MHz
Supported crystal
equivalent series re-
sistance (ESR)
Crystal frequency 32 MHz
Crystal frequency 4 MHz
30
60 Ohm
ESRHFXO
400
1500 Ohm
gmHFXO
The transconduc-
tance of the HFXO
input transistor at
crystal startup
HFXOBOOST in CMU_CTRL
equals 0b11
20
5
mS
CHFXOL
Supported crystal
external load range
25 pF
µA
4 MHz: ESR=400 Ohm,
CL=20 pF, HFXOBOOST in
CMU_CTRL equals 0b11
85
165
400
Current consump-
tion for HFXO after
startup
IHFXO
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
µA
µs
Startup time
32 MHz: ESR=30 Ohm,
CL=10 pF, HFXOBOOST in
CMU_CTRL equals 0b11
tHFXO
Pulse width re-
moved by glitch de-
tector
1
4
ns
3.9.3 LFRCO
Table 3.10. LFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fLFRCO
Oscillation frequen-
cy , VDD= 3.0 V,
TAMB=25°C
31.29
32.768
150
34.24 kHz
tLFRCO
Startup time not in-
cluding software
calibration
µs
ILFRCO
Current consump-
tion
190
±0.02
±15
nA
TCLFRCO
Temperature coeffi-
cient
%/°C
%/V
%
VCLFRCO
Supply voltage co-
efficient
TUNESTEPL- Frequency step
1.5
for LSB change in
FRCO
TUNING value
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Figure 3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage
42
40
38
36
34
32
30
42
40
38
36
34
32
30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
3.9.4 HFRCO
Table 3.11. HFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
28 MHz frequency band
21 MHz frequency band
14 MHz frequency band
11 MHz frequency band
7 MHz frequency band
1 MHz frequency band
fHFRCO = 14 MHz
27.16
20.37
13.58
10.67
6.402
1.164
28
21
28.84 MHz
21.63 MHz
14.42 MHz
11.33 MHz
6.798 MHz
1.236 MHz
Oscillation frequen-
cy, VDD= 3.0 V,
TAMB=25°C
14
fHFRCO
11
6.61
1.22
0.6
Settling time after
start-up
Cycles
tHFRCO_settling
Settling time after
band switch
25
Cycles
fHFRCO = 28 MHz
fHFRCO = 21 MHz
fHFRCO = 14 MHz
fHFRCO = 11 MHz
fHFRCO = 6.6 MHz
fHFRCO = 1.2 MHz
fHFRCO = 14 MHz
106
93
190 µA
155 µA
120 µA
110 µA
90 µA
Current consump-
tion (Production test
condition = 14 MHz)
77
IHFRCO
72
63
22
32 µA
DCHFRCO
Duty cycle
48.5
50
51
%
%
TUNESTEPH- Frequency step
0.33
for LSB change in
FRCO
TUNING value
1For devices with prod. rev. < 19, Typ = 7MHz and Min/Max values not applicable.
2For devices with prod. rev. < 19, Typ = 1MHz and Min/Max values not applicable.
3The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment
range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature. By
using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the
frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating conditions.
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Figure 3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
1.45
1.40
1.35
1.30
1.25
1.20
1.15
1.10
1.05
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
6.70
6.65
6.60
6.55
6.50
6.45
6.40
6.35
6.30
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature
11.2
11.1
11.0
10.9
10.8
10.7
10.6
11.2
11.1
11.0
10.9
10.8
10.7
10.6
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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Figure 3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
14.2
14.1
14.0
13.9
13.8
13.7
13.6
13.5
13.4
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature
21.2
21.0
20.8
20.6
20.4
20.2
21.2
21.0
20.8
20.6
20.4
20.2
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
Figure 3.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
28.4
28.2
28.0
27.8
27.6
27.4
27.2
27.0
26.8
- 40°C
25°C
85°C
2.0 V
3.0 V
3.8 V
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd [V]
Temperature [°C]
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3.9.5 AUXHFRCO
Table 3.12. AUXHFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fAUXHFRCO
Oscillation frequen- 14 MHz frequency band
cy, VDD= 3.0 V,
TAMB=25°C
13.580
48.5
14.0
0.6
14.420 MHz
tAUXHFRCO_settlingSettling time after
start-up
fAUXHFRCO = 14 MHz
fAUXHFRCO = 14 MHz
Cycles
DCAUXHFRCO
Duty cycle
50
51 %
TUNESTEPAUX-Frequency step
0.31
%
for LSB change in
HFRCO
TUNING value
1The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. By using a stable
frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band
to maintain the AUXHFRCO frequency at any arbitrary value in the 14 MHz range across operating conditions.
3.9.6 ULFRCO
Table 3.13. ULFRCO
Symbol
Parameter
Condition
Min
Typ
Max
Unit
fULFRCO
Oscillation frequen- 25°C, 3V
cy
0.70
1.75 kHz
TCULFRCO
Temperature coeffi-
cient
0.05
%/°C
%/V
VCULFRCO
Supply voltage co-
efficient
-18.2
3.10 Analog Digital Converter (ADC)
Table 3.14. ADC
Symbol
VADCIN
Parameter
Condition
Single ended
Differential
Min
Typ
Max
Unit
0
-VREF/2
1.25
VREF
VREF/2
VDD
V
V
V
Input voltage range
VADCREFIN
Input range of exter-
nal reference volt-
age, single ended
and differential
VADCREFIN_CH7 Input range of ex-
ternal negative ref-
erence voltage on
See VADCREFIN
0
0.625
0
VDD - 1.1
V
V
channel 7
VADCREFIN_CH6 Input range of ex-
ternal positive ref-
See VADCREFIN
VDD
erence voltage on
channel 6
VADCCMIN
Common mode in-
put range
VDD
V
IADCIN
Input current
2pF sampling capacitors
<100
nA
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
CMRRADC
Analog input com-
mon mode rejection
ratio
65
dB
1 MSamples/s, 12 bit, external
reference
351
411
67
µA
µA
µA
1 MSamples/s, 12 bit, internal
reference
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b00, ADC_CLK running at
13MHz
Average active cur-
rent
IADC
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b01, ADC_CLK running at
13MHz
63
64
2
µA
µA
10 kSamples/s 12 bit, internal
1.25 V reference, WARMUP-
MODE in ADCn_CTRL set to
0b10, ADC_CLK running at
13MHz
CADCIN
RADCIN
RADCFILT
Input capacitance
pF
Input ON resistance
1
MOhm
kOhm
Input RC filter resis-
tance
10
CADCFILT
Input RC filter/de-
coupling capaci-
tance
250
fF
fADCCLK
ADC Clock Fre-
quency
13 MHz
6 bit
7
11
13
1
ADC-
CLK
Cycles
8 bit
ADC-
CLK
Cycles
tADCCONV
Conversion time
Acquisition time
12 bit
ADC-
CLK
Cycles
tADCACQ
Programmable
256 ADC-
CLK
Cycles
tADCACQVDD3
Required acquisi-
tion time for VDD/3
reference
2
µs
Startup time of ref-
erence generator
and ADC core in
NORMAL mode
5
1
µs
tADCSTART
Startup time of ref-
erence generator
and ADC core in
µs
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
KEEPADCWARM
mode
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
59
dB
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
63
65
60
65
54
67
69
62
dB
dB
dB
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
Signal to Noise Ra-
tio (SNR)
SNRADC
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
63
67
63
66
66
69
70
58
dB
dB
dB
dB
dB
dB
dB
dB
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
63
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
62
64
60
64
54
dB
dB
dB
dB
dB
1 MSamples/s, 12 bit, single
ended, VDD reference
SIgnal-to-Noise
And Distortion-ratio
(SINAD)
SINADADC
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, 5V reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
1 MSamples/s, 12 bit, differen-
tial, VDD reference
66
68
61
dB
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
dB
dB
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
65
66
63
66
66
68
69
64
dB
dB
dB
dB
dB
dB
dB
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
200 kSamples/s, 12 bit, differ-
ential, 5V reference
200 kSamples/s, 12 bit, differ-
ential, VDD reference
62
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
1 MSamples/s, 12 bit, single
ended, internal 1.25V refer-
ence
1 MSamples/s, 12 bit, single
ended, internal 2.5V reference
76
73
66
77
76
75
69
75
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
1 MSamples/s, 12 bit, single
ended, VDD reference
1 MSamples/s, 12 bit, differen-
tial, internal 1.25V reference
1 MSamples/s, 12 bit, differen-
tial, internal 2.5V reference
1 MSamples/s, 12 bit, differen-
tial, VDD reference
Spurious-Free Dy-
namic Range (SF-
DR)
1 MSamples/s, 12 bit, differen-
tial, 2xVDD reference
SFDRADC
1 MSamples/s, 12 bit, differen-
tial, 5V reference
200 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
200 kSamples/s, 12 bit, single
ended, internal 2.5V reference
75
76
79
79
dBc
dBc
dBc
dBc
200 kSamples/s, 12 bit, single
ended, VDD reference
200 kSamples/s, 12 bit, differ-
ential, internal 1.25V reference
200 kSamples/s, 12 bit, differ-
ential, internal 2.5V reference
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
200 kSamples/s, 12 bit, differ-
ential, 5V reference
78
79
79
dBc
200 kSamples/s, 12 bit, differ-
ential, VDD reference
68
-4
dBc
dBc
200 kSamples/s, 12 bit, differ-
ential, 2xVDD reference
After calibration, single ended
After calibration, differential
0.3
0.3
4
mV
VADCOFFSET
Offset voltage
mV
-1.92
-6.3
mV/°C
Thermometer out-
put gradient
ADC
Codes/
°C
TGRADADCTH
DNLADC
INLADC
Differential non-lin-
earity (DNL)
VDD = 3.0 V, external 2.5V ref-
erence
-1
±0.7
±1.2
4
LSB
Integral non-linear-
ity (INL), End point
method
VDD = 3.0 V, external 2.5V ref-
erence
±3 LSB
MCADC
No missing codes
11.9991
12
bits
1On the average every ADC will have one missing code, most likely to appear around 2048 ± n*512 where n can be a value in
the set {-3, -2, -1, 1, 2, 3}. There will be no missing code around 2048, and in spite of the missing code the ADC will be monotonic
at all times so that a response to a slowly increasing input will always be a slowly increasing output. Around the one code that is
missing, the neighbour codes will look wider in the DNL plot. The spectra will show spurs on the level of -78dBc for a full scale
input for chips that have the missing code issue.
The integral non-linearity (INL) and differential non-linearity parameters are explained in Figure 3.27 (p.
36) and Figure 3.28 (p. 37) , respectively.
Figure 3.27. Integral Non-Linearity (INL)
Digital ouput code
INL= |[(VD- VSS)/ VLSBIDEAL] - D| where 0 < D < 2N - 1
4095
4094
Actual ADC
tranfer function
before offset and
4093
Actual ADC
gain correction
4092
tranfer function
after offset and
gain correction
INL Error
(End Point INL)
Ideal transfer
curve
3
2
1
0
VOFFSET
Analog Input
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Figure 3.28. Differential Non-Linearity (DNL)
Digital
ouput
DNL= |[(VD+ 1 - VD)/ VLSBIDEAL] - 1| where 0 < D < 2N - 2
code
4095
4094
4093
4092
Full Scale Range
Example: Adjacent
input value VD+ 1
corrresponds to digital
output code D+ 1
Actual transfer
function with one
missing code.
Example: Input value
VD corrresponds to
digital output code D
Code width = 2 LSB
DNL= 1 LSB
Ideal transfer
curve
0.5
LSB
Ideal spacing
between two
adjacent codes
VLSBIDEAL= 1 LSB
5
4
3
2
1
0
Ideal 50%
Transition Point
Ideal Code Center
Analog Input
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3.10.1 Typical performance
Figure 3.29. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C
1.25V Reference
2XVDDVSS Reference
VDD Reference
2.5V Reference
5VDIFF Reference
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Figure 3.30. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.31. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C
1.25V Reference
2.5V Reference
2XVDDVSS Reference
5VDIFF Reference
VDD Reference
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Figure 3.32. ADC Absolute Offset, Common Mode = Vdd /2
5
4
3
2
1
0
2.0
1.5
Vref= 1V25
VRef= 1V25
Vref= 2V5
VRef= 2V5
Vref= 2XVDDVSS
Vref= 5VDIFF
Vref= VDD
VRef= 2XVDDVSS
VRef= 5VDIFF
VRef= VDD
1.0
0.5
–1
0.0
–2
–3
–4
–0.5
–1.0
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
–40
–15
5
25
45
65
85
Vdd (V)
Temp (C)
Offset vs Supply Voltage, Temp = 25°C
Offset vs Temperature, Vdd = 3V
Figure 3.33. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V
71
70
69
68
67
66
65
64
63
79.4
79.2
79.0
78.8
78.6
78.4
78.2
78.0
2XVDDV
Vdd
1V25
Vdd
2V5
5VDIFF
2V5
2XVDDV
5VDIFF
1V25
–40
–15
5
25
45
65
85
–40
–15
5
25
45
65
85
Temperature [°C]
Temperature [°C]
Signal to Noise Ratio (SNR)
Spurious-Free Dynamic Range (SFDR)
3.11 Digital Analog Converter (DAC)
Table 3.15. DAC
Symbol
Parameter
Condition
Min
Typ
Max
Unit
VDACOUT
Output voltage
range
VDD voltage reference, single
ended
0
0
VDD
V
VDACCM
Output common
VDD
V
mode voltage range
500 kSamples/s, 12bit
100 kSamples/s, 12 bit
1 kSamples/s 12 bit
4001
2001
171
650 µA
250 µA
25 µA
Active current in-
cluding references
for 2 channels
IDAC
SRDAC
Sample rate
500 ksam-
ples/s
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
1000 kHz
250 kHz
250 kHz
Continuous Mode
Sample/Hold Mode
Sample/Off Mode
DAC clock frequen-
cy
fDAC
CYCDACCONV Clock cyckles per
conversion
2
tDACCONV
Conversion time
Settling time
2
µs
µs
dB
tDACSETTLE
5
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
58
Signal to Noise Ra-
tio (SNR)
SNRDAC
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
59
57
dB
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
Signal to Noise-
pulse Distortion Ra-
tio (SNDR)
SNDRDAC
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
54
62
dB
500 kSamples/s, 12 bit, sin-
gle ended, internal 1.25V refer-
ence
dBc
Spurious-Free
Dynamic
SFDRDAC
Range(SFDR)
500 kSamples/s, 12 bit, single
ended, internal 2.5V reference
56
dBc
mV
VDACOFFSET
Offset voltage
After calibration, single ended
2
VDACSHMDRIFT Sample-hold mode
voltage drift
540
µV/ms
DNLDAC
INLDAC
MCDAC
Differential non-lin-
earity
±1
±5
12
LSB
LSB
bits
Integral non-lineari-
ty
No missing codes
1Measured with a static input code and no loading on the output.
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3.12 Analog Comparator (ACMP)
Table 3.16. ACMP
Symbol
VACMPIN
VACMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
0
0
VDD
VDD
ACMP Common
V
Mode voltage range
BIASPROG=0b0000, FULL-
BIAS=0 and HALFBIAS=1 in
ACMPn_CTRL register
55
2.82
195
0
600 nA
12 µA
BIASPROG=0b1111, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
IACMP
Active current
BIASPROG=0b1111, FULL-
BIAS=1 and HALFBIAS=0 in
ACMPn_CTRL register
520 µA
0.5 µA
Internal voltage reference off.
Using external voltage refer-
ence
Current consump-
tion of internal volt-
age reference
IACMPREF
Internal voltage reference,
LPREF=1
0.050
3
µA
µA
Internal voltage reference,
LPREF=0
6
0
VACMPOFFSET Offset voltage
BIASPROG= 0b1010, FULL-
BIAS=0 and HALFBIAS=0 in
ACMPn_CTRL register
-12
12 mV
VACMPHYST
ACMP hysteresis
Programmable
17
39
mV
CSRESSEL=0b00 in
ACMPn_INPUTSEL
kOhm
CSRESSEL=0b01 in
ACMPn_INPUTSEL
71
104
136
kOhm
kOhm
kOhm
Capacitive Sense
Internal Resistance
RCSRES
CSRESSEL=0b10 in
ACMPn_INPUTSEL
CSRESSEL=0b11 in
ACMPn_INPUTSEL
tACMPSTART
Startup time
10 µs
The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference
as given in Equation 3.1 (p. 43) . IACMPREF is zero if an external voltage reference is used.
Total ACMP Active Current
IACMPTOTAL = IACMP + IACMPREF
(3.1)
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Figure 3.34. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1
2.5
2.0
1.5
1.0
0.5
0.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
HYSTSEL= 0.0
HYSTSEL= 2.0
HYSTSEL= 4.0
HYSTSEL= 6.0
0
4
8
12
0
2
4
6
8
10
12
14
ACMP_CTRL_BIASPROG
ACMP_CTRL_BIASPROG
Current consumption, HYSTSEL = 4
Response time
100
80
60
40
20
0
BIASPROG= 0.0
BIASPROG= 4.0
BIASPROG= 8.0
BIASPROG= 12.0
0
1
2
3
4
5
6
7
ACMP_CTRL_HYSTSEL
Hysteresis
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3.13 Voltage Comparator (VCMP)
Table 3.17. VCMP
Symbol
VVCMPIN
VVCMPCM
Parameter
Condition
Min
Typ
Max
Unit
V
Input voltage range
VDD
VDD
VCMP Common
V
Mode voltage range
BIASPROG=0b0000 and
HALFBIAS=1 in VCMPn_CTRL
register
0.3
22
10
1
µA
IVCMP
Active current
BIASPROG=0b1111 and
HALFBIAS=0 in VCMPn_CTRL
register. LPREF=0.
30 µA
µs
tVCMPREF
Startup time refer-
ence generator
NORMAL
Single ended
Differential
10
10
17
mV
mV
VVCMPOFFSET Offset voltage
VVCMPHYST
tVCMPSTART
VCMP hysteresis
Startup time
mV
10 µs
The VDD trigger level can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in
accordance with the following equation:
VCMP Trigger Level as a Function of Level Setting
VDD Trigger Level=1.667V+0.034 ×TRIGLEVEL
(3.2)
3.14 I2C
Table 3.18. I2C Standard-mode (Sm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
4.7
4.0
250
8
1001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
34502,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
4.7
4.0
4.0
4.7
µs
µs
µs
µs
1For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32G Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10-9 [s] * fHFPERCLK [Hz]) - 4).
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Table 3.19. I2C Fast-mode (Fm)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
1.3
0.6
100
8
4001 kHz
tLOW
SCL clock low time
µs
tHIGH
SCL clock high time
µs
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
ns
SDA hold time
9002,3 ns
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
0.6
0.6
0.6
1.3
µs
µs
µs
µs
1For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32G Reference Manual.
2The maximum SDA hold time (tHD,DAT) needs to be met only when the device does not stretch the low time of SCL (tLOW).
3When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10-9 [s] * fHFPERCLK [Hz]) - 4).
Table 3.20. I2C Fast-mode Plus (Fm+)
Symbol
fSCL
Parameter
Min
Typ
Max
Unit
SCL clock frequency
0
0.5
10001 kHz
tLOW
SCL clock low time
µs
µs
ns
ns
µs
µs
µs
µs
tHIGH
SCL clock high time
0.26
50
tSU,DAT
tHD,DAT
tSU,STA
tHD,STA
tSU,STO
tBUF
SDA set-up time
SDA hold time
8
Repeated START condition set-up time
(Repeated) START condition hold time
STOP condition set-up time
Bus free time between a STOP and START condition
0.26
0.26
0.26
0.5
1For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32G Reference Manual.
3.15 Digital Peripherals
Table 3.21. Digital Peripherals
Symbol
Parameter
Condition
Min
Typ
Max
Unit
IUSART
USART current
USART idle current, clock en-
abled
7.5
5.63
150
µA/
MHz
IUART
UART current
LEUART current
I2C current
UART idle current, clock en-
abled
µA/
MHz
ILEUART
LEUART idle current, clock en-
abled
nA
II2C
I2C idle current, clock enabled
6.25
8.75
150
µA/
MHz
ITIMER
TIMER current
LETIMER current
TIMER_0 idle current, clock
enabled
µA/
MHz
ILETIMER
LETIMER idle current, clock
enabled
nA
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Symbol
Parameter
Condition
Min
Typ
Max
Unit
IPCNT
PCNT current
PCNT idle current, clock en-
abled
100
nA
IRTC
IAES
RTC current
AES current
RTC idle current, clock enabled
AES idle current, clock enabled
100
2.5
nA
µA/
MHz
IGPIO
IPRS
IDMA
GPIO current
PRS current
DMA current
GPIO idle current, clock en-
abled
5.31
2,81
8.12
µA/
MHz
PRS idle current
µA/
MHz
Clock enable
µA/
MHz
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4 Pinout and Package
Note
Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for
guidelines on designing Printed Circuit Boards (PCB's) for the EFM32G210.
4.1 Pinout
The EFM32G210 pinout is shown in Figure 4.1 (p. 48) and Table 4.1 (p. 48). Alternate locations
are denoted by "#" followed by the location number (Multiple locations on the same pin are split with "/").
Alternate locations can be configured in the LOCATION bitfield in the *_ROUTE register in the module
in question.
Figure 4.1. EFM32G210 Pinout (top view, not to scale)
Table 4.1. Device Pinout
QFN32 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
0
1
2
VSS
PA0
PA1
Ground.
TIM0_CC0 #0/1
TIM0_CC1 #0/1
I2C0_SDA #0
I2C0_SCL #0
CMU_CLK1 #0
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QFN32 Pin#
and Name
Pin Alternate Functionality / Description
Pin Name
Analog
Timers
Communication
Other
3
4
5
6
7
8
PA2
IOVDD_1
PC0
TIM0_CC2 #0/1
CMU_CLK0 #0
Digital IO power supply 1.
ACMP0_CH0
PCNT0_S0IN #2
PCNT0_S1IN #2
US1_TX #0
US1_RX #0
US1_CLK #0
US1_CS #0
PC1
ACMP0_CH1
PB7
LFXTAL_P
PB8
LFXTAL_N
Reset input, active low.
9
RESETn
To apply an external reset source to this pin, it is required to only drive this pin low during reset, and let the internal pull-up
ensure that reset is released.
10
11
12
13
14
15
16
17
18
19
20
21
PB11
AVDD_2
PB13
DAC0_OUT0
Analog power supply 2.
HFXTAL_P
LETIM0_OUT0 #1
LEU0_TX #1
LEU0_RX #1
PB14
HFXTAL_N
IOVDD_3
AVDD_0
PD4
Digital IO power supply 3.
Analog power supply 0.
ADC0_CH4
LEU0_TX #0
LEU0_RX #0
I2C0_SDA #1
I2C0_SCL #1
PD5
ADC0_CH5
PD6
ADC0_CH6
LETIM0_OUT0 #0
LETIM0_OUT1 #0
PD7
ADC0_CH7
VDD_DREG
DECOUPLE
Power supply for on-chip voltage regulator.
Decouple output for on-chip voltage regulator. An external capacitance of size CDECOUPLE is required at this pin.
TIM0_CDTI0 #1/3
22
PC13
ACMP1_CH5
TIM1_CC0 #0
PCNT0_S0IN #0
TIM0_CDTI1 #1/3
TIM1_CC1 #0
PCNT0_S1IN #0
23
24
PC14
PC15
ACMP1_CH6
ACMP1_CH7
TIM0_CDTI2 #1/3
TIM1_CC2 #0
DBG_SWO #1
25
26
PF0
PF1
LETIM0_OUT0 #2
LETIM0_OUT1 #2
DBG_SWCLK #0/1
DBG_SWDIO #0/1
ACMP1_O #0
DBG_SWO #0
27
PF2
28
29
30
31
32
IOVDD_5
PE10
Digital IO power supply 5.
TIM1_CC0 #1
TIM1_CC1 #1
TIM1_CC2 #1
US0_TX #0
US0_RX #0
US0_CLK #0
US0_CS #0
BOOT_TX
BOOT_RX
PE11
PE12
PE13
ACMP0_O #0
4.2 Alternate Functionality Pinout
A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in
Table 4.2 (p. 50). The table shows the name of the alternate functionality in the first column, followed
by columns showing the possible LOCATION bitfield settings.
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Note
Some functionality, such as analog interfaces, do not have alternate settings or a LOCA-
TION bitfield. In these cases, the pinout is shown in the column corresponding to LOCA-
TION 0.
Table 4.2. Alternate functionality overview
Alternate
LOCATION
Functionality
ACMP0_CH0
ACMP0_CH1
ACMP0_O
0
1
2
3
Description
PC0
Analog comparator ACMP0, channel 0.
PC1
Analog comparator ACMP0, channel 1.
PE13
PC13
PC14
PC15
PF2
Analog comparator ACMP0, digital output.
Analog comparator ACMP1, channel 5.
ACMP1_CH5
ACMP1_CH6
ACMP1_CH7
ACMP1_O
Analog comparator ACMP1, channel 6.
Analog comparator ACMP1, channel 7.
Analog comparator ACMP1, digital output.
Analog to digital converter ADC0, input channel number 4.
Analog to digital converter ADC0, input channel number 5.
Analog to digital converter ADC0, input channel number 6.
Analog to digital converter ADC0, input channel number 7.
Bootloader RX.
ADC0_CH4
ADC0_CH5
ADC0_CH6
ADC0_CH7
BOOT_RX
PD4
PD5
PD6
PD7
PE11
PE10
PA2
BOOT_TX
Bootloader TX.
CMU_CLK0
CMU_CLK1
DAC0_OUT0
Clock Management Unit, clock output number 0.
Clock Management Unit, clock output number 1.
Digital to Analog Converter DAC0 output channel number 0.
Debug-interface Serial Wire clock input.
PA1
PB11
DBG_SWCLK
DBG_SWDIO
PF0
PF1
PF0
PF1
Note that this function is enabled to pin out of reset, and has a built-in pull
down.
Debug-interface Serial Wire data input / output.
Note that this function is enabled to pin out of reset, and has a built-in pull up.
Debug-interface Serial Wire viewer Output.
DBG_SWO
HFXTAL_N
PF2
PC15
Note that this function is not enabled after reset, and must be enabled by
software to be used.
High Frequency Crystal negative pin. Also used as external optional clock in-
put pin.
PB14
HFXTAL_P
I2C0_SCL
PB13
PA1
PA0
PD6
PD7
PD5
High Frequency Crystal positive pin.
I2C0 Serial Clock Line input / output.
I2C0 Serial Data input / output.
PD7
PD6
PB11
I2C0_SDA
LETIM0_OUT0
LETIM0_OUT1
LEU0_RX
PF0
PF1
Low Energy Timer LETIM0, output channel 0.
Low Energy Timer LETIM0, output channel 1.
LEUART0 Receive input.
PB14
PB13
LEUART0 Transmit output. Also used as receive input in half duplex commu-
nication.
LEU0_TX
PD4
PB8
Low Frequency Crystal (typically 32.768 kHz) negative pin. Also used as an
optional external clock input pin.
LFXTAL_N
LFXTAL_P
PB7
Low Frequency Crystal (typically 32.768 kHz) positive pin.
Pulse Counter PCNT0 input number 0.
PCNT0_S0IN
PCNT0_S1IN
PC13
PC14
PC0
PC1
Pulse Counter PCNT0 input number 1.
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Alternate
LOCATION
Functionality
TIM0_CC0
TIM0_CC1
TIM0_CC2
TIM0_CDTI0
TIM0_CDTI1
TIM0_CDTI2
TIM1_CC0
TIM1_CC1
TIM1_CC2
US0_CLK
0
1
2
3
Description
Timer 0 Capture Compare input / output channel 0.
Timer 0 Capture Compare input / output channel 1.
Timer 0 Capture Compare input / output channel 2.
Timer 0 Complimentary Deat Time Insertion channel 0.
Timer 0 Complimentary Deat Time Insertion channel 1.
Timer 0 Complimentary Deat Time Insertion channel 2.
Timer 1 Capture Compare input / output channel 0.
Timer 1 Capture Compare input / output channel 1.
Timer 1 Capture Compare input / output channel 2.
USART0 clock input / output.
PA0
PA1
PA2
PA0
PA1
PA2
PC13
PC14
PC15
PE10
PE11
PE12
PC13
PC14
PC15
PC13
PC14
PC15
PE12
PE13
US0_CS
USART0 chip select input / output.
USART0 Asynchronous Receive.
US0_RX
US0_TX
PE11
PE10
USART0 Synchronous mode Master Input / Slave Output (MISO).
USART0 Asynchronous Transmit.Also used as receive input in half duplex
communication.
USART0 Synchronous mode Master Output / Slave Input (MOSI).
USART1 clock input / output.
US1_CLK
US1_CS
PB7
PB8
USART1 chip select input / output.
USART1 Asynchronous Receive.
US1_RX
US1_TX
PC1
PC0
USART1 Synchronous mode Master Input / Slave Output (MISO).
USART1 Asynchronous Transmit.Also used as receive input in half duplex
communication.
USART1 Synchronous mode Master Output / Slave Input (MOSI).
4.3 GPIO Pinout Overview
The specific GPIO pins available in EFM32G210 is shown in Table 4.3 (p. 51). Each GPIO port is
organized as 16-bit ports indicated by letters A through F, and the individual pin on this port is indicated
by a number from 15 down to 0.
Table 4.3. GPIO Pinout
Port
Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin Pin
Pin
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
PA1
-
Port A
Port B
Port C
Port D
Port E
Port F
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PA2
PA0
PB14 PB13
PB11
-
PB8
PB7
-
-
-
-
-
-
PC0
-
PC15 PC14 PC13
-
-
-
-
-
-
-
-
-
-
-
-
-
PC1
-
-
-
-
-
-
-
-
-
PD7
PD6
PD5
PD4
-
-
-
PE13 PE12 PE11 PE10
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
PF2
PF1
PF0
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4.4 QFN32 Package
Figure 4.2. QFN32
Note:
1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.
2. All dimensions are in millimeters. Angles are in degrees.
3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm from
the terminal tip. Dimension L1 represents terminal full back from package edge up to 0.1 mm is
acceptable.
4. Coplanarity applies to the exposed heat slug as well as the terminal.
5. Radius on terminal is optional
Table 4.4. QFN32 (Dimensions in mm)
Symbol
Min
A
A1
A3
b
D
E
D2
E2
e
L
L1
aaa bbb ccc ddd
eee
0.80 0.00
0.25
0.30
0.35
4.30 4.30
4.40 4.40
4.50 4.50
0.30 0.00
0.35
0.203
REF
6.00 6.00
BSC BSC
0.65
BSC
Nom
Max
0.85
-
0.10 0.10 0.10 0.05 0.08
0.90 0.05
0.40 0.10
The QFN32 package uses Nickel-Palladium-Gold preplated leadframe.
All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).
For additional Quality and Environmental information, please see:
http://www.silabs.com/support/quality/pages/default.aspx
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5 PCB Layout and Soldering
5.1 Recommended PCB Layout
Figure 5.1. QFN32 PCB Land Pattern
a
p8
p7
p1
p6
b
p9
e
g
c
p2
p5
p3
p4
f
d
Table 5.1. QFN32 PCB Land Pattern Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.80
Symbol
Pin number
Symbol
Pin number
a
b
c
d
e
f
P1
P2
P3
P4
P5
-
1
8
P6
P7
P8
P9
-
24
25
32
33
-
0.35
0.65
26
16
17
-
6.00
6.00
4.40
-
-
g
4.40
-
-
-
-
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Figure 5.2. QFN32 PCB Solder Mask
a
b
c
e
g
f
d
Table 5.2. QFN32 PCB Solder Mask Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
0.92
a
b
c
d
e
f
0.47
0.65
6.00
6.00
4.52
g
4.52
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Figure 5.3. QFN32 PCB Stencil Design
a
b
c
x
y
e
z
d
Table 5.3. QFN32 PCB Stencil Design Dimensions (Dimensions in mm)
Symbol
Dim. (mm)
a
b
c
d
e
x
y
z
0.70
0.25
0.65
6.00
6.00
1.30
1.30
0.50
1. The drawings are not to scale.
2. All dimensions are in millimeters.
3. All drawings are subject to change without notice.
4. The PCB Land Pattern drawing is in compliance with IPC-7351B.
5. Stencil thickness 0.125 mm.
6. For detailed pin-positioning, see Figure 4.2 (p. 52) .
5.2 Soldering Information
The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.
Place as many and as small as possible vias underneath each of the solder patches under the ground
pad.
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6 Chip Marking, Revision and Errata
6.1 Chip Marking
In the illustration below package fields and position are shown.
Figure 6.1. Example Chip Marking (top view)
6.2 Revision
The revision of a chip can be determined from the "Revision" field in Figure 6.1 (p. 56) .
6.3 Errata
Please see the errata document for EFM32G210 for description and resolution of device erratas. This
document is available in Simplicity Studio and online at:
http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit
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7 Revision History
7.1 Revision 1.90
May 22nd, 2015
Added clarification on conditions for INLADC and DNLADC parameters.
Corrected EM2 current consumption condition in Electrical Characteristics section.
Added AUXHFRCO to block diagram and Electrical Characteristics.
Updated HFRCO table in the Electrical Characteristics section.
Updated EM0, EM2, EM3, and EM4 maximum current specifications in the Electrical Characteristics
section.
Updated the Output Low Voltage maximum for sinking 20 mA with VDD = 3.0 V in the Electrical Char-
acteristics section.
Updated the Input Leakage Current maximum in the Electrical Characteristics section.
Updated the minimum and maximum frequency specifications for the LFRCO, HFRCO, and AUXHFRCO
in the Electrical Characteristics section.
Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.
Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.
Added some minimum ADC SNR, SNDR, and SFDR specifications in the Electrical Characteristics sec-
tion.
Added some minimum and maximum ADC offset voltage, DNL, and INL specifications in the Electrical
Characteristics section.
Added maximum DAC current specifications in the Electrical Characteristics section.
Added maximum ACMP current and maximum and minimum offset voltage specifications in the Electrical
Characteristics section.
Added maximum VCMP current and updated typical VCMP current specifications in the Electrical Char-
acteristics section.
Updated references to energyAware Designer to Configurator.
7.2 Revision 1.80
July 2nd, 2014
Corrected single power supply voltage minimum value from 1.85V to 1.98V.
Updated current consumption.
Updated transition between energy modes.
Updated power management data.
Updated GPIO data.
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Updated LFXO, HFXO, HFRCO and ULFRCO data.
Updated LFRCO and HFRCO plots.
Updated ACMP data.
7.3 Revision 1.71
November 21st, 2013
Updated figures.
Updated errata-link.
Updated chip marking.
Added link to Environmental and Quality information.
Re-added missing DAC-data.
7.4 Revision 1.70
September 30th, 2013
Added I2C characterization data.
Corrected GPIO operating voltage from 1.8 V to 1.85 V.
Corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.
Updated Environmental information.
Updated trademark, disclaimer and contact information.
Other minor corrections.
7.5 Revision 1.60
June 28th, 2013
Updated power requirements in the Power Management section.
Removed minimum load capacitance figure and table. Added reference to application note.
Other minor corrections.
7.6 Revision 1.50
September 11th, 2012
Updated the HFRCO 1 MHz band typical value to 1.2 MHz.
Updated the HFRCO 7 MHz band typical value to 6.6 MHz.
Other minor corrections.
7.7 Revision 1.40
February 27th, 2012
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Updated Power Management section.
Corrected operating voltage from 1.8 V to 1.85 V.
Corrected TGRADADCTH parameter.
Corrected QFN32 package drawing.
Updated PCB land pattern, solder mask and stencil design.
7.8 Revision 1.30
May 20th, 2011
Updated LFXO load capacitance section.
7.9 Revision 1.20
December 17th, 2010
Increased max storage temperature.
Added data for <150°C and <70°C on Flash data retention.
Changed latch-up sensitivity test description.
Added IO leakage current.
Added Flash current consumption
Updated HFRCO data.
Updated LFRCO data.
Added graph for ADC Absolute Offset over temperature.
Added graph for ADC Temperature sensor readout.
7.10 Revision 1.11
November 17th, 2010
Corrected maximum DAC clock speed for continuous mode.
Added DAC sample-hold mode voltage drift rate.
Added pulse widths detected by the HFXO glitch detector.
Added power sequencing information to Power Management section.
7.11 Revision 1.10
September 13th, 2010
Added typical values for RADCFILT and CADCFILT
.
Added two conditions for DAC clock frequency; one for sample/hold and one for sample/off.
Added RoHS information and specified leadframe/solderballs material.
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Added Serial Bootloader to feature list and system summary.
Updated ADC characterization data.
Updated DAC characterization data.
Updated RCO characterization data.
Updated ACMP characterization data.
Updated VCMP characterization data.
7.12 Revision 1.00
April 23rd, 2010
ADC_VCM line removed.
Added pinout illustration and additional pinout table.
Changed "Errata" chapter. Errata description moved to separate document.
Document changed status from "Preliminary".
Updated "Electrical Characteristics" chapter.
7.13 Revision 0.85
February 19th, 2010
Renamed DBG_SWV pin to DBG_SWO.
7.14 Revision 0.83
January 25th, 2010
Updated errata section.
Specified flash word width in Section 3.7 (p. 18) .
Added Capacitive Sense Internal Resistor values in Section 3.12 (p. 43) .
7.15 Revision 0.82
December 9th, 2009
Updated contact information.
ADC current consumption numbers updated in Section 3.10 (p. 32) .
7.16 Revision 0.81
November 20th, 2009
Section 2.1.21 (p. 6) updated.
Section 3.1 (p. 9) updated.
Storage temperature in Section 3.2 (p. 9) updated.
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Temperature coefficient of band-gap reference in Section 3.6 (p. 17) added.
Erase times in Section 3.7 (p. 18) updated.
Definitions of DNL and INL added in Figure 3.27 (p. 36) and Figure 3.28 (p. 37) .
Current consumption of digital peripherals added in Section 3.15 (p. 46) .
Updated errata section.
7.17 Revision 0.80
Initial preliminary revision, October 19th, 2009
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A Disclaimer and Trademarks
A.1 Disclaimer
Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation
of all peripherals and modules available for system and software implementers using or intending to use
the Silicon Laboratories products. Characterization data, available modules and peripherals, memory
sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and
do vary in different applications. Application examples described herein are for illustrative purposes only.
Silicon Laboratories reserves the right to make changes without further notice and limitation to product
information, specifications, and descriptions herein, and does not give warranties as to the accuracy
or completeness of the included information. Silicon Laboratories shall have no liability for the conse-
quences of use of the information supplied herein. This document does not imply or express copyright
licenses granted hereunder to design or fabricate any integrated circuits. The products must not be
used within any Life Support System without the specific written consent of Silicon Laboratories. A "Life
Support System" is any product or system intended to support or sustain life and/or health, which, if it
fails, can be reasonably expected to result in significant personal injury or death. Silicon Laboratories
products are generally not intended for military applications. Silicon Laboratories products shall under no
circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological
or chemical weapons, or missiles capable of delivering such weapons.
A.2 Trademark Information
Silicon Laboratories Inc., Silicon Laboratories, Silicon Labs, SiLabs and the Silicon Labs logo, CMEMS®,
EFM, EFM32, EFR, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most ener-
gy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISO-
modem®, Precision32®, ProSLIC®, SiPHY®, USBXpress® and others are trademarks or registered
trademarks of Silicon Laboratories Inc. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or reg-
istered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products
or brand names mentioned herein are trademarks of their respective holders.
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B Contact Information
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Please visit the Silicon Labs Technical Support web page:
http://www.silabs.com/support/pages/contacttechnicalsupport.aspx
and register to submit a technical support request.
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Table of Contents
1. Ordering Information .................................................................................................................................. 2
2. System Summary ...................................................................................................................................... 3
2.1. System Introduction ......................................................................................................................... 3
2.2. Configuration Summary .................................................................................................................... 6
2.3. Memory Map ................................................................................................................................. 7
3. Electrical Characteristics ............................................................................................................................. 9
3.1. Test Conditions .............................................................................................................................. 9
3.2. Absolute Maximum Ratings .............................................................................................................. 9
3.3. General Operating Conditions ........................................................................................................... 9
3.4. Current Consumption ..................................................................................................................... 10
3.5. Transition between Energy Modes .................................................................................................... 17
3.6. Power Management ....................................................................................................................... 17
3.7. Flash .......................................................................................................................................... 18
3.8. General Purpose Input Output ......................................................................................................... 18
3.9. Oscillators .................................................................................................................................... 27
3.10. Analog Digital Converter (ADC) ...................................................................................................... 32
3.11. Digital Analog Converter (DAC) ...................................................................................................... 41
3.12. Analog Comparator (ACMP) .......................................................................................................... 43
3.13. Voltage Comparator (VCMP) ......................................................................................................... 45
3.14. I2C ........................................................................................................................................... 45
3.15. Digital Peripherals ....................................................................................................................... 46
4. Pinout and Package ................................................................................................................................. 48
4.1. Pinout ......................................................................................................................................... 48
4.2. Alternate Functionality Pinout .......................................................................................................... 49
4.3. GPIO Pinout Overview ................................................................................................................... 51
4.4. QFN32 Package ........................................................................................................................... 52
5. PCB Layout and Soldering ........................................................................................................................ 53
5.1. Recommended PCB Layout ............................................................................................................ 53
5.2. Soldering Information ..................................................................................................................... 55
6. Chip Marking, Revision and Errata .............................................................................................................. 56
6.1. Chip Marking ................................................................................................................................ 56
6.2. Revision ...................................................................................................................................... 56
6.3. Errata ......................................................................................................................................... 56
7. Revision History ...................................................................................................................................... 57
7.1. Revision 1.90 ............................................................................................................................... 57
7.2. Revision 1.80 ............................................................................................................................... 57
7.3. Revision 1.71 ............................................................................................................................... 58
7.4. Revision 1.70 ............................................................................................................................... 58
7.5. Revision 1.60 ............................................................................................................................... 58
7.6. Revision 1.50 ............................................................................................................................... 58
7.7. Revision 1.40 ............................................................................................................................... 58
7.8. Revision 1.30 ............................................................................................................................... 59
7.9. Revision 1.20 ............................................................................................................................... 59
7.10. Revision 1.11 .............................................................................................................................. 59
7.11. Revision 1.10 .............................................................................................................................. 59
7.12. Revision 1.00 .............................................................................................................................. 60
7.13. Revision 0.85 .............................................................................................................................. 60
7.14. Revision 0.83 .............................................................................................................................. 60
7.15. Revision 0.82 .............................................................................................................................. 60
7.16. Revision 0.81 .............................................................................................................................. 60
7.17. Revision 0.80 .............................................................................................................................. 61
A. Disclaimer and Trademarks ....................................................................................................................... 62
A.1. Disclaimer ................................................................................................................................... 62
A.2. Trademark Information ................................................................................................................... 62
B. Contact Information ................................................................................................................................. 63
B.1. ................................................................................................................................................. 63
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List of Figures
2.1. Block Diagram ....................................................................................................................................... 3
2.2. EFM32G210 Memory Map with largest RAM and Flash sizes .......................................................................... 8
3.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 28
MHz ........................................................................................................................................................ 11
3.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21
MHz ........................................................................................................................................................ 11
3.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14
MHz ........................................................................................................................................................ 12
3.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11
MHz ........................................................................................................................................................ 12
3.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 7
MHz ........................................................................................................................................................ 13
3.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28 MHz .............................. 13
3.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz .............................. 14
3.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz .............................. 14
3.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz .............................. 15
3.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 7 MHz .............................. 15
3.11. EM2 current consumption. RTC prescaled to 1kHz, 32.768 kHz LFRCO. ....................................................... 16
3.12. EM3 current consumption. ................................................................................................................... 16
3.13. EM4 current consumption. ................................................................................................................... 17
3.14. Typical Low-Level Output Current, 2V Supply Voltage ................................................................................ 21
3.15. Typical High-Level Output Current, 2V Supply Voltage ................................................................................ 22
3.16. Typical Low-Level Output Current, 3V Supply Voltage ................................................................................ 23
3.17. Typical High-Level Output Current, 3V Supply Voltage ................................................................................ 24
3.18. Typical Low-Level Output Current, 3.8V Supply Voltage .............................................................................. 25
3.19. Typical High-Level Output Current, 3.8V Supply Voltage ............................................................................. 26
3.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage .............................................................. 29
3.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature ............................................ 30
3.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 30
3.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature ........................................... 31
3.27. Integral Non-Linearity (INL) ................................................................................................................... 36
3.28. Differential Non-Linearity (DNL) .............................................................................................................. 37
3.29. ADC Frequency Spectrum, Vdd = 3V, Temp = 25°C ................................................................................. 38
3.30. ADC Integral Linearity Error vs Code, Vdd = 3V, Temp = 25°C ................................................................... 39
3.31. ADC Differential Linearity Error vs Code, Vdd = 3V, Temp = 25°C ............................................................... 40
3.32. ADC Absolute Offset, Common Mode = Vdd /2 ........................................................................................ 41
3.33. ADC Dynamic Performance vs Temperature for all ADC References, Vdd = 3V .............................................. 41
3.34. ACMP Characteristics, Vdd = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1 ............................................. 44
4.1. EFM32G210 Pinout (top view, not to scale) ............................................................................................... 48
4.2. QFN32 ................................................................................................................................................ 52
5.1. QFN32 PCB Land Pattern ...................................................................................................................... 53
5.2. QFN32 PCB Solder Mask ....................................................................................................................... 54
5.3. QFN32 PCB Stencil Design .................................................................................................................... 55
6.1. Example Chip Marking (top view) ............................................................................................................. 56
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List of Tables
1.1. Ordering Information ................................................................................................................................ 2
2.1. Configuration Summary ............................................................................................................................ 6
3.1. Absolute Maximum Ratings ...................................................................................................................... 9
3.2. General Operating Conditions ................................................................................................................... 9
3.3. Current Consumption ............................................................................................................................. 10
3.4. Energy Modes Transitions ...................................................................................................................... 17
3.5. Power Management ............................................................................................................................... 18
3.6. Flash .................................................................................................................................................. 18
3.7. GPIO .................................................................................................................................................. 18
3.8. LFXO .................................................................................................................................................. 27
3.9. HFXO ................................................................................................................................................. 28
3.10. LFRCO .............................................................................................................................................. 28
3.11. HFRCO ............................................................................................................................................. 29
3.12. AUXHFRCO ....................................................................................................................................... 32
3.13. ULFRCO ............................................................................................................................................ 32
3.14. ADC .................................................................................................................................................. 32
3.15. DAC .................................................................................................................................................. 41
3.16. ACMP ............................................................................................................................................... 43
3.17. VCMP ............................................................................................................................................... 45
3.18. I2C Standard-mode (Sm) ...................................................................................................................... 45
3.19. I2C Fast-mode (Fm) ............................................................................................................................ 46
3.20. I2C Fast-mode Plus (Fm+) .................................................................................................................... 46
3.21. Digital Peripherals ............................................................................................................................... 46
4.1. Device Pinout ....................................................................................................................................... 48
4.2. Alternate functionality overview ................................................................................................................ 50
4.3. GPIO Pinout ........................................................................................................................................ 51
4.4. QFN32 (Dimensions in mm) .................................................................................................................... 52
5.1. QFN32 PCB Land Pattern Dimensions (Dimensions in mm) .......................................................................... 53
5.2. QFN32 PCB Solder Mask Dimensions (Dimensions in mm) ........................................................................... 54
5.3. QFN32 PCB Stencil Design Dimensions (Dimensions in mm) ........................................................................ 55
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List of Equations
3.1. Total ACMP Active Current ..................................................................................................................... 43
3.2. VCMP Trigger Level as a Function of Level Setting ..................................................................................... 45
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