EFM32G210F128G-E-QFN32

EFM32 Gecko Family

EFM32G Data Sheet

The EFM32 Gecko MCUs are the world’s most energy-friendly mi-

crocontrollers.

KEY FEATURES

• ARM Cortex-M3 at 32 MHz

The EFM32G offers unmatched performance and ultra low power consumption in both

active and sleep modes. EFM32G devices consume as little as 0.6 μA in Stop mode and

180 μA/MHz in Run mode. It also features autonomous peripherals, high overall chip and

analog integration, and the performance of the industry standard 32-bit ARM Cortex-M3

processor, making it perfect for battery-powered systems and systems with high-per-

formance, low-energy requirements.

• Ultra low power operation

• 0.6 μA current in Stop (EM3), with

brown-out detection and RAM retention

• 45 μA/MHz in EM1

• 180 μA/MHz in Run mode (EM0)

• Fast wake-up time of 2 µs

EFM32G applications include the following:

• Hardware cryptography (AES)

• Up to 128 kB of Flash and 16 kB of RAM

• Alarm and security systems

• Energy, gas, water and smart metering

• Industrial and home automation

• Health and fitness applications

• Smart accessories

Core / Memory

Clock Management

Energy Management

Security

High Frequency

Crystal Oscillator

High Frequency

RC Oscillator

ARM Cortex^TM

M3 processor

Memory

Protection Unit

Voltage

Regulator

Voltage

Comparator

Hardware AES

Low Frequency

RC Oscillator

Auxiliary High

Freq. RC Osc.

Flash Program

Memory

Debug Interface

DMA Controller

Brown-Out

Detector

Low Frequency

Crystal

Oscillator

Power-On Reset

Watchdog

Oscillator

RAM Memory

32-bit bus

Peripheral Reflex System

Serial Interfaces

I/O Ports

Timers and Triggers

Analog Interfaces

Pulse Counter

Timer/Counter

General

External Bus

USART

UART

I²C

ADC

DAC

Interface

Purpose I/O

Low Energy Timer

Watchdog Timer

External

Interrupts

Low Energy

UART^TM

Analog

Comparator

LCD Controller

Pin Reset

Real Time

Counter

Lowest power mode with peripheral operational:

EM0 - Active

EM2 – Deep Sleep

EM1 - Sleep

EM3 - Stop

EM4 - Shutoff

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Rev. 2.10

EFM32G Data Sheet

Feature List

1. Feature List

• ARM Cortex-M3 CPU platform

• High Performance 32-bit processor @ up to 32 MHz

• Memory Protection Unit

• Wake-up Interrupt Controller

• SysTick System Timer

• Flexible Energy Management System

• 20 nA @ 3 V Shutoff Mode

• 0.6 µA @ 3 V Stop Mode, including Power-on Reset, Brown-out Detector, RAM and CPU retention

• 0.9 µA @ 3 V Deep Sleep Mode, including RTC with 32.768 kHz oscillator, Power-on Reset, Brown-out Detector, RAM and CPU

retention

• 45 µA/MHz @ 3 V Sleep Mode

• 180 µA/MHz @ 3 V Run Mode, with code executed from flash

• 128/64/32 KB Flash

• 16/8 KB RAM

• Up to 90 General Purpose I/O pins

• Configurable push-pull, open-drain, pull-up/down, input filter, drive strength

• Configurable peripheral I/O locations

• 16 asynchronous external interrupts

• Output state retention and wake-up from Shutoff Mode

• 8 Channel DMA Controller

• 8 Channel Peripheral Reflex System (PRS) for autonomous inter-peripheral signaling

• Hardware AES with 128/256-bit keys in 54/75 cycles

• Timers/Counters

• 3 × 16-bit Timer/Counter

• 3×3 Compare/Capture/PWM channels

• Dead-Time Insertion on TIMER0

• 16-bit Low Energy Timer

• 1× 24-bit Real-Time Counter

• 3× 8-bit Pulse Counter

• Watchdog Timer with dedicated RC oscillator @ 50 nA

• Integrated LCD Controller for up to 4×40 segments

• Voltage boost, adjustable contrast and autonomous animation

• External Bus Interface for up to 4x64 MB of external memory mapped space

• TFT Controller with Direct Drive

• Communication interfaces

• Up to 3× Universal Synchronous/Asynchronous Receiver/ Transmitter

• UART/SPI/SmartCard (ISO 7816)/IrDA/I2S

• Triple buffered full/half-duplex operation

• 1× Universal Asynchronous Receiver/Transmitter

• 2× Low Energy UART

• Autonomous operation with DMA in Deep Sleep Mode

I²C Interface with SMBus support

• Address recognition in Stop Mode

•

• Ultra low power precision analog peripherals

• 12-bit 1 Msamples/s Analog to Digital Converter

• 8 single-ended channels/4 differential channels

• On-chip temperature sensor

• 12-bit 500 ksamples/s Digital to Analog Converter

• 2 single-ended channels/1 differential channel

• 2× Analog Comparator

• Capacitive sensing with up to 16 inputs

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Rev. 2.10 | 2

EFM32G Data Sheet

Feature List

• Supply Voltage Comparator

• Ultra efficient Power-on Reset and Brown-Out Detector

• 2-pin Serial Wire Debug Interface

• 1-pin Serial Wire Viewer

• Pre-Programmed USB/UART Bootloader

• Temperature range -40 to 85 ºC

• Single power supply 1.98 to 3.8 V

• Packages

• BGA112

• LQFP100

• TQFP64

• TQFP48

• QFN64

• QFN32

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Rev. 2.10 | 3

EFM32G Data Sheet

Ordering Information

2. Ordering Information

The following table shows the available EFM32G devices.

Table 2.1. Ordering Information

Max Speed Supply Volt- Tempera-

Ordering Code

Flash (kB)

16

RAM (kB)

(MHz)

32

age (V)

ture (ºC)

-40 - 85

Package

QFN32

EFM32G200F16G-E-QFN32

EFM32G200F32G-E-QFN32

EFM32G200F64G-E-QFN32

EFM32G210F128G-E-QFN32

EFM32G222F32G-E-QFP48

EFM32G222F64G-E-QFP48

EFM32G222F128G-E-QFP48

EFM32G230F32G-E-QFN64

EFM32G230F64G-E-QFN64

EFM32G230F128G-E-QFN64

EFM32G232F32G-E-QFP64

EFM32G232F64G-E-QFP64

EFM32G232F128G-E-QFP64

EFM32G280F32G-E-QFP100

EFM32G280F64G-E-QFP100

EFM32G280F128G-E-QFP100

EFM32G290F32G-E-BGA112

EFM32G290F64G-E-BGA112

EFM32G290F128G-E-BGA112

EFM32G840F32G-E-QFN64

EFM32G840F64G-E-QFN64

EFM32G840F128G-E-QFN64

EFM32G842F32G-E-QFP64

EFM32G842F64G-E-QFP64

EFM32G842F128G-E-QFP64

EFM32G880F32G-E-QFP100

EFM32G880F64G-E-QFP100

EFM32G880F128G-E-QFP100

EFM32G890F32G-E-BGA112

EFM32G890F64G-E-BGA112

EFM32G890F128G-E-BGA112

8

1.98 - 3.8

32

8

QFN32

64

16

8

QFN32

128

32

QFN32

TQFP48

QFN64

64

16

8

128

32

64

16

8

QFN64

128

32

QFN64

TQFP64

LQFP100

BGA112

QFN64

64

16

8

128

32

64

16

8

128

32

64

16

8

128

32

64

16

8

QFN64

128

32

QFN64

TQFP64

LQFP100

BGA112

64

16

8

128

32

64

16

8

128

32

64

16

128

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Rev. 2.10 | 4

EFM32G Data Sheet

Ordering Information

EFM32 G 890 F 128 G – E – BGA 112 R

Tape and Reel (Optional)

Pin Count

Package

Revision

Temperature Grade – G (-40 to +85 °C)

Memory Size in kB

Memory Type (Flash)

Feature Set Code

Gecko

Energy Friendly Microcontroller 32-bit

Figure 2.1. Ordering Code Decoder

Adding the suffix 'R' to the part number (e.g., EFM32G890F128G-E-BGA112R) denotes tape and reel.

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Rev. 2.10 | 5

Table of Contents

1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.1 System Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.1.1 ARM Cortex-M3 Core . . . . . . . . . . . . . . . . . . . . . . . . .10

3.1.2 Debug Interface (DBG). . . . . . . . . . . . . . . . . . . . . . . . .10

3.1.3 Memory System Controller (MSC) . . . . . . . . . . . . . . . . . . . . .10

3.1.4 Direct Memory Access Controller (DMA) . . . . . . . . . . . . . . . . . . .11

3.1.5 Reset Management Unit (RMU) . . . . . . . . . . . . . . . . . . . . . .11

3.1.6 Energy Management Unit (EMU) . . . . . . . . . . . . . . . . . . . . .11

3.1.7 Clock Management Unit (CMU) . . . . . . . . . . . . . . . . . . . . . .11

3.1.8 Watchdog (WDOG) . . . . . . . . . . . . . . . . . . . . . . . . . .11

3.1.9 Peripheral Reflex System (PRS) . . . . . . . . . . . . . . . . . . . . .11

3.1.10 External Bus Interface (EBI) . . . . . . . . . . . . . . . . . . . . . .11

3.1.11 Inter-Integrated Circuit Interface (I2C) . . . . . . . . . . . . . . . . . . .11

3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) . . . . . . . .11

3.1.13 Pre-Programmed USB/UART Bootloader . . . . . . . . . . . . . . . . . .11

3.1.14 Universal Asynchronous Receiver/Transmitter (UART) . . . . . . . . . . . . .12

3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART) . . . . . . . .12

3.1.16 Timer/Counter (TIMER) . . . . . . . . . . . . . . . . . . . . . . . .12

3.1.17 Real Time Counter (RTC) . . . . . . . . . . . . . . . . . . . . . . .12

3.1.18 Low Energy Timer (LETIMER) . . . . . . . . . . . . . . . . . . . . . .12

3.1.19 Pulse Counter (PCNT) . . . . . . . . . . . . . . . . . . . . . . . .12

3.1.20 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . .12

3.1.21 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . .12

3.1.22 Analog to Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . .12

3.1.23 Digital to Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . .12

3.1.24 Advanced Encryption Standard Accelerator (AES) . . . . . . . . . . . . . . .13

3.1.25 General Purpose Input/Output (GPIO) . . . . . . . . . . . . . . . . . . .13

3.1.26 Liquid Crystal Display Driver (LCD) . . . . . . . . . . . . . . . . . . . .13

3.2 Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.2.1 EFM32G200 . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

3.2.2 EFM32G210 . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

3.2.3 EFM32G222 . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3.2.4 EFM32G230 . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.2.5 EFM32G232 . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

3.2.6 EFM32G280 . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

3.2.7 EFM32G290 . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

3.2.8 EFM32G840 . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

3.2.9 EFM32G842 . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

3.2.10 EFM32G880 . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

3.2.11 EFM32G890 . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

3.3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

4. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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4.1 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.1.1 Typical Values . . . . . . . . . . . . . . . . . . . . . . . . . . .29

4.1.2 Minimum and Maximum Values . . . . . . . . . . . . . . . . . . . . . .29

4.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . .29

4.3 General Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . .29

4.4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . .30

4.4.1 EM0 Current Consumption . . . . . . . . . . . . . . . . . . . . . . .31

4.4.2 EM1 Current Consumption . . . . . . . . . . . . . . . . . . . . . . .34

4.4.3 EM2 Current Consumption . . . . . . . . . . . . . . . . . . . . . . .37

4.4.4 EM3 Current Consumption . . . . . . . . . . . . . . . . . . . . . . .38

4.4.5 EM4 Current Consumption . . . . . . . . . . . . . . . . . . . . . . .39

4.5 Transition between Energy Modes . . . . . . . . . . . . . . . . . . . . . . .39

4.6 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

4.7 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

4.8 General Purpose Input Output . . . . . . . . . . . . . . . . . . . . . . . .42

4.9 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.9.1 LFXO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

4.9.2 HFXO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

4.9.3 LFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

4.9.4 HFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

4.9.5 AUXHFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.9.6 ULFRCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

4.10 Analog Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . .58

4.10.1 Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . .67

4.11 Digital Analog Converter (DAC) . . . . . . . . . . . . . . . . . . . . . . .71

4.12 Analog Comparator (ACMP) . . . . . . . . . . . . . . . . . . . . . . . .73

4.13 Voltage Comparator (VCMP) . . . . . . . . . . . . . . . . . . . . . . . .75

4.14 LCD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

4.15 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

4.16 Digital Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

5. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.1 EFM32G200 & EFM32G210 (QFN32). . . . . . . . . . . . . . . . . . . . . .79

5.1.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

5.1.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .82

5.1.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . .84

5.2 EFM32G222 (TQFP48). . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.2.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

5.2.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .88

5.2.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . .90

5.3 EFM32G230 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.3.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

5.3.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . . .94

5.3.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . .97

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5.4 EFM32G232 (TQFP64). . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.4.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98

5.4.2 Alternate Functionality Pinout

5.4.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 103

5.5 EFM32G280 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .104

5.5.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 04

5.5.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 1.09

. . . . . . . . . . . . . . . . . . . . 1.01

5.5.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 113

5.6 EFM32G290 (BGA112). . . . . . . . . . . . . . . . . . . . . . . . . . 114

5.6.1 Pinout

5.6.2 Alternate Functionality Pinout

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 14

. . . . . . . . . . . . . . . . . . . . 1.19

5.6.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 123

5.7 EFM32G840 (QFN64) . . . . . . . . . . . . . . . . . . . . . . . . . . 124

5.7.1 Pinout

5.7.2 Alternate Functionality Pinout

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 24

. . . . . . . . . . . . . . . . . . . . 1.27

5.7.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 131

5.8 EFM32G842 (TQFP64). . . . . . . . . . . . . . . . . . . . . . . . . . 132

5.8.1 Pinout

5.8.2 Alternate Functionality Pinout

5.8.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 139

5.9 EFM32G880 (LQFP100) . . . . . . . . . . . . . . . . . . . . . . . . .140

5.9.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 40

5.9.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . 1.46

5.9.3 GPIO Pinout Overview . . . . . . . . . . . . . . . . . . . . . . . . 152

5.10 EFM32G890 (BGA112) . . . . . . . . . . . . . . . . . . . . . . . . .153

. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 32

. . . . . . . . . . . . . . . . . . . . 1.35

5.10.1 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153

5.10.2 Alternate Functionality Pinout . . . . . . . . . . . . . . . . . . . . .159

5.10.3 GPIO Pinout Overview

6. BGA112 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .166

6.1 BGA112 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .166

. . . . . . . . . . . . . . . . . . . . . . 1. 65

6.2 BGA112 PCB Layout

. . . . . . . . . . . . . . . . . . . . . . . . . .167

. . . . . . . . . . . . . . . . . . . . . . . 1.69

6.3 BGA112 Package Marking

7. LQFP100 Package Specifications . . . . . . . . . . . . . . . . . . . . . . . 170

7.1 LQFP100 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . 170

7.2 LQFP100 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . 172

7.3 LQFP100 Package Marking . . . . . . . . . . . . . . . . . . . . . . . .174

8. TQFP64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .175

8.1 TQFP64 Package Dimensions

. . . . . . . . . . . . . . . . . . . . . . .175

8.2 TQFP64 PCB Layout

. . . . . . . . . . . . . . . . . . . . . . . . . .177

. . . . . . . . . . . . . . . . . . . . . . . 1.79

8.3 TQFP64 Package Marking

9. TQFP48 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .180

9.1 TQFP48 Package Dimensions

. . . . . . . . . . . . . . . . . . . . . . .180

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Rev. 2.10 | 8

9.2 TQFP48 PCB Layout

. . . . . . . . . . . . . . . . . . . . . . . . . .182

. . . . . . . . . . . . . . . . . . . . . . . 1.84

9.3 TQFP48 Package Marking

10. QFN64 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .185

10.1 QFN64 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .185

10.2 QFN64 PCB Layout

. . . . . . . . . . . . . . . . . . . . . . . . . .187

. . . . . . . . . . . . . . . . . . . . . . . 1.89

10.3 QFN64 Package Marking

11. QFN32 Package Specifications . . . . . . . . . . . . . . . . . . . . . . .190

11.1 QFN32 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . .190

11.2 QFN32 PCB Layout

. . . . . . . . . . . . . . . . . . . . . . . . . .191

. . . . . . . . . . . . . . . . . . . . . . . 1.93

11.3 QFN32 Package Marking

12. Chip Revision, Solder Information, Errata . . . . . . . . . . . . . . . . . . .194

12.1 Chip Revision . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 94

12.2 Soldering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 194

12.3 Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .194

13. Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

13.1 Revision 2.10

13.2 Revision 2.00

13.3 Revision 1.90

13.4 Revision 1.80

13.5 Revision 1.71

13.6 Revision 1.70

13.7 Revision 1.60

13.8 Revision 1.50

13.9 Revision 1.40

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.95

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.96

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.97

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.98

. . . . . . . . . . . . . . . . . . . . . . . . . . . 1.99

13.10 Revision 1.30 . . . . . . . . . . . . . . . . . . . . . . . . . . . .199

13.11 Revision 1.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

13.12 Revision 1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . .200

13.13 Revision 1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

13.14 Revision 1.00 . . . . . . . . . . . . . . . . . . . . . . . . . . . .201

13.15 Revision 0.90 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

13.16 Revision 0.85 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

13.17 Revision 0.84 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

13.18 Revision 0.83 . . . . . . . . . . . . . . . . . . . . . . . . . . . .202

13.19 Revision 0.82 . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

13.20 Revision 0.81 . . . . . . . . . . . . . . . . . . . . . . . . . . . .203

13.21 Revision 0.80 . . . . . . . . . . . . . . . . . . . . . . . . . . . .204

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Rev. 2.10 | 9

EFM32G Data Sheet

System Overview

3. System Overview

3.1 System Introduction

The EFM32 MCUs are the world’s most energy friendly microcontrollers. With a unique combination of the powerful 32-bit ARM Cortex-

M3, innovative low energy techniques, short wake-up time from energy saving modes, and a wide selection of peripherals, the EFM32G

microcontroller is well suited for any battery operated application as well as other systems requiring high performance and low-energy

consumption. This section gives a short introduction to each of the modules in general terms and also shows a summary of the configu-

ration for the EFM32G devices. For a complete feature set and in-depth information on the modules, the reader is referred to the

EFM32G Reference Manual.

The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device fea-

tures, consult Ordering Information.

Core / Memory

Clock Management

Energy Management

Security

High Frequency

Crystal Oscillator

High Frequency

RC Oscillator

ARM Cortex^TM

M3 processor

Memory

Protection Unit

Voltage

Regulator

Voltage

Comparator

Hardware AES

Low Frequency

RC Oscillator

Auxiliary High

Freq. RC Osc.

Flash Program

Memory

Debug Interface

DMA Controller

Brown-Out

Detector

Low Frequency

Crystal

Oscillator

Power-On Reset

Watchdog

Oscillator

RAM Memory

32-bit bus

Peripheral Reflex System

Serial Interfaces

I/O Ports

Timers and Triggers

Analog Interfaces

Pulse Counter

Timer/Counter

General

External Bus

USART

UART

I²C

ADC

DAC

Interface

Purpose I/O

Low Energy Timer

Watchdog Timer

External

Interrupts

Low Energy

UART^TM

Analog

Comparator

LCD Controller

Pin Reset

Real Time

Counter

Lowest power mode with peripheral operational:

EM0 - Active

EM2 – Deep Sleep

EM1 - Sleep

EM3 - Stop

EM4 - Shutoff

Figure 3.1. Block Diagram

3.1.1 ARM Cortex-M3 Core

The ARM Cortex-M3 includes a 32-bit RISC processor which can achieve as much as 1.25 Dhrystone MIPS/MHz. A Memory Protection

Unit with support for up to 8 memory segments is included, as well as a Wake-up Interrupt Controller handling interrupts triggered while

the CPU is asleep. The EFM32 implementation of the Cortex-M3 is described in detail in EFM32G Reference Manual.

3.1.2 Debug Interface (DBG)

This device includes hardware debug support through a 2-pin serial-wire debug interface . In addition there is also a 1-wire Serial Wire

Viewer pin which can be used to output profiling information, data trace and software-generated messages.

3.1.3 Memory System Controller (MSC)

The Memory System Controller (MSC) is the program memory unit of the EFM32G microcontroller. The flash memory is readable and

writable from both the Cortex-M3 and DMA. The flash memory is divided into two blocks; the main block and the information block.

Program code is normally written to the main block. Additionally, the information block is available for special user data and flash lock

bits. There is also a read-only page in the information block containing system and device calibration data. Read and write operations

are supported in the energy modes EM0 and EM1.

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EFM32G Data Sheet

System Overview

3.1.4 Direct Memory Access Controller (DMA)

The Direct Memory Access (DMA) controller performs memory operations independently of the CPU. This has the benefit of reducing

the energy consumption and the workload of the CPU, and enables the system to stay in low energy modes when moving for instance

data from the USART to RAM or from the External Bus Interface to a PWM-generating timer. The DMA controller uses the PL230

µDMA controller licensed from ARM.

3.1.5 Reset Management Unit (RMU)

The RMU is responsible for handling the reset functionality of the EFM32G.

3.1.6 Energy Management Unit (EMU)

The Energy Management Unit (EMU) manage all the low energy modes (EM) in EFM32G microcontrollers. Each energy mode man-

ages if the CPU and the various peripherals are available. The EMU can also be used to turn off the power to unused SRAM blocks.

3.1.7 Clock Management Unit (CMU)

The Clock Management Unit (CMU) is responsible for controlling the oscillators and clocks on-board the EFM32G. The CMU provides

the capability to turn on and off the clock on an individual basis to all peripheral modules in addition to enable/disable and configure the

available oscillators. The high degree of flexibility enables software to minimize energy consumption in any specific application by not

wasting power on peripherals and oscillators that are inactive.

3.1.8 Watchdog (WDOG)

The purpose of the watchdog timer is to generate a reset in case of a system failure, to increase application reliability. The failure may

e.g. be caused by an external event, such as an ESD pulse, or by a software failure.

3.1.9 Peripheral Reflex System (PRS)

The Peripheral Reflex System (PRS) system is a network which lets the different peripheral module communicate directly with each

other without involving the CPU. Peripheral modules which send out Reflex signals are called producers. The PRS routes these reflex

signals to consumer peripherals which apply actions depending on the data received. The format for the Reflex signals is not given, but

edge triggers and other functionality can be applied by the PRS.

3.1.10 External Bus Interface (EBI)

The External Bus Interface provides access to external parallel interface devices such as SRAM, FLASH, ADCs and LCDs. The inter-

face is memory mapped into the address bus of the Cortex-M3. This enables seamless access from software without manually manipu-

lating the IO settings each time a read or write is performed. The data and address lines are multiplexed in order to reduce the number

of pins required to interface the external devices. The timing is adjustable to meet specifications of the external devices. The interface is

limited to asynchronous devices.

3.1.11 Inter-Integrated Circuit Interface (I2C)

The I²C module provides an interface between the MCU and a serial I²C-bus. It is capable of acting as both a master and a slave, and

supports multi-master buses. Both standard-mode, fast-mode and fastmode plus speeds are supported, allowing transmission rates all

the way from 10 kbit/s up to 1 Mbit/s. Slave arbitration and timeouts are also provided to allow implementation of an SMBus compliant

system. The interface provided to software by the I²C module, allows both fine-grained control of the transmission process and close to

automatic transfers. Automatic recognition of slave addresses is provided in all energy modes.

3.1.12 Universal Synchronous/Asynchronous Receiver/Transmitter (USART)

The Universal Synchronous Asynchronous serial Receiver and Transmitter (USART) is a very flexible serial I/O module. It supports full

duplex asynchronous UART communication as well as RS-485, SPI, MicroWire and 3-wire. It can also interface with ISO7816 Smart-

Cards, and IrDA devices.

3.1.13 Pre-Programmed USB/UART Bootloader

The bootloader presented in application note AN0003 is pre-programmed in the device at factory. Autobaud and destructive write are

supported. The autobaud feature, interface and commands are described further in the application note.

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Rev. 2.10 | 11

EFM32G Data Sheet

System Overview

3.1.14 Universal Asynchronous Receiver/Transmitter (UART)

The Universal Asynchronous serial Receiver and Transmitter (UART) is a very flexible serial I/O module. It supports full- and half-du-

plex asynchronous UART communication.

3.1.15 Low Energy Universal Asynchronous Receiver/Transmitter (LEUART)

The unique LEUART^TM, the Low Energy UART, is a UART that allows two-way UART communication on a strict power budget. Only a

32.768 kHz clock is needed to allow UART communication up to 9600 baud/ s. The LEUART includes all necessary hardware support

to make asynchronous serial communication possible with minimum of software intervention and energy consumption.

3.1.16 Timer/Counter (TIMER)

The 16-bit general purpose Timer has 3 compare/capture channels for input capture and compare/Pulse-Width Modulation (PWM) out-

put. TIMER0 also includes a Dead-Time Insertion module suitable for motor control applications.

3.1.17 Real Time Counter (RTC)

The Real Time Counter (RTC) contains a 24-bit counter and is clocked either by a 32.768 kHz crystal oscillator, or a 32.768 kHz RC

oscillator. In addition to energy modes EM0 and EM1, the RTC is also available in EM2. This makes it ideal for keeping track of time

since the RTC is enabled in EM2 where most of the device is powered down.

3.1.18 Low Energy Timer (LETIMER)

The unique LETIMER^TM, the Low Energy Timer, is a 16-bit timer that is available in energy mode EM2 in addition to EM1 and EM0.

Because of this, it can be used for timing and output generation when most of the device is powered down, allowing simple tasks to be

performed while the power consumption of the system is kept at an absolute minimum. The LETIMER can be used to output a variety of

waveforms with minimal software intervention. It is also connected to the Real Time Counter (RTC), and can be configured to start

counting on compare matches from the RTC.

3.1.19 Pulse Counter (PCNT)

The Pulse Counter (PCNT) can be used for counting pulses on a single input or to decode quadrature encoded inputs. It runs off either

the internal LFACLK or the PCNTn_S0IN pin as external clock source. The module may operate in energy mode EM0 - EM3.

3.1.20 Analog Comparator (ACMP)

The Analog Comparator is used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is high-

er. Inputs can either be one of the selectable internal references or from external pins. Response time and thereby also the current

consumption can be configured by altering the current supply to the comparator.

3.1.21 Voltage Comparator (VCMP)

The Voltage Supply Comparator is used to monitor the supply voltage from software. An interrupt can be generated when the supply

falls below or rises above a programmable threshold. Response time and thereby also the current consumption can be configured by

altering the current supply to the comparator.

3.1.22 Analog to Digital Converter (ADC)

The ADC is a Successive Approximation Register (SAR) architecture, with a resolution of up to 12 bits at up to one million samples per

second. The integrated input mux can select inputs from 8 external pins and 6 internal signals.

3.1.23 Digital to Analog Converter (DAC)

The Digital to Analog Converter (DAC) can convert a digital value to an analog output voltage. The DAC is fully differential rail-to-rail,

with 12-bit resolution. It has two single-ended output buffers which can be combined into one differential output. The DAC may be used

for a number of different applications such as sensor interfaces or sound output.

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EFM32G Data Sheet

System Overview

3.1.24 Advanced Encryption Standard Accelerator (AES)

The AES accelerator performs AES encryption and decryption with 128-bit or 256-bit keys. Encrypting or decrypting one 128-bit data

block takes 52 HFCORECLK cycles with 128-bit keys and 75 HFCORECLK cycles with 256-bit keys. The AES module is an AHB slave

which enables efficient access to the data and key registers. All write accesses to the AES module must be 32-bit operations, i.e. 8- or

16-bit operations are not supported.

3.1.25 General Purpose Input/Output (GPIO)

General Purpose Input/Output (GPIO) pins are organized into ports with up to 16 pins each. These pins can individually be configured

as either an output or input. More advanced configurations like open-drain, filtering and drive strength can also be configured individual-

ly for the pins. The GPIO pins can also be overridden by peripheral pin connections, like Timer PWM outputs or USART communica-

tion, which can be routed to several locations on the device. The GPIO supports up to 16 asynchronous external pin interrupts, which

enables interrupts from any pin on the device. Also, the input value of a pin can be routed through the Peripheral Reflex System to

other peripherals.

3.1.26 Liquid Crystal Display Driver (LCD)

The LCD driver is capable of driving a segmented LCD display with up to 4x40 segments. A voltage boost function enables it to provide

the LCD display with higher voltage than the supply voltage for the device. In addition, an animation feature can run custom animations

on the LCD display without any CPU intervention. The LCD driver can also remain active even in Energy Mode 2 and provides a Frame

Counter interrupt that can wake-up the device on a regular basis for updating data.

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Rev. 2.10 | 13

EFM32G Data Sheet

System Overview

3.2 Configuration Summary

3.2.1 EFM32G200

The features of the EFM32G200 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.1. EFM32G200 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

Full configuration, 8-bit count register

Full configuration

24 pins

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

NA

WDOG

PRS

NA

I2C0

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

LEU0_TX, LEU0_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

LEUART0

TIMER0

TIMER1

RTC

NA

LETIMER0

PCNT0

ACMP0

ACMP1

VCMP

ADC0

LET0_O[1:0]

PCNT0_S[1:0]

ACMP0_CH[1:0], ACMP0_O

ACMP1_CH[7:5], ACMP1_O

NA

ADC0_CH[7:4]

DAC0

DAC0_OUT[0]

GPIO

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 14

EFM32G Data Sheet

System Overview

3.2.2 EFM32G210

The features of the EFM32G210 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.2. EFM32G210 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

Full configuration, 8-bit count register

Full configuration

24 pins

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

WDOG

PRS

NA

I2C0

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

LEU0_TX, LEU0_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

LEUART0

TIMER0

TIMER1

RTC

NA

LETIMER0

PCNT0

ACMP0

ACMP1

VCMP

ADC0

LET0_O[1:0]

PCNT0_S[1:0]

ACMP0_CH[1:0], ACMP0_O

ACMP1_CH[7:5], ACMP1_O

NA

ADC0_CH[7:4]

DAC0

DAC0_OUT[0]

AES

NA

GPIO

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 15

EFM32G Data Sheet

System Overview

3.2.3 EFM32G222

The features of the EFM32G222 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.3. EFM32G222 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

Full configuration, 8-bit count register

Full configuration

37 pins

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

WDOG

PRS

NA

I2C0

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

LEU0_TX, LEU0_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

LEUART0

TIMER0

TIMER1

TIMER2

RTC

TIM2_CC[2:0]

NA

LETIMER0

PCNT0

PCNT1

ACMP0

ACMP1

VCMP

ADC0

LET0_O[1:0]

PCNT0_S[1:0]

PCNT1_S[1:0]

ACMP0_CH[4:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

ADC0_CH[7:4]

DAC0

DAC0_OUT[1]

AES

NA

GPIO

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 16

EFM32G Data Sheet

System Overview

3.2.4 EFM32G230

The features of the EFM32G230 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.4. EFM32G230 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

Full configuration

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

Full configuration

NA

DMA

Full configuration

NA

RMU

Full configuration

NA

EMU

Full configuration

NA

CMU

Full configuration

CMU_OUT0, CMU_OUT1

NA

WDOG

PRS

Full configuration

NA

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

USART2

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

ADC0

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0]

AES

Full configuration

NA

GPIO

56 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 17

EFM32G Data Sheet

System Overview

3.2.5 EFM32G232

The features of the EFM32G232 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.5. EFM32G232 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

Full configuration

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

Full configuration

NA

DMA

Full configuration

NA

RMU

Full configuration

NA

EMU

Full configuration

NA

CMU

Full configuration

CMU_OUT0, CMU_OUT1

NA

WDOG

PRS

Full configuration

NA

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

USART2

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

ADC0

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[15:8], ACMP1_O

NA

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[0]

AES

Full configuration

NA

GPIO

53 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 18

EFM32G Data Sheet

System Overview

3.2.6 EFM32G280

The features of the EFM32G280 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.6. EFM32G280 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

WDOG

PRS

NA

EBI

EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,

EBI_CS[3:0], EBI_AD[15:0]

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

U0_TX, U0_RX

USART0

USART1

USART2

UART0

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

Full configuration

ADC0

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0]

AES

Full configuration

NA

GPIO

86 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 19

EFM32G Data Sheet

System Overview

3.2.7 EFM32G290

The features of the EFM32G290 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.7. EFM32G290 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

WDOG

PRS

NA

EBI

EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,

EBI_CS[3:0], EBI_AD[15:0]

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

U0_TX, U0_RX

USART0

USART1

USART2

UART0

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

Full configuration

ADC0

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0]

AES

Full configuration

NA

GPIO

90 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 20

EFM32G Data Sheet

System Overview

3.2.8 EFM32G840

The features of the EFM32G840 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.8. EFM32G840 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

Full configuration

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

Full configuration

NA

DMA

Full configuration

NA

RMU

Full configuration

NA

EMU

Full configuration

NA

CMU

Full configuration

CMU_OUT0, CMU_OUT1

NA

WDOG

PRS

Full configuration

NA

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

USART2

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

ADC0

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:4], ACMP0_O

ACMP1_CH[7:4], ACMP1_O

NA

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0]

AES

Full configuration

NA

GPIO

56 pins

Available pins are shown in Table 4.3 (p. 57)

LCD

Full configuration

LCD_SEG[23:0], LCD_COM[3:0], LCD_BCAP_P,

LCD_BCAP_N, LCD_BEXT

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Rev. 2.10 | 21

EFM32G Data Sheet

System Overview

3.2.9 EFM32G842

The features of the EFM32G842 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.9. EFM32G842 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

Full configuration

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

Full configuration

NA

DMA

Full configuration

NA

RMU

Full configuration

NA

EMU

Full configuration

NA

CMU

Full configuration

CMU_OUT0, CMU_OUT1

NA

WDOG

PRS

Full configuration

NA

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

USART0

USART1

USART2

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

ADC0

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[3:0], ACMP0_O

ACMP1_CH[7:4], ACMP1_O

NA

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[0]

AES

Full configuration

NA

GPIO

53 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 22

EFM32G Data Sheet

System Overview

3.2.10 EFM32G880

The features of the EFM32G880 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.10. EFM32G880 Configuration Summary

Module

Cortex-M3

DBG

Module

Full configuration

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

WDOG

PRS

NA

EBI

EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,

EBI_CS[3:0], EBI_AD[15:0]

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

U0_TX, U0_RX

USART0

USART1

USART2

UART0

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

Full configuration

ADC0

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0]

AES

Full configuration

NA

GPIO

86 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 23

EFM32G Data Sheet

System Overview

Module

LCD

Full configuration

LCD_SEG[39:0], LCD_COM[3:0], LCD_BCAP_P,

LCD_BCAP_N, LCD_BEXT

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Rev. 2.10 | 24

EFM32G Data Sheet

System Overview

3.2.11 EFM32G890

The features of the EFM32G890 is a subset of the feature set described in the EFM32G Reference Manual. The following table de-

scribes device specific implementation of the features.

Table 3.11. EFM32G890 Configuration Summary

Module

Cortex-M3

DBG

Configuration

Pin Connections

Full configuration

NA

DBG_SWCLK, DBG_SWDIO, DBG_SWO

MSC

NA

DMA

NA

RMU

NA

EMU

NA

CMU

CMU_OUT0, CMU_OUT1

WDOG

PRS

NA

EBI

EBI_ARDY, EBI_ALE, EBI_WEn, EBI_REn,

EBI_CS[3:0], EBI_AD[15:0]

I2C0

Full configuration

I2C0_SDA, I2C0_SCL

US0_TX, US0_RX. US0_CLK, US0_CS

US1_TX, US1_RX, US1_CLK, US1_CS

US2_TX, US2_RX, US2_CLK, US2_CS

U0_TX, U0_RX

USART0

USART1

USART2

UART0

LEUART0

LEUART1

TIMER0

TIMER1

TIMER2

RTC

Full configuration with IrDA

Full configuration

LEU0_TX, LEU0_RX

LEU1_TX, LEU1_RX

TIM0_CC[2:0], TIM0_CDTI[2:0]

TIM1_CC[2:0]

Full configuration

Full configuration with DTI

Full configuration

TIM2_CC[2:0]

Full configuration

NA

LETIMER0

PCNT0

PCNT1

PCNT2

ACMP0

ACMP1

VCMP

Full configuration

LET0_O[1:0]

Full configuration, 8-bit count register

Full configuration

PCNT0_S[1:0]

PCNT1_S[1:0]

PCNT2_S[1:0]

ACMP0_CH[7:0], ACMP0_O

ACMP1_CH[7:0], ACMP1_O

NA

Full configuration

ADC0

Full configuration

ADC0_CH[7:0]

DAC0

Full configuration

DAC0_OUT[1:0]

AES

Full configuration

NA

GPIO

90 pins

Available pins are shown in Table 4.3 (p. 57)

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Rev. 2.10 | 25

EFM32G Data Sheet

System Overview

Module

Configuration

Pin Connections

LCD

Full configuration

LCD_SEG[39:0], LCD_COM[7:0], LCD_BCAP_P,

LCD_BCAP_N, LCD_BEXT

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Rev. 2.10 | 26

EFM32G Data Sheet

System Overview

3.3 Memory Map

The EFM32G memory map is shown in the figure below. RAM and Flash sizes are for the largest memory configuration.

Figure 3.2. System Address Space with Core and Code Space Listing

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Rev. 2.10 | 27

EFM32G Data Sheet

System Overview

Figure 3.3. System Address Space with Peripheral Listing

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Rev. 2.10 | 28

EFM32G Data Sheet

Electrical Characteristics

4. Electrical Characteristics

4.1 Test Conditions

4.1.1 Typical Values

The typical data are based on T_AMB=25°C and V_DD=3.0 V, as defined in Table 4.2 General Operating Conditions on page 29, unless

otherwise specified.

4.1.2 Minimum and Maximum Values

The minimum and maximum values represent the worst conditions of ambient temperature, supply voltage and frequencies, as defined

in Table 4.2 General Operating Conditions on page 29, unless otherwise specified.

4.2 Absolute Maximum Ratings

The absolute maximum ratings are stress ratings, and functional operation under such conditions are not guaranteed. Stress beyond

the limits specified in the following table may affect the device reliability or cause permanent damage to the device. Functional operat-

ing conditions are given in Table 4.2 General Operating Conditions on page 29.

Table 4.1. Absolute Maximum Ratings

Parameter

Symbol

T_STG

T_S

Test Condition

Min

-40

—

Typ

—

Max

150

260

Unit

°C

Storage temperature range

Maximum soldering temperature

Latest IPC/JEDEC J-

STD-020 Standard

—

°C

External main supply voltage

Voltage on any I/O pin

V_DDMAX

0

-0.3

—

3.8

V_DD+0.3

100

V

V_IOPIN

Current per I/O pin (sink)

Current per I/O pin (source)

I_{IOMAX_SINK}

I_{IOMAX_SOURCE}

mA

—

-100

4.3 General Operating Conditions

Table 4.2. General Operating Conditions

Parameter

Symbol

T_AMB

V_DDOP

f_APB

Min

-40

1.98

—

Typ

—

Max

85

Unit

Ambient temperature range

Operating supply voltage

Internal APB clock frequency

Internal AHB clock frequency

°C

V

—

3.8

32

—

MHz

f_AHB

—

32

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Rev. 2.10 | 29

EFM32G Data Sheet

Electrical Characteristics

4.4 Current Consumption

Table 4.3. Current Consumption

Test Condition

Parameter

Symbol

Min

Typ

Max

Unit

32 MHz HFXO, all peripheral clocks disabled,

V_DD= 3.0 V

—

180

—

µA/MHz

28 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

—

181

183

185

186

191

220

45

206

207

211

215

218

—

µA/MHz

μA

21 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

EM0 current. No prescaling.

Running prime number cal-

culation code from Flash.

(Production test condition =

14 MHz)

14 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

I_EM0

11 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

6.6 MHz HFRCO, all peripheral clocks disa-

bled, V_DD= 3.0 V

1.2 MHz HFRCO, all peripheral clocks disa-

bled, V_DD= 3.0 V

32 MHz HFXO, all peripheral clocks disabled,

V_DD= 3.0 V

—

28 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

47

62

21 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

48

64

14 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

50

69

EM1 current (Production test

condition = 14 MHz)

I_EM1

11 MHz HFRCO, all peripheral clocks disabled,

V_DD= 3.0 V

51

72

6.6 MHz HFRCO, all peripheral clocks disa-

bled, V_DD= 3.0 V

56

83

1.2 MHz HFRCO. all peripheral clocks disa-

bled, V_DD= 3.0 V

103

0.9

3.0

—

EM2 current with RTC prescaled to 1 Hz,

32.768 kHz LFRCO, V_DD= 3.0 V, T_AMB=25 ºC

1.5

6.0

I_EM2

EM2 current

EM2 current with RTC prescaled to 1 Hz,

µA

32.768 kHz LFRCO, V_DD= 3.0 V, T_AMB=85 ºC

V_DD= 3.0 V, T_AMB=25 ºC

V_DD= 3.0 V, T_AMB=85 ºC

V_DD= 3.0 V, T_AMB=25 ºC

V_DD= 3.0 V, T_AMB=85 ºC

—

0.59

2.75

0.02

0.25

1.0

5.8

µA

I_EM3

EM3 current

EM4 current

0.045

0.7

I_EM4

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Rev. 2.10 | 30

EFM32G Data Sheet

Electrical Characteristics

4.4.1 EM0 Current Consumption

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

Vdd=2.0V

Vdd=2.2V

Vdd=2.4V

Vdd=2.6V

Vdd=2.8V

Vdd=3.0V

Vdd=3.2V

Vdd=3.4V

Vdd=3.6V

Vdd=3.8V

85.0°C

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.1. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 28

MHz

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Rev. 2.10 | 31

EFM32G Data Sheet

Electrical Characteristics

4.0

3.9

3.8

3.7

3.6

3.5

4.0

3.9

3.8

3.7

3.6

3.5

85.0°C

65.0°C

Vdd=2.0V

Vdd=2.2V

Vdd=2.4V

Vdd=2.6V

Vdd=2.8V

Vdd=3.0V

Vdd=3.2V

Vdd=3.4V

Vdd=3.6V

Vdd=3.8V

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.2. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 21

MHz

2.75

2.70

2.65

2.60

2.55

2.50

2.45

2.40

2.35

2.75

2.70

2.65

2.60

2.55

2.50

2.45

2.40

2.35

Vdd=2.0V

Vdd=2.2V

Vdd=2.4V

Vdd=2.6V

Vdd=2.8V

Vdd=3.0V

Vdd=3.2V

Vdd=3.4V

Vdd=3.6V

Vdd=3.8V

85.0°C

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.3. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 14

MHz

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Rev. 2.10 | 32

EFM32G Data Sheet

Electrical Characteristics

2.20

2.15

2.10

2.05

2.00

1.95

1.90

1.85

2.20

2.15

2.10

2.05

2.00

1.95

1.90

1.85

Vdd=2.0V

Vdd=2.2V

Vdd=2.4V

Vdd=2.6V

Vdd=2.8V

Vdd=3.0V

Vdd=3.2V

Vdd=3.4V

Vdd=3.6V

Vdd=3.8V

85.0°C

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.4. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 11

MHz

1.45

1.40

1.35

1.30

1.25

1.20

1.45

1.40

1.35

1.30

1.25

1.20

Vdd=2.0V

Vdd=2.2V

Vdd=2.4V

Vdd=2.6V

Vdd=2.8V

Vdd=3.0V

Vdd=3.2V

Vdd=3.4V

Vdd=3.6V

Vdd=3.8V

85.0°C

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.5. EM0 Current consumption while executing prime number calculation code from flash with HFRCO running at 7

MHz

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Rev. 2.10 | 33

EFM32G Data Sheet

Electrical Characteristics

4.4.2 EM1 Current Consumption

1.40

1.35

1.30

1.25

1.20

1.15

1.40

1.35

1.30

1.25

1.20

1.15

Vdd=2.0V

Vdd=2.4V

Vdd=2.8V

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

85.0°C

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.6. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 28 MHz

1.08

Vdd=2.0V

Vdd=2.4V

85.0°C

Vdd=2.8V

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

65.0°C

1.04

45.0°C

1.02

1.00

0.98

0.96

0.94

0.92

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.7. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 21 MHz

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Rev. 2.10 | 34

EFM32G Data Sheet

Electrical Characteristics

0.76

0.74

0.72

0.70

0.68

0.66

0.64

0.76

0.74

0.72

0.70

0.68

0.66

0.64

Vdd=2.0V

Vdd=2.4V

Vdd=2.8V

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

85.0°C

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.8. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 14 MHz

0.62

0.60

0.58

0.56

0.54

0.52

0.62

85.0°C

Vdd=2.0V

Vdd=2.4V

Vdd=2.8V

Vdd=3.0V

Vdd=3.4V

0.60

65.0°C

Vdd=3.8V

45.0°C

0.58

0.56

0.54

0.52

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.9. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 11 MHz

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Rev. 2.10 | 35

EFM32G Data Sheet

Electrical Characteristics

0.44

0.43

0.42

0.41

0.40

0.39

0.38

0.37

0.36

0.44

0.43

0.42

0.41

0.40

0.39

0.38

0.37

0.36

85.0°C

Vdd=2.0V

Vdd=2.4V

Vdd=2.8V

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

65.0°C

45.0°C

25.0°C

5.0°C

-15.0°C

-40.0°C

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.10. EM1 Current consumption with all peripheral clocks disabled and HFRCO running at 7 MHz

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Rev. 2.10 | 36

EFM32G Data Sheet

Electrical Characteristics

4.4.3 EM2 Current Consumption

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

-40.0°C

-15.0°C

5.0°C

Vdd=1.8V

Vdd=2.2V

Vdd=2.6V

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

25.0°C

45.0°C

65.0°C

85.0°C

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.11. EM2 Current Consumption, RTC prescaled to 1 kHz, 32.768 kHz LFRCO

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Rev. 2.10 | 37

EFM32G Data Sheet

Electrical Characteristics

4.4.4 EM3 Current Consumption

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-40.0°C

-15.0°C

5.0°C

Vdd=1.8V

Vdd=2.2V

Vdd=2.6V

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

25.0°C

45.0°C

65.0°C

85.0°C

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.12. EM3 Current Consumption

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EFM32G Data Sheet

Electrical Characteristics

4.4.5 EM4 Current Consumption

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

-40.0°C

Vdd=1.8V

Vdd=2.2V

Vdd=2.6V

Vdd=3.0V

Vdd=3.4V

Vdd=3.8V

-15.0°C

5.0°C

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0.00

25.0°C

45.0°C

65.0°C

85.0°C

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd [V]

Temperature [°C]

Figure 4.13. EM4 Current Consumption

4.5 Transition between Energy Modes

The transition times are measured from the trigger to the first clock edge in the CPU.

Table 4.4. Energy Modes Transitions

Parameter

Symbol

Min

Typ

Max

Unit

Transition time from EM1 to EM0

t_EM10

—

0

—

HFCORECLK

cycles

Transition time from EM2 to EM0

Transition time from EM3 to EM0

Transition time from EM4 to EM0

t_EM20

t_EM30

t_EM40

—

2

—

µs

163

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Rev. 2.10 | 39

EFM32G Data Sheet

Electrical Characteristics

4.6 Power Management

The EFM32G requires the AVDD_x, VDD_DREG and IOVDD_x pins to be connected together (with optional filter) at the PCB level. For

practical schematic recommendations, please see the application note, "AN0002 EFM32 Hardware Design Considerations".

Table 4.5. Power Management

Parameter

Symbol

Test Condition

Min

1.74

—

Typ

—

Max

1.96

—

Unit

V

BOD threshold on falling external sup- V_BODextthr-EM0

ply voltage

EM1

—

V

EM2

—

V

BOD threshold on rising external sup- V_BODextthr+EM0

ply voltage

1.85

V

Power-on Reset (POR) threshold on

rising external supply voltage

V_PORthr+

—

1.98

—

V

Delay from reset is released until pro- t_RESETdly

gram execution starts

Applies to Power-on Re-

set, Brown-out Reset and

pin reset.

163

µs

negative pulse length to ensure com-

plete reset of device

t_RESET

50

—

1

—

ns

Voltage regulator decoupling capaci-

tor.

C_DECOUPLEX5R capacitor recom-

mended. Apply between

DECOUPLE pin and

µF

GROUND

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Rev. 2.10 | 40

EFM32G Data Sheet

Electrical Characteristics

4.7 Flash

Table 4.6. Flash

Parameter

Symbol

Test Condition

Min

20000

10000

10

Typ

—

Max

—

Unit

cycles

h

Flash erase cycles before failure

EC_FLASH

T_AMB<150 ºC

—

RET_FLASHT_AMB<85 ºC

T_AMB<70 ºC

t_{W_PROG}

—

years

µs

Flash data retention

20

—

Word (32-bit) programming time

Page erase time²

20

—

t_{P_ERASE}

20.7

22.0

24.8

ms

Device erase time³

Erase current

t_{D_ERASE}

41.8

—

45.0

—

49.2

7¹

ms

mA

V

I_ERASE

7¹

Write current

I_WRITE

—

Supply voltage during flash erase and V_FLASH

write

1.98

—

3.8

Note:

1. Measured at 25 °C.

2. From setting ERASEPAGE bit in MSC_WRITECMD to 1 to reading 1 in ERASE bit in MSC_IF. Internal setup and hold times for

flash control signals are included.

3. From setting DEVICEERASE bit in AAP_CMD to 1 to reading 0 in ERASEBUSY bit in AAP_STATUS. Internal setup and hold

times for flash control signals are included.

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Rev. 2.10 | 41

EFM32G Data Sheet

Electrical Characteristics

4.8 General Purpose Input Output

Table 4.7. GPIO

Parameter

Symbol Test Condition

V_IOIL

Min

Typ

Max

0.30×V_DD

—

Unit

1

Input low voltage

—

V

1

Input high voltage

V_IOIH

—

V

0.70×V_DD

Sourcing 0.1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

—

0.80×V_DD

—

Sourcing 0.1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

—

0.90×V_DD

V

Sourcing 1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

0.85×V_DD

Sourcing 1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

0.90×V_DD

Output high voltage (Production

test condition = 3.0 V, DRIVE-

MODE = STANDARD)

V_IOOH

Sourcing 6 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

0.75×V_DD

0.85×V_DD

0.60×V_DD

0.80×V_DD

—

Sourcing 6 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

Sourcing 20 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

Sourcing 20 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

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Rev. 2.10 | 42

EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol Test Condition

Sinking 0.1 mA, V_DD=1.98 V,

Min

Typ

Max

Unit

—

0.20×V_DD

—

V

GPIO_Px_CTRL DRIVEMODE

= LOWEST

Sinking 0.1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOWEST

—

0.10×V_DD

—

V

Sinking 1 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

0.10×V_DD

—

Sinking 1 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= LOW

0.05×V_DD

—

V

Output low voltage (Production

test condition = 3.0 V, DRIVE-

MODE = STANDARD)

V_IOOL

Sinking 6 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

—

0.30×V_DD

0.20×V_DD

0.35×V_DD

0.25×V_DD

±40

V

Sinking 6 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= STANDARD

V

Sinking 20 mA, V_DD=1.98 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

—

V

Sinking 20 mA, V_DD=3.0 V,

GPIO_Px_CTRL DRIVEMODE

= HIGH

—

V

Input leakage current

I_IOLEAK

High Impedance IO connected

to GROUND or V_DD

±0.1

nA

I/O pin pull-up resistor

R_PU

—

10

40

—

50

kΩ

Ω

I/O pin pull-down resistor

Internal ESD series resistor

R_PD

R_IOESD

200

—

Pulse width of pulses to be re- t_IOGLITCH

moved by the glitch suppres-

sion filter

ns

GPIO_Px_CTRL DRIVEMODE

= LOWEST and load capaci-

tance C_L=12.5-25pF.

20+0.1C_L

0.1×V_DD

—

250

—

ns

V

t_IOOF

Output fall time

GPIO_Px_CTRL DRIVEMODE

= LOW and load capacitance

C_L=350-600pF

I/O pin hysteresis (V_IOTHR+

-

V_IOHYSTV_DD= 1.98 - 3.8 V

V_IOTHR-

)

Note:

1. If the GPIO input voltage is between 0.3×V_DDand 0.7×V_DD, the current consumption will increase.

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Rev. 2.10 | 43

EFM32G Data Sheet

Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0.20

0.15

0.10

0.05

0.00

20

15

10

5

-40°C

25°C

85°C

-40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Low-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

5

4

3

2

1

45

40

35

30

25

20

15

10

5

-40°C

25°C

85°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

Low-Level Output Voltage [V]

Figure 4.14. Typical Low-Level Output Current, 2V Supply Voltage

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Rev. 2.10 | 44

EFM32G Data Sheet

Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0.00

–0.05

–0.10

–0.15

–0.20

0.0

–0.5

–1.0

–1.5

–2.0

–2.5

-40°C

25°C

85°C

-40°C

25°C

85°C

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

High-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

0

-40°C

25°C

85°C

-40°C

25°C

85°C

–10

–5

–20

–30

–40

–50

–10

–15

–20

0.0

0.5

1.0

1.5

2.0

0.0

0.5

1.0

1.5

2.0

High-Level Output Voltage [V]

Figure 4.15. Typical High-Level Output Current, 2V Supply Voltage

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Rev. 2.10 | 45

EFM32G Data Sheet

Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0.5

0.4

0.3

0.2

0.1

0.0

10

8

6

4

2

-40°C

25°C

85°C

-40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Low-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

40

35

30

25

20

15

10

5

50

40

30

20

10

0

-40°C

25°C

85°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Low-Level Output Voltage [V]

Figure 4.16. Typical Low-Level Output Current, 3V Supply Voltage

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EFM32G Data Sheet

Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

0

-40°C

25°C

85°C

-40°C

25°C

85°C

–1

–2

–3

–4

–5

–6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

High-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

0

-40°C

25°C

85°C

-40°C

25°C

85°C

–10

–20

–30

–40

–50

–20

–30

–40

–50

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

High-Level Output Voltage [V]

Figure 4.17. Typical High-Level Output Current, 3V Supply Voltage

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Rev. 2.10 | 47

EFM32G Data Sheet

Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

14

12

10

8

6

4

2

-40°C

25°C

85°C

-40°C

25°C

85°C

0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Low-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

50

40

30

20

10

0

50

40

30

20

10

0

-40°C

25°C

85°C

25°C

85°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

Low-Level Output Voltage [V]

Figure 4.18. Typical Low-Level Output Current, 3.8V Supply Voltage

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Rev. 2.10 | 48

EFM32G Data Sheet

Electrical Characteristics

GPIO_Px_CTRL DRIVEMODE = LOWEST

GPIO_Px_CTRL DRIVEMODE = LOW

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

0

-40°C

25°C

85°C

-40°C

25°C

85°C

–1

–2

–3

–4

–5

–6

–7

–8

–9

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

High-Level Output Voltage [V]

GPIO_Px_CTRL DRIVEMODE = STANDARD

GPIO_Px_CTRL DRIVEMODE = HIGH

0

-40°C

25°C

85°C

-40°C

25°C

85°C

–10

–20

–30

–40

–50

–20

–30

–40

–50

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

High-Level Output Voltage [V]

Figure 4.19. Typical High-Level Output Current, 3.8V Supply Voltage

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Rev. 2.10 | 49

EFM32G Data Sheet

Electrical Characteristics

4.9 Oscillators

4.9.1 LFXO

Table 4.8. LFXO

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Supported nominal crystal fre-

quency

f_LFXO

—

32.768

—

kHz

Supported crystal equivalent ser- ESR_LFXO

ies resistance (ESR)

—

30

—

120

25

—

kOhm

pF

X¹

—

Supported crystal external load

range

C_LFXOL

Current consumption for core and I_LFXO

buffer after startup

ESR=30 kΩ, C_L=10 pF, LFXO-

BOOST in CMU_CTRL is 1

190

400

nA

Start-up time

t_LFXO

ESR=30 kΩ, C_L=10 pF, 40% -

60% duty cycle has been

reached, LFXOBOOST in

CMU_CTRL is 1

—

ms

Note:

1. See Minimum Load Capacitance (C_LFXOL) Requirement For Safe Crystal Startup in Configurator in Simplicity Studio.

For safe startup of a given crystal, the Configurator tool in Simplicity Studio contains a tool to help users configure both load capaci-

tance and software settings for using the LFXO. For details regarding the crystal configuration, the reader is referred to application note

"AN0016 EFM32 Oscillator Design Consideration".

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EFM32G Data Sheet

Electrical Characteristics

4.9.2 HFXO

Parameter

Table 4.9. HFXO

Symbol

Test Condition

Min

Typ

Max

Unit

Supported nominal crystal Fre-

quency

f_HFXO

4

—

32

MHz

Crystal frequency 32 MHz

Crystal frequency 4 MHz

—

20

30

400

—

60

1500

—

Ω

Supported crystal equivalent ser-

ies resistance (ESR)

ESR_HFXO

The transconductance of the

HFXO input transistor at crystal

startup

g_mHFXO

HFXOBOOST in CMU_CTRL

equals 0b11

mS

Supported crystal external load

range

C_HFXOL

5

—

25

—

pF

µA

4 MHz: ESR=400 Ω, C_L=20 pF,

HFXOBOOST in CMU_CTRL

equals 0b11

—

85

Current consumption for HFXO

after startup

I_HFXO

32 MHz: ESR=30 Ω, C_L=10 pF,

HFXOBOOST in CMU_CTRL

equals 0b11

—

1

165

400

—

4

µA

µs

ns

Startup time

32 MHz: ESR=30 Ω, C_L=10 pF,

HFXOBOOST in CMU_CTRL

equals 0b11

t_HFXO

Pulse width removed by glitch de-

tector

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Rev. 2.10 | 51

EFM32G Data Sheet

Electrical Characteristics

4.9.3 LFRCO

Parameter

Table 4.10. LFRCO

Test Condition

Symbol

Min

Typ

Max

Unit

Oscillation frequency, V_DD= 3.0 f_LFRCO

V, T_AMB=25°C

31.29

32.768

34.24

kHz

Startup time not including soft- t_LFRCO

ware calibration

—

150

—

µs

Current consumption

I_LFRCO

—

190

±0.02

±15

—

nA

%/°C

%/V

%

Temperature coefficient

Supply voltage coefficient

TC_LFRCO

VC_LFRCO

Frequency step for LSB change TUNESTEP_LFRCO

in TUNING value

1.5

Figure 4.20. Calibrated LFRCO Frequency vs Temperature and Supply Voltage

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EFM32G Data Sheet

Electrical Characteristics

4.9.4 HFRCO

Parameter

Table 4.11. HFRCO

Symbol

Test Condition

Min

Typ

28

Max

Unit

MHz

28 MHz frequency band

21 MHz frequency band

14 MHz frequency band

11 MHz frequency band

7 MHz frequency band

27.16

20.37

13.58

10.67

6.402

28.84

21.63

14.42

11.33

6.798

21

14

Oscillation frequency, V_DD= 3.0

V, T_AMB=25 ºC

f_HFRCO

11

6.6¹

1.2²

0.6

25

1 MHz frequency band

1.164

1.236

MHz

After start-up, f_HFRCO= 14 MHz

After band switch

—

Cycles

µA

t_{HFRCO_settling}

Settling time

f_HFRCO= 28 MHz

f_HFRCO= 21 MHz

f_HFRCO= 14 MHz

f_HFRCO= 11 MHz

f_HFRCO= 6.6 MHz

f_HFRCO= 1.2 MHz

f_HFRCO= 14 MHz

—

158

125

99

190

155

120

110

90

—

µA

—

µA

Current consumption (Produc-

tion test condition = 14 MHz)

I_HFRCO

—

88

µA

—

72

µA

—

24

32

µA

Duty cycle

DC_HFRCO

48.5

—

50

51

%

0.3³

Frequency step for LSB change TUNESTEP_HFRCO

in TUNING value

—

%

Note:

1. For devices with prod. rev. < 19, Typ = 7 MHz and Min/Max values not applicable.

2. For devices with prod. rev. < 19, Typ = 1 MHz and Min/Max values not applicable.

3. The TUNING field in the CMU_HFRCOCTRL register may be used to adjust the HFRCO frequency. There is enough adjustment

range to ensure that the frequency bands above 7 MHz will always have some overlap across supply voltage and temperature.

By using a stable frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and

the frequency band to maintain the HFRCO frequency at any arbitrary value between 7 MHz and 28 MHz across operating condi-

tions.

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Rev. 2.10 | 53

EFM32G Data Sheet

Electrical Characteristics

Figure 4.21. Calibrated HFRCO 1 MHz Band Frequency vs Supply Voltage and Temperature

Figure 4.22. Calibrated HFRCO 7 MHz Band Frequency vs Supply Voltage and Temperature

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Rev. 2.10 | 54

EFM32G Data Sheet

Electrical Characteristics

Figure 4.23. Calibrated HFRCO 11 MHz Band Frequency vs Supply Voltage and Temperature

Figure 4.24. Calibrated HFRCO 14 MHz Band Frequency vs Supply Voltage and Temperature

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Rev. 2.10 | 55

EFM32G Data Sheet

Electrical Characteristics

Figure 4.25. Calibrated HFRCO 21 MHz Band Frequency vs Supply Voltage and Temperature

Figure 4.26. Calibrated HFRCO 28 MHz Band Frequency vs Supply Voltage and Temperature

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Rev. 2.10 | 56

EFM32G Data Sheet

Electrical Characteristics

4.9.5 AUXHFRCO

Parameter

Table 4.12. AUXHFRCO

Test Condition

Symbol

Min

Typ

Max

Unit

Oscillation frequency, V_DD= 3.0 f_AUXHFRCO

V, T_AMB=25 ºC

14 MHz frequency band

13.580

14.0

14.420

MHz

Settling time after start-up

Duty cycle

t_{AUXHFRCO_settling}

DC_AUXHFRCO

f_AUXHFRCO= 14 MHz

—

48.5

—

0.6

50

—

51

—

Cycles

%

0.3¹

Frequency step for LSB change TUNESTEP_AUXHFRCO

in TUNING value

%

Note:

1. The TUNING field in the CMU_AUXHFRCOCTRL register may be used to adjust the AUXHFRCO frequency. By using a stable

frequency reference such as the LFXO or HFXO, a firmware calibration routine can vary the TUNING bits and the frequency band

to maintain the AUXHFRCO frequency at any arbitrary value in the 14 MHz range across operating conditions.

4.9.6 ULFRCO

Table 4.13. ULFRCO

Parameter

Symbol

Test Condition

Min

0.7

—

Typ

—

Max

1.75

—

Unit

kHz

Oscillation frequency

Temperature coefficient

Supply voltage coefficient

f_ULFRCO

25 °C, 3 V

TC_ULFRCO

VC_ULFRCO

0.05

-18.2

%/°C

%/V

—

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EFM32G Data Sheet

Electrical Characteristics

4.10 Analog Digital Converter (ADC)

Table 4.14. ADC

Parameter

Symbol

Test Condition

Single-ended

Differential

Min

0

Typ

—

Max

V_REF

V_REF/2

V_DD

Unit

V

V_ADCIN

Input voltage range

-V_REF/2

1.25

—

V

Input range of external refer-

ence voltage, single-ended and

differential

V_ADCREFIN

—

V

Input range of external negative V_{ADCREFIN_CH7}

reference voltage on channel 7

See V_ADCREFIN

0

—

V_DD- 1.1

V

Input range of external positive V_{ADCREFIN_CH6}

reference voltage on channel 6

See V_ADCREFIN

0.625

V_DD

Common mode input range

Input current

V_ADCCMIN

I_ADCIN

0

—

<100

65

V_DD

—

V

2 pF sampling capacitors

—

nA

dB

Analog input common mode re- CMRR_ADC

jection ratio

—

735¹

760¹

346¹

354¹

52¹

1 Msamples/s, 12 bit, external

reference, ADC_CLK = 13 MHz,

BIASPROG = 0xF4B

—

µA

1 Msamples/s, 12 bit, internal

1.25V reference, ADC_CLK =

13 MHz, BIASPROG = 0xF4B

500 Ksamples/s, 12 bit, external

reference, ADC_CLK = 7 MHz,

BIASPROG = 0x747

500 Ksamples/s, 12 bit, internal

1.25V reference, ADC_CLK = 7

MHz, BIASPROG = 0x747

I_ADC

Average active current

10 kSamples/s, 12 bit, internal

1.25 V reference, WARMUP =

00b, ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

50¹

54¹

10 kSamples/s, 12 bit, internal

1.25 V reference, WARMUP =

01b, ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

—

µA

10 kSamples/s, 12 bit, internal

1.25 V reference, WARMUP =

10b, ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

Input capacitance

C_ADCIN

—

1

2

—

pF

MΩ

kΩ

fF

Input ON resistance

Input RC filter resistance

R_ADCIN

R_ADCFILT

C_ADCFILT

—

10

250

Input RC filter/decoupling ca-

pacitance

Input bias current

I_ADCBIASIN

VSS < VIN < VDD

-40

—

40

nA

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

VSS < VIN < VDD

BIASPROG=0x747

BIASPROG=0xF4B

6 bit

Min

-40

—

Typ

—

Max

40

7

Unit

nA

Input offset current

ADC Clock Frequency

I_ADCOFFSETIN

f_ADCCLK

—

MHz

—

13

—

7

—

ADCCLK

Cycles

8 bit

11

13

1

—

ADCCLK

Cycles

t_ADCCONV

Conversion time

Acquisition time

12 bit

ADCCLK

Cycles

t_ADCACQ

Programmable

256

—

ADCCLK

Cycles

Required acquisition time for

VDD/3 reference

t_ADCACQVDD3

2

µs

Startup time of reference gener- t_ADCSTART

ator and ADC core

NORMAL mode

—

5

1

—

µs

KEEPADCWARM mode

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal-to-Noise Ratio (SNR)

SNR_ADC

1 MSamples/s, 12 bit, single-

ended, internal 1.25 V refer-

ence, ADC_CLK = 13 MHz,

BIASPROG = 0xF4B

—

59

—

dB

1 MSamples/s, 12 bit, single-

ended, internal 2.5 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

—

63

67

63

66

—

dB

1 MSamples/s, 12 bit, single-

ended, V_DDreference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, internal 1.25 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, internal 2.5 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, 5 V reference, ADC_CLK

=13 MHz, BIASPROG = 0xF4B

—

63

—

66

69

70

—

dB

1 MSamples/s, 12 bit, differen-

tial, V_DDreference, ADC_CLK=

13 MHz, BIASPROG =0xF4B

1 MSamples/s, 12 bit, differen-

tial, 2xV_DDreference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

200 kSamples/s, 12 bit, single-

ended, internal 1.25 V refer-

ence, ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

—

62

63

67

63

66

—

dB

200 kSamples/s, 12 bit, single-

ended, internal 2.5 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, single-

ended, V_DDreference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, internal 1.25 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, internal 2.5 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, 5 V reference, ADC_CLK =

7 MHz, BIASPROG = 0x747

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal-to-Noise Ratio (SNR)

SNR_ADC

200 kSamples/s, 12 bit, differen-

tial, V_DDreference,ADC_CLK =

7 MHz, BIASPROG = 0x747

63

69

—

dB

200 kSamples/s, 12 bit, differen-

tial, 2xV_DDreference,ADC_CLK

= 7 MHz, BIASPROG = 0x747

—

70

—

dB

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal-to-Noise And Distortion

Ratio (SINAD)

SINAD_ADC

1 MSamples/s, 12 bit, single-

ended, internal 1.25 V refer-

ence, ADC_CLK = 13 MHz,

BIASPROG = 0xF4B

—

58

—

dB

1 MSamples/s, 12 bit, single-

ended, internal 2.5 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

—

62

66

63

66

—

dB

1 MSamples/s, 12 bit, single-

ended, V_DDreference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, internal 1.25 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, internal 2.5 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, 5 V reference, ADC_CLK =

13 MHz, BIASPROG = 0xF4B

—

62

—

66

68

—

dB

1 MSamples/s, 12 bit, differen-

tial, V_DDreference, ADC_CLK =

13 MHz, BIASPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, 2xV_DDreference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

200 kSamples/s, 12 bit, single-

ended, internal 1.25 V refer-

ence, ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

—

61

62

66

63

66

—

dB

200 kSamples/s, 12 bit, single-

ended, internal 2.5 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, single-

ended, VDD reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, internal 1.25 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, internal 2.5 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, 5V reference, ADC_CLK= 7

MHz, BIASPROG = 0x747

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Signal-to-Noise And Distortion

Ratio (SINAD)

SINAD_ADC

200 kSamples/s, 12 bit, differen-

tial, V_DDreference, ADC_CLK =

7 MHz, BIASPROG = 0x747

62

68

—

dB

200 kSamples/s, 12 bit, differen-

tial, 2xV_DDreference,

—

69

—

dB

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Spurious-Free Dynamic Range SFDR_ADC

(SFDR)

1 MSamples/s, 12 bit, single-

ended, internal 1.25 V refer-

ence, ADC_CLK = 13 MHz,

BIASPROG = 0xF4B

—

75

—

dBc

1 MSamples/s, 12 bit, single-

ended, internal 2.5 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

—

76

78

77

—

dBc

1 MSamples/s, 12 bit, single-

ended, V_DDreference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, internal 1.25 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, internal 2.5 V reference,

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, V_DDreference, ADC_CLK=

13 MHz, BIASPROG = 0xF4B

—

76

79

—

dBc

1 MSamples/s, 12 bit, differen-

tial, 2xV_DDreference,

68

ADC_CLK = 13 MHz, BIA-

SPROG = 0xF4B

1 MSamples/s, 12 bit, differen-

tial, 5 V reference, ADC_CLK

=13 MHz, BIASPROG = 0xF4B

—

79

75

—

dBc

200 kSamples/s, 12 bit, single-

ended, internal 1.25 V refer-

ence, ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, single-

ended, internal 2.5 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

—

75

76

79

78

—

dBc

200 kSamples/s, 12 bit, single-

ended, V_DDreference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, internal 1.25 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, internal 2.5 V reference,

ADC_CLK = 7 MHz, BIA-

SPROG = 0x747

200 kSamples/s, 12 bit, differen-

tial, 5 V reference, ADC_CLK =

7 MHz, BIASPROG = 0x747

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

Spurious-Free Dynamic Range SFDR_ADC

(SFDR)

200 kSamples/s, 12 bit, differen-

tial, V_DDreference, ADC_CLK =

7 MHz, BIASPROG = 0x747

68

79

—

dBc

200 kSamples/s, 12 bit, differen-

tial, 2xV_DDreference,ADC_CLK

= 7 MHz, BIASPROG = 0x747

—

79

—

dBc

Offset voltage

V_ADCOFFSET

After calibration, single-ended

After calibration, differential

—

-4

—

0.3

—

4

mV

Thermometer output gradient

TGRAD_ADCTH

-1.92

-6.3

—

mV/°C

ADC Co-

des/°C

Differential non-linearity (DNL)

DNL_ADC

V_DD= 3.0 V, external 2.5 V ref-

erence

-1

±0.7

±1.2

4

LSB

Integral non-linearity (INL), End INL_ADC

point method

V_DD= 3.0 V, external 2.5 V ref-

erence

—

±3

LSB

Missing codes

Gain error drift

MC_ADC

GAIN_ED

—

3

LSB

%/°C

0.01²

0.00²

0.033³

0.03³

0.06³

1.25 V reference

2.5 V reference

1.25 V reference

2.5 V reference

%/°C

Offset error drift

OFFSET_ED

LSB/°C

0.00²

1.25

2.5

0.04³

1.3

VREF voltage

V_REF

1.25 V reference

2.5 V reference

1.2

2.4

V

2.6

VREF voltage drift

V_{REF_VDRIFT}

V_{REF_TDRIFT}

I_VREF

1.25 V reference

2.5 V reference, VDD > 2.5 V

1.25 V reference

2.5 V reference

-12.4

-24.6

-132

-231

—

2.9

18.2

35.2

677

1271

114

82

mV/V

µV/°C

µA

5.7

VREF temperature drift

VREF current consumption

272

545

67

1.25 V reference

2.5 V reference

—

55

µA

ADC and DAC VREF matching V_{REF_MATCH}

1.25 V reference

2.5 V reference

—

99.85

100.01

—

%

—

%

Note:

1. Includes required contribution from the voltage reference.

2. Typical numbers given by abs(Mean) / (85 - 25).

3. Max number given by (abs(Mean) + 3x stddev) / (85 - 25).

The integral non-linearity (INL) and differential non-linearity parameters are explained in the following figures.

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EFM32G Data Sheet

Electrical Characteristics

Digital output code

INL=|[(V_D-V_SS)/V_LSBIDEAL] - D| where 0 < D < 2^N

- 1

4095

4094

Actual ADC

tranfer function

before offset and

gain correction

4093

4092

Actual ADC

tranfer function

after offset and

gain correction

INL Error

(End Point INL)

Ideal transfer

curve

3

2

1

0

V_OFFSET

Analog Input

Figure 4.27. Integral Non-Linearity (INL)

Digital

output

code

DNL=|[(V_D+1- V_D)/V_LSBIDEAL] - 1| where 0 < D < 2^N

- 2

Full Scale Range

4095

4094

4093

4092

Example: Adjacent

input value V^D+1

corrresponds to digital

output code D+1

Actual transfer

function with one

missing code.

Example: Input value

_VDcorrresponds to

digital output code D

Code width =2 LSB

DNL=1 LSB

Ideal transfer

curve

0.5

LSB

Ideal spacing

between two

adjacent codes

V_LSBIDEAL=1 LSB

5

4

3

2

1

0

Ideal 50%

Transition Point

Ideal Code Center

Analog Input

Figure 4.28. Differential Non-Linearity (DNL)

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EFM32G Data Sheet

Electrical Characteristics

4.10.1 Typical Performance

1.25V Reference

2.5V Reference

2XVDDVSS Reference

5VDIFF Reference

VDD Reference

Figure 4.29. ADC Frequency Spectrum, VDD = 3V, Temp = 25°C

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EFM32G Data Sheet

Electrical Characteristics

1.25V Reference

2.5V Reference

2XVDDVSS Reference

5VDIFF Reference

VDD Reference

Figure 4.30. ADC Integral Linearity Error vs Code, VDD = 3V, Temp = 25°C

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EFM32G Data Sheet

Electrical Characteristics

1.25V Reference

2.5V Reference

2XVDDVSS Reference

5VDIFF Reference

VDD Reference

Figure 4.31. ADC Differential Linearity Error vs Code, VDD = 3V, Temp = 25°C

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EFM32G Data Sheet

Electrical Characteristics

Offset vs Supply Voltage, Temp = 25°C

Offset vs Temperature, VDD = 3V

5

4

3

2

1

0

2.0

1.5

Vref=1V25

Vref=2V5

VRef=1V25

VRef=2V5

Vref=2XVDDVSS

VRef=2XVDDVSS

VRef=5VDIFF

VRef=VDD

Vref=5VDIFF

Vref=VDD

1.0

0.5

–1

0.0

–2

–3

–4

–0.5

–1.0

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

–40

–15

5

25

45

65

85

Vdd (V)

Temp (C)

Figure 4.32. ADC Absolute Offset, Common Mode = VDD/2

Signal to Noise Ratio (SNR)

Spurious-Free Dynamic Range (SFDR)

71

70

69

68

67

66

65

64

63

79.4

79.2

79.0

78.8

78.6

78.4

78.2

78.0

2XVDDVSS

Vdd

1V25

Vdd

2V5

5VDIFF

2V5

2XVDDVSS

5VDIFF

85

1V25

–40

–15

5

25

45

65

85

–40

–15

5

25

45

65

Temperature [°C]

Figure 4.33. ADC Dynamic Performance vs Temperature for all ADC References, VDD = 3V

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EFM32G Data Sheet

Electrical Characteristics

4.11 Digital Analog Converter (DAC)

Table 4.15. DAC

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

VDD voltage reference, single-

ended

0

—

V_DD

V

V_DACOUT

Output voltage range

VDD voltage reference, differen-

tial

-V_DD

—

V_DD

V

Output common mode voltage

range

V_DACCM

0

V_DD

400¹

200¹

17¹

650¹

250¹

25¹

500 kSamples/s, 12 bit, internal

1.25 V reference, Continuous

Mode

—

µA

100 kSamples/s, 12 bit, internal

1.25 V reference, Sample/Hold

Mode

—

µA

I_DAC

Average active current

1 kSamples/s 12 bit, internal

1.25 V reference, Sample/Off

Mode

Sample rate

SR_DAC

—

2

—

2

500

1000

250

—

ksamples/s

kHz

Continuous Mode

Sample/Hold Mode

Sample/Off Mode

f_DAC

DAC clock frequency

kHz

Clock cycles per conversion

Conversion time

CYC_DACCONV

t_DACCONV

cycles

µs

—

5

—

Settling time

t_DACSETTLE

—

µs

500 kSamples/s, 12 bit, single-

ended, internal 1.25 V reference

58

—

dB

500 kSamples/s, 12 bit, single-

ended, internal 2.5 V reference

—

59

58

59

—

dB

500 kSamples/s, 12 bit, differen-

tial, internal 1.25 V reference

SNR_DAC

Signal-to-Noise Ratio (SNR)

500 kSamples/s, 12 bit, differen-

tial, internal 2.5 V reference

500 kSamples/s, 12 bit, differen-

tial, V_DDreference

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EFM32G Data Sheet

Electrical Characteristics

Parameter

Symbol

Test Condition

Min

Typ

Max

Unit

500 kSamples/s, 12 bit, single-

ended, internal 1.25 V reference

—

57

—

dB

500 kSamples/s, 12 bit, single-

ended, internal 2.5 V reference

—

54

56

53

55

62

56

61

55

60

—

dB

500 kSamples/s, 12 bit, differen-

tial, internal 1.25 V reference

Signal-to-Noise plus Distortion

Ratio (SNDR)

SNDR_DAC

500 kSamples/s, 12 bit, differen-

tial, internal 2.5 V reference

dB

500 kSamples/s, 12 bit, differen-

tial, V_DDreference

dB

500 kSamples/s, 12 bit, single-

ended, internal 1.25V reference

dBc

500 kSamples/s, 12 bit, single-

ended, internal 2.5 V reference

500 kSamples/s, 12 bit, differen-

tial, internal 1.25 V reference

Spurious-Free Dynamic Range

(SFDR)

SFDR_DAC

500 kSamples/s, 12 bit, differen-

tial, internal 2.5 V reference

500 kSamples/s, 12 bit, differen-

tial, V_DDreference

After calibration, single-ended

After calibration, differential

—

2

—

mV

V_DACOFFSET

Offset voltage

Sample-hold mode voltage drift V_DACSHMDRIFT

—

540

±1

—

µV/ms

LSB

bits

Differential non-linearity

Integral non-linearity

No missing codes

Load current

DNL_DAC

INL_DAC

MC_DAC

I_{LOAD_DC}

V_REF

—

±5

—

12

—

11

mA

VREF voltage

1.25 V reference

2.5 V reference

1.2

2.4

-12.4

-24.6

-132

-231

—

1.25

2.5

2.9

5.7

272

545

67

1.3

2.6

18.2

35.2

677

1271

114

82

V

VREF voltage drift

V_{REF_VDRIFT}

V_{REF_TDRIFT}

I_VREF

1.25 V reference

2.5 V reference, VDD > 2.5 V

1.25 V reference

2.5 V reference

mV/V

µV/°C

µA

VREF temperature drift

VREF current consumption

1.25 V reference

2.5 V reference

—

55

µA

ADC and DAC VREF matching V_{REF_MATCH}

1.25 V reference

2.5 V reference

—

99.85

100.01

—

%

—

%

Note:

1. Measured with a static input code and no loading on the output. Includes required contribution from the voltage reference.

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EFM32G Data Sheet

Electrical Characteristics

4.12 Analog Comparator (ACMP)

Table 4.16. ACMP

Test Condition

Parameter

Symbol

V_ACMPIN

Min

0

Typ

—

Max

V_DD

Unit

V

Input voltage range

ACMP Common Mode voltage V_ACMPCM

range

0

—

V

BIASPROG=0b0000, FULL-

BIAS=0 and HALFBIAS=1 in

ACMPn_CTRL register

—

55

2.82

250

0

600

12

µA

BIASPROG=0b1111, FULL-

BIAS=0 and HALFBIAS=0 in

ACMPn_CTRL register

I_ACMP

Active current

BIASPROG=0b1111, FULL-

BIAS=1 and HALFBIAS=0 in

ACMPn_CTRL register

520

0.5

Internal voltage reference off.

Using external voltage refer-

ence

Current consumption of internal

voltage reference

I_ACMPREF

Internal voltage reference,

LPREF=1

—

0.050

3

µA

Internal voltage reference,

LPREF=0

6

0

—

12

Offset voltage

V_ACMPOFFSET

BIASPROG= 0b1010, FULL-

BIAS=0 and HALFBIAS=0 in

ACMPn_CTRL register

-12

mV

ACMP hysteresis

V_ACMPHYST

Programmable

—

17

39

—

mV

kΩ

CSRESSEL=0b00 in

ACMPn_INPUTSEL

CSRESSEL=0b01 in

ACMPn_INPUTSEL

—

71

104

136

—

10

kΩ

µs

Capacitive Sense Internal Re-

sistance

R_CSRES

CSRESSEL=0b10 in

ACMPn_INPUTSEL

CSRESSEL=0b11 in

ACMPn_INPUTSEL

Startup time

t_ACMPSTART

The total ACMP current is the sum of the contributions from the ACMP and its internal voltage reference as given in the following equa-

tion. I_ACMPREFis zero if an external voltage reference is used.

I

= I

+ I

ACMP ACMPREF

ACMPTOTAL

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EFM32G Data Sheet

Electrical Characteristics

Current Consumption, HYSTSEL = 4

Response Time

2.5

2.0

1.5

1.0

0.5

0.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

HYSTSEL=0.0

HYSTSEL=2.0

HYSTSEL=4.0

HYSTSEL=6.0

0

4

8

12

0

2

4

6

8

10

12

14

ACMP_CTRL_BIASPROG

Hysteresis

100

80

60

40

20

0

BIASPROG=0.0

BIASPROG=4.0

BIASPROG=8.0

BIASPROG=12.0

0

1

2

3

4

5

6

7

ACMP_CTRL_HYSTSEL

Figure 4.34. ACMP Characteristics, VDD = 3V, Temp = 25°C, FULLBIAS = 0, HALFBIAS = 1

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EFM32G Data Sheet

Electrical Characteristics

4.13 Voltage Comparator (VCMP)

Table 4.17. VCMP

Test Condition

Parameter

Symbol

V_VCMPIN

Min

—

Typ

V_DD

Max

—

Unit

V

Input voltage range

VCMP Common Mode voltage V_VCMPCM

range

—

V

Active current

I_VCMP

BIASPROG=0b0000 and HALF-

BIAS=1 in VCMPn_CTRL regis-

ter

—

0.3

22

10

1

µA

µs

BIASPROG=0b1111 and HALF-

BIAS=0 in VCMPn_CTRL regis-

ter. LPREF=0.

30

—

Startup time reference genera- t_VCMPREF

tor

NORMAL

Offset voltage

V_VCMPOFFSET

Single-ended

Differential

—

10

40

—

10

mV

µs

VCMP hysteresis

Startup time

V_VCMPHYST

t_VCMPSTART

The V_{DD Trigger Level}can be configured by setting the TRIGLEVEL field of the VCMP_CTRL register in accordance with the following

equation:

V

= 1.667V + 0.034 × TRIGLEVEL

DD Trigger Level

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EFM32G Data Sheet

Electrical Characteristics

4.14 LCD

Table 4.18. LCD

Parameter

Symbol

f_LCDFR

NUM_SEG

V_LCD

Test Condition

Min

30

Typ

—

Max

200

—

Unit

Hz

seg

V

Frame rate

Number of segments supported

LCD supply voltage range

—

4×40

—

Internal boost circuit enabled

2.0

—

3.8

—

Display disconnected, static mode,

framerate 32 Hz, all segments on.

250

nA

Display disconnected, quadruplex

mode, framerate 32 Hz, all seg-

ments on, bias mode to ONE-

THIRD in LCD_DISPCTRL regis-

ter.

—

550

—

nA

I_LCD

Steady state current consumption.

Internal voltage boost off

—

0

—

µA

Steady state Current contribution

of internal boost.

I_LCDBOOST

Internal voltage boost on, boosting

from 2.2 V to 3.0 V.

8.4

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL0

—

3.0

—

V

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL1

3.08

3.17

3.26

3.34

3.43

3.52

3.6

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL2

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL3

V_BOOST

Boost Voltage

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL4

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL5

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL6

VBLEV of LCD_DISPCTRL regis-

ter to LEVEL7

The total LCD current is given by the following equation. I_LCDBOOSTis zero if internal boost is off.

= I + I

I

LCDTOTAL

LCD

LCDBOOST

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EFM32G Data Sheet

Electrical Characteristics

4.15 I2C

Table 4.19. I2C Standard-mode (Sm)

Parameter

Symbol

Min

Typ

Max

Unit

100¹

—

SCL clock frequency

f_SCL

0

—

kHz

SCL clock low time

t_LOW

4.7

4.0

250

8

—

µs

ns

µs

SCL clock high time

t_HIGH

—

SDA set-up time

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

—

3450^2,3

—

SDA hold time

Repeated START condition set-up time

(Repeated) START condition hold time

STOP condition set-up time

4.7

4.0

4.7

—

Bus free time between a STOP and a START

condition

—

Note:

1. For the minimum HFPERCLK frequency required in Standard-mode, see the I2C chapter in the EFM32G Reference Manual.

2. The maximum SDA hold time (t_HD,DAT) needs to be met only when the device does not stretch the low time of SCL (t_LOW).

3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((3450*10^-9[s] * f_HFPERCLK[Hz]) - 4).

Table 4.20. I2C Fast-mode (Fm)

Parameter

Symbol

Min

Typ

Max

Unit

400¹

—

SCL clock frequency

f_SCL

0

—

kHz

SCL clock low time

t_LOW

1.3

0.6

100

8

—

µs

ns

µs

SCL clock high time

t_HIGH

—

SDA set-up time

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

—

900^2,3

—

SDA hold time

Repeated START condition set-up time

(Repeated) START condition hold time

STOP condition set-up time

0.6

1.3

—

Bus free time between a STOP and a START

condition

—

Note:

1. For the minimum HFPERCLK frequency required in Fast-mode, see the I2C chapter in the EFM32G Reference Manual.

2. The maximum SDA hold time (t_HD,DAT) needs to be met only when the device does not stretch the low time of SCL (t_LOW).

3. When transmitting data, this number is guaranteed only when I2Cn_CLKDIV < ((900*10^-9[s] * f_HFPERCLK[Hz]) - 4).

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EFM32G Data Sheet

Electrical Characteristics

Table 4.21. I2C Fast-mode Plus (Fm+)

Parameter

Symbol

Min

Typ

Max

Unit

1000¹

—

SCL clock frequency

f_SCL

0

—

kHz

SCL clock low time

t_LOW

0.5

0.26

50

—

µs

ns

µs

SCL clock high time

t_HIGH

—

SDA set-up time

t_SU,DAT

t_HD,DAT

t_SU,STA

t_HD,STA

t_SU,STO

t_BUF

—

SDA hold time

8

—

Repeated START condition set-up time

(Repeated) START condition hold time

STOP condition set-up time

0.26

0.5

—

Bus free time between a STOP and a START

condition

—

Note:

1. For the minimum HFPERCLK frequency required in Fast-mode Plus, see the I2C chapter in the EFM32G Reference Manual.

4.16 Digital Peripherals

Table 4.22. Digital Peripherals

Parameter

Symbol

I_USART

I_UART

I_LEUART

I_I2C

Test Condition

Min

—

Typ

7.5

Max

—

Unit

µA/MHz

nA

USART current

UART current

LEUART current

I2C current

USART idle current, clock enabled

UART idle current, clock enabled

LEUART idle current, clock enabled

I2C idle current, clock enabled

TIMER_0 idle current, clock enabled

LETIMER idle current, clock enabled

PCNT idle current, clock enabled

RTC idle current, clock enabled

LCD idle current, clock enabled

AES idle current, clock enabled

GPIO idle current, clock enabled

EBI idle current, clock enabled

PRS idle current

5.63

150

6.25

8.75

150

100

2.5

µA/MHz

nA

TIMER current

LETIMER current

PCNT current

RTC current

LCD current

AES current

GPIO current

EBI current

I_TIMER

I_LETIMER

I_PCNT

I_RTC

nA

I_LCD

nA

I_AES

µA/MHz

I_GPIO

I_EBI

5.31

1.56

2.81

8.12

PRS current

DMA current

I_PRS

I_DMA

Clock enable

Note: Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" forguidelines on designing Printed Circuit

Boards (PCB's) for the EFM32G.

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EFM32G Data Sheet

Pin Definitions

5. Pin Definitions

Note: Please refer to the application note "AN0002 EFM32 Hardware Design Considerations" for guidelines on designing Printed Cir-

cuit Boards (PCBs) for the EFM32G.

5.1 EFM32G200 & EFM32G210 (QFN32)

5.1.1 Pinout

The EFM32G200 and EFM32G210 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by

the location number (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bit-

field in the *_ROUTE register in the module in question.

Figure 5.1. EFM32G200 & EFM32G210 Pinout (top view, not to scale)

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EFM32G Data Sheet

Pin Definitions

Table 5.1. Device Pinout

QFN32 Pin# and Name

Pin Alternate Functionality / Description

Pin #

Pin Name

VSS

Analog

Ground.

Timers

Communication

Other

0

1

2

3

4

5

6

7

8

PA0

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

I2C0_SDA #0

I2C0_SCL #0

PA1

CMU_CLK1 #0

CMU_CLK0 #0

PA2

IOVDD_1

PC0

Digital IO power supply 1.

ACMP0_CH0

ACMP0_CH1

LFXTAL_P

PCNT0_S0IN #2

PCNT0_S1IN #2

US1_TX #0

US1_RX #0

US1_CLK #0

US1_CS #0

PC1

PB7

PB8

LFXTAL_N

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low

during reset, and let the internal pull-up ensure that reset is released.

9

RESETn

10

11

12

13

14

15

16

17

18

19

20

PB11

AVDD_2

PB13

DAC0_OUT0

LETIM0_OUT0 #1

Analog power supply 2.

HFXTAL_P

LEU0_TX #1

LEU0_RX #1

PB14

HFXTAL_N

IOVDD_3

AVDD_0

PD4

Digital IO power supply 3.

Analog power supply 0.

ADC0_CH4

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

PD5

ADC0_CH5

PD6

ADC0_CH6

ADC0_CH7

LETIM0_OUT0 #0

LETIM0_OUT1 #0

PD7

VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this

pin.

21

22

23

24

DECOUPLE

PC13

TIM0_CDTI0 #1/3 TIM1_CC0

ACMP1_CH5

#0 PCNT0_S0IN #0

TIM0_CDTI1 #1/3 TIM1_CC1

ACMP1_CH6

PC14

#0 PCNT0_S1IN #0

TIM0_CDTI2 #1/3 TIM1_CC2

PC15

ACMP1_CH7

DBG_SWO #1

#0

25

26

27

28

29

30

PF0

PF1

LETIM0_OUT0 #2

LETIM0_OUT1 #2

DBG_SWCLK #0/1

DBG_SWDIO #0/1

PF2

ACMP1_O #0 DBG_SWO #0

IOVDD_5

PE10

PE11

Digital IO power supply 5.

TIM1_CC0 #1

TIM1_CC1 #1

US0_TX #0

US0_RX #0

BOOT_TX

BOOT_RX

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EFM32G Data Sheet

Pin Definitions

QFN32 Pin# and Name

Pin Alternate Functionality / Description

Pin #

31

Pin Name

PE12

Analog

Timers

TIM1_CC2 #1

Communication

US0_CLK #0

US0_CS #0

Other

32

PE13

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.1.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.2. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_O

0

1

2

3

Description

PC0

PC1

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

PE13

PC13

PC14

PC15

PF2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 5.

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

DAC0_OUT0

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

Digital to Analog Converter DAC0 output channel number 0.

Debug-interface Serial Wire clock input.

PA1

PB11

DBG_SWCLK

DBG_SWDIO

PF0

PF1

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO

HFXTAL_N

PF2

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PD6

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PB11

I2C0_SDA

LETIM0_OUT0

PF0

Low Energy Timer LETIM0, output channel 0.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

LETIM0_OUT1

LEU0_RX

0

1

2

3

Description

PD7

PD5

PF1

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

PD4

PB13

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

PB7

LFXTAL_P

PCNT0_S0IN

PCNT0_S1IN

TIM0_CC0

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

US0_CLK

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PC13

PC14

PA0

PC0

PC1

Pulse Counter PCNT0 input number 1.

PA0

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

USART0 clock input / output.

PA1

PA2

PC13

PC14

PC15

PE10

PE11

PE12

PC13

PC14

PC15

PC13

PC14

PC15

PE12

PE13

US0_CS

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

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EFM32G Data Sheet

Pin Definitions

5.1.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G200 and EFM32G210 is shown in the following table. Each GPIO port is organized as 16-

bit ports indicated by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.3. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

—

PB11

—

PA2 PA1 PA0

PB14 PB13

PB8 PB7

—

PC15 PC14 PC13

—

PC1 PC0

—

PD7 PD6 PD5 PD4

—

PE13 PE12 PE11 PE10

—

PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.2 EFM32G222 (TQFP48)

5.2.1 Pinout

The EFM32G222 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.2. EFM32G222 Pinout (top view, not to scale)

Table 5.4. Device Pinout

TQFP48 Pin# and

Pin Alternate Functionality / Description

Name

Pin #

Pin Name

PA0

Analog

Timers

Communication

I2C0_SDA #0

I2C0_SCL #0

Other

1

2

3

4

5

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

PA1

CMU_CLK1 #0

CMU_CLK0 #0

PA2

IOVDD_0

VSS

Digital IO power supply 0.

Ground.

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EFM32G Data Sheet

Pin Definitions

TQFP48 Pin# and

Name

Pin Alternate Functionality / Description

Pin #

Pin Name

PC0

Analog

Timers

Communication

US1_TX #0

Other

6

7

8

9

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

PCNT0_S0IN #2

PCNT0_S1IN #2

PC1

US1_RX #0

PC2

PC3

LETIM0_OUT0 #3

PCNT1_S0IN #0

10

PC4

ACMP0_CH4

11

12

13

14

15

PB7

PB8

PA8

PA9

PA10

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

TIM2_CC0 #0

TIM2_CC1 #0

TIM2_CC2 #0

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low

during reset, and let the internal pull-up ensure that reset is released.

16

RESETn

17

18

19

20

21

22

23

24

25

26

27

28

PB11

VSS

DAC0_OUT0

Ground.

LETIM0_OUT0 #1

AVDD_1

PB13

Analog power supply 1.

HFXTAL_P

LEU0_TX #1

LEU0_RX #1

PB14

HFXTAL_N

IOVDD_3

AVDD_0

PD4

Digital IO power supply 3.

Analog power supply 0.

ADC0_CH4

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

PD5

ADC0_CH5

PD6

ADC0_CH6

ADC0_CH7

LETIM0_OUT0 #0

LETIM0_OUT1 #0

PD7

VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this

pin.

29

DECOUPLE

30

31

32

33

PC8

PC9

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

TIM2_CC0 #2

TIM2_CC1 #2

TIM2_CC2 #2

US0_CS #2

US0_CLK #2

US0_RX #2

US0_TX #2

PC10

PC11

TIM0_CDTI0 #1/3 TIM1_CC0

#0 PCNT0_S0IN #0

34

35

PC13

PC14

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

TIM0_CDTI1 #1/3 TIM1_CC1

#0 PCNT0_S1IN #0

TIM0_CDTI2 #1/3 TIM1_CC2

#0

36

37

PC15

PF0

DBG_SWO #1

LETIM0_OUT0 #2

DBG_SWCLK #0/1

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EFM32G Data Sheet

Pin Definitions

TQFP48 Pin# and

Name

Pin Alternate Functionality / Description

Pin #

38

39

40

41

42

43

44

45

46

47

48

Pin Name

PF1

Analog

Timers

Communication

Other

LETIM0_OUT1 #2

DBG_SWDIO #0/1

PF2

ACMP1_O #0 DBG_SWO #0

PF3

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

PF4

PF5

IOVDD_5

VSS

Digital IO power supply 5.

Ground.

PE10

PE11

PE12

PE13

TIM1_CC0 #1

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

BOOT_TX

BOOT_RX

TIM1_CC1 #1

TIM1_CC2 #1

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.2.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.5. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

PC4

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

Analog comparator ACMP1, channel 1.

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

PE13

PC8

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PC9

PC10

PC11

PC13

PC14

PC15

PF2

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

DAC0_OUT0

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

Digital to Analog Converter DAC0 output channel number 0.

Debug-interface Serial Wire clock input.

PA1

PB11

DBG_SWCLK

DBG_SWDIO

PF0

PF1

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

Debug-interface Serial Wire viewer Output.

DBG_SWO

PF2

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PD6

PD7

PD5

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PB11

I2C0_SDA

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PF0

PF1

PC4

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB14

PB13

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

PD4

PB8

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

LFXTAL_P

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

TIM0_CC0

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

US0_CLK

PB7

PC13

PC14

PC4

PA0

PA1

PA2

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PC0

PC1

Pulse Counter PCNT0 input number 1.

Pulse Counter PCNT1 input number 0.

PA0

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

USART0 clock input / output.

PA1

PA2

PC13

PC14

PC15

PE10

PE11

PE12

PF3

PF4

PF5

PC13

PC14

PC15

PC13

PC14

PC15

PA8

PC8

PC9

PA9

PA10

PE12

PE13

PC10

PC9

PC8

US0_CS

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

PE11

PC10

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

US0_TX

PE10

PC11

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

5.2.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G222 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.6. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

—

PA10 PA9 PA8

—

PA2 PA1 PA0

PB14 PB13

PB11

—

PB8 PB7

—

PC15 PC14 PC13

PC11 PC10 PC9 PC8

—

PC4 PC3 PC2 PC1 PC0

—

PD7 PD6 PD5 PD4

—

PE13 PE12 PE11 PE10

—

PF5 PF4 PF3 PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.3 EFM32G230 (QFN64)

5.3.1 Pinout

The EFM32G230 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.3. EFM32G230 Pinout (top view, not to scale)

Table 5.7. Device Pinout

QFN64 Pin# and Name

Pin Alternate Functionality / Description

Pin #

Pin Name

VSS

Analog

Ground.

Timers

Communication

Other

0

1

2

3

4

5

PA0

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

TIM0_CDTI0 #0

TIM0_CDTI1 #0

I2C0_SDA #0

I2C0_SCL #0

PA1

CMU_CLK1 #0

CMU_CLK0 #0

PA2

PA3

PA4

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EFM32G Data Sheet

Pin Definitions

QFN64 Pin# and Name

Pin Alternate Functionality / Description

Pin #

6

Pin Name

PA5

Analog

Timers

TIM0_CDTI2 #0

Communication

LEU1_TX #1

Other

6

PA6

LEU1_RX #1

8

IOVDD_0

PC0

Digital IO power supply 0.

PCNT0_S0IN #1

9

US1_TX #0

US1_RX #0

US2_CLK #0

US2_CS #0

10

11

12

PC1

PCNT0_S1IN #1

PC2

PC3

LETIM0_OUT0 #3

PCNT1_S0IN #0

13

14

PC4

PC5

ACMP0_CH4

ACMP0_CH5

US2_CLK #0

US2_CS #0

LETIM0_OUT1 #3

PCNT1_S1IN #0

15

16

17

18

19

PB7

PB8

PA8

PA9

PA10

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

TIM2_CC0 #0

TIM2_CC1 #0

TIM2_CC2 #0

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low

during reset, and let the internal pull-up ensure that reset is released.

20

RESETn

21

22

23

24

25

26

27

28

PB11

PB12

DAC0_OUT0

DAC0_OUT1

LETIM0_OUT0 #1

LETIM0_OUT1 #1

AVDD_1

PB13

Analog power supply 1.

HFXTAL_P

LEU0_TX #1

LEU0_RX #1

PB14

HFXTAL_N

IOVDD_3

AVDD_0

PD0

Digital IO power supply 3.

Analog power supply 0.

ADC0_CH0

ADC0_CH1

PCNT2_S0IN #0

US1_TX #1

US1_RX #1

TIM0_CC0 #3 PCNT2_S1IN

#0

29

PD1

30

31

32

33

34

35

36

37

38

39

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PC6

PC7

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

TIM0_CC1 #3

TIM0_CC2 #3

US1_CLK #1

US1_CS #1

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

LETIM0_OUT0 #0

LETIM0_OUT1 #0

CMU_CLK1 #1

ACMP0_CH6

ACMP0_CH7

LEU1_TX #0 I2C0_SDA #2

LEU1_RX #0 I2C0_SCL #2

VDD_DREG Power supply for on-chip voltage regulator.

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EFM32G Data Sheet

Pin Definitions

QFN64 Pin# and Name

Pin Alternate Functionality / Description

Timers Communication

Pin #

Pin Name

Analog

Other

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this

pin.

40

DECOUPLE

41

42

43

44

45

PC8

PC9

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

TIM2_CC0 #2

TIM2_CC1 #2

TIM2_CC2 #2

US0_CS #2

US0_CLK #2

US0_RX #2

US0_TX #2

PC10

PC11

PC12

CMU_CLK0 #1

DBG_SWO #1

TIM0_CDTI0 #1/3 TIM1_CC0

#0 PCNT0_S0IN #0

46

47

48

PC13

PC14

PC15

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

TIM0_CDTI1 #1/3 TIM1_CC1

#0 PCNT0_S1IN #0

TIM0_CDTI2 #1/3 TIM1_CC2

#0

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

PF0

PF1

LETIM0_OUT0 #2

LETIM0_OUT1 #2

DBG_SWCLK #0/1

DBG_SWDIO #0/1

PF2

ACMP1_O #0 DBG_SWO #0

PF3

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

PF4

PF5

IOVDD_5

PE8

Digital IO power supply 5.

PCNT2_S0IN #1

PE9

PCNT2_S1IN #1

TIM1_CC0 #1

TIM1_CC1 #1

TIM1_CC2 #1

PE10

PE11

PE12

PE13

PE14

PE15

PA15

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

LEU0_TX #2

LEU0_RX #2

BOOT_TX

BOOT_RX

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.3.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.8. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC8

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PC9

Analog comparator ACMP2, channel 1.

PC10

PC11

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP3, channel 2.

Analog comparator ACMP4, channel 3.

Analog comparator ACMP1, channel 4.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

PC12

PD8

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

PA1

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

DAC0_OUT0

DAC0_OUT1

0

1

2

3

Description

PB11

Digital to Analog Converter DAC0 output channel number 0.

Digital to Analog Converter DAC0 output channel number 1.

Debug-interface Serial Wire clock input.

PB12

DBG_SWCLK

DBG_SWDIO

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

Debug-interface Serial Wire viewer Output.

DBG_SWO

HFXTAL_N

PF2

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PD6

PD7

PD5

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PC7

PC6

PF0

PF1

I2C0_SDA

PD6

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PB11

PB12

PB14

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PA1

PA2

PA3

PA4

PA5

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

PC0

PC1

Pulse Counter PCNT0 input number 1.

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

PE8

Pulse Counter PCNT2 input number 0.

PE9

Pulse Counter PCNT2 input number 1.

PA0

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

TIM0_CC1

PA1

TIM0_CC2

PA2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

PC13

PC14

PC15

PF3

PF4

PF5

PC13

PC14

PC15

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

US0_CLK

US0_CS

0

1

2

3

Description

PC13

PE10

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

USART0 clock input / output.

PC14

PC15

PA8

PE11

PE12

PC8

PC9

PA9

PA10

PE12

PE13

PC10

PC9

PC8

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PC10

PC11

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

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EFM32G Data Sheet

Pin Definitions

5.3.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G230 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.9. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

PA8

—

Port A

PA15

—

PA10 PA8

—

PA6 PA5 PA4 PA3 PA2 PA1 PA0

Port B

Port C

Port D

Port E

Port F

PB14 PB13 PB12 PB11

—

PB8 PB7

—

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

—

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8

—

PF5 PF4 PF3 PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.4 EFM32G232 (TQFP64)

5.4.1 Pinout

The EFM32G232 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.4. EFM32G232 Pinout (top view, not to scale)

Table 5.10. Device Pinout

TQFP64 Pin# and

Pin Alternate Functionality / Description

Name

Pin #

Pin Name

PA0

Analog

Timers

Communication

I2C0_SDA #0

I2C0_SCL #0

Other

1

2

3

4

5

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

TIM0_CDTI0 #0

TIM0_CDTI1 #0

PA1

CMU_CLK1 #0

CMU_CLK0 #0

PA2

PA3

PA4

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EFM32G Data Sheet

Pin Definitions

TQFP64 Pin# and

Name

Pin Alternate Functionality / Description

Pin #

6

Pin Name

PA5

Analog

Timers

TIM0_CDTI2 #0

Communication

Other

LEU1_TX #1

7

IOVDD_0

VSS

Digital IO power supply 0.

Ground.

8

9

PC0

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

PCNT0_S0IN #1

US1_TX #1

US1_RX #1

US1_CLK #1

US1_CS #1

10

11

12

PC1

PCNT0_S1IN #1

PC2

PC3

LETIM0_OUT0 #3

PCNT1_S0IN #0

13

14

PC4

PC5

ACMP0_CH4

ACMP0_CH5

US2_CLK #0

US2_CS #0

LETIM0_OUT1 #3

PCNT1_S1IN #0

15

16

17

18

19

PB7

PB8

PA8

PA9

PA10

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

TIM2_CC0 #0

TIM2_CC1 #0

TIM2_CC2 #0

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low

during reset, and let the internal pull-up ensure that reset is released.

20

RESETn

21

22

23

24

25

26

27

28

PB11

VSS

DAC0_OUT0

Ground.

LETIM0_OUT0 #1

AVDD_1

PB13

Analog power supply 1.

HFXTAL_P

LEU0_TX #1

LEU0_RX #1

PB14

HFXTAL_N

IOVDD_3

AVDD_0

PD0

Digital IO power supply 3.

Analog power supply 0.

ADC0_CH0

ADC0_CH1

PCNT2_S0IN #0

US1_TX #1

US1_RX #1

TIM0_CC0 #3 PCNT2_S1IN

#0

29

PD1

30

31

32

33

34

35

36

37

38

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PC6

PC7

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

TIM0_CC1 #3

TIM0_CC2 #3

US1_CLK #1

US1_CS #1

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

LETIM0_OUT0 #0

LETIM0_OUT1 #0

CMU_CLK1 #1

ACMP0_CH6

ACMP0_CH7

LEU1_TX #0 I2C0_SDA #2

LEU1_RX #0 I2C0_SCL #2

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EFM32G Data Sheet

Pin Definitions

TQFP64 Pin# and

Name

Pin Alternate Functionality / Description

Pin #

Pin Name

Analog

Timers

Communication

Other

39

VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this

pin.

40

DECOUPLE

41

42

43

44

45

PC8

PC9

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

TIM2_CC0 #2

TIM2_CC1 #2

TIM2_CC2 #2

US0_CS #2

US0_CLK #2

US0_RX #2

US0_TX #2

PC10

PC11

PC12

CMU_CLK0 #1

DBG_SWO #1

TIM0_CDTI0 #1/3 TIM1_CC0

#0 PCNT0_S0IN #0

46

47

48

PC13

PC14

PC15

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

TIM0_CDTI1 #1/3 TIM1_CC1

#0 PCNT0_S1IN #0

TIM0_CDTI2 #1/3 TIM1_CC2

#0

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

PF0

PF1

LETIM0_OUT0 #2

LETIM0_OUT1 #2

DBG_SWCLK #0/1

DBG_SWDIO #0/1

PF2

ACMP1_O #0 DBG_SWO #0

PF3

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

PF4

PF5

IOVDD_5

VSS

Digital IO power supply 5.

Ground.

PE8

PCNT2_S0IN #1

PE9

PCNT2_S1IN #1

TIM1_CC0 #1

TIM1_CC1 #1

TIM1_CC2 #1

PE10

PE11

PE12

PE13

PE14

PE15

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

LEU0_TX #2

LEU0_RX #2

BOOT_TX

BOOT_RX

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.4.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.11. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

PE13

PC8

PC9

PC10

PC11

PF2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_O

Analog comparator ACMP1, channel 1.

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

DAC0_OUT0

PC12

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

Digital to Analog Converter DAC0 output channel number 0.

Debug-interface Serial Wire clock input.

PA1

PD8

PB11

DBG_SWCLK

DBG_SWDIO

PF0

PF1

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

Debug-interface Serial Wire viewer Output.

DBG_SWO

PF2

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PD6

PD7

PD5

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PB11

PC7

PC6

PF0

PF1

I2C0_SDA

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB14

PB13

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

PA5

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

PB7

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PC0

PC1

Pulse Counter PCNT0 input number 1.

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

PE8

Pulse Counter PCNT2 input number 0.

PE9

Pulse Counter PCNT2 input number 1.

PA0

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

USART0 clock input / output.

TIM0_CC1

PA1

TIM0_CC2

PA2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

PA3

PC13

PC14

PC15

PE10

PE11

PE12

PF3

PF4

PF5

PC13

PC14

PC15

PA4

PA5

PC13

PC14

PC15

PA8

TIM1_CC1

TIM1_CC2

TIM2_CC0

PC8

PC9

PC10

PC9

TIM2_CC1

PA9

TIM2_CC2

PA10

PE12

US0_CLK

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

US0_CS

0

1

2

3

Description

PE13

PC8

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PC10

PC11

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

5.4.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G2322 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.12. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

—

PA10 PA9 PA8

—

PA5 PA4 PA3 PA2 PA1 PA0

PB14 PB13

PB11

—

PB8 PB7

—

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

—

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8

—

PF5 PF4 PF3 PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.5 EFM32G280 (LQFP100)

5.5.1 Pinout

The EFM32G280 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.5. EFM32G280 Pinout (top view, not to scale)

Table 5.13. Device Pinout

LQFP100 Pin#

Pin Alternate Functionality / Description

and Name

Pin # Pin Name

Analog

EBI

Timers

Communication

I2C0_SDA #0

I2C0_SCL #0

Other

1

2

3

4

5

PA0

PA1

PA2

PA3

PA4

EBI_AD09 #0

EBI_AD10 #0

EBI_AD11 #0

EBI_AD12 #0

EBI_AD13 #0

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

TIM0_CDTI0 #0

TIM0_CDTI1 #0

CMU_CLK1 #0

CMU_CLK0 #0

U0_TX #2

U0_RX #2

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

6

PA5

PA6

EBI_AD14 #0

EBI_AD15 #0

TIM0_CDTI2 #0

LEU1_TX #1

LEU1_RX #1

7

8

IOVDD_0 Digital IO power supply 0.

9

PB0

PB1

PB2

PB3

PB4

PB5

PB6

TIM1_CC0 #2

TIM1_CC1 #2

TIM1_CC2 #2

PCNT1_S0IN #1

PCNT1_S1IN #1

10

11

12

13

14

15

16

17

US2_TX #1

US2_RX #1

US2_CLK #1

US2_CS #1

VSS

Ground.

IOVDD_1 Digital IO power supply 1.

ACMP0_C

18

19

20

21

22

23

PC0

H0

PCNT0_S0IN #2

PCNT0_S1IN #2

US1_TX #0

US1_RX #0

US2_TX #0

US2_RX #0

US2_CLK #0

US2_CS #0

ACMP0_C

PC1

H1

ACMP0_C

PC2

H2

ACMP0_C

PC3

H3

ACMP0_C

LETIM0_OUT0 #3

PCNT1_S0IN #0

PC4

H4

ACMP0_C

LETIM0_OUT1 #3

PCNT1_S1IN #0

PC5

H5

24

25

26

27

28

29

30

31

32

33

34

35

PB7

PB8

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

PA7

PA8

TIM2_CC0 #0

TIM2_CC1 #0

TIM2_CC2 #0

PA9

PA10

PA11

IOVDD_2 Digital IO power supply 2.

VSS

PA12

PA13

PA14

Ground.

TIM2_CC0 #1

TIM2_CC1 #1

TIM2_CC2 #1

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during

reset, and let the internal pull-up ensure that reset is released.

36

RESETn

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

37

38

PB9

PB10

DAC0_OU

T0

39

PB11

PB12

LETIM0_OUT0 #1

LETIM0_OUT1 #1

DAC0_OU

T1

40

41

42

AVDD_1 Analog power supply 1.

HFXTAL_

PB13

P

LEU0_TX #1

LEU0_RX #1

HFXTAL_

43

PB14

N

44

45

IOVDD_3 Digital IO power supply 3.

AVDD_0 Analog power supply 0.

ADC0_CH

46

47

48

49

50

51

52

PD0

0

PCNT2_S0IN #0

US1_TX #1

US1_RX #1

US1_CLK #1

US1_CS #1

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

ADC0_CH

TIM0_CC0 #3

PCNT2_S1IN #0

PD1

1

ADC0_CH

PD2

2

TIM0_CC1 #3

TIM0_CC2 #3

ADC0_CH

PD3

3

ADC0_CH

PD4

4

ADC0_CH

PD5

5

ADC0_CH

PD6

6

LETIM0_OUT0 #0

LETIM0_OUT1 #0

ADC0_CH

53

54

55

PD7

7

PD8

CMU_CLK1 #1

ACMP0_C

LEU1_TX #0

I2C0_SDA #2

PC6

H6

ACMP0_C

LEU1_RX #0

I2C0_SCL #2

56

PC7

H7

VDD_DRE

57

58

59

Power supply for on-chip voltage regulator.

Ground.

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this pin.

G

VSS

DECOU-

PLE

60

61

62

PE0

PE1

PE2

PCNT0_S0IN #1

PCNT0_S1IN #1

U0_TX #1

U0_RX #1

ACMP0_O #1

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

63

64

65

66

67

PE3

PE4

PE5

PE6

PE7

ACMP1_O #1

US0_CS #1

US0_CLK #1

US0_RX #1

US0_TX #1

ACMP1_C

H0

68

69

70

71

72

PC8

PC9

TIM2_CC0 #2

TIM2_CC1 #2

TIM2_CC2 #2

US0_CS #2

US0_CLK #2

US0_RX #2

US0_TX #2

ACMP1_C

H1

ACMP1_C

H2

PC10

PC11

PC12

ACMP1_C

H3

ACMP1_C

H4

CMU_CLK0 #1

TIM0_CDTI0 #1/3

TIM1_CC0 #0

PCNT0_S0IN #0

ACMP1_C

H5

73

PC13

TIM0_CDTI1 #1/3

TIM1_CC1 #0

PCNT0_S1IN #0

ACMP1_C

H6

74

75

PC14

PC15

U0_TX #3

U0_RX #3

ACMP1_C

H7

TIM0_CDTI2 #1/3

TIM1_CC2 #0

DBG_SWO #1

76

77

PF0

PF1

LETIM0_OUT0 #2

LETIM0_OUT1 #2

DBG_SWCLK #0/1

DBG_SWDIO #0/1

ACMP1_O #0

DBG_SWO #0

78

PF2

EBI_ARDY #0

79

80

81

82

83

84

85

86

87

88

89

90

91

PF3

PF4

PF5

EBI_ALE #0

EBI_WEn #0

EBI_REn #0

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

IOVDD_5 Digital IO power supply 5.

VSS

PF6

Ground.

TIM0_CC0 #2

TIM0_CC1 #2

TIM0_CC2 #2

U0_TX #0

U0_RX #0

PF7

PF8

PF9

PD9

PD10

PD11

PD12

EBI_CS0 #0

EBI_CS1 #0

EBI_CS2 #0

EBI_CS3 #0

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

92

93

94

95

96

97

98

99

100

PE8

PE9

EBI_AD00 #0

EBI_AD01 #0

EBI_AD02 #0

EBI_AD03 #0

EBI_AD04 #0

EBI_AD05 #0

EBI_AD06 #0

EBI_AD07 #0

EBI_AD08 #0

PCNT2_S0IN #1

PCNT2_S1IN #1

TIM1_CC0 #1

TIM1_CC1 #1

TIM1_CC2 #1

PE10

PE11

PE12

PE13

PE14

PE15

PA15

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

LEU0_TX #2

LEU0_RX #2

BOOT_TX

BOOT_RX

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.5.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.14. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC8

PE2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PC9

Analog comparator ACMP1, channel 1.

PC10

PC11

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, channel 4.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

PE3

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

PC12

PD8

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

PA1

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

DAC0_OUT0

DAC0_OUT1

0

1

2

3

Description

PB11

Digital to Analog Converter DAC0 output channel number 0.

Digital to Analog Converter DAC0 output channel number 1.

Debug-interface Serial Wire clock input.

PB12

DBG_SWCLK

DBG_SWDIO

DBG_SWO

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

PF1

PF2

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

Debug-interface Serial Wire viewer Output.

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

External Bus Interface (EBI) address and data input / output

pin 00.

EBI_AD00

EBI_AD01

EBI_AD02

EBI_AD03

EBI_AD04

EBI_AD05

EBI_AD06

EBI_AD07

EBI_AD08

EBI_AD09

EBI_AD10

EBI_AD11

EBI_AD12

EBI_AD13

EBI_AD14

PE8

External Bus Interface (EBI) address and data input / output

pin 01.

PE9

External Bus Interface (EBI) address and data input / output

pin 02.

PE10

PE11

PE12

PE13

PE14

PE15

PA15

PA0

External Bus Interface (EBI) address and data input / output

pin 03.

External Bus Interface (EBI) address and data input / output

pin 04.

External Bus Interface (EBI) address and data input / output

pin 05.

External Bus Interface (EBI) address and data input / output

pin 06.

External Bus Interface (EBI) address and data input / output

pin 07.

External Bus Interface (EBI) address and data input / output

pin 08.

External Bus Interface (EBI) address and data input / output

pin 09.

External Bus Interface (EBI) address and data input / output

pin 10.

PA1

External Bus Interface (EBI) address and data input / output

pin 11.

PA2

External Bus Interface (EBI) address and data input / output

pin 12.

PA3

External Bus Interface (EBI) address and data input / output

pin 13.

PA4

External Bus Interface (EBI) address and data input / output

pin 14.

PA5

External Bus Interface (EBI) address and data input / output

pin 15.

EBI_AD15

EBI_ALE

PA6

PF3

External Bus Interface (EBI) Address Latch Enable output.

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EFM32G Data Sheet

Pin Definitions

Alternate

Functionality

EBI_ARDY

EBI_CS0

EBI_CS1

EBI_CS2

EBI_CS3

EBI_REn

EBI_WEn

LOCATION

0

1

2

3

Description

PF2

PD9

External Bus Interface (EBI) Hardware Ready Control input.

External Bus Interface (EBI) Chip Select output 0.

External Bus Interface (EBI) Chip Select output 1.

External Bus Interface (EBI) Chip Select output 2.

External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) Write Enable output.

PD10

PD11

PD12

PF5

PF4

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PD6

PD7

PD5

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PC7

PC6

PF0

PF1

I2C0_SDA

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PB11

PB12

PB14

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PE0

PC0

PC1

PE1

Pulse Counter PCNT0 input number 1.

PB3

Pulse Counter PCNT1 input number 0.

PB4

Pulse Counter PCNT1 input number 1.

PE8

Pulse Counter PCNT2 input number 0.

PE9

Pulse Counter PCNT2 input number 1.

PA0

PF6

PF7

PF8

PF3

PF4

PF5

PB0

PB1

PB2

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

TIM0_CC1

PA1

TIM0_CC2

PA2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

PA3

PC13

PC14

PC15

PE10

PE11

PE12

PC13

PC14

PC15

PA4

PA5

PC13

PC14

PC15

TIM1_CC1

TIM1_CC2

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EFM32G Data Sheet

Pin Definitions

Alternate

Functionality

TIM2_CC0

TIM2_CC1

TIM2_CC2

U0_RX

LOCATION

0

1

2

3

Description

PA8

PA9

PA12

PC8

PC9

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

UART0 Receive input.

PA13

PA14

PE1

PA10

PF7

PC10

PA4

PC15

PC14

UART0 Transmit output. Also used as receive input in half du-

plex communication.

U0_TX

PF6

PE0

PA3

US0_CLK

US0_CS

PE12

PE13

PE5

PE4

PC9

PC8

USART0 clock input / output.

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PE6

PE7

PC10

PC11

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

PB4

PB3

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

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EFM32G Data Sheet

Pin Definitions

5.5.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G280 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.15. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

—

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EFM32G Data Sheet

Pin Definitions

5.6 EFM32G290 (BGA112)

5.6.1 Pinout

The EFM32G290 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.6. EFM32G280 Pinout (top view, not to scale)

Table 5.16. Device Pinout

BGA112 Pin# and

Pin Alternate Functionality / Description

Name

Pin # Pin Name

Analog

EBI

Timers

Communication

LEU0_RX #2

LEU0_TX #2

US0_CLK #0

Other

A1

A2

A3

A4

A5

PE15

PE14

PE12

PE9

EBI_AD07 #0

EBI_AD06 #0

EBI_AD04 #0

EBI_AD01 #0

EBI_CS1 #0

TIM1_CC2 #1

PCNT2_S1IN #1

PD10

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

A6

A7

A8

A9

PF7

PF5

PF4

PE4

TIM0_CC1 #2

TIM0_CDTI2 #2

TIM0_CDTI1 #2

U0_RX #0

EBI_REn #0

EBI_WEn #0

US0_CS #1

U0_TX #3

TIM0_CDTI1 #1/3

TIM1_CC1 #0

PCNT0_S1IN #0

ACMP1_C

H6

A10

A11

PC14

PC15

ACMP1_C

H7

TIM0_CDTI2 #1/3

TIM1_CC2 #0

U0_RX #3

DBG_SWO #1

B1

B2

B3

B4

B5

B6

B7

B8

B9

PA15

PE13

PE11

PE8

EBI_AD08 #0

EBI_AD05 #0

EBI_AD03 #0

EBI_AD00 #0

EBI_CS2 #0

US0_CS #0

US0_RX #0

ACMP0_O #0

BOOT_RX

TIM1_CC1 #1

PCNT2_S0IN #1

PD11

PF8

TIM0_CC2 #2

TIM0_CC0 #2

TIM0_CDTI0 #2

PF6

U0_TX #0

PF3

EBI_ALE #0

PE5

US0_CLK #1

ACMP1_C

H4

B10

B11

PC12

PC13

CMU_CLK0 #1

TIM0_CDTI0 #1/3

TIM1_CC0 #0

PCNT0_S0IN #0

ACMP1_C

H5

C1

C2

C3

C4

C5

C6

C7

PA1

PA0

EBI_AD10 #0

EBI_AD09 #0

EBI_AD02 #0

TIM0_CC1 #0/1

TIM0_CC0 #0/1

TIM1_CC0 #1

I2C0_SCL #0

I2C0_SDA #0

US0_TX #0

CMU_CLK1 #0

BOOT_TX

PE10

PD13

PD12

PF9

EBI_CS3 #0

VSS

Ground.

ACMP1_O #0

DBG_SWO #0

C8

C9

PF2

PE6

EBI_ARDY #0

US0_RX #1

US0_RX #2

ACMP1_C

H2

C10

PC10

TIM2_CC2 #2

ACMP1_C

H3

C11

PC11

US0_TX #2

U0_TX #2

D1

D2

PA3

PA2

EBI_AD12 #0

EBI_AD11 #0

TIM0_CDTI0 #0

TIM0_CC2 #0/1

CMU_CLK0 #0

Rev. 2.10 | 115

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

D3

D4

D5

PB15

VSS

Ground.

IOVDD_6 Digital IO power supply 6.

LCD_SEG

D6

PD9

EBI_CS0 #0

28

D7

D8

D9

IOVDD_5 Digital IO power supply 5.

PF1

PE7

LETIM0_OUT1 #2

DBG_SWDIO #0/1

US0_TX #1

US0_CS #2

ACMP1_C

D10

D11

PC8

H0

TIM2_CC0 #2

TIM2_CC1 #2

ACMP1_C

PC9

H1

US0_CLK #2

E1

E2

E3

E4

E8

E9

E10

E11

F1

PA6

PA5

PA4

PB0

PF0

PE0

PE1

PE3

PB1

PB2

PB3

PB4

EBI_AD15 #0

LEU1_RX #1

LEU1_TX #1

U0_RX #2

EBI_AD14 #0

EBI_AD13 #0

TIM0_CDTI2 #0

TIM0_CDTI1 #0

TIM1_CC0 #2

LETIM0_OUT0 #2

PCNT0_S0IN #1

PCNT0_S1IN #1

DBG_SWCLK #0/1

ACMP1_O #1

U0_TX #1

U0_RX #1

TIM1_CC1 #2

TIM1_CC2 #2

F2

F3

PCNT1_S0IN #1

PCNT1_S1IN #1

US2_TX #1

US2_RX #1

F4

VDD_DRE

G

F8

Power supply for on-chip voltage regulator.

Ground for on-chip voltage regulator.

VSS_DRE

G

F9

F10

F11

PE2

ACMP0_O #1

DECOU-

PLE

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this pin.

G1

G2

G3

G4

G8

G9

PB5

PB6

VSS

US2_CLK #1

US2_CS #1

Ground.

IOVDD_0 Digital IO power supply 0.

IOVDD_4 Digital IO power supply 4.

VSS

Ground.

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

ACMP0_C

H6

LEU1_TX #0

I2C0_SDA #2

G10

G11

H1

PC6

PC7

PC0

PC2

ACMP0_C

H7

LEU1_RX #0

I2C0_SCL #2

ACMP0_C

H0

PCNT0_S0IN #2

US1_TX #0

ACMP0_C

H2

US2_TX #0

H3

H4

H5

H6

H7

H8

PD14

PA7

PA8

VSS

I2C0_SDA #3

TIM2_CC0 #0

Ground.

IOVDD_3 Digital IO power supply 3.

PD8

CMU_CLK1 #1

ADC0_CH

H9

H10

H11

J1

PD5

5

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

US1_RX #0

ADC0_CH

PD6

6

LETIM0_OUT0 #0

LETIM0_OUT1 #0

PCNT0_S1IN #2

ADC0_CH

PD7

7

ACMP0_C

PC1

H1

ACMP0_C

J2

PC3

H3

US2_RX #0

J3

J4

J5

J6

J7

J8

PD15

PA12

PA9

I2C0_SCL #3

TIM2_CC0 #1

TIM2_CC1 #0

TIM2_CC2 #0

PA10

PB9

PB10

ADC0_CH

J9

PD2

2

TIM0_CC1 #3

TIM0_CC2 #3

US1_CLK #1

US1_CS #1

ADC0_CH

J10

PD3

3

ADC0_CH

J11

K1

PD4

4

LEU0_TX #0

US1_CLK #0

US2_CLK #0

PB7

PC4

LFXTAL_P

ACMP0_C

H4

LETIM0_OUT0 #3

PCNT1_S0IN #0

K2

K3

K4

PA13

VSS

TIM2_CC1 #1

Ground.

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Timers Communication

Pin # Pin Name

Analog

EBI

Other

K5

K6

PA11

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during

reset, and let the internal pull-up ensure that reset is released.

RESETn

K7

K8

AVSS_1 Analog ground 1.

AVDD_2 Analog power supply 2.

AVDD_1 Analog power supply 1.

AVSS_0 Analog ground 0.

K9

K10

ADC0_CH

TIM0_CC0 #3

PCNT2_S1IN #0

K11

L1

PD1

1

US1_RX #1

US1_CS #0

US2_CS #0

PB8

PC5

LFXTAL_N

ACMP0_C

H5

LETIM0_OUT1 #3

PCNT1_S1IN #0

L2

L3

L4

PA14

TIM2_CC2 #1

IOVDD_1 Digital IO power supply 1.

DAC0_OU

L5

PB11

T0

LETIM0_OUT0 #1

LETIM0_OUT1 #1

DAC0_OU

L6

L7

L8

PB12

T1

AVSS_2 Analog ground 2.

HFXTAL_

PB13

P

LEU0_TX #1

LEU0_RX #1

HFXTAL_

L9

PB14

N

L10

L11

AVDD_0 Analog power supply 0.

ADC0_CH

PD0

0

PCNT2_S0IN #0

US1_TX #1

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EFM32G Data Sheet

Pin Definitions

5.6.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.17. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC8

PE2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PC9

Analog comparator ACMP1, channel 1.

PC10

PC11

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, channel 4.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

PE3

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

PC12

PD8

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

PA1

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

DAC0_OUT0

DAC0_OUT1

0

1

2

3

Description

PB11

Digital to Analog Converter DAC0 output channel number 0.

Digital to Analog Converter DAC0 output channel number 1.

Debug-interface Serial Wire clock input.

PB12

DBG_SWCLK

DBG_SWDIO

DBG_SWO

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

PF1

PF2

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

Debug-interface Serial Wire viewer Output.

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

External Bus Interface (EBI) address and data input / output

pin 00.

EBI_AD00

EBI_AD01

EBI_AD02

EBI_AD03

EBI_AD04

EBI_AD05

EBI_AD06

EBI_AD07

EBI_AD08

EBI_AD09

EBI_AD10

EBI_AD11

EBI_AD12

EBI_AD13

EBI_AD14

PE8

External Bus Interface (EBI) address and data input / output

pin 01.

PE9

External Bus Interface (EBI) address and data input / output

pin 02.

PE10

PE11

PE12

PE13

PE14

PE15

PA15

PA0

External Bus Interface (EBI) address and data input / output

pin 03.

External Bus Interface (EBI) address and data input / output

pin 04.

External Bus Interface (EBI) address and data input / output

pin 05.

External Bus Interface (EBI) address and data input / output

pin 06.

External Bus Interface (EBI) address and data input / output

pin 07.

External Bus Interface (EBI) address and data input / output

pin 08.

External Bus Interface (EBI) address and data input / output

pin 09.

External Bus Interface (EBI) address and data input / output

pin 10.

PA1

External Bus Interface (EBI) address and data input / output

pin 11.

PA2

External Bus Interface (EBI) address and data input / output

pin 12.

PA3

External Bus Interface (EBI) address and data input / output

pin 13.

PA4

External Bus Interface (EBI) address and data input / output

pin 14.

PA5

External Bus Interface (EBI) address and data input / output

pin 15.

EBI_AD15

EBI_ALE

PA6

PF3

External Bus Interface (EBI) Address Latch Enable output.

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EFM32G Data Sheet

Pin Definitions

Alternate

Functionality

EBI_ARDY

EBI_CS0

EBI_CS1

EBI_CS2

EBI_CS3

EBI_REn

EBI_WEn

LOCATION

0

1

2

3

Description

PF2

PD9

External Bus Interface (EBI) Hardware Ready Control input.

External Bus Interface (EBI) Chip Select output 0.

External Bus Interface (EBI) Chip Select output 1.

External Bus Interface (EBI) Chip Select output 2.

External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) Write Enable output.

PD10

PD11

PD12

PF5

PF4

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

PB13

PA1

PA0

PD6

PD7

PD5

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PC7

PC6

PF0

PF1

PD15

I2C0_SDA

PD14

PC4

PC5

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PB11

PB12

PB14

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PE0

PC0

PC1

PE1

Pulse Counter PCNT0 input number 1.

PB3

Pulse Counter PCNT1 input number 0.

PB4

Pulse Counter PCNT1 input number 1.

PE8

Pulse Counter PCNT2 input number 0.

PE9

Pulse Counter PCNT2 input number 1.

PA0

PF6

PF7

PF8

PF3

PF4

PF5

PB0

PB1

PB2

PD1

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

TIM0_CC1

PA1

PD2

TIM0_CC2

PA2

PD3

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

PA3

PC13

PC14

PC15

PE10

PE11

PE12

PC13

PC14

PC15

PA4

PA5

PC13

PC14

PC15

TIM1_CC1

TIM1_CC2

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EFM32G Data Sheet

Pin Definitions

Alternate

Functionality

TIM2_CC0

TIM2_CC1

TIM2_CC2

U0_RX

LOCATION

0

1

2

3

Description

PA8

PA9

PA12

PC8

PC9

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

UART0 Receive input.

PA13

PA14

PE1

PA10

PF7

PC10

PA4

PC15

PC14

UART0 Transmit output. Also used as receive input in half du-

plex communication.

U0_TX

PF6

PE0

PA3

US0_CLK

US0_CS

PE12

PE13

PE5

PE4

PC9

PC8

USART0 clock input / output.

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PE6

PE7

PC10

PC11

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

PB4

PB3

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

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EFM32G Data Sheet

Pin Definitions

5.6.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G290 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.18. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

—

PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.7 EFM32G840 (QFN64)

5.7.1 Pinout

The EFM32G840 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.7. EFM32G840 Pinout (top view, not to scale)

Table 5.19. Device Pinout

QFN64 Pin# and Name

Pin Alternate Functionality / Description

Pin #

Pin Name

VSS

Analog

Ground.

Timers

Communication

Other

0

1

2

3

4

5

PA0

LCD_SEG13

LCD_SEG14

LCD_SEG15

LCD_SEG16

LCD_SEG17

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

TIM0_CDTI0 #0

TIM0_CDTI1 #0

I2C0_SDA #0

I2C0_SCL #0

PA1

CMU_CLK1 #0

CMU_CLK0 #0

PA2

PA3

PA4

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EFM32G Data Sheet

Pin Definitions

QFN64 Pin# and Name

Pin Alternate Functionality / Description

Pin #

6

Pin Name

PA5

Analog

Timers

TIM0_CDTI2 #0

Communication

LEU1_TX #1

Other

LCD_SEG18

LCD_SEG19

6

PA6

LEU1_RX #1

8

IOVDD_0

PB3

Digital IO power supply 0.

9

LCD_SEG20

LCD_SEG21

LCD_SEG22

LCD_SEG23

PCNT1_S0IN #1

US2_TX #1

US2_RX #1

US2_CLK #1

US2_CS #1

10

11

12

PB4

PCNT1_S1IN #1

PB5

PB6

LETIM0_OUT0 #3

PCNT1_S0IN #0

13

14

PC4

PC5

ACMP0_CH4

ACMP0_CH5

US2_CLK #0

US2_CS #0

LETIM0_OUT1 #3

PCNT1_S1IN #0

15

16

PB7

PB8

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

LCD_BCAP_

P

17

PA12

TIM2_CC0 #1

LCD_BCAP_

N

18

19

20

PA13

PA14

TIM2_CC1 #1

TIM2_CC2 #1

LCD_BEXT

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low

during reset, and let the internal pull-up ensure that reset is released.

RESETn

21

22

23

24

25

26

27

28

PB11

PB12

DAC0_OUT0

DAC0_OUT1

LETIM0_OUT0 #1

LETIM0_OUT1 #1

AVDD_1

PB13

Analog power supply 1.

HFXTAL_P

LEU0_TX #1

LEU0_RX #1

PB14

HFXTAL_N

IOVDD_3

AVDD_0

PD0

Digital IO power supply 3.

Analog power supply 0.

ADC0_CH0

ADC0_CH1

PCNT2_S0IN #0

US1_TX #1

US1_RX #1

TIM0_CC0 #3 PCNT2_S1IN

#0

29

PD1

30

31

32

33

34

35

36

37

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PC6

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

TIM0_CC1 #3

TIM0_CC2 #3

US1_CLK #1

US1_CS #1

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

LETIM0_OUT0 #0

LETIM0_OUT1 #0

CMU_CLK1 #1

ACMP0_CH6

LEU1_TX #0 I2C0_SDA #2

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EFM32G Data Sheet

Pin Definitions

QFN64 Pin# and Name

Pin Alternate Functionality / Description

Pin #

38

Pin Name

Analog

Timers

Communication

Other

PC7

ACMP0_CH7

LEU1_RX #0 I2C0_SCL #2

39

VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this

pin.

40

DECOUPLE

41

42

43

44

45

PE4

PE5

PE6

PE7

PC12

LCD_COM0

LCD_COM1

LCD_COM2

LCD_COM3

ACMP1_CH4

US0_CS #1

US0_CLK #1

US0_RX #1

US0_TX #1

CMU_CLK0 #1

DBG_SWO #1

TIM0_CDTI0 #1/3 TIM1_CC0

#0 PCNT0_S0IN #0

46

47

48

PC13

PC14

PC15

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

TIM0_CDTI1 #1/3 TIM1_CC1

#0 PCNT0_S1IN #0

TIM0_CDTI2 #1/3 TIM1_CC2

#0

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

PF0

PF1

LETIM0_OUT0 #2

LETIM0_OUT1 #2

DBG_SWCLK #0/1

DBG_SWDIO #0/1

PF2

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG3

ACMP1_O #0 DBG_SWO #0

PF3

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

PF4

PF5

IOVDD_5

PE8

Digital IO power supply 5.

LCD_SEG4

LCD_SEG5

LCD_SEG6

LCD_SEG7

LCD_SEG8

LCD_SEG9

LCD_SEG10

LCD_SEG11

LCD_SEG12

PCNT2_S0IN #1

PE9

PCNT2_S1IN #1

TIM1_CC0 #1

TIM1_CC1 #1

TIM1_CC2 #1

PE10

PE11

PE12

PE13

PE14

PE15

PA15

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

LEU0_TX #2

LEU0_RX #2

BOOT_TX

BOOT_RX

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.7.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.20. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 4.

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

DAC0_OUT0

DAC0_OUT1

PC12

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

Digital to Analog Converter DAC0 output channel number 0.

Digital to Analog Converter DAC0 output channel number 1.

Debug-interface Serial Wire clock input.

PA1

PD8

PB11

PB12

DBG_SWCLK

DBG_SWDIO

PF0

PF1

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

Debug-interface Serial Wire viewer Output.

DBG_SWO

PF2

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

I2C0_SDA

PB13

PA1

PA0

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PC7

PC6

LCD voltage booster (optional), boost capacitor, negative pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD_BCAP_N

LCD_BCAP_P

PA13

PA12

LCD voltage booster (optional), boost capacitor, positive pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If using the LCD

voltage booster, connect a 1 uF capacitor between this pin

and VSS.

LCD_BEXT

PA14

An external LCD voltage may also be applied to this pin if the

booster is not enabled.

If AVDD is used directly as the LCD supply voltage, this pin

may be left unconnected or used as a GPIO.

LCD_COM0

LCD_COM1

LCD_COM2

LCD_COM3

PE4

PE5

PE6

PE7

LCD driver common line number 0.

LCD driver common line number 1.

LCD driver common line number 2.

LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG3

LCD_SEG4

LCD_SEG5

LCD_SEG6

LCD_SEG7

LCD_SEG8

PF2

LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

PF3

LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

PF4

LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

PF5

LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

PE8

PE9

PE10

PE11

PE12

LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

LCD segment line 9. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

LCD_SEG9

LCD_SEG10

LCD_SEG11

LCD_SEG12

LCD_SEG13

LCD_SEG14

LCD_SEG15

LCD_SEG16

LCD_SEG17

LCD_SEG18

LCD_SEG19

LCD_SEG20

LCD_SEG21

LCD_SEG22

LCD_SEG23

PE13

LCD segment line 10. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

PE14

PE15

PA15

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PB3

PB4

PB5

PB6

LCD segment line 11. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 21. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 22. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 23. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PD6

PD7

PD5

PB11

PF0

PF1

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB12

PB14

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PCNT0_S0IN

PCNT0_S1IN

PC13

PC14

Pulse Counter PCNT0 input number 1.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

US0_CLK

0

1

2

3

Description

PC4

PC5

PD0

PD1

PA0

PA1

PA2

PA3

PA4

PA5

PB3

PB4

PE8

PE9

PA0

PA1

PA2

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

Pulse Counter PCNT2 input number 0.

Pulse Counter PCNT2 input number 1.

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

USART0 clock input / output.

PC13

PC14

PC15

PE10

PE11

PE12

PA12

PA13

PA14

PE5

PF3

PF4

PF5

PC13

PC14

PC15

PC13

PC14

PC15

PE12

PE13

US0_CS

PE4

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PE6

PE7

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

PB4

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

US2_TX

PB3

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

5.7.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G840 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.21. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

PA15 PA14 PA13 PA12

—

PA6 PA5 PA4 PA3 PA2 PA1 PA0

—

PB14 PB13 PB12 PB11

PB8 PB7 PB6 PB5 PB4 PB3

PC7 PC6 PC5 PC4

—

PC15 PC14 PC13 PC12

—

PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4

—

PF5 PF4 PF3 PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.8 EFM32G842 (TQFP64)

5.8.1 Pinout

The EFM32G842 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.8. EFM32G842 Pinout (top view, not to scale)

Table 5.22. Device Pinout

TQFP64 Pin# and

Pin Alternate Functionality / Description

Name

Pin #

Pin Name

PA0

Analog

Timers

Communication

I2C0_SDA #0

I2C0_SCL #0

Other

1

2

3

4

5

LCD_SEG13

LCD_SEG14

LCD_SEG15

LCD_SEG16

LCD_SEG17

TIM0_CC0 #0/1

TIM0_CC1 #0/1

TIM0_CC2 #0/1

TIM0_CDTI0 #0

TIM0_CDTI1 #0

PA1

CMU_CLK1 #0

CMU_CLK0 #0

PA2

PA3

PA4

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EFM32G Data Sheet

Pin Definitions

TQFP64 Pin# and

Name

Pin Alternate Functionality / Description

Pin #

6

Pin Name

PA5

Analog

Timers

TIM0_CDTI2 #0

Communication

Other

LCD_SEG18

LEU1_TX #1

7

IOVDD_0

VSS

Digital IO power supply 0.

Ground.

8

9

PB3

LCD_SEG20

LCD_SEG21

LCD_SEG22

LCD_SEG23

PCNT1_S0IN #1

US2_TX #1

US2_RX #1

US2_CLK #1

US2_CS #1

10

11

12

PB4

PCNT1_S1IN #1

PB5

PB6

LETIM0_OUT0 #3

PCNT1_S0IN #0

13

14

PC4

PC5

ACMP0_CH4

ACMP0_CH5

US2_CLK #0

US2_CS #0

LETIM0_OUT1 #3

PCNT1_S1IN #0

15

16

PB7

PB8

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

LCD_BCAP_

P

17

PA12

TIM2_CC0 #1

LCD_BCAP_

N

18

19

20

PA13

PA14

TIM2_CC1 #1

TIM2_CC2 #1

LCD_BEXT

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low

during reset, and let the internal pull-up ensure that reset is released.

RESETn

21

22

23

24

25

26

27

28

PB11

VSS

DAC0_OUT0

Ground.

LETIM0_OUT0 #1

AVDD_1

PB13

Analog power supply 1.

HFXTAL_P

LEU0_TX #1

LEU0_RX #1

PB14

HFXTAL_N

IOVDD_3

AVDD_0

PD0

Digital IO power supply 3.

Analog power supply 0.

ADC0_CH0

ADC0_CH1

PCNT2_S0IN #0

US1_TX #1

US1_RX #1

TIM0_CC0 #3 PCNT2_S1IN

#0

29

PD1

30

31

32

33

34

35

36

37

PD2

PD3

PD4

PD5

PD6

PD7

PD8

PC6

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

TIM0_CC1 #3

TIM0_CC2 #3

US1_CLK #1

US1_CS #1

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

LETIM0_OUT0 #0

LETIM0_OUT1 #0

CMU_CLK1 #1

ACMP0_CH6

LEU1_TX #0 I2C0_SDA #2

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EFM32G Data Sheet

Pin Definitions

TQFP64 Pin# and

Name

Pin Alternate Functionality / Description

Pin #

38

Pin Name

Analog

Timers

Communication

Other

PC7

ACMP0_CH7

LEU1_RX #0 I2C0_SCL #2

39

VDD_DREG Power supply for on-chip voltage regulator.

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this

pin.

40

DECOUPLE

41

42

43

44

45

PE4

PE5

PE6

PE7

PC12

LCD_COM0

LCD_COM1

LCD_COM2

LCD_COM3

ACMP1_CH4

US0_CS #1

US0_CLK #1

US0_RX #1

US0_TX #1

CMU_CLK0 #1

DBG_SWO #1

TIM0_CDTI0 #1/3 TIM1_CC0

#0 PCNT0_S0IN #0

46

47

48

PC13

PC14

PC15

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

TIM0_CDTI1 #1/3 TIM1_CC1

#0 PCNT0_S1IN #0

TIM0_CDTI2 #1/3 TIM1_CC2

#0

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

PF0

PF1

LETIM0_OUT0 #2

LETIM0_OUT1 #2

DBG_SWCLK #0/1

DBG_SWDIO #0/1

PF2

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG3

ACMP1_O #0 DBG_SWO #0

PF3

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

PF4

PF5

IOVDD_5

VSS

Digital IO power supply 5.

Ground.

PE8

LCD_SEG4

LCD_SEG5

LCD_SEG6

LCD_SEG7

LCD_SEG8

LCD_SEG9

LCD_SEG10

LCD_SEG11

PCNT2_S0IN #1

PE9

PCNT2_S1IN #1

TIM1_CC0 #1

TIM1_CC1 #1

TIM1_CC2 #1

PE10

PE11

PE12

PE13

PE14

PE15

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

LEU0_TX #2

LEU0_RX #2

BOOT_TX

BOOT_RX

ACMP0_O #0

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EFM32G Data Sheet

Pin Definitions

5.8.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.23. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 4.

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

DAC0_OUT0

PC12

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

Digital to Analog Converter DAC0 output channel number 0.

Debug-interface Serial Wire clock input.

PA1

PD8

PB11

DBG_SWCLK

DBG_SWDIO

PF0

PF1

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

Debug-interface Serial Wire viewer Output.

DBG_SWO

PF2

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

I2C0_SDA

PB13

PA1

PA0

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PC7

PC6

LCD voltage booster (optional), boost capacitor, negative pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD_BCAP_N

LCD_BCAP_P

PA13

PA12

LCD voltage booster (optional), boost capacitor, positive pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If using the LCD

voltage booster, connect a 1 uF capacitor between this pin

and VSS.

LCD_BEXT

PA14

An external LCD voltage may also be applied to this pin if the

booster is not enabled.

If AVDD is used directly as the LCD supply voltage, this pin

may be left unconnected or used as a GPIO.

LCD_COM0

LCD_COM1

LCD_COM2

LCD_COM3

PE4

PE5

PE6

PE7

LCD driver common line number 0.

LCD driver common line number 1.

LCD driver common line number 2.

LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG3

LCD_SEG4

LCD_SEG5

LCD_SEG6

LCD_SEG7

LCD_SEG8

PF2

LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

PF3

LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

PF4

LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

PF5

LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

PE8

PE9

PE10

PE11

PE12

LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 8. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

LCD segment line 9. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

LCD_SEG9

LCD_SEG10

LCD_SEG11

LCD_SEG13

LCD_SEG14

LCD_SEG15

LCD_SEG16

LCD_SEG17

LCD_SEG18

LCD_SEG20

LCD_SEG21

LCD_SEG22

LCD_SEG23

PE13

LCD segment line 10. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

PE14

PE15

PA0

PA1

PA2

PA3

PA4

PA5

PB3

PB4

PB5

PB6

LCD segment line 11. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

LCD segment line 13. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 21. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 22. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 23. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PD6

PD7

PD5

PB11

PF0

PF1

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB14

PB13

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

PA5

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

Pulse Counter PCNT0 input number 1.

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

Pulse Counter PCNT2 input number 0.

Pulse Counter PCNT2 input number 1.

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

PC13

PC14

PC4

PC5

PD0

PD1

PB3

PB4

PE8

PE9

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

TIM0_CC0

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

US0_CLK

0

1

2

3

Description

PA0

PA1

PA2

PA3

PA4

PA5

PA0

PA1

PA2

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

USART0 clock input / output.

PC13

PC14

PC15

PE10

PE11

PE12

PA12

PA13

PA14

PE5

PF3

PF4

PF5

PC13

PC14

PC15

PC13

PC14

PC15

PE12

PE13

US0_CS

PE4

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PE6

PE7

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PB4

PB3

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

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Rev. 2.10 | 138

EFM32G Data Sheet

Pin Definitions

5.8.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G842 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.24. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

—

PA14 PA13 PA12

PB14 PB13

—

PB11

—

PA5 PA4 PA3 PA2 PA1 PA0

—

PB8 PB7 PB6 PB5 PB4 PB3

PC7 PC6 PC5 PC4

—

PC15 PC14 PC13 PC12

—

PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4

—

PF5 PF4 PF3 PF2 PF1 PF0

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EFM32G Data Sheet

Pin Definitions

5.9 EFM32G880 (LQFP100)

5.9.1 Pinout

The EFM32G880 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.9. EFM32G880 Pinout (top view, not to scale)

Table 5.25. Device Pinout

LQFP100 Pin#

Pin Alternate Functionality / Description

and Name

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

LCD_SEG

13

1

2

3

PA0

PA1

PA2

EBI_AD09 #0

TIM0_CC0 #0/1

I2C0_SDA #0

LCD_SEG

14

EBI_AD10 #0

EBI_AD11 #0

TIM0_CC1 #0/1

TIM0_CC2 #0/1

I2C0_SCL #0

CMU_CLK1 #0

CMU_CLK0 #0

LCD_SEG

15

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

LCD_SEG

16

4

5

6

PA3

PA4

PA5

PA6

EBI_AD12 #0

TIM0_CDTI0 #0

U0_TX #2

U0_RX #2

LCD_SEG

17

EBI_AD13 #0

EBI_AD14 #0

EBI_AD15 #0

TIM0_CDTI1 #0

TIM0_CDTI2 #0

LCD_SEG

18

LEU1_TX #1

LEU1_RX #1

LCD_SEG

19

7

8

9

IOVDD_0 Digital IO power supply 0.

LCD_SEG

PB0

32

TIM1_CC0 #2

TIM1_CC1 #2

TIM1_CC2 #2

PCNT1_S0IN #1

PCNT1_S1IN #1

LCD_SEG

10

11

12

13

14

15

PB1

33

LCD_SEG

PB2

34

LCD_SEG

PB3

20

US2_TX #1

US2_RX #1

US2_CLK #1

US2_CS #1

LCD_SEG

PB4

21

LCD_SEG

PB5

22

LCD_SEG

PB6

23

16

17

VSS

Ground.

IOVDD_1 Digital IO power supply 1.

ACMP0_C

18

19

20

21

22

23

PC0

H0

PCNT0_S0IN #2

PCNT0_S1IN #2

US1_TX #0

US1_RX #0

US2_TX #0

US2_RX #0

US2_CLK #0

US2_CS #0

ACMP0_C

PC1

H1

ACMP0_C

PC2

H2

ACMP0_C

PC3

H3

ACMP0_C

LETIM0_OUT0 #3

PCNT1_S0IN #0

PC4

H4

ACMP0_C

LETIM0_OUT1 #3

PCNT1_S1IN #0

PC5

H5

24

25

PB7

PB8

LFXTAL_P

LFXTAL_N

US1_CLK #0

US1_CS #0

LCD_SEG

35

26

27

PA7

PA8

LCD_SEG

36

TIM2_CC0 #0

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

LCD_SEG

37

28

29

30

PA9

PA10

PA11

TIM2_CC1 #0

LCD_SEG

38

TIM2_CC2 #0

LCD_SEG

39

31

32

IOVDD_2 Digital IO power supply 2.

VSS

Ground.

LCD_BCA

P_P

33

34

35

36

PA12

TIM2_CC0 #1

TIM2_CC1 #1

TIM2_CC2 #1

LCD_BCA

P_N

PA13

PA14

LCD_BEX

T

Reset input, active low.To apply an external reset source to this pin, it is required to only drive this pin low during

reset, and let the internal pull-up ensure that reset is released.

RESETn

37

38

PB9

PB10

DAC0_OU

LETIM0_OUT0 #1

T0

39

PB11

PB12

DAC0_OU

LETIM0_OUT1 #1

T1

40

41

42

AVDD_1 Analog power supply 1.

HFXTAL_

PB13

P

LEU0_TX #1

LEU0_RX #1

HFXTAL_

43

PB14

N

44

45

IOVDD_3 Digital IO power supply 3.

AVDD_0 Analog power supply 0.

ADC0_CH

46

47

48

49

50

51

52

PD0

0

PCNT2_S0IN #0

US1_TX #1

US1_RX #1

US1_CLK #1

US1_CS #1

LEU0_TX #0

LEU0_RX #0

I2C0_SDA #1

ADC0_CH

TIM0_CC0 #3

PCNT2_S1IN #0

PD1

1

ADC0_CH

PD2

2

TIM0_CC1 #3

TIM0_CC2 #3

ADC0_CH

PD3

3

ADC0_CH

PD4

4

ADC0_CH

PD5

5

ADC0_CH

PD6

6

LETIM0_OUT0 #0

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

ADC0_CH

7

53

54

55

PD7

PD8

PC6

LETIM0_OUT1 #0

I2C0_SCL #1

CMU_CLK1 #1

ACMP0_C

H6

LEU1_TX #0

I2C0_SDA #2

ACMP0_C

H7

LEU1_RX #0

I2C0_SCL #2

56

PC7

VDD_DRE

G

57

58

59

Power supply for on-chip voltage regulator.

Ground.

VSS

DECOU-

PLE

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this pin.

60

61

62

63

PE0

PE1

PE2

PE3

PCNT0_S0IN #1

PCNT0_S1IN #1

U0_TX #1

U0_RX #1

ACMP0_O #1

ACMP1_O #1

LCD_COM

0

64

65

66

67

68

69

70

71

72

PE4

PE5

US0_CS #1

US0_CLK #1

US0_RX #1

US0_TX #1

US0_CS #2

US0_CLK #2

US0_RX #2

US0_TX #2

LCD_COM

1

LCD_COM

2

PE6

LCD_COM

3

PE7

ACMP1_C

H0

PC8

TIM2_CC0 #2

TIM2_CC1 #2

TIM2_CC2 #2

ACMP1_C

H1

PC9

ACMP1_C

H2

PC10

PC11

PC12

ACMP1_C

H3

ACMP1_C

H4

CMU_CLK0 #1

TIM0_CDTI0 #1/3

TIM1_CC0 #0

PCNT0_S0IN #0

ACMP1_C

H5

73

74

PC13

PC14

TIM0_CDTI1 #1/3

TIM1_CC1 #0

PCNT0_S1IN #0

ACMP1_C

H6

U0_TX #3

U0_RX #3

ACMP1_C

H7

TIM0_CDTI2 #1/3

TIM1_CC2 #0

75

76

PC15

PF0

DBG_SWO #1

LETIM0_OUT0 #2

DBG_SWCLK #0/1

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

77

78

PF1

PF2

LETIM0_OUT1 #2

DBG_SWDIO #0/1

LCD_SEG

0

ACMP1_O #0

DBG_SWO #0

EBI_ARDY #0

EBI_ALE #0

EBI_WEn #0

EBI_REn #0

LCD_SEG

1

79

80

81

PF3

PF4

PF5

TIM0_CDTI0 #2

TIM0_CDTI1 #2

TIM0_CDTI2 #2

LCD_SEG

2

LCD_SEG

3

82

83

IOVDD_5 Digital IO power supply 5.

VSS

PF6

Ground.

LCD_SEG

24

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

TIM0_CC0 #2

TIM0_CC1 #2

TIM0_CC2 #2

U0_TX #0

U0_RX #0

LCD_SEG

25

PF7

PF8

LCD_SEG

26

LCD_SEG

27

PF9

LCD_SEG

28

PD9

EBI_CS0 #0

EBI_CS1 #0

EBI_CS2 #0

EBI_CS3 #0

EBI_AD00 #0

EBI_AD01 #0

EBI_AD02 #0

EBI_AD03 #0

EBI_AD04 #0

EBI_AD05 #0

EBI_AD06 #0

EBI_AD07 #0

LCD_SEG

29

PD10

PD11

PD12

PE8

LCD_SEG

30

LCD_SEG

31

LCD_SEG

4

PCNT2_S0IN #1

PCNT2_S1IN #1

TIM1_CC0 #1

TIM1_CC1 #1

TIM1_CC2 #1

LCD_SEG

5

PE9

LCD_SEG

6

PE10

PE11

PE12

PE13

PE14

PE15

US0_TX #0

US0_RX #0

US0_CLK #0

US0_CS #0

LEU0_TX #2

LEU0_RX #2

BOOT_TX

BOOT_RX

LCD_SEG

7

LCD_SEG

8

LCD_SEG

9

ACMP0_O #0

LCD_SEG

10

LCD_SEG

11

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EFM32G Data Sheet

Pin Definitions

LQFP100 Pin#

and Name

Pin Alternate Functionality / Description

Timers Communication

Pin # Pin Name

Analog

EBI

Other

LCD_SEG

12

100

PA15

EBI_AD08 #0

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EFM32G Data Sheet

Pin Definitions

5.9.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.26. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC8

PE2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PC9

Analog comparator ACMP1, channel 1.

PC10

PC11

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, channel 4.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

PE3

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

PC12

PD8

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

PA1

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

DAC0_OUT0

DAC0_OUT1

0

1

2

3

Description

PB11

Digital to Analog Converter DAC0 output channel number 0.

Digital to Analog Converter DAC0 output channel number 1.

Debug-interface Serial Wire clock input.

PB12

DBG_SWCLK

DBG_SWDIO

DBG_SWO

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

PF1

PF2

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

Debug-interface Serial Wire viewer Output.

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

External Bus Interface (EBI) address and data input / output

pin 00.

EBI_AD00

EBI_AD01

EBI_AD02

EBI_AD03

EBI_AD04

EBI_AD05

EBI_AD06

EBI_AD07

EBI_AD08

EBI_AD09

EBI_AD10

EBI_AD11

EBI_AD12

EBI_AD13

EBI_AD14

PE8

External Bus Interface (EBI) address and data input / output

pin 01.

PE9

External Bus Interface (EBI) address and data input / output

pin 02.

PE10

PE11

PE12

PE13

PE14

PE15

PA15

PA0

External Bus Interface (EBI) address and data input / output

pin 03.

External Bus Interface (EBI) address and data input / output

pin 04.

External Bus Interface (EBI) address and data input / output

pin 05.

External Bus Interface (EBI) address and data input / output

pin 06.

External Bus Interface (EBI) address and data input / output

pin 07.

External Bus Interface (EBI) address and data input / output

pin 08.

External Bus Interface (EBI) address and data input / output

pin 09.

External Bus Interface (EBI) address and data input / output

pin 10.

PA1

External Bus Interface (EBI) address and data input / output

pin 11.

PA2

External Bus Interface (EBI) address and data input / output

pin 12.

PA3

External Bus Interface (EBI) address and data input / output

pin 13.

PA4

External Bus Interface (EBI) address and data input / output

pin 14.

PA5

External Bus Interface (EBI) address and data input / output

pin 15.

EBI_AD15

EBI_ALE

PA6

PF3

External Bus Interface (EBI) Address Latch Enable output.

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EFM32G Data Sheet

Pin Definitions

Alternate

Functionality

EBI_ARDY

EBI_CS0

EBI_CS1

EBI_CS2

EBI_CS3

EBI_REn

EBI_WEn

LOCATION

0

1

2

3

Description

PF2

PD9

External Bus Interface (EBI) Hardware Ready Control input.

External Bus Interface (EBI) Chip Select output 0.

External Bus Interface (EBI) Chip Select output 1.

External Bus Interface (EBI) Chip Select output 2.

External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) Write Enable output.

PD10

PD11

PD12

PF5

PF4

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

I2C0_SDA

PB13

PA1

PA0

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PC7

PC6

LCD voltage booster (optional), boost capacitor, negative pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD_BCAP_N

LCD_BCAP_P

PA13

PA12

LCD voltage booster (optional), boost capacitor, positive pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If using the LCD

voltage booster, connect a 1 uF capacitor between this pin

and VSS.

LCD_BEXT

PA14

An external LCD voltage may also be applied to this pin if the

booster is not enabled.

If AVDD is used directly as the LCD supply voltage, this pin

may be left unconnected or used as a GPIO.

LCD_COM0

LCD_COM1

LCD_COM2

LCD_COM3

PE4

PE5

PE6

PE7

LCD driver common line number 0.

LCD driver common line number 1.

LCD driver common line number 2.

LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG3

LCD_SEG4

LCD_SEG5

LCD_SEG6

PF2

PF3

PF4

PF5

PE8

PE9

PE10

LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD_SEG7

LCD_SEG8

LCD_SEG9

LCD_SEG10

LCD_SEG11

LCD_SEG12

LCD_SEG13

LCD_SEG14

LCD_SEG15

LCD_SEG16

LCD_SEG17

LCD_SEG18

LCD_SEG19

LCD_SEG20

LCD_SEG21

LCD_SEG22

LCD_SEG23

LCD_SEG24

LCD_SEG25

LCD_SEG26

LCD_SEG27

LCD_SEG28

LCD_SEG29

PE11

LCD segment line 8. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

PE12

PE13

PE14

PE15

PA15

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PB3

PB4

PB5

PB6

PF6

LCD segment line 9. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 21. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 22. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 23. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 24. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

PF7

LCD segment line 26. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

PF8

LCD segment line 27. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

PF9

LCD segment line 28. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

PD9

PD10

LCD segment line 29. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

LCD segment line 30. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

LCD_SEG30

LCD_SEG31

LCD_SEG32

LCD_SEG33

LCD_SEG34

LCD_SEG35

LCD_SEG36

LCD_SEG37

LCD_SEG38

LCD_SEG39

PD11

LCD segment line 31. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

PD12

PB0

LCD segment line 32. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

PB1

LCD segment line 34. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

PB2

LCD segment line 35. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

PA7

LCD segment line 36. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

PA8

LCD segment line 37. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

PA9

LCD segment line 38. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

PA10

PA11

LCD segment line 39. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PD6

PD7

PD5

PB11

PF0

PF1

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB12

PB14

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PA1

PA2

PA3

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

PE0

PE1

PB3

PB4

PE8

PE9

PA0

PA1

PA2

PC13

PC0

PC1

Pulse Counter PCNT0 input number 1.

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

Pulse Counter PCNT2 input number 0.

Pulse Counter PCNT2 input number 1.

PF6

PF7

PF8

PF3

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

PC13

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

U0_RX

0

1

2

3

Description

PA4

PA5

PC14

PF4

PF5

PB0

PB1

PB2

PC8

PC9

PC14

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

UART0 Receive input.

PC15

PE10

PE11

PE12

PA12

PA13

PA14

PE1

PC15

PC13

PC14

PC15

PA8

PA9

PA10

PF7

PC10

PA4

PC15

PC14

UART0 Transmit output. Also used as receive input in half du-

plex communication.

U0_TX

PF6

PE0

PA3

US0_CLK

US0_CS

PE12

PE13

PE5

PE4

PC9

PC8

USART0 clock input / output.

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PE6

PE7

PC10

PC11

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

PB4

PB3

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

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EFM32G Data Sheet

Pin Definitions

5.9.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G880 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.27. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

—

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EFM32G Data Sheet

Pin Definitions

5.10 EFM32G890 (BGA112)

5.10.1 Pinout

The EFM32G890 pinout is shown in the following figure and table. Alternate locations are denoted by "#" followed by the location num-

ber (Multiple locations on the same pin are split with "/"). Alternate locations can be configured in the LOCATION bitfield in the

*_ROUTE register in the module in question.

Figure 5.10. EFM32G890 Pinout (top view, not to scale)

Table 5.28. Device Pinout

BGA112 Pin# and

Pin Alternate Functionality / Description

Name

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

LCD_SEG

11

A1

A2

A3

PE15

PE14

PE12

EBI_AD07 #0

LEU0_RX #2

LCD_SEG

10

EBI_AD06 #0

EBI_AD04 #0

LEU0_TX #2

US0_CLK #0

LCD_SEG

8

TIM1_CC2 #1

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

LCD_SEG

5

A4

A5

A6

A7

A8

A9

PE9

PD10

PF7

PF5

PF4

PE4

EBI_AD01 #0

PCNT2_S1IN #1

LCD_SEG

29

EBI_CS1 #0

LCD_SEG

25

TIM0_CC1 #2

TIM0_CDTI2 #2

TIM0_CDTI1 #2

U0_RX #0

LCD_SEG

3

EBI_REn #0

EBI_WEn #0

LCD_SEG

2

LCD_COM

0

US0_CS #1

U0_TX #3

U0_RX #3

TIM0_CDTI1 #1/3

TIM1_CC1 #0

PCNT0_S1IN #0

ACMP1_C

H6

A10

PC14

ACMP1_C

H7

TIM0_CDTI2 #1/3

TIM1_CC2 #0

A11

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

PC15

PA15

PE13

PE11

PE8

DBG_SWO #1

LCD_SEG

12

EBI_AD08 #0

EBI_AD05 #0

EBI_AD03 #0

EBI_AD00 #0

EBI_CS2 #0

LCD_SEG

9

US0_CS #0

US0_RX #0

ACMP0_O #0

BOOT_RX

LCD_SEG

7

TIM1_CC1 #1

LCD_SEG

4

PCNT2_S0IN #1

LCD_SEG

30

PD11

PF8

LCD_SEG

26

TIM0_CC2 #2

TIM0_CC0 #2

TIM0_CDTI0 #2

LCD_SEG

24

PF6

U0_TX #0

LCD_SEG

1

PF3

EBI_ALE #0

LCD_COM

1

PE5

US0_CLK #1

ACMP1_C

H4

PC12

CMU_CLK0 #1

CMU_CLK1 #0

TIM0_CDTI0 #1/3

TIM1_CC0 #0

PCNT0_S0IN #0

ACMP1_C

H5

B11

PC13

LCD_SEG

14

C1

C2

PA1

PA0

EBI_AD10 #0

EBI_AD09 #0

TIM0_CC1 #0/1

TIM0_CC0 #0/1

I2C0_SCL #0

I2C0_SDA #0

LCD_SEG

13

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

LCD_SEG

6

C3

C4

C5

PE10

PD13

PD12

EBI_AD02 #0

TIM1_CC0 #1

US0_TX #0

BOOT_TX

LCD_SEG

31

EBI_CS3 #0

LCD_SEG

27

C6

C7

C8

PF9

VSS

PF2

Ground.

LCD_SEG

0

ACMP1_O #0

DBG_SWO #0

EBI_ARDY #0

LCD_COM

2

C9

C10

C11

D1

PE6

PC10

PC11

PA3

US0_RX #1

US0_RX #2

US0_TX #2

U0_TX #2

ACMP1_C

H2

TIM2_CC2 #2

ACMP1_C

H3

LCD_SEG

16

EBI_AD12 #0

EBI_AD11 #0

TIM0_CDTI0 #0

TIM0_CC2 #0/1

LCD_SEG

15

D2

PA2

CMU_CLK0 #0

D3

D4

D5

PB15

VSS

Ground.

IOVDD_6 Digital IO power supply 6.

LCD_SEG

D6

PD9

EBI_CS0 #0

28

D7

D8

IOVDD_5 Digital IO power supply 5.

PF1

LETIM0_OUT1 #2

DBG_SWDIO #0/1

LCD_COM

D9

D10

D11

E1

PE7

3

US0_TX #1

US0_CS #2

US0_CLK #2

LEU1_RX #1

LEU1_TX #1

U0_RX #2

ACMP1_C

PC8

H0

TIM2_CC0 #2

TIM2_CC1 #2

ACMP1_C

PC9

H1

LCD_SEG

PA6

PA5

PA4

EBI_AD15 #0

19

LCD_SEG

18

E2

EBI_AD14 #0

EBI_AD13 #0

TIM0_CDTI2 #0

TIM0_CDTI1 #0

LCD_SEG

17

E3

LCD_SEG

32

E4

E8

PB0

PF0

TIM1_CC0 #2

LETIM0_OUT0 #2

DBG_SWCLK #0/1

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

E9

PE0

PE1

PE3

PCNT0_S0IN #1

PCNT0_S1IN #1

U0_TX #1

U0_RX #1

E10

E11

ACMP1_O #1

LCD_SEG

33

F1

F2

F3

F4

F8

PB1

PB2

PB3

PB4

TIM1_CC1 #2

TIM1_CC2 #2

LCD_SEG

34

LCD_SEG

20

PCNT1_S0IN #1

PCNT1_S1IN #1

US2_TX #1

US2_RX #1

LCD_SEG

21

VDD_DRE

G

Power supply for on-chip voltage regulator.

Ground for on-chip voltage regulator.

VSS_DRE

G

F9

F10

F11

PE2

ACMP0_O #1

DECOU-

PLE

Decouple output for on-chip voltage regulator. An external capacitance of size C_DECOUPLEis required at this pin.

LCD_SEG

US2_CLK #1

22

G1

G2

PB5

LCD_SEG

US2_CS #1

23

PB6

VSS

G3

G4

G8

G9

Ground.

IOVDD_0 Digital IO power supply 0.

IOVDD_4 Digital IO power supply 4.

VSS

PC6

Ground.

ACMP0_C

H6

LEU1_TX #0

I2C0_SDA #2

G10

G11

H1

ACMP0_C

H7

LEU1_RX #0

I2C0_SCL #2

PC7

PC0

ACMP0_C

H0

PCNT0_S0IN #2

US1_TX #0

ACMP0_C

H2

H3

H4

PC2

PD14

PA7

US2_TX #0

I2C0_SDA #3

LCD_SEG

35

LCD_SEG

36

H5

PA8

VSS

TIM2_CC0 #0

H6

H7

H8

Ground.

IOVDD_3 Digital IO power supply 3.

PD8

CMU_CLK1 #1

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

ADC0_CH

5

H9

H10

H11

J1

PD5

PD6

PD7

PC1

LEU0_RX #0

I2C0_SDA #1

I2C0_SCL #1

US1_RX #0

ADC0_CH

6

LETIM0_OUT0 #0

LETIM0_OUT1 #0

PCNT0_S1IN #2

ADC0_CH

7

ACMP0_C

H1

ACMP0_C

H3

J2

J3

J4

PC3

PD15

PA12

US2_RX #0

I2C0_SCL #3

LCD_BCA

P_P

TIM2_CC0 #1

TIM2_CC1 #0

TIM2_CC2 #0

LCD_SEG

37

J5

J6

PA9

LCD_SEG

38

PA10

J7

J8

PB9

PB10

ADC0_CH

2

J9

PD2

PD3

TIM0_CC1 #3

TIM0_CC2 #3

US1_CLK #1

US1_CS #1

ADC0_CH

3

J10

ADC0_CH

4

J11

K1

PD4

PB7

PC4

LEU0_TX #0

US1_CLK #0

US2_CLK #0

LFXTAL_P

ACMP0_C

H4

LETIM0_OUT0 #3

PCNT1_S0IN #0

K2

LCD_BCA

P_N

K3

K4

K5

PA13

VSS

TIM2_CC1 #1

Ground.

LCD_SEG

39

PA11

Reset input, active low. To apply an external reset source to this pin, it is required to only drive this pin low during

reset, and let the internal pull-up ensure that reset is released.

K6

RESETn

K7

K8

AVSS_1 Analog ground 1.

AVDD_2 Analog power supply 2.

AVDD_1 Analog power supply 1.

AVSS_0 Analog ground 0.

K9

K10

ADC0_CH

TIM0_CC0 #3

PCNT2_S1IN #0

K11

L1

PD1

1

US1_RX #1

US1_CS #0

PB8

LFXTAL_N

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EFM32G Data Sheet

Pin Definitions

BGA112 Pin# and

Name

Pin Alternate Functionality / Description

Pin # Pin Name

Analog

EBI

Timers

Communication

Other

ACMP0_C

H5

LETIM0_OUT1 #3

PCNT1_S1IN #0

L2

PC5

US2_CS #0

LCD_BEX

T

L3

L4

L5

PA14

TIM2_CC2 #1

IOVDD_1 Digital IO power supply 1.

DAC0_OU

PB11

T0

LETIM0_OUT0 #1

LETIM0_OUT1 #1

DAC0_OU

L6

L7

L8

PB12

T1

AVSS_2 Analog ground 2.

HFXTAL_

PB13

P

LEU0_TX #1

LEU0_RX #1

HFXTAL_

L9

PB14

N

L10

L11

AVDD_0 Analog power supply 0.

ADC0_CH

PD0

0

PCNT2_S0IN #0

US1_TX #1

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EFM32G Data Sheet

Pin Definitions

5.10.2 Alternate Functionality Pinout

A wide selection of alternate functionality is available for multiplexing to various pins. This is shown in the following table. The table

shows the name of the alternate functionality in the first column, followed by columns showing the possible LOCATION bitfield settings.

Note: Some functionality, such as analog interfaces, do not have alternate settings or a LOCATION bitfield. In these cases, the pinout

is shown in the column corresponding to LOCATION 0.

Table 5.29. Alternate functionality overview

Alternate

LOCATION

Functionality

ACMP0_CH0

ACMP0_CH1

ACMP0_CH2

ACMP0_CH3

ACMP0_CH4

ACMP0_CH5

ACMP0_CH6

ACMP0_CH7

ACMP0_O

0

1

2

3

Description

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

Analog comparator ACMP0, channel 0.

Analog comparator ACMP0, channel 1.

Analog comparator ACMP0, channel 2.

Analog comparator ACMP0, channel 3.

Analog comparator ACMP0, channel 4.

Analog comparator ACMP0, channel 5.

Analog comparator ACMP0, channel 6.

Analog comparator ACMP0, channel 7.

PE13

PC8

PE2

Analog comparator ACMP0, digital output.

Analog comparator ACMP1, channel 0.

ACMP1_CH0

ACMP1_CH1

ACMP1_CH2

ACMP1_CH3

ACMP1_CH4

ACMP1_CH5

ACMP1_CH6

ACMP1_CH7

ACMP1_O

PC9

Analog comparator ACMP1, channel 1.

PC10

PC11

PC12

PC13

PC14

PC15

PF2

Analog comparator ACMP1, channel 2.

Analog comparator ACMP1, channel 3.

Analog comparator ACMP1, channel 4.

Analog comparator ACMP1, channel 5.

Analog comparator ACMP1, channel 6.

Analog comparator ACMP1, channel 7.

PE3

Analog comparator ACMP1, digital output.

Analog to digital converter ADC0, input channel number 0.

Analog to digital converter ADC0, input channel number 1.

Analog to digital converter ADC0, input channel number 2.

Analog to digital converter ADC0, input channel number 3.

Analog to digital converter ADC0, input channel number 4.

Analog to digital converter ADC0, input channel number 5.

Analog to digital converter ADC0, input channel number 6.

Analog to digital converter ADC0, input channel number 7.

Bootloader RX.

ADC0_CH0

ADC0_CH1

ADC0_CH2

ADC0_CH3

ADC0_CH4

ADC0_CH5

ADC0_CH6

ADC0_CH7

BOOT_RX

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

PE11

PE10

PA2

BOOT_TX

Bootloader TX.

CMU_CLK0

CMU_CLK1

PC12

PD8

Clock Management Unit, clock output number 0.

Clock Management Unit, clock output number 1.

PA1

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

DAC0_OUT0

DAC0_OUT1

0

1

2

3

Description

PB11

Digital to Analog Converter DAC0 output channel number 0.

Digital to Analog Converter DAC0 output channel number 1.

Debug-interface Serial Wire clock input.

PB12

DBG_SWCLK

DBG_SWDIO

DBG_SWO

PF0

PF1

Note that this function is enabled to pin out of reset, and has a

built-in pull down.

Debug-interface Serial Wire data input / output.

PF1

PF2

Note that this function is enabled to pin out of reset, and has a

built-in pull up.

Debug-interface Serial Wire viewer Output.

PC15

Note that this function is not enabled after reset, and must be

enabled by software to be used.

External Bus Interface (EBI) address and data input / output

pin 00.

EBI_AD00

EBI_AD01

EBI_AD02

EBI_AD03

EBI_AD04

EBI_AD05

EBI_AD06

EBI_AD07

EBI_AD08

EBI_AD09

EBI_AD10

EBI_AD11

EBI_AD12

EBI_AD13

EBI_AD14

PE8

External Bus Interface (EBI) address and data input / output

pin 01.

PE9

External Bus Interface (EBI) address and data input / output

pin 02.

PE10

PE11

PE12

PE13

PE14

PE15

PA15

PA0

External Bus Interface (EBI) address and data input / output

pin 03.

External Bus Interface (EBI) address and data input / output

pin 04.

External Bus Interface (EBI) address and data input / output

pin 05.

External Bus Interface (EBI) address and data input / output

pin 06.

External Bus Interface (EBI) address and data input / output

pin 07.

External Bus Interface (EBI) address and data input / output

pin 08.

External Bus Interface (EBI) address and data input / output

pin 09.

External Bus Interface (EBI) address and data input / output

pin 10.

PA1

External Bus Interface (EBI) address and data input / output

pin 11.

PA2

External Bus Interface (EBI) address and data input / output

pin 12.

PA3

External Bus Interface (EBI) address and data input / output

pin 13.

PA4

External Bus Interface (EBI) address and data input / output

pin 14.

PA5

External Bus Interface (EBI) address and data input / output

pin 15.

EBI_AD15

EBI_ALE

PA6

PF3

External Bus Interface (EBI) Address Latch Enable output.

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EFM32G Data Sheet

Pin Definitions

Alternate

Functionality

EBI_ARDY

EBI_CS0

EBI_CS1

EBI_CS2

EBI_CS3

EBI_REn

EBI_WEn

LOCATION

0

1

2

3

Description

PF2

PD9

External Bus Interface (EBI) Hardware Ready Control input.

External Bus Interface (EBI) Chip Select output 0.

External Bus Interface (EBI) Chip Select output 1.

External Bus Interface (EBI) Chip Select output 2.

External Bus Interface (EBI) Chip Select output 3.

External Bus Interface (EBI) Read Enable output.

External Bus Interface (EBI) Write Enable output.

PD10

PD11

PD12

PF5

PF4

High Frequency Crystal negative pin. Also used as external

optional clock input pin.

HFXTAL_N

PB14

HFXTAL_P

I2C0_SCL

I2C0_SDA

PB13

PA1

PA0

High Frequency Crystal positive pin.

I2C0 Serial Clock Line input / output.

I2C0 Serial Data input / output.

PD7

PD6

PC7

PC6

PD15

PD14

LCD voltage booster (optional), boost capacitor, negative pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD_BCAP_N

LCD_BCAP_P

PA13

PA12

LCD voltage booster (optional), boost capacitor, positive pin.

If using the LCD voltage booster, connect a 22 nF capacitor

between LCD_BCAP_N and LCD_BCAP_P.

LCD voltage booster (optional), boost output. If using the LCD

voltage booster, connect a 1 uF capacitor between this pin

and VSS.

LCD_BEXT

PA14

An external LCD voltage may also be applied to this pin if the

booster is not enabled.

If AVDD is used directly as the LCD supply voltage, this pin

may be left unconnected or used as a GPIO.

LCD_COM0

LCD_COM1

LCD_COM2

LCD_COM3

PE4

PE5

PE6

PE7

LCD driver common line number 0.

LCD driver common line number 1.

LCD driver common line number 2.

LCD driver common line number 3.

LCD segment line 0. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD_SEG0

LCD_SEG1

LCD_SEG2

LCD_SEG3

LCD_SEG4

LCD_SEG5

LCD_SEG6

PF2

PF3

PF4

PF5

PE8

PE9

PE10

LCD segment line 1. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD segment line 2. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD segment line 3. Segments 0, 1, 2 and 3 are controlled by

SEGEN0.

LCD segment line 4. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 5. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD segment line 6. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

LCD segment line 7. Segments 4, 5, 6 and 7 are controlled by

SEGEN1.

LCD_SEG7

LCD_SEG8

LCD_SEG9

LCD_SEG10

LCD_SEG11

LCD_SEG12

LCD_SEG13

LCD_SEG14

LCD_SEG15

LCD_SEG16

LCD_SEG17

LCD_SEG18

LCD_SEG19

LCD_SEG20

LCD_SEG21

LCD_SEG22

LCD_SEG23

LCD_SEG24

LCD_SEG25

LCD_SEG26

LCD_SEG27

LCD_SEG28

LCD_SEG29

PE11

LCD segment line 8. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

PE12

PE13

PE14

PE15

PA15

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PB3

PB4

PB5

PB6

PF6

LCD segment line 9. Segments 8, 9, 10 and 11 are controlled

by SEGEN2.

LCD segment line 10. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

LCD segment line 11. Segments 8, 9, 10 and 11 are control-

led by SEGEN2.

LCD segment line 12. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 13. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 14. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 15. Segments 12, 13, 14 and 15 are con-

trolled by SEGEN3.

LCD segment line 16. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 17. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 18. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 19. Segments 16, 17, 18 and 19 are con-

trolled by SEGEN4.

LCD segment line 20. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 21. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 22. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 23. Segments 20, 21, 22 and 23 are con-

trolled by SEGEN5.

LCD segment line 24. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

LCD segment line 25. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

PF7

LCD segment line 26. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

PF8

LCD segment line 27. Segments 24, 25, 26 and 27 are con-

trolled by SEGEN6.

PF9

LCD segment line 28. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

PD9

PD10

LCD segment line 29. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

0

1

2

3

Description

LCD segment line 30. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

LCD_SEG30

LCD_SEG31

LCD_SEG32

LCD_SEG33

LCD_SEG34

LCD_SEG35

LCD_SEG36

LCD_SEG37

LCD_SEG38

LCD_SEG39

PD11

LCD segment line 31. Segments 28, 29, 30 and 31 are con-

trolled by SEGEN7.

PD12

PB0

LCD segment line 32. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

LCD segment line 33. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

PB1

LCD segment line 34. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

PB2

LCD segment line 35. Segments 32, 33, 34 and 35 are con-

trolled by SEGEN8.

PA7

LCD segment line 36. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

PA8

LCD segment line 37. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

PA9

LCD segment line 38. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

PA10

PA11

LCD segment line 39. Segments 36, 37, 38 and 39 are con-

trolled by SEGEN9.

LETIM0_OUT0

LETIM0_OUT1

LEU0_RX

PD6

PD7

PD5

PB11

PF0

PF1

PC4

PC5

Low Energy Timer LETIM0, output channel 0.

Low Energy Timer LETIM0, output channel 1.

LEUART0 Receive input.

PB12

PB14

PE15

PE14

LEUART0 Transmit output. Also used as receive input in half

duplex communication.

LEU0_TX

LEU1_RX

LEU1_TX

PD4

PC7

PC6

PB13

PA6

PA5

LEUART1 Receive input.

LEUART1 Transmit output. Also used as receive input in half

duplex communication.

Low Frequency Crystal (typically 32.768 kHz) negative pin. Al-

so used as an optional external clock input pin.

LFXTAL_N

PB8

LFXTAL_P

PB7

PC13

PC14

PC4

PC5

PD0

PD1

PA0

PA1

PA2

PA3

Low Frequency Crystal (typically 32.768 kHz) positive pin.

Pulse Counter PCNT0 input number 0.

PCNT0_S0IN

PCNT0_S1IN

PCNT1_S0IN

PCNT1_S1IN

PCNT2_S0IN

PCNT2_S1IN

TIM0_CC0

PE0

PE1

PB3

PB4

PE8

PE9

PA0

PA1

PA2

PC13

PC0

PC1

Pulse Counter PCNT0 input number 1.

Pulse Counter PCNT1 input number 0.

Pulse Counter PCNT1 input number 1.

Pulse Counter PCNT2 input number 0.

Pulse Counter PCNT2 input number 1.

PF6

PF7

PF8

PF3

PD1

PD2

PD3

Timer 0 Capture Compare input / output channel 0.

Timer 0 Capture Compare input / output channel 1.

Timer 0 Capture Compare input / output channel 2.

Timer 0 Complimentary Deat Time Insertion channel 0.

TIM0_CC1

TIM0_CC2

TIM0_CDTI0

PC13

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EFM32G Data Sheet

Pin Definitions

Alternate

LOCATION

Functionality

TIM0_CDTI1

TIM0_CDTI2

TIM1_CC0

TIM1_CC1

TIM1_CC2

TIM2_CC0

TIM2_CC1

TIM2_CC2

U0_RX

0

1

2

3

Description

PA4

PA5

PC14

PF4

PF5

PB0

PB1

PB2

PC8

PC9

PC14

Timer 0 Complimentary Deat Time Insertion channel 1.

Timer 0 Complimentary Deat Time Insertion channel 2.

Timer 1 Capture Compare input / output channel 0.

Timer 1 Capture Compare input / output channel 1.

Timer 1 Capture Compare input / output channel 2.

Timer 2 Capture Compare input / output channel 0.

Timer 2 Capture Compare input / output channel 1.

Timer 2 Capture Compare input / output channel 2.

UART0 Receive input.

PC15

PE10

PE11

PE12

PA12

PA13

PA14

PE1

PC15

PC13

PC14

PC15

PA8

PA9

PA10

PF7

PC10

PA4

PC15

PC14

UART0 Transmit output. Also used as receive input in half du-

plex communication.

U0_TX

PF6

PE0

PA3

US0_CLK

US0_CS

PE12

PE13

PE5

PE4

PC9

PC8

USART0 clock input / output.

USART0 chip select input / output.

USART0 Asynchronous Receive.

US0_RX

US0_TX

PE11

PE10

PE6

PE7

PC10

PC11

USART0 Synchronous mode Master Input / Slave Output (MI-

SO).

USART0 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART0 Synchronous mode Master Output / Slave Input

(MOSI).

US1_CLK

US1_CS

PB7

PB8

PD2

PD3

USART1 clock input / output.

USART1 chip select input / output.

USART1 Asynchronous Receive.

US1_RX

US1_TX

PC1

PC0

PD1

PD0

USART1 Synchronous mode Master Input / Slave Output (MI-

SO).

USART1 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART1 Synchronous mode Master Output / Slave Input

(MOSI).

US2_CLK

US2_CS

PC4

PC5

PB5

PB6

USART2 clock input / output.

USART2 chip select input / output.

USART2 Asynchronous Receive.

US2_RX

US2_TX

PC3

PC2

PB4

PB3

USART2 Synchronous mode Master Input / Slave Output (MI-

SO).

USART2 Asynchronous Transmit.Also used as receive input

in half duplex communication.

USART2 Synchronous mode Master Output / Slave Input

(MOSI).

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Rev. 2.10 | 164

EFM32G Data Sheet

Pin Definitions

5.10.3 GPIO Pinout Overview

The specific GPIO pins available in EFM32G890 is shown in the following table. Each GPIO port is organized as 16-bit ports indicated

by letters A through F, and the individual pin on this port is indicated by a number from 15 down to 0.

Table 5.30. GPIO Pinout

Port

15

14

13

12

11

Pin Pin 9 Pin 8 Pin 7 Pin 6 Pin 5 Pin 4 Pin 3 Pin 2 Pin 1 Pin 0

10

Port A

Port B

Port C

Port D

Port E

Port F

PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

PB15 PB14 PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0

PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0

PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

—

PF9 PF8 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0

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Rev. 2.10 | 165

EFM32G Data Sheet

BGA112 Package Specifications

6. BGA112 Package Specifications

6.1 BGA112 Package Dimensions

BOTTOM VIEW

TOP VIEW

SIDE VIEW

Figure 6.1. BGA112

Note:

1. The dimensions in parenthesis are reference.

2. Datum 'C' and seating plane are defined by the crown of the solder balls.

3. All dimensions are in millimeters.

The BGA112 Package uses SAC105 solderballs.

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.

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Rev. 2.10 | 166

EFM32G Data Sheet

BGA112 Package Specifications

6.2 BGA112 PCB Layout

b

a

e

d

Figure 6.2. BGA112 PCB Land Pattern

Table 6.1. BGA112 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.35

a

b

d

e

0.80

8.00

b

a

e

d

Figure 6.3. BGA112 PCB Solder Mask

Table 6.2. BGA112 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.48

a

b

d

e

0.80

8.00

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Rev. 2.10 | 167

EFM32G Data Sheet

BGA112 Package Specifications

b

a

e

d

Figure 6.4. BGA112 PCB Stencil Design

Table 6.3. BGA112 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.33

a

b

d

e

0.80

8.00

Note:

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see Pin Definitions.

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Rev. 2.10 | 168

EFM32G Data Sheet

BGA112 Package Specifications

6.3 BGA112 Package Marking

In the illustration below package fields and position are shown.

Figure 6.5. Example Chip Marking (Top View)

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Rev. 2.10 | 169

EFM32G Data Sheet

LQFP100 Package Specifications

7. LQFP100 Package Specifications

7.1 LQFP100 Package Dimensions

Figure 7.1. LQFP100

Note:

1. Datum 'T', 'U' and 'Z' to be determined at datum plane 'H'

2. Datum 'D' and 'E' to be determined at seating plane datum 'Y'.

3. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25 per side. Dimensions 'D1' and 'E1' do include

mold mismatch and are determined at datum plane datum 'H'.

4. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause thelead width to exceed the maxi-

mum 'b' dimension by more than 0.08 mm. Dambar can not be locatedon the lower radius or the foot. Minimum space between

protrusion and an adjacent lead is 0.07 mm.

5. Exact shape of each corner is optional.

Table 7.1. LQFP100 (Dimensions in mm)

SYMBOL

MIN

—

NOM

—

MAX

1.6

total thickness

stand off

A

A1

A2

b

0.05

1.35

0.17

0.09

—

0.15

1.45

0.27

0.23

0.2

mold thickness

lead width (plating)

lead width

1.4

0.2

—

b1

c

L/F thickness (plating)

lead thickness

—

c1

—

0.16

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EFM32G Data Sheet

LQFP100 Package Specifications

SYMBOL

D

MIN

NOM

MAX

x

y

x

y

16 BSC

14 BSC

0.5 BSC

0.6

E

D1

E1

e

body size

lead pitch

L

0.45

0.75

footprint

L1

1 REF

3.5º

θ

0º

7º

—

θ1

—

θ2

11º

0.08

0.2

12º

13º

—

θ3

12º

R1

S

—

0.2

—

package edge tolerance

lead edge tolerance

coplanarity

aaa

bbb

ccc

ddd

eee

0.2

0.08

0.05

lead offset

mold flatness

The LQFP100 Package uses Nickel-Palladium-Gold preplated leadframe.

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx

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Rev. 2.10 | 171

EFM32G Data Sheet

LQFP100 Package Specifications

7.2 LQFP100 PCB Layout

a

p8

p7

p6

p1

b

c

e

p2

p5

p3

p4

d

Figure 7.2. LQFP100 PCB Land Pattern

Table 7.2. LQFP100 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.45

Symbol

P1

Pin Number

Symbol

P6

Pin Number

a

b

c

d

e

1

75

76

0.30

P2

25

26

50

51

P7

0.50

P3

P8

100

15.40

P4

P5

a

b

c

e

d

Figure 7.3. LQFP100 PCB Solder Mask

Table 7.3. LQFP100 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.57

a

b

c

d

e

0.42

0.50

15.40

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Rev. 2.10 | 172

EFM32G Data Sheet

LQFP100 Package Specifications

a

b

c

e

d

Figure 7.4. LQFP100 PCB Stencil Design

Table 7.4. LQFP100 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.35

a

b

c

d

e

0.20

0.50

15.40

Note:

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see Pin Definitions.

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Rev. 2.10 | 173

EFM32G Data Sheet

LQFP100 Package Specifications

7.3 LQFP100 Package Marking

In the illustration below package fields and position are shown.

Figure 7.5. Example Chip Marking (Top View)

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Rev. 2.10 | 174

EFM32G Data Sheet

TQFP64 Package Specifications

8. TQFP64 Package Specifications

8.1 TQFP64 Package Dimensions

F

C

L

Figure 8.1. TQFP64

Note:

1. All dimensions & tolerancing confirm to ASME Y14.5M-1994.

2. The top package body size may be smaller than the bottom package body size.

3. Datum 'A,B', and 'B' to be determined at datum plane 'H'.

4. To be determined at seating place 'C'.

5. Dimension 'D1' and 'E1' do not include mold protrusions. Allowable protrusion is 0.25mm per side.'D1' and 'E1' are maximum plas-

tic body size dimension including mold mismatch. Dimension 'D1' and'E1' shall be determined at datum plane 'H'.

6. Detail of Pin 1 indicatifier are option all but must be located within the zone indicated.

7. Dimension 'b' does not include dambar protrusion. Allowable dambar protrusion shall not cause thelead width to exceed the maxi-

mum 'b' dimension by more than 0.08 mm. Dambar can not be locatedon the lower radius or the foot. Minimum space between

protrusion and an adjacent lead is 0.07 mm.

8. Exact shape of each corner is optional.

9. These dimension apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

10. All dimensions are in millimeters.

Table 8.1. QFP64 (Dimensions in mm)

DIM

A

MIN

—

NOM

1.10

—

MAX

1.20

0.15

1.05

DIM

L1

MIN

NOM

—

MAX

A1

A2

0.05

0.95

R1

R2

0.08

—

1.00

—

0.20

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Rev. 2.10 | 175

EFM32G Data Sheet

TQFP64 Package Specifications

DIM

b

MIN

0.17

0.09

NOM

0.22

0.20

—

MAX

0.27

0.23

0.20

0.16

DIM

S

MIN

0.20

0°

NOM

—

MAX

—

b1

c

θ

3.5°

—

7°

θ1

θ2

θ3

0°

—

C1

D

—

11°

12°

13°

12.0 BSC

D1

e

10.0 BSC

0.50 BSC

12.0 BSC

10.0 BSC

E

E1

L

0.45

0.60

0.75

The TQFP64 Package is 10 by 10 mm in size and has a 0.5 mm pin pitch.

The TQFP64 Package uses Nickel-Palladium-Gold preplated leadframe.

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.

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Rev. 2.10 | 176

EFM32G Data Sheet

TQFP64 Package Specifications

8.2 TQFP64 PCB Layout

a

p8

p7

p6

p1

b

c

e

p2

p5

p3

p4

d

Figure 8.2. TQFP64 PCB Land Pattern

Table 8.2. TQFP64 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.60

Symbol

P1

Pin Number

Symbol

P6

Pin Number

a

b

c

d

e

1

48

49

64

0.30

P2

16

17

32

33

P7

0.50

P3

P8

11.50

P4

P5

a

b

c

e

d

Figure 8.3. TQFP64 PCB Solder Mask

Table 8.3. TQFP64 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.72

a

b

c

d

e

0.42

0.50

11.50

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Rev. 2.10 | 177

EFM32G Data Sheet

TQFP64 Package Specifications

a

b

c

e

d

Figure 8.4. TQFP64 PCB Stencil Design

Table 8.4. TQFP64 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.50

a

b

c

d

e

0.20

0.50

11.50

Note:

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see Pin Definitions.

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Rev. 2.10 | 178

EFM32G Data Sheet

TQFP64 Package Specifications

8.3 TQFP64 Package Marking

In the illustration below package fields and position are shown.

Figure 8.5. Example Chip Marking (Top View)

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Rev. 2.10 | 179

EFM32G Data Sheet

TQFP48 Package Specifications

9. TQFP48 Package Specifications

9.1 TQFP48 Package Dimensions

Figure 9.1. TQFP48

Note:

1. Dimensions and tolerance per ASME Y14.5M-1994

2. Control dimension: Millimeter

3. Datum plane AB is located at bottom of lead and is coincident with the lead where the lead existsfrom the plastic body at the bot-

tom of the parting line.

4. Datums T, U and Z to be determined at datum plane AB.

5. Dimensions S and V to be determined at seating plane AC.

6. Dimensions A and B do not include mold protrusion. Allowable protrusion is 0.250 per side. Dimensions A and B do include mold

mismatch and are determined at datum AB.

7. Dimension D does not include dambar protrusion. Dambar protrusion shall not cause the D dimensionto exceed 0.350.

8. Minimum solder plate thickness shall be 0.0076.

9. Exact shape of each corner is optional.

Table 9.1. QFP48 (Dimensions in mm)

DIM

A

MIN

—

NOM

MAX

—

DIM

M

N

MIN

—

NOM

12DEG REF

—

MAX

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

—

A1

B

—

0.090

—

0.160

—

P

0.250 BSC

—

B1

C

—

R

0.150

—

0.250

—

1.000

1.200

S

9.000 BSC

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Rev. 2.10 | 180

EFM32G Data Sheet

TQFP48 Package Specifications

DIM

D

MIN

0.170

0.950

0.170

—

NOM

MAX

0.270

1.050

0.230

—

DIM

S1

V

MIN

—

NOM

MAX

—

4.500 BSC

9.000 BSC

4.5000 BSC

0.200 BSC

1.000BSC

E

—

F

—

V1

W

—

G

H

0.500 BSC

—

0.050

0.090

0.500

—

0.150

0.200

0.700

AA

—

J

K

0DE

G

L

—

7DEG

The TQFP48 Package is 7 by 7 mm in size and has a 0.5 mm pin pitch.

The TQFP48 Package uses Nickel-Palladium-Gold preplated leadframe.

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx

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Rev. 2.10 | 181

EFM32G Data Sheet

TQFP48 Package Specifications

9.2 TQFP48 PCB Layout

a

p8

p7

p6

p1

b

c

e

p2

p5

p3

p4

d

Figure 9.2. TQFP48 PCB Land Pattern

Table 9.2. TQFP48 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.60

Symbol

P1

Pin Number

Symbol

P6

Pin Number

a

b

c

d

e

1

36

37

48

0.30

P2

12

13

24

25

P7

0.50

P3

P8

8.50

P4

8.50

P5

a

b

c

e

d

Figure 9.3. TQFP48 PCB Solder Mask

Table 9.3. TQFP48 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.72

a

b

c

d

e

0.42

0.50

8.50

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Rev. 2.10 | 182

EFM32G Data Sheet

TQFP48 Package Specifications

a

b

c

e

d

Figure 9.4. TQFP48 PCB Stencil Design

Table 9.4. TQFP48 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

1.50

a

b

c

d

e

0.20

0.50

8.50

Note:

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see 5. Pin Definitions.

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Rev. 2.10 | 183

EFM32G Data Sheet

TQFP48 Package Specifications

9.3 TQFP48 Package Marking

In the illustration below package fields and position are shown.

Figure 9.5. Example Chip Marking (Top View)

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Rev. 2.10 | 184

EFM32G Data Sheet

QFN64 Package Specifications

10. QFN64 Package Specifications

10.1 QFN64 Package Dimensions

49

64

48

1

33

16

32

17

m

Figure 10.1. QFN64

Note:

1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.

2. All dimensions are in millimeters. Angles are in degrees.

3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. Dimension L1

represents terminal full back from package edge up to 0.1 mm isacceptable.

4. Coplanarity applies to the exposed heat slug as well as the terminal.

5. Radius on terminal is optional.

Table 10.1. QFN64 (Dimensions in mm)

Symbol

Min

0.80

0.00

Nom

0.85

Max

0.90

0.05

A

A1

A3

b

—

0.203 REF

0.30

0.25

0.35

D

9.00 BSC

7.20

E

D2

E2

7.10

7.30

7.20

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Rev. 2.10 | 185

EFM32G Data Sheet

QFN64 Package Specifications

Symbol

e

Min

Nom

0.50 BSC

0.45

Max

L

0.40

0.00

0.50

0.10

L1

—

aaa

bbb

ccc

ddd

eee

0.10

0.05

0.08

The QFN64 Package uses Nickel-Palladium-Gold preplated leadframe.

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx.

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Rev. 2.10 | 186

EFM32G Data Sheet

QFN64 Package Specifications

10.2 QFN64 PCB Layout

a

p8

p7

p1

p6

b

c

p9

g

e

p2

p5

p3

p4

f

d

Figure 10.2. QFN64 PCB Land Pattern

Table 10.2. QFN64 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.85

Symbol

P1

Pin Number

Symbol

P8

Pin Number

a

b

c

d

e

f

1

64

65

0.30

P2

16

17

32

33

48

49

P9

0.50

P3

8.90

P4

8.90

P5

7.20

P6

g

7.20

P7

a

b

c

g

e

f

d

Figure 10.3. QFN64 PCB Solder Mask

Table 10.3. QFN64 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.97

Symbol

Dim. (mm)

a

b

c

e

f

8.90

7.32

0.42

0.50

g

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Rev. 2.10 | 187

EFM32G Data Sheet

QFN64 Package Specifications

Symbol

Dim. (mm)

Symbol

Dim. (mm)

d

8.90

-

a

b

c

x

y

e

z

d

Figure 10.4. QFN64 PCB Stencil Design

Table 10.4. QFN64 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.75

Symbol

Dim. (mm)

8.90

a

b

c

d

e

x

y

z

0.22

2.70

0.50

2.70

8.90

0.80

Note:

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see Pin Definitions.

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Rev. 2.10 | 188

EFM32G Data Sheet

QFN64 Package Specifications

10.3 QFN64 Package Marking

In the illustration below package fields and position are shown.

Figure 10.5. Example Chip Marking (Top View)

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Rev. 2.10 | 189

EFM32G Data Sheet

QFN32 Package Specifications

11. QFN32 Package Specifications

11.1 QFN32 Package Dimensions

D2

D

25

26

27

28

29

30

31

32

1

24

23

22

21

20

19

18

17

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

32xL

32xb

m

G

M

SEATING PLANE

DETAIL G

VIEW ROTATED 90° CLOCKWISE

e

EVEN / ODD TERMINL SIDE

M

Figure 11.1. QFN32

Note:

1. Dimensioning & tolerancing confirm to ASME Y14.5M-1994.

2. All dimensions are in millimeters. Angles are in degrees.

3. Dimension 'b' applies to metallized terminal and is measured between 0.25 mm and 0.30 mm fromthe terminal tip. Dimension L1

represents terminal full back from package edge up to 0.1 mm isacceptable.

4. Coplanarity applies to the exposed heat slug as well as the terminal.

5. Radius on terminal is optional.

Table 11.1. QFN32 (Dimensions in mm)

Symbol

Min

A

A1

0.80 0.00

0.85

0.90 0.05

A3

b

D

E

D2

E2

e

L

L1

aaa

bbb

ccc

ddd

eee

0.25

0.30

0.35

4.30 4.30

4.40 4.40

4.50 4.50

0.30 0.00

0.35

0.203

REF

6.00 6.00

BSC BSC

0.65

BSC

Nom

Max

—

0.10 0.10 0.10 0.05 0.08

0.40 0.10

The QFN32 Package uses Nickel-Palladium-Gold preplated leadframe.

All EFM32 packages are RoHS compliant and free of Bromine (Br) and Antimony (Sb).

For additional Quality and Environmental information, please see: http://www.silabs.com/support/quality/pages/default.aspx

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Rev. 2.10 | 190

EFM32G Data Sheet

QFN32 Package Specifications

11.2 QFN32 PCB Layout

a

p8

p7

p1

p6

b

c

p9

g

e

p2

p5

p3

p4

f

d

Figure 11.2. QFN32 PCB Land Pattern

Table 11.2. QFN32 PCB Land Pattern Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.80

Symbol

P1

Pin Number

Symbol

P6

Pin Number

a

b

c

d

e

f

1

8

24

25

32

33

0.35

P2

P7

0.65

P3

9

P8

6.00

P4

16

17

P9

6.00

P5

4.40

g

4.40

a

b

c

g

e

f

d

Figure 11.3. QFN32 PCB Solder Mask

Table 11.3. QFN32 PCB Solder Mask Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.92

a

b

c

0.47

0.65

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Rev. 2.10 | 191

EFM32G Data Sheet

QFN32 Package Specifications

Symbol

Dim. (mm)

d

e

f

6.00

4.52

g

a

b

c

x

y

e

z

d

Figure 11.4. QFN32 PCB Stencil Design

Table 11.4. QFN32 PCB Stencil Design Dimensions (Dimensions in mm)

Symbol

Dim. (mm)

0.70

a

b

c

d

e

x

y

z

0.25

0.65

6.00

1.30

0.50

Note:

1. The drawings are not to scale.

2. All dimensions are in millimeters.

3. All drawings are subject to change without notice.

4. The PCB Land Pattern drawing is in compliance with IPC-7351B.

5. Stencil thickness 0.125 mm.

6. For detailed pin-positioning, see 5. Pin Definitions.

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Rev. 2.10 | 192

EFM32G Data Sheet

QFN32 Package Specifications

11.3 QFN32 Package Marking

In the illustration below package fields and position are shown.

Figure 11.5. Example Chip Marking (Top View)

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Rev. 2.10 | 193

EFM32G Data Sheet

Chip Revision, Solder Information, Errata

12. Chip Revision, Solder Information, Errata

12.1 Chip Revision

The revision of a chip can be determined from the "Revision" field in the package marking.

12.2 Soldering Information

The latest IPC/JEDEC J-STD-020 recommendations for Pb-Free reflow soldering should be followed.

12.3 Errata

Please see the errata document for description and resolution of device errata. This document is available in Simplicity Studio and on-

line at: http://www.silabs.com/support/pages/document-library.aspx?p=MCUs--32-bit

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Rev. 2.10 | 194

EFM32G Data Sheet

Revision History

13. Revision History

13.1 Revision 2.10

July 19, 2017

In 4.8 General Purpose Input Output:

• Added missing multiply symbols.

In 4.10 Analog Digital Converter (ADC):

• Updated average active current.

• Updated SNR.

• Updated SINAD.

• Updated SFDR.

• Renamed VREF Output Voltage to VREF Voltage.

In 4.11 Digital Analog Converter (DAC):

• Renamed VREF Output Voltage to VREF Voltage.

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Rev. 2.10 | 195

EFM32G Data Sheet

Revision History

13.2 Revision 2.00

May 10th, 2017

Consolidated all EFM32G data sheets:

• EFM32G200

• EFM32G210

• EFM32G222

• EFM32G230

• EFM32G232

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G842

• EFM32G880

• EFM32G890

New formatting throughout.

Added 1. Feature List.

Updated ordering codes in 2. Ordering Information for Revision E and tape and reel.

Added Figure 2.1 Ordering Code Decoder on page 5.

Separated Memory Map figure into Figure 3.2 System Address Space with Core and Code Space Listing on page 27 and Figure

3.3 System Address Space with Peripheral Listing on page 28 for readability.

Removed footnote for storage temperature range in 4.2 Absolute Maximum Ratings.

In 4.6 Power Management:

• Updated EM0 condition for V_BODextthr-specification.

• Added V_BODextthr-in EM1 and EM2 specifications.

• Updated EM0 condition for V_BODextthr+specification.

Updated Flash page erase time and device erase time in 4.7 Flash and added footnotes.

Updated figures in 4.9.3 LFRCO.

Updated figures and HFRCO current consumption typical values in 4.9.4 HFRCO.

In 4.10 Analog Digital Converter (ADC):

• Updated test conditions, updated specifications, and added footnote for average active current.

• Added input bias current.

• Added input offset current.

• Updated ADC clock frequency.

• Updated SNR, SINAD and SFDR.

• Updated offset voltage.

• Updated missing codes.

• Added gain error drift and offset error drift.

• Added VREF output voltage, VREF voltage drift, VREF temperature drift, VREF current consumption, and ADC and DAC VREF

matching.

In 4.11 Digital Analog Converter (DAC):

• Updated I_DACparameter, test conditions, and footnote.

• Added DAC load current specification to 4.11 Digital Analog Converter (DAC).

• Added VREF output voltage, VREF voltage drift, VREF temperature drift, VREF current consumption, and ADC and DAC VREF

matching.

Updated ACMP active current (BIASPROG=0b1111, FULLBIAS=1 and HALFBIAS=0 in ACMPn_CTRL register) typical value in

4.12 Analog Comparator (ACMP).

Updated VCMP hysteresis typical value in 4.13 Voltage Comparator (VCMP).

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Rev. 2.10 | 196

EFM32G Data Sheet

Revision History

Corrected pin number for symbol P3 in Table 11.2 QFN32 PCB Land Pattern Dimensions (Dimensions in mm) on page 191.

Updated package marking figures to include temperature grade.

13.3 Revision 1.90

May 22nd, 2015

For devices with an ADC, Added clarification on conditions for INL_ADCand DNL_ADCparameters.

Corrected EM2 current consumption condition in Electrical Characteristics section.

Added AUXHFRCO to block diagram and Electrical Characteristics.

Updated HFRCO table in the Electrical Characteristics section.

Updated EM0, EM2, EM3, and EM4 maximum current specifications in the Electrical Characteristics section.

Updated the Output Low Voltage maximum for sinking 20 mA with VDD = 3.0 V in the Electrical Characteristics section.

Updated the Input Leakage Current maximum in the Electrical Characteristics section.

Updated the minimum and maximum frequency specifications for the LFRCO, HFRCO, and AUXHFRCO in the Electrical Characteris-

tics section.

Updated the maximum current consumption of the HFRCO in the Electrical Characteristics section.

Added some minimum ADC SNR, SNDR, and SFDR specifications in the Electrical Characteristics section.

Added some minimum and maximum ADC offset voltage, DNL, and INL specifications in the Electrical Characteristics section.

Added maximum DAC current specifications in the Electrical Characteristics section.

Added maximum ACMP current and maximum and minimum offset voltage specifications in the Electrical Characteristics section.

Added maximum VCMP current and updated typical VCMP current specifications in the Electrical Characteristics section.

Updated references to energyAware Designer to Configurator.

13.4 Revision 1.80

July 2nd, 2014

Corrected single power supply voltage minimum value from 1.85V to 1.98V.

Updated current consumption.

Updated transition between energy modes.

Updated power management data.

Updated GPIO data.

Updated LFXO, HFXO, HFRCO and ULFRCO data.

Updated LFRCO and HFRCO plots.

For devices with an ACMP, updated ACMP data.

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Rev. 2.10 | 197

EFM32G Data Sheet

Revision History

13.5 Revision 1.71

November 21st, 2013

Updated figures.

Updated errata-link.

Updated chip marking.

Added link to Environmental and Quality information.

For devices with a DAC, re-added missing DAC-data.

13.6 Revision 1.70

September 30th, 2013

For devices with an I2C, added I2C characterization data.

Corrected GPIO operating voltage from 1.8 V to 1.85 V.

For devices with an ADC, corrected the ADC resolution from 12, 10 and 6 bit to 12, 8 and 6 bit.

For QFN64 devices, updated the Max V_ESDCDMvalue to 750 V.

Updated Environmental information.

Updated trademark, disclaimer and contact information.

Other minor corrections.

13.7 Revision 1.60

June 28th, 2013

For BGA devices, updated PCB Land Pattern, PCB Solder Mask and PCB Stencil Design figures.

Updated power requirements in the Power Management section.

Removed minimum load capacitance figure and table. Added reference to application note.

Other minor corrections.

13.8 Revision 1.50

September 11th, 2012

Updated the HFRCO 1 MHz band typical value to 1.2 MHz.

Updated the HFRCO 7 MHz band typical value to 6.6 MHz.

For BGA devices, corrected BGA solder balls material from Sn96.5/Ag3/Cu0.5 to SAC105.

Other minor corrections.

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Rev. 2.10 | 198

EFM32G Data Sheet

Revision History

13.9 Revision 1.40

February 27th, 2012

Updated Power Management section.

Corrected operating voltage from 1.8 V to 1.85 V.

Corrected TGRAD_ADCTHparameter.

Corrected package drawing.

Updated PCB land pattern, solder mask and stencil design.

For LQFP48 devices, corrected available Pulse Counters from 3 to 2.

For LQFP48 devices, corrected available LEUARTs from 2 to 1.

For LQFP64 devices, corrected ordering codes in the ordering information table.

13.10 Revision 1.30

May 20th, 2011

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

Updated LFXO load capacitance section.

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Rev. 2.10 | 199

EFM32G Data Sheet

Revision History

13.11 Revision 1.20

December 17th, 2010

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

Increased max storage temperature.

Added data for <150°C and <70°C on Flash data retention.

Changed latch-up sensitivity test description.

Added IO leakage current.

For LQFP100 devices, updated ESD CDM value.

Added Flash current consumption.

Updated HFRCO data.

Updated LFRCO data.

Added graph for ADC Absolute Offset over temperature.

Added graph for ADC Temperature sensor readout.

13.12 Revision 1.11

November 17th, 2010

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

Corrected maximum DAC clock speed for continuous mode.

Added DAC sample-hold mode voltage drift rate.

Added pulse widths detected by the HFXO glitch detector.

Added power sequencing information to Power Management section.

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Rev. 2.10 | 200

EFM32G Data Sheet

Revision History

13.13 Revision 1.10

September 13th, 2010

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

For LQFP100 devices, corrected number of GPIO pins.

Added typical values for R_ADCFILTand C_ADCFILT

.

Added two conditions for DAC clock frequency; one for sample/hold and one for sample/off.

Added RoHS information and specified leadframe/solderballs material.

Added Serial Bootloader to feature list and system summary.

Updated ADC characterization data.

Updated DAC characterization data.

Updated RCO characterization data.

Updated ACMP characterization data.

Updated VCMP characterization data.

13.14 Revision 1.00

April 23rd, 2010

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

ADC_VCM line removed.

Added pinout illustration and additional pinout table.

Changed "Errata" chapter. Errata description moved to separate document.

Document changed status from "Preliminary".

Updated "Electrical Characteristics" chapter.

For EFM32G222

May 20th, 2011

Updated LFXO load capacitance section.

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Rev. 2.10 | 201

EFM32G Data Sheet

Revision History

13.15 Revision 0.90

This revision applies the following devices:

• EFM32G222

Initial preliminary revision, April 14th, 2011

This revision applies the following devices:

• EFM32G232

• EFM32G842

Initial preliminary revision, June 30th, 2011

13.16 Revision 0.85

February 19th, 2010

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

Renamed DBG_SWV pin to DBG_SWO.

13.17 Revision 0.84

February 11th, 2010

This revision applies the following devices:

• EFM32G230

• EFM32G840

Corrected pinout tables.

13.18 Revision 0.83

January 25th, 2010

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

Updated errata section.

Specified flash word width in Flash Electrical Characteristics.

Added Capacitive Sense Internal Resistor values in ACMP Electrical Characteristics.

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Rev. 2.10 | 202

EFM32G Data Sheet

Revision History

13.19 Revision 0.82

December 9th, 2009

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

For LQFP100 devices, incorrect pin 0 removed from pinout table.

Updated contact information.

ADC current consumption numbers updated in ADC Electrical Characteristics.

For devices with LCD, updated LCD supply voltage range in LCD Electrical Characteristics.

13.20 Revision 0.81

November 20th, 2009

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

For devices without a differential DAC, System Summary updated.

Electrical Characteristics updated.

Storage temperature in Electrical Characteristics updated.

Temperature coefficient of band-gap reference in Electrical Characteristics added.

Erase times in Flash Electrical Characteristics updated.

Definitions of DNL and INL added in ADC section.

For devices with and LCD, LCD Electrical Characteristics added.

Current consumption of digital peripherals added in Electrical Characteristics.

For LQFP100 devices, package information in Pinout and Package corrected.

For BGA112 devices, pinout information in Pinout table corrected.

Updated errata section.

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Rev. 2.10 | 203

EFM32G Data Sheet

Revision History

13.21 Revision 0.80

October 19th, 2009

This revision applies the following devices:

• EFM32G200

• EFM32G210

• EFM32G230

• EFM32G280

• EFM32G290

• EFM32G840

• EFM32G880

• EFM32G890

Initial preliminary revision

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Rev. 2.10 | 204

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wireless tools, documentation,

software, source code libraries &

more. Available for Windows,

Mac and Linux!

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Disclaimer

Silicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or

intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical"

parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes

without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included

information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted

hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of

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型号：	EFM32G210F128G-E-QFN32
厂家：	SILICON
描述：	RISC Microcontroller, 时钟微控制器外围集成电路
文件：	总205页 (文件大小：3175K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

EFM32G210F128G-E-QFN32 [SILICON]

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