CY28419ZXC_技术文档

CY28419

Clock Synthesizer with Differential SRC and CPU Outputs

• Four differential CPU clock pairs

• One differential SRC clock

• I²C support with readback capabilities

Features

• CK409B-compliant

• Supports Intel Pentium^4-type CPUs

• Selectable CPU frequencies

• 3.3V power supply

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 56-pin SSOP package

• Ten copies of PCI clocks

CPU

x 4

SRC

x 1

3V66

x 5

PCI

REF

x 2

48M

x 2

• Two copies 48 MHz clock

• Five copies of 3V66 with one optional VCH

x 10

[1]

Block Diagram

Pin Configuration

VDD_REF

REF0:1

REF_0

REF_1

VDD_REF

XIN

1

2

3

4

5

6

7

8

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

FS_B

VDD_A

VSS_A

VSS_IREF

IREF

FS_A

CPUT3

CPUC3

VDD_CPU

CPUT2

CPUC2

VSS_CPU

CPUT1

CPUC1

VDD_CPU

CPUT0

CPUC0

VSS_SRC

SRCT

SRCC

VDD_SRC

VTT_PWRGD#

VDD_48

VSS_48

DOT_48

USB_48

SDATA

3V66_4/VCH

XIN

XTAL

OSC

XOUT

PLL Ref Freq

VDD_CPU

CPUT(0:3), CPUC(0:3)

Divider

Network

PLL 1

XOUT

VDD_SRC

VSS_REF

PCIF0

PCIF1

SRCT, SRCC

FS_(A:B)

VTT_PWRGD#

PCIF2

9

IREF

VDD_PCI

VSS_PCI

PCI0

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VDD_3V66

3V66_(0:3)

PCI1

PCI2

PCI3

VDD_PCI

PCIF(0:2)

PLL2

2

PCI(0:6)

VDD_PCI

VSS_PCI

PCI4

3V66_4/VCH

PCI5

PCI6

PD#

VDD_48MHz

DOT_48

PD#

3V66_0

3V66_1

VDD_3V66

VSS_3V66

3V66_2

3V66_3

SCLK

USB_48

I²C

Logic

SDATA

SCLK

SSOP-56

Note:

1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.

Rev 1.0, November 22, 2006

Page 1 of 15

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555

Fax:(408) 855-0550

www.SpectraLinear.com

CY28419

Pin Description

Pin No.

1,2

Pin Name

Pin Type

Pin Description

REF(0:1)

XIN

O, SE Reference Clock. 3.3V 14.318-Mz clock output.

4

I

Crystal Connection or External Reference Frequency Input. This pin has dual

functions. It can be used as an external 14.318-MHz crystal connection or as an

external reference frequency input.

5

XOUT

O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output.

41,44,47,50 CPUT(0:3)

O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency config-

uration.

40,43,46,49 CPUC(0:3)

O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency config-

uration.

38, 37

SRCT, SRCC

O, DIF Differential serial reference clock.

22,23,26,27 3V66(3:0)

O, SE 66 MHz Clock Output. 3.3V 66-MHz clock from internal VCO.

O, SE 48/66 MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz.

O, SE Free Running PCI Output. 33-MHz clocks divided down from 3V66.

O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66.

29

3V66_4VCH

PCIF(0:2)

7,8,9

12,13,14,15, PCI(0:6)

18,19,20

31,

32

USB_48

DOT_48

FS_A, FS_B

IREF

O, SE Fixed 48 MHz clock output.

51,56

52

I

3.3V LVTTL input for CPU frequency selection.

Current Reference. A precision resistor is attached to this pin which is connected to

the internal current reference.

21

35

PD#

I, PU

I

3.3V LVTTL input for power-down# active LOW.

VTT_PWRGD#

3.3V LVTTL input is a level-sensitive strobe used to latch the FS0 input (active

LOW).

30

SDATA

I/O

SMBus-compatible SDATA.

SMBus-compatible SCLOCK.

Ground for current reference.

3.3V power supply for PLL.

Ground for PLL.

28

SCLK

I

53

VSS_IREF

VDD_A

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

55

54

VSS_A

42,48

45

VDD_CPU

VSS_CPU

VDD_SRC

VSS_SRC

VDD_48

3.3V power supply for outputs.

Ground for outputs.

36

3.3V power supply for outputs.

Ground for outputs.

39

34

3.3V power supply for outputs.

Ground for outputs.

33

VSS_48

10,16

11,17

24

VDD_PCI

VSS_PCI

VDD_3V66

VSS_3V66

VDD_REF

VSS_REF

3.3V power supply for outputs.

Ground for outputs.

3.3V power supply for outputs.

Ground for outputs.

25

3

3.3V power supply for outputs.

Ground for outputs.

6

Rev 1.0,November 22, 2006

Page 2 of 15

CY28419

VTT_PWRGD# has been sampled low, all further

VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In

the case where FS_B is at mid level when VTT_PWRGD# is

sampled low, the clock chip will assume “Test Clock Mode”.

Once “Test Clock Mode” has been invoked, all further FS_B

transitions will be ignored and FS_A will asynchronously

select between the Hi-Z and REF/N mode. Exiting test mode

is accomplished by cycling power with FS_B in a high or low

state.

Frequency Select Pins (FS_A, FS_B)

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A and FS_B inputs prior to

VTT_PWRGD# assertion (as seen by the clock synthesizer).

Upon VTT_PWRGD# being sampled low by the clock chip

(indicating processor VTT voltage is stable), the clock chip

samples the FS_A and FS_B input values. For all logic levels

of FS_A and FS_B except MID, VTT_PWRGD# employs a

one-shot functionality in that once

a

valid low on

Table 1. Frequency Select Table (FS_A FS_B)

FS_A

FS_B

0

CPU

SRC

3V66

66 MHz

REF/N

66 MHz

Hi-Z

PCIF/PCI

33 MHz

REF/N

33 MHz

Hi-Z

REF0

14.3 MHz

REF/N

REF1

14.31 MHz

REF/N

USB/DOT

48 MHz

REF/N

0

1

100 MHz

REF/N

100/200 MHz

REF/N

MID

1

200 MHz

133 MHz

166 MHz

Hi-Z

100/200 MHz

Hi-Z

14.3 MHz

Hi-Z

14.31 MHz

Hi-Z

48 MHz

Hi-Z

0

1

MID

Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1

FS_A

FS_B

CPU

SRC

3V66

PCIF/PCI

33 MHz

REF0

REF1

USB/DOT

48 MHz

0

1

0

1

0

1

200 MHz

400 MHz

266 MHz

333 MHz

100/200 MHz

66 MHz

14.3 MHz

14.31 MHz

first) with the ability to stop after any complete byte has been

transferred. For byte write and byte read operations, the sys-

tem controller can access individually indexed bytes. The off-

set of the indexed byte is encoded in the command code, as

described in Table 3.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initializes to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

The block write and block read protocol is outlined in Table 4

while Table 5 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Table 3. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte

read or byte write operation

Data Protocol

(6:0)

Byte offset for byte read or byte write operation.

For block read or block write operations, these bits

should be '0000000'

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in se-

quential order from lowest to highest byte (most significant bit

Table 4. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

2:8

9

Slave address – 7 bits

Write = 0

2:8

9

Slave address – 7 bits

Write = 0

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code – 8 bits

'00000000' stands for block operation

11:18

Command Code – 8 bits

'00000000' stands for block operation

Rev 1.0,November 22, 2006

Page 3 of 15

CY28419

Table 4. Block Read and Block Write Protocol (continued)

Block Write Protocol

Block Read Protocol

Acknowledge from slave

19

20:27 Byte Count – 8 bits

28 Acknowledge from slave

29:36 Data byte 1 – 8 bits

37 Acknowledge from slave

38:45 Data byte 2 – 8 bits

Acknowledge from slave

19

20

Repeat start

21:27

28

Slave address – 7 bits

Read = 1

29

Acknowledge from slave

Byte count from slave – 8 bits

Acknowledge from master

Data byte from slave – 8 bits

Acknowledge from master

Data byte from slave – 8 bits

Acknowledge from master

Data byte N from slave – 8 bits

Acknowledge from master

Stop

30:37

38

46

....

Acknowledge from slave

......................

39:46

47

Data Byte (N–1) –8 bits

Acknowledge from slave

Data Byte N –8 bits

Acknowledge from slave

Stop

48:55

56

....

Table 5. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

2:8

9

Slave address – 7 bits

Write = 0

2:8

9

Slave address – 7 bits

Write = 0

10

Acknowledge from slave

10

Acknowledge from slave

11:18

Command Code – 8 bits

11:18

Command Code – 8 bits

'100xxxxx' stands for byte operation, bits[6:0] of the

command code represents the offset of the byte to

be accessed

'100xxxxx' stands for byte operation, bits[6:0] of

the command code represents the offset of the

byte to be accessed

19

20:27

28

Acknowledge from slave

Data byte from master – 8 bits

Acknowledge from slave

Stop

19

20

Acknowledge from slave

Repeat start

21:27

28

Slave address – 7 bits

Read = 1

29

Acknowledge from slave

Data byte from slave – 8 bits

Acknowledge from master

Stop

30:37

38

39

Rev 1.0,November 22, 2006

Page 4 of 15

CY28419

Byte 0: Control Register 0

Bit

7

@Pup

Name

Description

0

1

0

1

Reserved

6

5

4

3

2

1

Externally FS_B

Selected

FS_B reflects the value of the FS_B pin sampled on power-up.

0 = FS_B low at power-up

0

Externally FS_A

Selected

FS_A reflects the value of the FS_A pin sampled on power-up.

0 = FS_A low at power-up

Byte 1: Control Register 1

Bit

@Pup

Name

SRCT, SRCC

Description

7

0

Allow control of SRCT/C with assertion of PCI_STP#

0 = Free Running, 1 = Stopped with PCI_STP#

6

1

SRCT, SRCC

SRCT/C Output Enable

0 = Disabled (three-state), 1 = Enabled

5

4

3

2

1

Reserved

CPUT2, CPUC2

CPUT/C2 Output Enable

0 = Disabled (three-state), 1 = Enabled

1

0

1

CPUT1, CPUC1

CPUT0, CPUC0

CPUT/C1 Output Enable,

0 = Disabled (three-state), 1 = Enabled

CPUT/C0 Output Enable

0 = Disabled (three-state), 1 = Enabled

Byte 2: Control Register 2

Bit

@Pup

Name

SRCT, SRCC

Description

7

0

SRCT/C Pwrdwn drive mode

0 = Driven in power-down, 1 = Three-state in power-down

6

5

4

3

0

SRCT, SRCC

SRCT/C Stop drive mode

0 = Driven in PCI_STP, 1 = Three-state in power-down

CPUT2, CPUC2

CPUT1, CPUC1

CPUT0, CPUC0

CPUT/C2 Pwrdwn drive mode

0 = Driven in power-down, 1 = Three-state in power-down

CPUT/C1 Pwrdwn drive mode

0 = Driven in power-down, 1 = Three-state in power-down

CPUT/C0 Pwrdwn drive mode

0 = Driven in power-down, 1 = Three-state in power-down

2

1

0

Reserved

Rev 1.0,November 22, 2006

Page 5 of 15

CY28419

Byte 3: Control Register 3

Bit @Pup Name

Description

7

1

All PCI and SRC Clock outputs PCI_STP Control. 0 = SW PCI_STP not enabled and only the PCI_STP# pin will

except PCIF and SRC clocks stop the PCI stop enabled outputs, 1 = the PCI_STP function is enabled and the

set to free-running

stop enabled outputs will be stopped in a synchronous manner with no short pulses.

6

5

4

3

2

1

0

1

PCI6

PCI6 Output Enable

0 = Disabled, 1 = Enabled

PCI5

PCI4

PCI3

PCI2

PCI1

PCI0

PCI5 Output Enable

0 = Disabled, 1 = Enabled

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2 Output Enable

0 = Disabled, 1 = Enabled

PCI1 Output Enable

0 = Disabled, 1 = Enabled

PCI0 Output Enable

0 = Disabled, 1 = Enabled

Byte 4: Control Register 4

Bit

@Pup

Name

USB_ 48MHz

Description

7

0

USB_48 Drive Strength

0 = High drive strength, 1 = Normal drive strength

6

5

4

3

2

1

0

1

0

1

USB_ 48MHz

PCIF2

USB_48 Output Enable

0 = Disabled, 1 = Enabled

Allow control of PCIF2 with assertion of PCI_STP#

0 = Free Running, 1 = Stopped with PCI_STP#

PCIF1

Allow control of PCIF1 with assertion of PCI_STP#

0 = Free Running, 1 = Stopped with PCI_STP#

PCIF0

Allow control of PCIF0 with assertion of PCI_STP#

0 = Free Running, 1 = Stopped with PCI_STP#

PCIF2

PCIF2 Output Enable

0 = Disabled, 1 = Enabled

PCIF1

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

PCIF0

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

1

DOT_48

DOT_48 Output Enable

0 = Disabled, 1 = Enabled

6

5

1

0

CPUT3, CPUC3

3V66_4/VCH

0 = three-state, 1 = Enabled

VCH Select 66 MHz/48 MHz

0 = 3V66 mode, 1 = VCH (48MHz) mode

4

3

2

1

0

1

3V66_4/VCH

3V66_3

3V66_4/VCH Output Enable

0 = Disabled, 1 = Enabled

3V66_3 Output Enable

0 = Disabled, 1 = Enabled

3V66_2

3V66_2 Output Enable

0 = Disabled, 1 = Enabled

3V66_1

3V66_1 Output Enable

0 = Disabled, 1 = Enabled

3V66_0

3V66_0 Output Enable

0 = Disabled, 1 = Enabled

Rev 1.0,November 22, 2006

Page 6 of 15

CY28419

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

REF

PCIF

Test Clock Mode

0= Disabled, 1 = Enabled

PCI

3V66

USB_48

DOT_48

CPUT/C

SRCT/C

6

5

0

Reserved, Set = 0

CPUC0, CPUT0

CPUC1, CPUT1

CPUC2, CPUT2

CPUC3, CPUT3

FS_A & FS_B Operation

0 = Normal, 1 = Test mode

4

0

SRCT, SRCC

SRC Frequency Select

0 = 100 MHz, 1 = 200 MHz

3

2

0

Reserved, Set = 0

PCIF

PCI

Spread Spectrum Mode

0 = Spread Off, 1 = Spread On

3V66

SRC(T/C)

CPUT/ C

1

0

1

REF_1

REF_1 Output Enable

0 = Disabled, 1 = Enabled

REF_0

REF_0 Output Enable

0 = Disabled, 1 = Enabled

Byte 7: Vendor ID

Bit @Pup

Name

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

Description

7

6

5

4

3

2

1

0

1

0

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

Vendor ID Bit 2

Vendor ID Bit 1

Vendor ID Bit 0

Crystal Recommendations

The CY28419 requires a Parallel Resonance Crystal.

Substituting a series resonance crystal will cause the

CY28419 to operate at the wrong frequency and violate the

ppm specification. For most applications there is a 300-ppm

frequency shift between series and parallel crystals due to

incorrect loading.

Table 6. Crystal Recommendations

Frequency

(Fund)

Drive

(max.)

Shunt Cap Motional

(max.)

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

Cut

Loading Load Cap

Parallel 20 pF

(max.)

14.31818 MHz

AT

0.1 mW

5 pF

0.016 pF

50 ppm

5 ppm

Rev 1.0,November 22, 2006

Page 7 of 15

CY28419

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the total capac-

itance on each side of the crystal must be twice the specified

load capacitance(CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capac-

itors(Ce1,Ce2) should be calculated to provide equal capaci-

tative loading on both sides.

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low-ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

The following diagram shows a typical crystal configuration

using the two trim capacitors. An important clarification for the

following discussion is that the trim capacitors are in series

with the crystal not parallel. It’s a common misconception that

load capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

Use the following formulas to calculate the trim capacitor

values fro Ce1 and Ce2.

Load Capacitance (each side)

Ce = 2 * CL – (Cs + Ci)

Total Capacitance (as seen by the crystal)

1

CLe

=

1

Ce2 + Cs2 + Ci2

1

Ce1 + Cs1 + Ci1

(

)

+

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

..................................... using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs........................................... Stray capacitance (trace, etc.)

Figure 1. Crystal Capacitive Clarification

Ci ...........................................................Internalcapacitance

................................................ (lead frame, bond wires, etc.)

Calculating Load Capacitors

PD# (Power-down) Clarification

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

The PD# pin is used to shut off all clocks and PLLs without

having to remove power from the device. All clocks are shut

down in a synchronous manner so has not to cause glitches

while transitioning to the power-down state.

PD#–Assertion

When PD# is sampled low by two consecutive rising edges of

the CPUC clock then all clock outputs (except CPU) clocks

must be held low on their next high to low transition. CPU

clocks must be held with CPUT clock pin driven high with a

value of 2x Iref and CPUC undriven as the default condition.

There exists an I2C bit that allows for the CPUT/C outputs to

be three-stated during power-down. Due to the state of internal

logic, stopping and holding the REF clock outputs in the LOW

state may require more than one clock cycle to complete.

Clock Chip

(CY28419)

Ci2

Ci1

3 to 6p

X2

X1

Cs2

Cs1

Trace

2.8pF

XTAL

Ce1

Ce2

Trim

33pF

Figure 2. Crystal Loading Example

Rev 1.0,November 22, 2006

Page 8 of 15

CY28419

PD#

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF

Figure 3. Power-down Assertion Timing Waveforms

PD# Deassertion

The power-up latency between PD# rising to a valid logic ‘1’

level and the starting of all clocks is less than 1.8 ms. The

CPUT/C outputs must be driven to greater than 200 mV is less

than 300 us.

Tstable

<1.8ms

PD#

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

3V66, 66MHz

USB, 48MHz

PCI, 33MHz

REF

Tdrive_PWRDN#

<300µS, >200mV

Figure 4. Power-down Deassertion Timing Waveforms

Rev 1.0,November 22, 2006

Page 9 of 15

CY28419

FS_A, FS_B

VTT_PWRGD#

PWRGD_VRM

0.2-0.3mS

Delay

Wait for

VTT_PWRGD#

Device is not affected,

VTT_PWRGD# is ignored

Sample Sels

State 2

VDD Clock Gen

Clock State

State 0

Off

State 1

State 3

On

Clock Outputs

Clock VCO

On

Off

Figure 5. VTTPWRGD Timing Diagram

S2

S1

VTT_PWRGD# = Low

Delay

>0.25mS

Sample

Inputs straps

VDD_A = 2.0V

Wait for <1.8ms

S0

S3

VDD_A = off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 6. Clock Generator Power-up/Run State Diagram

Rev 1.0,November 22, 2006

Page 10 of 15

CY28419

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Condition

Min.

–0.5

–65

0

Max.

Unit

V

4.6

V_{DD_A}

V_IN

Analog Supply Voltage

Input Voltage

V

Relative to V _SS

V_DD+ 0.5

+150

70

VDC

°C

T_S

Temperature, Storage

Non-functional

T_A

Temperature, Operating Ambient

Temperature, Junction

Functional

°C

T_J

Functional

–

150

15

°C

Ø_JC

Dissipation, Junction to Case

Dissipation, Junction to Ambient

Mil-Spec 883E Method 1012.1

JEDEC (JESD 51)

–

°C/W

V

Ø_JA

–

45

ESD_HBM

UL-94

MSL

ESD Protection (Human Body Model) MIL-STD-883, Method 3015

2000

–

Flammability Rating

At 1/8 in.

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing

is NOT required.

DC Electrical Specifications

Parameter

Description

Conditions

Min.

Max.

Unit

V

V_DD, V_{DD_A}3.3 Operating Voltage

3.3V 5%

3.135

3.465

V_ILI2C

V_IHI2C

V_IL

Input Low Voltage

SDATA, SCLK

–

1.0

V

Input High Voltage

Input Low Voltage

2.2

–

V

V_SS– 0.5

0.8

V

V_IH

Input High Voltage

Input Leakage Current

Input High Voltage

Output Low Voltage

Output High Voltage

High-impedance Output Current

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

2.0

V_DD+ 0.5

V

I_IL

except Pull-ups or Pull-downs 0 < V_IN< V_DD

–5

5

–

µA

V

I_ILI2C

V_OL

V_OH

I_OZ

SDATA, SCLK

I_OL= 1 mA

2.2

–

0.4

–

V

I_OH= –1 mA

2.4

V

–10

10

µA

pF

nH

V

C_IN

2

5

C_OUT

L_IN

3

6

–

7

V_XIH

V_XIL

I_DD

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

280

Xin Low Voltage

0

–

V

Dynamic Supply Current

At 200 MHz and all outputs loaded per Table 9

and Figure 7

mA

I_PD

Power-down Supply Current

PD# asserted, Outputs Three-stated

–

1

mA

Unit

%

AC Electrical Specifications

Parameter

Description

Conditions

Min.

47.5

Max.

52.5

Crystal

T_DC

XIN Duty Cycle

The device will operate reliably with input duty

cycles up to 30/70 but the REF clock duty cycle

will not be within specification

T_PERIOD

T_R/ T_F

T_CCJ

XIN Period

When XIN is driven from an external clock source 69.841

71.0

10.0

500

300

ns

XIN Rise and Fall Times

XIN Cycle-to-Cycle Jitter

Long-term Accuracy

Measured between 0.3V_DDand 0.7V_DD

As an average over 1-µs duration

Over 150 ms

–

ps

L_ACC

ppm

Rev 1.0,November 22, 2006

Page 11 of 15

CY28419

AC Electrical Specifications (continued)

Parameter

Description

Conditions

Min.

Max.

Unit

CPU at 0.7V

T_DC

CPUT and CPUC Duty Cycle

Measured at crossing point V_OX

45

9.9970

7.4978

5.9982

4.9985

–

55

10.003

7.5023

6.0018

5.0015

100

%

ns

ps

%

T_PERIOD

T_SKEW

T_CCJ

100-MHz CPUT and CPUC Period Measured at crossing point V_OX

133-MHz CPUT and CPUC Period Measured at crossing point V_OX

166-MHz CPUT and CPUC Period Measured at crossing point V_OX

200-MHz CPUT and CPUC Period Measured at crossing point V_OX

Any CPU to CPU Clock Skew

CPU Cycle-to-Cycle Jitter

Measured at crossing point V_OX

–

125

T_R/T_F

T_RFM

CPUT/CPUC Rise and Fall Times Measured from V_OL= 0.175 to V_OH= 0.525V

175

–

700

Rise/Fall Matching

Rise Time Variation

Fall Time Variation

Voltage High

Determined as a fraction of 2*(T_R–T_F)/ (T_R+T_F)

20

∆T_R

–

125

ps

mv

∆T_F

–

125

V_HIGH

V_LOW

V_OX

Math average, see Figure 7

660

–150

850

Voltage Low

–

Crossing Point voltage at 0.7V

Swing

250

550

mv

V_OVS

V_UDS

V_RB

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

–

–0.3

–

V_HIGH+ 0.3

V

–

See Figure 7. Measure SE

0.2

SRC

T_DC

SRCT and SRCC Duty Cycle

Measured at crossing point V_OX

45

9.9970

4.9985

–

55

10.003

5.0015

125

300

700

20

%

ns

T_PERIOD

T_CCJ

100-MHz SRCT and SRCC Period Measured at crossing point V_OX

200-MHz SRCT and SRCC Period Measured at crossing point V_OX

ns

SRC Cycle-to-Cycle Jitter

Measured at crossing point V_OX

ps

L_ACC

SRCT/C Long-term Accuracy

–

ppm

ps

T_R/ T_F

T_RFM

∆T_R

SRCT/SRCT\C Rise and Fall Times Measured from V_OL= 0.175 to V_OH= 0.525V

175

–

Rise/Fall Matching

Rise Time Variation

Fall Time Variation

Voltage High

Determined as a fraction of 2*(T_R–T_F)/ (T_R+T_F)

%

–

125

850

–

ps

∆T_F

–

ps

V_HIGH

V_LOW

V_OX

Math average, see Figure 7

660

–150

mv

Voltage Low

Crossing Point Voltage at 0.7V

Swing

250

550

mV

V_OVS

V_UDS

V_RB

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

–

–0.3

–

V_HIGH+0.3

V

–

See Figure 7. Measure SE

0.2

3V66

T_DC

3V66 Duty Cycle

Measurement at 1.5V

Measurement at 2.0V

Measurement at 0.8V

Measured between 0.8V and 2.0V

45

55

%

ns

ps

T_PERIOD

T_HIGH

Spread Disabled 3V66 Period

Spread Enabled 3V66 Period

3V66 High Time

14.9955 15.0045

14.9955 15.0799

4.9500

–

T_LOW

3V66 Low Time

4.5500

–

T_R/ T_F

T_SKEW

T_CCJ

3V66 Rise and Fall Times

0.5

–

2.0

250

Any 3V66 to Any 3V66 Clock Skew Measurement at 1.5V

3V66 Cycle-to-Cycle Jitter Measurement at 1.5V

–

Rev 1.0,November 22, 2006

Page 12 of 15

CY28419

AC Electrical Specifications (continued)

Parameter

Description

Conditions

Min.

Max.

Unit

PCI / PCIF

T_DC

PCIF and PCI Duty Cycle

Measurement at 1.5V

45

55

%

ns

nS

T_PERIOD

T_HIGH

Spread Disabled PCIF/PCI Period Measurement at 1.5V

Spread Enabled PCIF/PCI Period Measurement at 1.5V

29.9910 30.0009

29.9910 30.1598

PCIF and PCI High Time

PCIF and PCI Low Time

Measurement at 2.0V

12.0

0.5

–

T_LOW

Measurement at 0.8V

T_R/ T_F

T_SKEW

PCIF and PCI rise and fall times

Measured between 0.8V and 2.0V

Measurement at 1.5V

2.0

Any PCI Clock to Any PCI Clock

Skew

–

500

250

pS

ps

T_CCJ

PCIF and PCI Cycle-to-Cycle Jitter Measurement at 1.5V

DOT

T_DC

DOT Duty Cycle

DOT Period

Measurement at 1.5V

Measurement at 2.0V

Measurement at 0.8V

Measured between 0.8V and 2.0V

10-µs period

45

55

%

ns

nS

ns

T_PERIOD

T_HIGH

T_LOW

20.8257 20.8340

DOT High Time

DOT Low Time

Rise and Fall Times

Long-term Jitter

8.994

8.794

0.5

10.486

10.386

1.0

T_R/ T_F

T_LTJ

–

2.0

USB

T_DC

USB Duty Cycle

USB Period

Measurement at 1.5V

Measurement at 2.0V

Measurement at 0.8V

Measured between 0.8V and 2.0V

125-µs period

45

55

%

ns

nS

ns

T_PERIOD

T_HIGH

T_LOW

20.8257 20.8340

USB High Time

USB Low Time

Rise and Fall Times

Long-term Jitter

8.094

7.694

1.0

10.036

9.836

2.0

T_R/ T_F

T_LTJ

–

6.0

REF

T_DC

REF Duty Cycle

Measurement at 1.5V

45

69.827

1.0

55

69.855

4.0

%

ns

T_PERIOD

T_R/ T_F

T_CCJ

REF Period

Measurement at 1.5V

REF Rise and Fall Times

REF Cycle-to-Cycle Jitter

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

–

1000

ENABLE/DISABLE and SET-UP

T_STABLEClock Stabilization from Power-up

T_SS

–

10.0

0

1.8

–

ms

ns

Stopclock Set-up Time

Stopclock Hold Time

T_SH

–

Table 7. Group Timing Relationship and Tolerances

Offset

Table 9. Maximum Lumped Capacitive Output Loads

Clock

Max Load

Unit

pF

Group

Conditions

Min.

Max.

PCI Clocks

3V66 Clocks

USB Clock

DOT Clock

REF Clock

30

20

10

30

3V66 to PCI

3V66 Leads PCI

1.5 ns 3.5 ns

pF

Table 8. USB to DOT Phase Offset

pF

Parameter

DOT Skew

USB Skew

VCH SKew

Typical

0°

Value

0.0ns

Tolerance

1000 ps

pF

180°

0°

Rev 1.0,November 22, 2006

Page 13 of 15

CY28419

Test and Measurement Set-up

For Differential CPU and SRC Output Signals

The following diagram shows lumped test load configurations

for the differential Host Clock Outputs.

M e a s u re m e n t

P o in t

T _{P C B}

3 3 Ω

C P U T

4 9 .9 Ω

2 p F

M e a s u re m e n t

P o in t

2 p F

T _{P C B}

4 9 .9 Ω

3 3 Ω

C P U C

IR E F

4 7 5 Ω

Figure 7. 0.7V Load Configuration

3.3V signals

tDC

-

3.3V

2.0V

1.5V

0.8V

0V

Tr

Tf

Figure 8. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)

Table 10.CPU Clock Current Select Function

Board Target Trace/Term Z

Reference R, Iref – V_DD(3*Rr)

Output Current

Voh @ Z

50 Ohms

R_REF= 475 1%, I_REF= 2.32 mA

Ioh = 6*Iref

0.7V @ 50

Ordering Information

Part Number

Package Type

Product Flow

CY28419OC

CY28419OCT 56-pin Shrunk Small Outline package (SSOP) – Tape and Reel

CY28419ZC 56-pin Thin Shrunk Small Outline package (TSSOP)

CY28419ZCT 56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel

Part Number Package Type - Lead Free

56-pin Shrunk Small Outline package (SSOP)

Commercial, 0° to 70°C

Product Flow

CY28419OXC 56-pin Shrunk Small Outline package (SSOP)

Commercial, 0° to 70°C

CY28419OXCT 56-pin Shrunk Small Outline package (SSOP) – Tape and Reel

CY28419ZXC 56-pin Thin Shrunk Small Outline package (TSSOP)

CY28419ZXCT 56-pin Thin Shrunk Small Outline package (TSSOP) – Tape and Reel

Rev 1.0,November 22, 2006

Page 14 of 15

CY28419

Package Drawing and Dimensions

56-Lead Shrunk Small Outline Package O56

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 14 mm) Z56

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, November 22, 2006

Page 15 of 15


型号：	CY28419ZXC
厂家：	SILICON
描述：	Processor Specific Clock Generator, 400MHz, CMOS, PDSO56, 6 X 14 MM, LEAD FREE, TSSOP-56 时钟光电二极管外围集成电路晶体
文件：	总15页 (文件大小：177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY28419ZXC [SILICON]

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