CY28435 [CYPRESS]
Clock Generator for Intel Grantsdale Chipset; 时钟发生器Intel的Grantsdale芯片组
| 型号： | CY28435 |
| 厂家： | 
CYPRESS |
| 描述： | Clock Generator for Intel Grantsdale Chipset |
| 文件： | 总23页 (文件大小：306K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CY28435
PRELIMINARY
Clock Generator for Intel Grantsdale Chipset
• Dial-A-Frequency
• Watchdog
• Two Independent Overclocking PLLs
Features
• Compliant to Intel CK410
• Supports Intel Prescott and Tejas CPU
• Selectable CPU frequencies
• Differential CPU clock pairs
• 100-MHz differential SRC clocks
• 96-MHz differential dot clock
• 48-MHz USB clocks
• Low-voltage frequency select input
• I2C support with readback capabilities
• Ideal Lexmark Spread Spectrum profile for maximum
electromagnetic interference (EMI) reduction
• 3.3V power supply
• 56-pin SSOP and TSSOP packages
• 33-MHz PCI clock
• Dynamic Frequency Control
CPU
x 2
SRC
x 7
PCI
x 9
REF
x 2
DOT96
x 1
USB
x 2
Block Diagram
Pin Configuration
VDD_RE
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDD_PCI
VSS_PCI
DF2/PCI3
*FS_E/PCI4
PCI5
VSS_PCI
PCI2/DF1
PCI1/DF0
F
Xin
Xout
14.318MHz
RE
F
Crystal
PCI0/SRESET#
REF1/**FS_C
REF0/**FS_D
VSS_REF
XIN
XOUT
VDD_REF
PLL Reference
IREF
VDD_CPU
CPUT
CPUC
VDD_PCI
**DF_EN/PCIF0
**SRESET_EN/PCIF1
CPU
Divider
PLL
VDD_CPU
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PCIF2
VDD_48
USB48_0
VSS_48
DOT96T
SDATA
SCLK
FS_[E:A]
ITP_EN
VDD_SRC
VSS_CPU
CPUT0
CPUC0
VDD_CPU
CPUT1
CPUC1
IREF
SRCT
SRCC
SRC
Divider
PLL
DOT96C
VDD_SRC
*FS_B/USB48_1
**VTTPWRGD#/PD
**FS_A
VDD_SRC
SRCT1
SRCC1
VDD_SRC
SRCT2
SRCC2
VSSA
VDDA
SDATA
Divider
PLL
SRCT4_SATA
SRCC4_SATA
SRCT7
SRCC7
VDD_SRC
SRCT6
SRCC6
SRCT5
VDD_48Mhz
SRCT3
FIX
DOT96T
DOT96C
Divider
PLL
SRCC3
SRCT4_SATA
SRCC4_SATA
VDD_SRC
VDD_48
USB
SRCC5
VSS_SRC
VTTPWR_GD#/PD
VDD_PCI
PCI
* indicates internal pull-up
** indicates internal pull-down
DF_EN
VDD_PCI
Dynamic
DF[2:0]
PCIF
Frequency
Watchdog
Timer
I2C
SDATA
SCLK
SRESET#
Logic
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-07664 Rev. *B
Revised December 21, 2004
CY28435
PRELIMINARY
Pin Description
Pin No.
1,7
2,6
Name
VDD_PCI
VSS_PCI
Type
Description
PWR 3.3V power supply for outputs.
GND Ground for outputs.
3,55,56
4
DF/PCI
FS_E/PCI4
I/O, SE 3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output.
I/O,PU, 3.3V-tolerant input for CPU frequency selection/33-MHz clock.
SE
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
5
8
PCI
DF_EN/PCIF0
O, SE 33-MHz clock.
I/O,SE, 3.3V LVTTL input to enable Dynamic Frequency input/33-MHz clock output.
PD (sampled on the VTT_PWRGD# assertion).
1 = Enable, 0 = Disable
9
SRESET_EN/PCIF I/O,SE, 3.3V LVTTL input to enable Watchdog/33-MHz clocks.
1
PD 1 = Enable, 0 = Disable
10
17
PCIF2
O, SE 33-MHz clocks.
VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C,FS_D and FS_E inputs. After VTT_PWRGD# (active LOW) assertion,
this pin becomes a real-time input for asserting power down (active HIGH).
11
12
18
VDD_48
USB48_0
FS_A
PWR 3.3V power supply for outputs.
48-MHz clock output.
O
I, PD 3.3V-tolerant input for CPU frequency selection.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
13
VSS_48
GND Ground for outputs.
14,15
16
DOT96T, DOT96C O, DIF Fixed 96-MHz clock output.
FS_B/USB48_1 I/O,PU, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
19,20,22,23, SRCT/C
O, DIF Differential serial reference clocks. Outputs have overclocking capability.
24,25,30,31,
32,33,36, 35
21,28,34
26,27
VDD_SRC
PWR 3.3V power supply for outputs.
O, DIF Differential serial reference clock. Recommended output for SATA.
SRC4_SATAT,
SRC4_SATAC
29
37
38
39
VSS_SRC
VDDA
VSSA
GND Ground for outputs.
PWR 3.3V power supply for PLL.
GND Ground for PLL.
IREF
I
A precision resistor is attached to this pin, which is connected to the internal
current reference.
42
VDD_CPU
PWR 3.3V power supply for outputs.
O, DIF Differential CPU clock outputs.
GND Ground for outputs.
41,40,44,43 CPUT/C
45
46
47
48
49
50
51
52
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
I
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
I/O
PWR 3.3V power supply for outputs.
O, SE 14.318-MHz crystal output.
I
14.318-MHz crystal input.
VSS_REF
FS_D/REF0
GND Ground for outputs.
I/O, SE, 3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Document #: 38-07664 Rev. *B
Page 2 of 23
CY28435
PRELIMINARY
Pin Description (continued)
Pin No.
Name
Type
Description
53
FS_C/REF1
I/O, 3.3V-tolerant input for CPU frequency selection/Reference clock.
PD Selects test mode if pulled to VIHFS_C when VTT_PWRGD# is asserted LOW.
Refer to DC Electrical Specifications table for VILFS_C,VIMFS_C,VIHFS_C specifica-
tions.
54
SRESET#/PCI0
O, PU 3.3V LVTTL output for Watchdog reset/33-MHz clock output.
When configured as SRESET# output this output becomes open drain type with a
high (>100 kΩ) internal pull-up resistor.
been sampled, all further VTT_PWRGD#, FS_A, FS_B,
Frequency Select Pins (FS_[A:E])
FS_C,FS_D and FS_E transitions will be ignored, except in
test mode.
Host clock frequency selection is achieved by applying the
appropriate logic levels to FS_A, FS_B, FS_C,FS_D and
FS_E inputs prior to VTT_PWRGD# assertion (as seen by the
clock synthesizer). Upon VTT_PWRGD# being sampled LOW
by the clock chip (indicating processor VTT voltage is stable),
the clock chip samples the FS_A, FS_B, FS_C,FS_D and
FS_E input values. For all logic levels of FS_A, FS_B,
FS_C,FS_D and FS_E, VTT_PWRGD# employs a one-shot
functionality in that once a valid low on VTT_PWRGD# has
FS_C is a three level input, when sampled at a voltage greater
than 2.1V by VTTPWRGD#, the device will enter test mode as
selected by the voltage level on the FS_B input.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
No Spread Spectrum and Center spread spectrum on CPU PLL
Input Conditions
Output Frequency
FS_E
FS_D
FS_C FS_B
FS_A
CPU
SRC
CPU PLL CPU M
CPU N
CPU N
SRC PLL
Gear
SRC M
Gear
Constant
s
divider DEFAULT allowable
divider (not
range for Constants changeable
DAF
by user)
HW only FSEL_3 FSEL_2 FSEL_1 FSEL_0
(MHz)
(MHz)
(G)
FS_5
(byte 16
bit 5)
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
1
1
100
133.3333333
166.6666667
200
266.6666667
333.3333333
400
100.952381
133.968254
167
200.952381
266.6666667
334
400.6451613
100
133.33
166.67
200
266.67
333.33
400
100.95
133.97
166.98
200.95
266.67
333.97
400.65
100
133.33
166.67
200
266.67
333.33
400
100.95
133.97
100
100
30
40
60
60
63
60
60
63
60
63
63
60
63
60
60
62
60
60
63
60
60
63
60
63
63
60
63
60
60
62
60
60
63
60
60
63
60
63
63
200
200
175
200
200
175
200
212
211
167
211
200
167
207
200
200
175
200
200
175
200
212
211
167
211
200
167
207
200
200
175
200
200
175
200
212
211
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
167 - 250
211 - 262
200 - 250
167 - 250
207 - 258
200 - 250
200 - 250
175 - 262
200 - 250
200 - 250
175 - 262
200 - 250
212 - 262
211 - 262
30
30
30
30
30
30
30
30
30
30
30
30
30
30
40
40
40
40
40
40
40
40
40
40
40
40
40
40
60
60
60
60
60
60
60
60
60
60
60
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
100
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
60
100
60
80
100
100
120
120
30
100
100
100
40
100
60
100
60
100
80
100
120
120
30
100
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
111.333333
167
40
60
60
80
120
120
30
40
60
60
80
120
120
30
X
X
X
X
X
X
X
X
X
167
40
167
60
167
60
167
80
167
120
120
30
167
167
167
40
Figure 1. CPU and SRC Frequency Select Tables
Document #: 38-07664 Rev. *B
Page 3 of 23
CY28435
PRELIMINARY
Data Interface, various device functions, such as individual
clock output buffers, can be individually enabled or disabled.
The registers associated with the Serial Data Interface
initializes to their default setting upon power-up, and therefore
use of this interface is optional. Clock device register changes
are normally made upon system initialization, if any are
required. The interface cannot be used during system
operation for power management functions.
block write/read operation, the bytes must be accessed in
sequential order from lowest to highest byte (most significant
bit first) with the ability to stop after any complete byte has
been transferred. For byte write and byte read operations, the
system controller can access individually indexed bytes. The
offset of the indexed byte is encoded in the command code,
as described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
Table 1. Command Code Definition
Bit
Description
7
0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0)
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 2. Block Read and Block Write Protocol
Block Write Protocol
Block Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
18:11
19
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
10
18:11
19
Acknowledge from slave
Command Code – 8 bits
Acknowledge from slave
Repeat start
27:20
Byte Count – 8 bits
20
(Skip this step if I2C_EN bit set)
28
36:29
37
45:38
46
....
....
....
....
Acknowledge from slave
Data byte 1 – 8 bits
Acknowledge from slave
Data byte 2 – 8 bits
Acknowledge from slave
Data Byte /Slave Acknowledges
Data Byte N – 8 bits
Acknowledge from slave
Stop
27:21
28
29
37:30
38
46:39
47
Slave address – 7 bits
Read = 1
Acknowledge from slave
Byte Count from slave – 8 bits
Acknowledge
Data byte 1 from slave – 8 bits
Acknowledge
Data byte 2 from slave – 8 bits
Acknowledge
55:48
56
....
....
....
Data bytes from slave / Acknowledge
Data Byte N from slave – 8 bits
NOT Acknowledge
....
Stop
Table 3. Byte Read and Byte Write Protocol
Byte Write Protocol
Byte Read Protocol
Description
Bit
1
Description
Bit
1
Start
Start
8:2
9
Slave address – 7 bits
Write
8:2
9
Slave address – 7 bits
Write
10
Acknowledge from slave
10
Acknowledge from slave
Document #: 38-07664 Rev. *B
Page 4 of 23
CY28435
PRELIMINARY
Table 3. Byte Read and Byte Write Protocol (continued)
Byte Write Protocol
Description
Command Code – 8 bits
Acknowledge from slave
Data byte – 8 bits
Acknowledge from slave
Stop
Byte Read Protocol
Description
Command Code – 8 bits
Acknowledge from slave
Repeated start
Slave address – 7 bits
Read
Bit
18:11
19
27:20
28
Bit
18:11
19
20
27:21
28
29
29
37:30
38
Acknowledge from slave
Data from slave – 8 bits
NOT Acknowledge
Stop
39
Control Registers
Byte 0: Control Register 0
Bit
@Pup
Name
Description
7
1
SRC[T/C]7
SRC[T/C]7 Output Enable
0 = Disable (Tri-state), 1 = Enable
6
5
4
3
2
1
0
1
1
1
1
1
1
1
SRC[T/C]6
SRC[T/C]5
SRC[T/C]6 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]5 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]4_SATA
SRC[T/C]3
SRC[T/C]4_SATA Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]3 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]2
SRC[T/C]2 Output Enable
0 = Disable (Tri-state), 1 = Enable
SRC[T/C]1
SRC[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enable
RESERVED
RESERVED, Set = 1
Byte 1: Control Register 1
Bit
@Pup
Name
Description
7
1
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
1
1
1
DOT_96T/C
USB48_0
REF0
DOT_96 MHz Output Enable
0 = Disable (Tri-state), 1 = Enabled
USB48_0 MHz Output Enable
0 = Disabled, 1 = Enabled
REF0 Output Enable
0 = Disabled, 1 = Enabled
3
2
0
1
RESERVED
CPU[T/C]1
RESERVED, Set = 0
CPU[T/C]1 Output Enable
0 = Disable (Tri-state), 1 = Enabled
1
0
1
0
CPU[T/C]0
CPU
CPU[T/C]0 Output Enable
0 = Disable (Tri-state), 1 = Enabled
PLL1 (CPU PLL) Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Document #: 38-07664 Rev. *B
Page 5 of 23
CY28435
PRELIMINARY
Byte 2: Control Register 2
Bit
@Pup
Name
Description
7
1
PCI5
PCI5 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
PCI4
PCI3
PCI2
PCI1
PCI0
PCIF2
PCIF1
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
Byte 3: Control Register 3
Bit
@Pup
Name
Description
7
0
SRC[T/C]7
Allow control of SRC[T/C]7 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
6
5
4
3
2
1
0
0
0
0
0
0
0
0
SRC[T/C]6
SRC[T/C]5
Allow control of SRC[T/C]6 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]5 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
SRC[T/C]4_SATA
SRC[T/C]3
Allow control of SRC[T/C]4_SATA with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
Allow control of SRC[T/C]3 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
SRC[T/C]2
Allow control of SRC[T/C]2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
SRC[T/C]1
Allow control of SRC[T/C]1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
RESERVED
RESERVED, Set = 0
Byte 4: Control Register 4
Bit
@Pup
Name
Description
7
HW
FS_E
FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E
was LOW during VTT_PWRGD# assertion.
6
5
4
3
0
0
0
0
DOT96[T/C]
PCIF2
DOT_PWRDWN Drive Mode
0 = Driven in PWRDWN, 1 = Tri-state
Allow control of PCIF2 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
PCIF1
Allow control of PCIF1 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
PCIF0
Allow control of PCIF0 with assertion of SW PCI_STP#
0 = Free running, 1 = Stopped with PCI_STP#
2
1
0
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED, Set = 1
RESERVED, Set = 1
RESERVED, Set = 1
Document #: 38-07664 Rev. *B
Page 6 of 23
CY28435
PRELIMINARY
Byte 5: Control Register 5
Bit
@Pup
Name
Description
7
0
SRC[T/C]
SRC[T/C] Stop Drive Mode
0 = Driven when SW PCI_STP# asserted,1 = Tri-state when SW
PCI_STP# asserted
6
5
4
3
0
0
0
0
RESERVED
RESERVED
RESERVED
SRC[T/C][7:1]
RESERVED, Set = 0
RESERVED, Set = 0
RESERVED, Set = 0
SRC[T/C][7:1] PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
2
1
0
0
RESERVED
CPU[T/C]1
RESERVED, Set = 0
CPU[T/C]1 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
0
0
CPU[T/C]0
CPU[T/C]0 PWRDWN Drive Mode
0 = Driven when PD asserted,1 = Tri-state when PD asserted
Byte 6: Control Register 6
Bit
@Pup
Name
Description
7
0
TEST_SEL
REF/N or Tri-state Select
0 = Tri-state, 1 = REF/N Clock
6
5
4
3
0
HW
1
TEST_MODE
FS_D
Test Clock Mode Entry Control
0 = Normal operation, 1 = REF/N or Tri-state mode,
FS_D reflects the value of the FS_D pin sampled on power-up.
0 = FS_D was LOW during VTT_PWRGD# assertion
REF0
REF Output Drive Strength
0 = High, 1 = Low
1
PCI, PCIF and SRC clock SW PCI_STP# Function
outputs except those set 0 = SW PCI_STP# assert, 1= SW PCI_STP# deassert
to free running
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
2
1
0
HW
HW
HW
FS_C
FS_B
FS_A
FS_C Reflects the value of the FS_C pin sampled on power-up
0 = FS_C was LOW during VTT_PWRGD# assertion
FS_B Reflects the value of the FS_B pin sampled on power-up
0 = FS_B was LOW during VTT_PWRGD# assertion
FS_A Reflects the value of the FS_A pin sampled on power-up
0 = FS_A was LOW during VTT_PWRGD# assertion
Byte 7: Vendor ID
Bit
7
6
5
4
3
2
1
0
@Pup
Name
Description
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
0
0
0
0
1
0
0
0
Revision Code Bit 3
Revision Code Bit 2
Revision Code Bit 1
Revision Code Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Document #: 38-07664 Rev. *B
Page 7 of 23
CY28435
PRELIMINARY
Byte 8: Control Register 8
Bit
@Pup
Name
Description
7
0
CPU_SS
Spread Selection for CPU PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
6
0
CPU_DWN_SS
Spread Selection for CPU PLL
0: Down spread.
1: Center spread
5
4
0
0
SRC_SS_OFF
SRC_SS
SRC Spread Spectrum Enable
0 = Spread off, 1 = Spread on
Spread Selection for SRC PLL
0: –0.5% (peak to peak)
1: –1.0% (peak to peak)
3
2
0
1
RESERVED
USB
RESERVED, Set = 0
48-MHz Output Drive Strength
0 = 2x, 1 = 1x
1
0
1
0
PCI
33-MHz Output Drive Strength
0 = 2x, 1 = 1x
RESERVED, Set = 0
RESERVED
Byte 9: Control Register 9
Bit
7
6
5
4
@Pup
Name
Description
0
0
0
0
DF_Limit2
DF_Limit1
DF_Limit0
DF_EN
Dynamic Frequency Max threshold. These three bits will set the max
allowed CPU frequency for Dynamic Frequency
Dynamic Frequency Enable
0 = Disable, 1 = Enable
3
2
1
0
0
0
0
0
FSEL_D
FSEL_C
FSEL_B
FSEL_A
SW Frequency selection bits. See Table 1.
Byte 10: Control Register 10
Bit
@Pup
Name
Description
7
0
Recovery_Frequency This bit allows selection of the frequency setting that the clock will be
restored to once the system is rebooted
0: Use HW settings 1: Recovery N[8:0]
6
0
Timer_SEL
Timer_SEL selects the WD reset function at SRESET pin when WD time
out.
0 = Reset and Reload Recovery_Frequency
1 = Only Reset
5
4
1
0
Time_Scale
WD_Alarm
Time_Scale allows selection of WD time scale
0 = 294 ms 1 = 2.34 s
WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when
the system clears the WD_TIMER time stamp.
3
2
1
0
0
0
WD_TIMER2
WD_TIMER1
WD_TIMER0
Watchdog timer time stamp selection
000: Reserved (test mode)
001: 1 * Time_Scale
010: 2 * Time_Scale
011: 3 * Time_Scale
100: 4 * Time_Scale
101: 5 * Time_Scale
110: 6 * Time_Scale
111: 7 * Time_Scale
Document #: 38-07664 Rev. *B
Page 8 of 23
CY28435
PRELIMINARY
Byte 10: Control Register 10 (continued)
Bit
@Pup
Name
Description
0
0
WD_EN
Watchdog timer enable, when the bit is asserted, Watchdog timer is
triggered and time stamp of WD_Timer is loaded
0 = Disable, 1 = Enable
Byte 11: Control Register 11
Bit
7
6
5
4
3
2
1
0
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N7
CPU_DAF_N6
CPU_DAF_N5
CPU_DAF_N4
CPU_DAF_N3
CPU_DAF_N2
CPU_DAF_N1
CPU_DAF_N0
If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and
CPU_DAF_M[6:0] will be used to determine the CPU output frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the FSEL[3:0] register will be used.
Byte 12: Control Register 12
Bit
7
6
5
4
3
2
1
0
@Pup
Name
Description
0
0
0
0
0
0
0
0
CPU_DAF_N8
CPU_DAF_M6
CPU_DAF_M5
CPU_DAF_M4
CPU_DAF_M3
CPU_DAF_M2
CPU_DAF_M1
CPU_DAF_M0
If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]
and CPU_FSEL_M[6:0] will be used to determine the CPU output
frequency.
The setting of FS_Override bit determines the frequency ratio for CPU and
other output clocks. When it is cleared, the same frequency ratio stated in
the Latched FS[E:A] register will be used. When it is set, the frequency
ratio stated in the FSEL[3:0] register will be used.
Byte 13: Control Register 13
Bit
7
6
5
4
3
2
1
0
@Pup
Name
Description
SRC Dial-A-Frequency Bit N7
SRC Dial-A-Frequency Bit N6
SRC Dial-A-Frequency Bit N5
SRC Dial-A-Frequency Bit N4
SRC Dial-A-Frequency Bit N3
SRC Dial-A-Frequency Bit N2
SRC Dial-A-Frequency Bit N1
SRC Dial-A-Frequency Bit N0
0
0
0
0
0
0
0
0
SRC_N7
SRC_N6
SRC_N5
SRC_N4
SRC_N3
SRC_N2
SRC_N1
SRC_N0
Byte 14: Control Register 14
Bit
7
@Pup
Name
SRC_N8
Description
0
SRC Dial-A-Frequency Bit N8
6
0
SW_RESET
Software Reset.
When set the device will assert a reset signal on SRESET# upon
completion of the block/word/byte write that set it. After asserting and
deasserting the SRESET# this bit will self clear (set to 0).
The SRESET# pin must be enabled by latching SRESET#_EN on
VTT_PRWGD# to utilize this feature.
5
0
FS_[E:A]
FS_Override
0 = Select operating frequency by FS(E:A) input pins
1 = Select operating frequency by FSEL_(4:0) settings
Document #: 38-07664 Rev. *B
Page 9 of 23
CY28435
PRELIMINARY
Byte 14: Control Register 14 (continued)
Bit
@Pup
Name
Description
4
0
SMSW_SEL
Smooth switch select
0: select CPU_PLL
1: select SRC_PLL.
3
2
1
0
0
1
RESERVED
RESERVED
PCIF
RESERVED, Set = 0
RESERVED, Set = 0
Free running 33-MHz Output Drive Strength
0 = 2x, 1 = 1x
0
0
Recovery_N8
Watchdog Recovery Bit
Byte 15: Control Register 15
Bit
7
6
5
4
3
2
1
0
@Pup
Name
Description
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
Watchdog Recovery Bit
0
0
0
0
0
0
0
0
Recovery N7
Recovery N6
Recovery N5
Recovery N4
Recovery N3
Recovery N2
Recovery N1
Recovery N0
Byte 16: Control Register 16
Bit
@Pup
Name
Description
7
1
REF1
REF1 Output Enable
0 = Disable, 1 = Enable
6
5
1
0
USB48_1
USB48_1 Output Enable
0 = Disable, 1 = Enable
SRC_FREQ_SEL
SRC Frequency selection
0: SRC frequency is selected via the FSE pin
1: SRC frequency is initially set to 167MHz.
4
3
0
0
RESERVED
SRC_SATA
RESERVED, Set = 0
SATA PLL Spread Spectrum Enable
0 = Spread off, 1 = Spread on
2
1
0
0
0
1
Prog_SRC_EN
Prog_CPU_EN
Programmable SRC frequency enable
0 = disabled, 1 = enabled.
Programmable CPU frequency enable
0 = disabled, 1 = enabled.
Watchdog Autorecovery Watchdog Autorecovery Mode
0 = Disable (Manual), 1= Enable (Auto)
Crystal Recommendations
Crystal Loading
The CY28435 requires a Parallel Resonance Crystal. Substi-
tuting a series resonance crystal will cause the CY28435 to
operate at the wrong frequency and violate the ppm specifi-
cation. For most applications there is a 300-ppm frequency
shift between series and parallel crystals due to incorrect
loading.
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).
Figure 2 shows a typical crystal configuration using the two
trim capacitors. An important clarification for the following
discussion is that the trim capacitors are in series with the
crystal not parallel. It’s a common misconception that load
capacitors are in parallel with the crystal and should be
approximately equal to the load capacitance of the crystal.
This is not true.
Document #: 38-07664 Rev. *B
Page 10 of 23
CY28435
PRELIMINARY
Table 4. Crystal Recommendations
Frequency
Drive
Shunt Cap Motional
Tolerance
(max.)
Stability
Aging
(max.)
Cut
Loading Load Cap
(Fund)
(max.)
(max.)
(max.)
(max.)
14.31818 MHz
AT
Parallel
20 pF
0.1 mW
5 pF
0.016 pF
35 ppm
30 ppm
5 ppm
As mentioned previously, the capacitance on each side of the
crystal is in series with the crystal. This mean the total capac-
itance on each side of the crystal must be twice the specified
load capacitance (CL). While the capacitance on each side of
the crystal is in series with the crystal, trim capacitors
(Ce1,Ce2) should be calculated to provide equal capacitance
loading on both sides.
Use the following formulas to calculate the trim capacitor
values for Ce1 and Ce2.
Figure 2. Crystal Capacitive Clarification
Load Capacitance (each side)
Calculating Load Capacitors
Ce = 2 * CL – (Cs + Ci)
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading. As mentioned previously,
the capacitance on each side of the crystal is in series with the
crystal. This means the total capacitance on each side of the
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in
series with the crystal, trim capacitors (Ce1,Ce2) should be
calculated to provide equal capacitive loading on both sides.
Total Capacitance (as seen by the crystal)
1
+
CLe
=
1
1
(
)
Ce2 + Cs2 + Ci2
Ce1 + Cs1 + Ci1
CL....................................................Crystal load capacitance
CLe.........................................Actual loading seen by crystal
using standard value trim capacitors
Ce.....................................................External trim capacitors
Cs..............................................Stray capacitance (terraced)
Clock Chip
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
Ci2
Ci1
CL....................................................Crystal load capacitance
Pin
3 to 6p
CLe.........................................Actual loading seen by crystal
using standard value trim capacitors
Ce.....................................................External trim capacitors
Cs..............................................Stray capacitance (terraced)
X2
X1
Cs2
Cs1
Ci .......................................................... Internal capacitance
Trace
2.8pF
(lead frame, bond wires etc.)
XTAL
Ce1
Ce2
Trim
33pF
Figure 3. Crystal Loading Example
Document #: 38-07664 Rev. *B
Page 11 of 23
CY28435
PRELIMINARY
CPU_DAF_N – There will be nine bits (for 512 values) to
linearly change the CPU frequency (limited by VCO range).
Default = 0, (0000). The allowable values for N are detailed in
the frequency select table in Figure 1.
CPU DAF M – There will be 7 bits (for 128 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, the allowable values for M are detailed in the frequency
select table in section Figure 1
SRC_DAF Enable – This bit enables SRC DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the SRC_DAF_N
register. Note: the SRC_DAF_N register must contain valid
values before SRC_DAF is set. Default = 0, (No DAF).
Dynamic Frequency
Dynamic Frequency – Dynamic Frequency (DF) is a technique
to increase the CPU frequency dynamically from any starting
value. The user selects the starting point, either by HW, FSEL,
or DAF then enables DF. After that, DF will dynamically change
as determined by the value on the DF[2:0] pins.
DF/PCI pin – These PCI pins incorporate dual functions, either
DF or PCI. The function is selected by the DF_EN pin. When
used as DF, these three pins will map to eight entries that
correspond to different “N” values for Dynamic Frequency.
Below is a table that list the combinations along with the
increase in “N”.
SRC_DAF_N – There is nine bits (for 512 values) to linearly
change the CPU frequency (limited by VCO range). Default =
0, (0000). The allowable values for N are detailed in the
frequency select table in Figure 1.
Recovery – The recovery mechanism during CPU DAF when
the system locks up and the watchdog timer is enabled is
determined by the “Watchdog Recovery Mode” and
“Watchdog Auto recovery Enable” bits. The possible recovery
methods are A) Auto, B) Manual (by Recovery N), C) HW, and
D) No recovery - just send reset signal.
DOC[2:0]
000
DOC N value
Original Frequency
001
010
011
100
101
110
111
+2
+6
+10
+14
+18
+30
+40
There is no recovery mode for SRC Dial a frequency.
Software Frequency Select
This mode allows the user to select the CPU output
frequencies using the Software Frequency select bits in the
SMBUS register.
FSEL – There will be four bits (for 16 combinations) to select
predetermined CPU frequencies from a table. The table selec-
tions are detailed in section Figure 1
DF_EN bit – This bit enables the DF mode. By default, it is not
set. When set, the operating frequency is determined by
DF[2:0] pins. Default = 0, (No DF)
DF_Limit bit – There are three bits that allow the user to set an
upper limit to prevent CPU runaway. In the event that the user
uses DAF with DF, this feature will provide some safe guard
so the CPU won’t burn up.
FS_Override – This bit allows the CPU frequency to be
selected from HW or FSEL settings. By default, this bit is not
set and the CPU frequency is selected by HW. When this bit
is set, the CPU frequency is selected by the FSEL bits. Default
= 0.
Recovery – The recovery mechanism during FSEL when the
system locks up is determined by the “Watchdog Recovery
Mode” and “Watchdog Auto recovery Enable” bits. The only
possible recovery method is to Hardware Settings. Auto
recovery or manual recovery can cause a wrong output
frequency because the output divider may have changed with
the selected CPU frequency and these recovery methods will
not recover the original output divider setting.
Dial-A-Frequency (CPU & SRC)
This feature allows the user to over clock their system by
slowly stepping up the CPU or SRC frequency. When the
programmable output frequency feature is enabled, the CPU
and SRC frequencies are determined by the following
equation
Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M.
“N” and “M” are the values programmed in Programmable
Frequency Select N-Value Register and M-Value Register,
respectively. “G” stands for the PLL Gear Constant, which is
determined by the programmed value of FS[E:A]. See
Figure 1 for the Gear Constant for each Frequency selection.
The PCI Express only allows user control of the N register, the
M value is fixed and documented in Figure 1
Smooth Switching
In this mode, the user writes the desired N and M value into
the DAF I2C registers. The user cannot change only the M
value and must change both the M and the N values at the
same time, if they require a change to the M value. The user
may change only the N value if required.
The Device contains 1 smooth switch circuit which is shared
by the CPU PLL and SRC PLL. The smooth switch circuit
ensures that when the output frequency changes by
overclocking, the transition from the old frequency to the new
frequency is a slow, smooth transition containing no glitches.
The rate of change of output frequency when using the smooth
switch circuit is less than 1 MHz/0.667 µs. The frequency
overshoot and undershoot will be less than 2%.
The Smooth Switch circuit can be assigned to either PLL via
register byte 14 bit 4. By default the smooth switch circuit is
assigned to the CPU PLL. Either PLL can still be overclocked
when it does not have control of the smooth switch circuit but
Associated Register Bits
CPU_DAF Enable – This bit enables CPU DAF mode. By
default, it is not set. When set, the operating frequency is
determined by the values entered into the CPU_DAF_N
register. Note: the CPU_DAF_N and M register must contain
valid values before CPU_DAF is set. Default = 0, (No DAF).
Document #: 38-07664 Rev. *B
Page 12 of 23
CY28435
PRELIMINARY
it is not guaranteed to transition to the new frequency without
Watchdog Autorecovery Enable – This bit by default is set and
the recovered values are automatically written into the
“Watchdog Recovery Register” and reloaded by the Watchdog
function. When this bit is not set, the user is allowed to write to
the “Watchdog Recovery Register”. The value stored in the
“Watchdog Recovery Register” will be used for recovery.
Default = 1, Autorecovery.
large frequency glitches.
It is not recommended to enable overclocking and change the
N values of both PLLs in the same SMBUS block write.
Watchdog Timer
The Watchdog timer is used in the system in conjunction with
overclocking. It is used to provide a reset to a system that has
hung up due to overclocking the CPU and the Front side bus.
The watchdog is enabled by the user and if the system
completes its checkpoints, the system will clear the timer.
However, when the timer runs out, there will be a reset pulse
generated on the SRESET# pin for 20 ms that is used to reset
the system.
When the Watchdog is enabled (WD_EN = 1) the Watchdog
timer will start counting down from a value of Watchdog_timer
* time scale. If the Watchdog timer reaches 0 before the
WD_EN bit is cleared then it will assert the SRESET# signal
and set the Watchdog Alarm bit to 1.
To use the watchdog the SRESET# pin must be enabled by
SRESET_EN pin being sampled LOW by VTTPWRGD#
assertion during system boot up.
At any point if during the Watchdog timer countdown, if the
time stamp or Watchdog timer bits are changed the timer will
reset and start counting down from the new value.
Watchdog Recovery Register – This is a nine-bit register to
store the watchdog N recovery value. This value can be written
by the Auto recovery or User depending on the state of the
“Watchdog Auto Recovery Enable bit”.
Watchdog Recovery Modes
There are three operating modes that require Watchdog
recovery. The modes are Dial-A-Frequency (DAF), Dynamic
Clocking (DF), or Frequency Select. There are 4 different
recovery modes: the following diagram lists the operating
mode and the recovery mode associated with it.
Recover to Hardware M,N, O
When this recovery mode is selected, in the event of a
Watchdog timeout, the original M,N, and O values that were
latched by the HW FSEL pins at chip boot up should be
reloaded.
Autorecovery
When this recovery mode is selected, in the event of a
Watchdog timeout, the M and N values stored in the Recovery
M and N registers should be reloaded. The current values of
M and N will be latched into the internal recovery M and N
registers by the WD_EN bit being set.
After the Reset pulse, the watchdog will stay inactive until
either:
1. A new time stamp or watchdog timer value is loaded.
2. The WD_EN bit is cleared and then set again.
Watchdog Register Bits
Manual Recovery
The following register bits are associated with the Watchdog
When this recovery mode is selected, in the event of a
Watchdog timeout, the N value as programmed by the user in
the N recovery register, and the M value that is stored in the
Recovery M register (not accessible by the user) should be
restored. The current M value should be latched M recovery
register by the WD_EN bit being set.
timer:
Watchdog Enable – This bit (by default) is not set, which
disables the Watchdog. When set, the Watchdog is enabled.
Also, when there is a transition from LOW to HIGH, the timer
reloads. Default = 0, disable
Watchdog Timer – There will be three bits (for seven combina-
tions) to select the timer value. Default = 000, the value '000'
is a reserved test mode.
Watchdog Alarm – This bit is a flag and when it is set, it
indicates that the timer has expired. This bit is not set by
default. When the bit is set, the user is allowed to clear. Default
= 0.
Watchdog Time Scale – This bit selects the multiplier. When
this bit is not set, the multiplier will be 250 ms. When set (by
default), the multiplier will be 3s. Default = 1
Watchdog Reset Mode – This selects the Watchdog Reset
Mode. When this bit is not set (by default), the Watchdog will
send a reset pulse and reload the recovery frequency depends
on Watchdog Recovery Mode setting. When set, it just send a
reset pulse.Default = 0, Reset & Recover Frequency.
No Recovery
If no recovery mode is selected, in the event of a Watchdog
time out, the device should just assert the SRESET# and keep
the current values of M and N
Software Reset
Software reset is a reset function which is used to send out a
pulse from SRESET# pin. It is controlled by the SW_RESET
enable register bit. Upon completion of the byte/word/block
write in which the SW_RESET bit was set, the device will send
a RESET pulse on the SRESET# pin. The duration of the
SRESET# pulse should be the same as the duration of the
SRESET# pulse after a Watchdog timer time out.
After the SRESET# pulse is asserted the SW_RESET bit
should be automatically cleared by the device.
Watchdog Recovery Mode – This bit selects the location to
recover from. One option is to recover from the HW settings
(already stored in SMBUS registers for readback capability)
and the second is to recover from a register called “Recovery
N”. Default = 0 (Recover from the HW setting)
PD (Power-down) Clarification
The VTT_PWRGD# /PD pin is a dual-function pin. During
initial power-up, the pin functions as VTT_PWRGD#. Once
VTT_PWRGD# has been sampled LOW by the clock chip, the
pin assumes PD functionality. The PD pin is an asynchronous
Document #: 38-07664 Rev. *B
Page 13 of 23
CY28435
PRELIMINARY
active HIGH input used to shut off all clocks cleanly prior to
shutting off power to the device. This signal is synchronized
internal to the device prior to powering down the clock synthe-
sizer. PD is also an asynchronous input for powering up the
system. When PD is asserted HIGH, all clocks need to be
driven to a low value and held prior to turning off the VCOs and
the crystal oscillator.
both the “Diff clock” and the “Diff clock#” are tri-state. Note the
example below shows CPUT = 133 MHz and PD drive mode
= ‘1’ for all differential outputs. This diagram and description is
applicable to valid CPU frequencies 100, 133, 166, 200, 266,
333 and 400 MHz. In the event that PD mode is desired as the
initial power-on state, PD must be asserted high in less than
10 µs after asserting Vtt_PwrGd#.
PD (Power-down) – Assertion
PD Deassertion
When PD is sampled HIGH by two consecutive rising edges
of CPUC, all single-ended outputs will be held low on their next
HIGH-to-LOW transition and differential clocks must be held
high or tri-stated (depending on the state of the control register
drive mode bit) on the next diff clock# HIGH-to-LOW transition
within four clock periods. When the SMBus PD drive mode bit
corresponding to the differential (CPU, SRC, and DOT) clock
output of interest is programmed to ‘0’, the clock output are
held with “Diff clock” pin driven HIGH at 2 x Iref, and “Diff
clock#” tri-state. If the control register PD drive mode bit corre-
sponding to the output of interest is programmed to “1”, then
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300 µs of PD deassertion to a voltage greater than 200
mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33 MHz
REF
Figure 4. Power-down Assertion Timing Waveform
Tstable
<1.8ms
PD
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
USB, 48MHz
DOT96T
DOT96C
PCI, 33MHz
REF
Tdrive_PWRDN#
<300µS, >200mV
Figure 5. Power-down Deassertion Timing Waveform
Document #: 38-07664 Rev. *B
Page 14 of 23
CY28435
PRELIMINARY
FS_A, FS_B,FS_C
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS
Delay
Wait for
Device is not affected,
VTT_PWRGD# is ignored
Sample Sels
State 2
VDD Clock Gen
Clock State
VTT_PWRGD#
State 0
Off
State 1
State 3
On
Clock Outputs
Clock VCO
On
Off
Figure 6. VTT_PWRGD# Timing Diagram
S2
S1
VTT_PWRGD# = Low
Delay
>0.25mS
Sample
Inputs straps
VDD_A = 2.0V
S0
Wait for <1.8ms
S3
VDD_A = off
Normal
Operation
Enable Outputs
Power Off
VTT_PWRGD# = toggle
Figure 7. Clock Generator Power-up/Run State Diagram
Document #: 38-07664 Rev. *B
Page 15 of 23
CY28435
PRELIMINARY
Absolute Maximum Conditions
Parameter
VDD
VDD_A
VIN
Description
Core Supply Voltage
Analog Supply Voltage
Condition
Min.
–0.5
–0.5
Max.
4.6
4.6
Unit
V
V
Input Voltage
Relative to VSS
–0.5 VDD + 0.5 VDC
TS
TA
TJ
ØJC
Temperature, Storage
Temperature, Operating Ambient
Temperature, Junction
Dissipation, Junction to Case
Dissipation, Junction to Ambient
ESD Protection (Human Body Model)
Flammability Rating
Non-functional
Functional
Functional
Mil-STD-883E Method 1012.1
JEDEC (JESD 51)
MIL-STD-883, Method 3015
At 1/8 in.
–65
0
–
–
–
150
70
150
20
60
–
°C
°C
°C
°C/W
°C/W
V
ØJA
ESDHBM
UL-94
MSL
2000
V–0
1
Moisture Sensitivity Level
Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter
All VDDs
VILI2C
VIHI2C
VIL_FS
VIH_FS
VILFS_C
VIMFS_C
VIH FS_C
VIL
VIH
IIL
IIH
VOL
VOH
IOZ
CIN
COUT
LIN
Description
3.3V Operating Voltage
Input Low Voltage
Condition
Min.
3.135
–
2.2
Max.
3.465
1.0
–
0.35
VDD + 0.5
Unit
V
V
V
V
V
V
V
V
V
V
µA
µA
V
3.3 ± 5%
SDATA, SCLK
SDATA, SCLK
Input High Voltage
FS_[A:B,D:E] Input Low Voltage
FS_[A:B,D:E] Input High Voltage
FS_C Low Range
FS_C Mid Range
FS_C High Range
3.3V Input Low Voltage
3.3V Input High Voltage
Input Low Leakage Current
Input High Leakage Current
3.3V Output Low Voltage
3.3V Output High Voltage
High-impedance Output Current
Input Pin Capacitance
Output Pin Capacitance
Pin Inductance
VSS – 0.3
0.7
0
0.7
2.1
0.35
1.7
VDD
0.8
VSS – 0.3
2.0
–5
–
–
2.4
–10
3
3
VDD + 0.3
Except internal pull-up resistors, 0 < VIN < VDD
Except internal pull-down resistors, 0 < VIN < VDD
IOL = 1 mA
–
5
0.4
–
10
5
5
IOH = –1 mA
V
µA
pF
pF
nH
V
–
7
VXIH
VXIL
IDD3.3V
IPD3.3V
IPT3.3V
Xin High Voltage
Xin Low Voltage
Dynamic Supply Current
Power-down Supply Current
Power-down Supply Current
0.7VDD
VDD
0.3VDD
500
70
2
0
–
–
–
V
At max. load and freq. per Figure 10
PD asserted, Outputs Driven
PD asserted, Outputs Tri-state
mA
mA
mA
Document #: 38-07664 Rev. *B
Page 16 of 23
CY28435
PRELIMINARY
AC Electrical Specifications
Parameter
Description
Condition
Min.
Max.
Unit
Crystal
TDC
XIN Duty Cycle
XIN Period
The devicewill operate reliably with input
duty cycles up to 30/70 but the REFclock
duty cycle will not be within specification
47.5
52.5
%
TPERIOD
When XIN is driven from an external
69.841
71.0
ns
clock source
TR / TF
TCCJ
LACC
XIN Rise and Fall Times
XIN Cycle to Cycle Jitter
Long-term Accuracy
Measured between 0.3VDD and 0.7VDD
As an average over 1-µs duration
Over 150 ms
–
–
–
10.0
500
300
ns
ps
ppm
CPU at 0.7V (SSC refers to –0.5% spread spectrum)
TDC
CPUT and CPUC Duty Cycle
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
45
55
%
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
TPERIOD
100-MHz CPUT and CPUC Period
133-MHz CPUT and CPUC Period
166-MHz CPUT and CPUC Period
200-MHz CPUT and CPUC Period
266-MHz CPUT and CPUC Period
333-MHz CPUT and CPUC Period
400-MHz CPUT and CPUC Period
9.997001 10.00300 ns
7.497751 7.502251 ns
5.998201 6.001801 ns
4.998500 5.001500 ns
3.748875 3.751125 ns
2.999100 3.000900 ns
2.499250 2.500750 ns
9.997001 10.05327 ns
7.497751 7.539950 ns
5.998201 6.031960 ns
4.998500 5.026634 ns
3.748875 3.769975 ns
2.999100 3.015980 ns
2.499250 2.513317 ns
9.912001 10.08800 ns
7.412751 7.587251 ns
5.913201 6.086801 ns
4.913500 5.086500 ns
3.663875 3.836125 ns
2.914100 3.085900 ns
2.414250 2.585750 ns
9.912001 10.13827 ns
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODSS
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
TPERIODAbs
100-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
133-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
166-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
200-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
266-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
333-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
400-MHz CPUT and CPUC Period, SSC Measured at crossing point VOX
100-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
133-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
166-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
200-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
266-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
333-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
400-MHzCPUTandCPUCAbsoluteperiod Measured at crossing point VOX
TPERIODSSAbs 100-MHz CPUT and CPUC Absolute
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
period, SSC
TPERIODSSAbs 133-MHz CPUT and CPUC Absolute
period, SSC
7.412751 7.624950 ns
5.913201 6.116960 ns
4.913500 5.111634 ns
3.663875 3.854975 ns
2.914100 3.100980 ns
2.414250 2.598317 ns
TPERIODSSAbs 166-MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 200-MHz CPUT and CPUC Absolute
period, SSC
TPERIODSSAbs 266-MHz CPUT and CPU C Absolute Measured at crossing point VOX
period, SSC
TPERIODSSAbs 333-MHz CPUT and CPUC Absolute
period, SSC
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
TPERIODSSAbs 400-MHz CPUT and CPUC Absolute
period, SSC
TSKEW
CPU0 to CPU1
–
100
ps
Document #: 38-07664 Rev. *B
Page 17 of 23
CY28435
PRELIMINARY
AC Electrical Specifications (continued)
Parameter
TCCJ
LACC
Description
CPUT/C Cycle to Cycle Jitter
Long Term accuracy
Condition
Measured at crossing point VOX
Measured using frequency counter over
Min.
–
–
Max.
85
300
Unit
ps
ppm
0.15seconds.
TR / TF
TRFM
CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH
0.525V
=
175
–
700
20
ps
%
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
∆TR
∆TF
Rise Time Variation
Fall Time Variation
Voltage High
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
Minimum Undershoot Voltage
Ring Back Voltage
–
–
660
–150
250
–
125
125
850
–
ps
ps
mV
mV
mV
V
VHIGH
VLOW
VOX
VOVS
VUDS
VRB
Math averages Figure 10
Math averages Figure 10
550
VHIGH + 0.3
–0.3
–
–
0.2
V
V
See Figure 10. Measure SE
SRC
TDC
SRCT and SRCC Duty Cycle
100-MHz SRCT and SRCC Period
100-MHz SRCT and SRCC Period, SSC Measured at crossing point VOX
100-MHz SRCT and SRCCAbsolute Period Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
45
55
%
TPERIOD
TPERIODSS
TPERIODAbs
9.997001 10.00300 ns
9.997001 10.05327 ns
9.872001 10.12800 ns
9.872001 10.17827 ns
TPERIODSSAbs 100-MHz SRCT and SRCC Absolute
Measured at crossing point VOX
Period, SSC
TSKEW
TCCJ
LACC
TR / TF
TRFM
Any SRCT/C to SRCT/C Clock Skew
SRCT/C Cycle to Cycle Jitter
SRCT/C Long Term Accuracy
SRCT and SRCC Rise and Fall Times MeasuredfromVOL = 0.175 to VOH = 0.525V
Rise/Fall Matching
Measured at crossing point VOX
Measured at crossing point VOX
Measured at crossing point VOX
–
–
–
175
–
250
85
300
700
20
ps
ps
ppm
ps
Determined as a fraction of 2*(TR –
%
TF)/(TR + TF)
∆TR
∆TF
VHIGH
VLOW
VOX
VOVS
VUDS
VRB
Rise TimeVariation
Fall Time Variation
Voltage High
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
Minimum Undershoot Voltage
Ring Back Voltage
–
–
660
–150
250
–
125
125
850
–
ps
ps
mV
mV
mV
V
Math averages Figure 10
Math averages Figure 10
550
VHIGH + 0.3
–0.3
–
–
0.2
V
V
See Figure 10. Measure SE
PCI/PCIF
TDC
TPERIOD
TPERIODSS
TPERIODAbs
PCI Duty Cycle
Spread Disabled PCIF/PCI Period
Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
Spread Disabled PCIF/PCI Period Measurement at 1.5V
Measurement at 1.5V
Measurement at 1.5V
45
55
%
29.99100 30.00900 ns
29.9910 30.15980 ns
29.49100 30.50900 ns
29.49100 30.65980 ns
TPERIODSSAbs Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V
THIGH
TLOW
Edge Rate
PCIF and PCI high time
PCIF and PCI low time
Rising edge rate
Measurement at 2.4V
Measurement at 0.4V
Measured between 0.8V and 2.0V
12.0
12.0
1.0
–
–
4.0
ns
ns
V/ns
Document #: 38-07664 Rev. *B
Page 18 of 23
CY28435
PRELIMINARY
AC Electrical Specifications (continued)
Parameter
Edge Rate
TSKEW
Description
Falling edge rate
Any PCI clock to Any PCI clock Skew Measurement at 1.5V
Condition
Measured between 0.8V and 2.0V
Min.
1.0
–
Max.
4.0
500
500
Unit
V/ns
ps
TCCJ
PCIF and PCI Cycle to Cycle Jitter
Measurement at 1.5V
–
ps
DOT
TDC
DOT96T and DOT96C Duty Cycle
DOT96T and DOT96C Period
DOT96T and DOT96C Absolute Period Measured at crossing point VOX
DOT96T/C Cycle to Cycle Jitter
DOT96T/C Long Term Accuracy
Long Term jitter
Measured at crossing point VOX
Measured at crossing point VOX
45
55
%
TPERIOD
TPERIODAbs
TCCJ
LACC
TLTJ
10.41354 10.41979 ns
10.16354 10.66979 ns
Measured at crossing point VOX
Measured at crossing point VOX
Measurement taken from cross point
–
–
–
150
100
700
ps
ppm
ps
VOX@1 µs
Measurement taken from cross point
–
175
–
700
700
20
ps
ps
%
VOX@10 µs
TR / TF
TRFM
DOT96T and DOT96C Rise and Fall Times Measured from VOL = 0.175 to VOH
=
0.525V
Rise/Fall Matching
Determined as a fraction of
2*(TR – TF)/(TR + TF)
∆TR
∆TF
VHIGH
VLOW
VOX
Rise Time Variation
Fall Time Variation
Voltage High
Voltage Low
Crossing Point Voltage at 0.7V Swing
Maximum Overshoot Voltage
–
–
660
–150
250
–
125
125
850
–
ps
ps
mV
mV
mV
V
Math averages Figure 10
Math averages Figure 10
550
VOVS
VHIGH
+
0.3
VUDS
VRB
Minimum Undershoot Voltage
Ring Back Voltage
–0.3
–
–
0.2
V
V
See Figure 10. Measure SE
USB
TDC
Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
TPERIODAbs
THIGH
Period
Measurement at 1.5V
Measurement at 1.5V
Measurement at 2.4V
Measurement at 0.4V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
Measurement at 1.5V
20.83125 20.83542 ns
Absolute Period
USB high time
USB low time
Rising edge rate
Falling edge rate
Cycle to Cycle Jitter
Long Term jitter
20.48125 21.18542
ns
ns
ns
V/ns
V/ns
ps
8.094
7.694
1.0
1.0
–
10.036
9.836
2.0
2.0
200
TLOW
Edge Rate
Edge Rate
TCCJ
TLTJ
Measurement taken from cross point
–
1.5
ns
Vox@1us
Measurement taken from cross point
Vox@10us
–
–
1.5
1.5
ns
ns
Measurement taken from cross point
Vox@125us
REF
TDC
REF Duty Cycle
Measurement at 1.5V
45
55
%
TPERIOD
REF Period
Measurement at 1.5V
69.8203
69.8622
ns
TPERIODAbs
TR / TF
Edge Rate
REF Absolute Period
REF Rise and Fall Times
Rising edge rate
Measurement at 1.5V
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
68.82033 70.86224 ns
0.3
1.0
1.2
4.0
ns
V/ns
Document #: 38-07664 Rev. *B
Page 19 of 23
CY28435
PRELIMINARY
AC Electrical Specifications (continued)
Parameter
Edge Rate
TCCJ
Description
Falling edge rate
REF Cycle to Cycle Jitter
Condition
Measured between 0.8V and 2.0V
Measurement at 1.5V
Min.
1.0
–
Max.
4.0
1000
Unit
V/ns
ps
ENABLE/DISABLE and SET-UP
TSTABLE
Clock Stabilization from Power-up
–
1.8
ms
Test and Measurement Set-up
For PCI Single-ended Signals and Reference
The following diagram shows the test load configurations for
the single-ended PCI, USB, and REF output signals.
Measurement
Point
33Ω
PCI/
USB
60Ω
5pF
Measurement
Point
12Ω
60Ω
60Ω
5pF
REF
Measurement
12Ω
Point
5pF
Figure 8. Single-ended Load Configuration
Measurement
Point
12Ω
60Ω
5pF
Measurement
12Ω
PCI/
Point
USB
60Ω
5pF
Measurement
Point
12Ω
60Ω
5pF
Measurement
Point
12Ω
12Ω
REF
60Ω
60Ω
5pF
Measurement
Point
5pF
Figure 9. Single-ended Load Configuration HIGH DRIVE OPTION
Document #: 38-07664 Rev. *B
Page 20 of 23
CY28435
PRELIMINARY
For Differential CPU, SRC and DOT96 Output Signals
The following diagram shows the test load configuration for the
differential CPU and SRC outputs.
M e a s u re m e n t
P o in t
3 3 Ω
C P U T
S R C T
D O T 9 6 T
2 p F
4 9 .9 Ω
1 0 0 Ω D iffe re n tia l
M e a s u re m e n t
P o in t
C P U C
S R C C
D O T 9 6 C
3 3 Ω
2 p F
4 9 .9 Ω
IR E F
4 7 5 Ω
Figure 10. 0.7V Single-ended Load Configuration
3 .3 V s ig n a ls
T D C
-
-
3 .3 V
2 .4 V
1 .5 V
0 .4 V
0 V
T R
T F
Figure 11. Single-ended Output Signals (for AC Parameters Measurement)
Ordering Information
Part Number
Package Type
Product Flow
Lead-free
CY28435OXC
CY28435OXCT
CY28435ZXC
CY28435ZXCT
56-pin SSOP
56-pin SSOP – Tape and Reel
56-pin TSSOP
Commercial, 0° to 85°C
Commercial, 0° to 85°C
Commercial, 0° to 85°C
Commercial, 0° to 85°C
56-pin TSSOP – Tape and Reel
Document #: 38-07664 Rev. *B
Page 21 of 23
CY28435
PRELIMINARY
Package Diagrams
56-Lead Shrunk Small Outline Package O56
.020
28
1
0.395
0.420
0.292
0.299
DIMENSIONS IN INCHES MIN.
MAX.
29
56
0.720
0.730
SEATING PLANE
0.005
0.010
0.088
0.092
0.095
0.110
.010
GAUGE PLANE
0.110
0.024
0.040
0.025
BSC
0.008
0.016
0°-8°
0.008
0.0135
51-85062-*C
56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56
0.249[0.009]
28
1
DIMENSIONS IN MM[INCHES] MIN.
MAX.
7.950[0.313]
8.255[0.325]
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.42gms
5.994[0.236]
6.198[0.244]
PART #
Z5624 STANDARD PKG.
ZZ5624 LEAD FREE PKG.
29
56
13.894[0.547]
14.097[0.555]
1.100[0.043]
MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.508[0.020]
0.762[0.030]
0°-8°
0.051[0.002]
0.152[0.006]
0.851[0.033]
0.950[0.037]
0.500[0.020]
BSC
0.100[0.003]
0.200[0.008]
0.170[0.006]
0.279[0.011]
SEATING
PLANE
51-85060-*C
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. Dial-A-Frequency is a registered trademark
of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their
respective holders.
Document #: 38-07664 Rev. *B
Page 22 of 23
© Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY28435
PRELIMINARY
Document History Page
Document Title: CY28435 Clock Generator for Intel Grantsdale Chipset
Document Number: 38-07664
Orig. of
REV.
**
ECN NO. Issue Date Change
Description of Change
214042
See ECN
RGL
New Data Sheet
*A
268575
See ECN
RGL
Changed the tri-state test mode from 12 mA to 2 mA
Fixed the Single-ended load configuration diagram
*B
305734
See ECN
RGL
Corrected the TLTJ for USB to 1.5 ns
Corrected the Frequency table values
Document #: 38-07664 Rev. *B
Page 23 of 23
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