CY28437OXC_技术文档

PRELIMINARY

CY28437

Clock Generator for Intel^£ꢀGrantsdale Chipset

• Dial-A-Frequency^£

Features

• Watchdog timer

• Compliant to Intel^£CK410

• Two Independent Overclocking PLLs

• Supports Intel Prescott and Tejas CPU

• Selectable CPU frequencies

• Differential CPU clock pairs

• 100 MHz differential SRC clocks

• 96 MHz differential dot clock

• 48 MHz USB clocks

• Low-voltage frequency select input

• I²C support with readback capabilities

• Ideal Lexmark Spread Spectrum profile for maximum

electromagnetic interference (EMI) reduction

• 3.3V power supply

• 56-pin SSOP and TSSOP packages

• 33 MHz PCI clock

CPU

x 2

SRC

x 8

PCI

x 8

REF

x 2

DOT96

x 1

USB

x 2

• Dynamic Frequency Control

Block Diagram

Pin Configuration

VDD_RE

F

RE

F

1

2

56

VDD_PCI

VSS_PCI

Xin

PCI2/DF1

PCI1/DF0

14.318MHz

Crystal

Xout

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

3

4

5

6

7

8

9

DF2/PCI3

*FS_E/PCI4

PCI5

VSS_PCI

VDD_PCI

PCI0/SRESET#

REF1/**FS_C

REF0/**FS_D

VSS_REF

PLL Reference

IREF

VDD_CPU

CPUT

CPUC

CPU

XIN

Divider

PLL

**DF_EN/PCIF0

**SRESET_EN/PCIF1

VTT_PWRGD#/PD

VDD_48

**FS_A/USB48_0

VSS_48

XOUT

VDD_REF

SDATA

SCLK

VSS_CPU

CPUT0

CPUC0

VDD_CPU

CPUT1

CPUC1

IREF

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

FS_[E:A]

VDD_SRC

SRCT

SRCC

DOT96T

DOT96C

*FS_B/USB48_1

SRCT0

SRC

Divider

PLL

SRCC0

SRCT1

SRCC1

VDD_SRC

SRCT2

SRCC2

SRCT3

SRCC3

SRCT4_SATA

SRCC4_SATA

VDD_SRC

VSSA

VDDA

SATA

Divider

PLL

SRCT4_SATA

SRCC4_SATA

SRCT7

SRCC7

VDD_SRC

SRCT6

SRCC6

SRCT5

VDD_48Mhz

FIX

DOT96T

DOT96C

Divider

PLL

VDD_48

USB48

SRCC5

VSS_SRC

VTTPWR_GD#/PD

VDD_PCI

PCI

* Indicates internal pull-up

DF_EN

VDD_PCI

** Indicates internal pull-down

Dynamic

Frequency

PCIF

DF[2:0]

Watchdog

Timer

I2C

Logic

SDATA

SCLK

SRESET#

Rev 1.0, November 20, 2006

Page 1 of 22

2200 Laurelwood Road, Santa Clara, CA 95054

Tel:(408) 855-0555 Fax:(408) 855-0550

www.SpectraLinear.com

CY28437

Pin Description

Pin No.

Name

VDD_PCI

VSS_PCI

Type

Description

1,7

2,6

4

PWR 3.3V power supply for outputs.

GND Ground for outputs.

FS_E/PCI4

I/O,SE, 3.3V-tolerant input for CPU frequency selection/33-MHz clock.

PU Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

5

8

PCI

O, SE 33 MHz clocks.

DF_EN/PCIF0

I/O, SE 3.3V LVTTL input to Enable DF pin/33-MHz Output.

PD 1 = Enable, 0 = Disable.

Intel Type-5 output buffer

9

SRESET_EN/PCIF I/O,PD, 3.3V LVTTL input to enable Watchdog/33-MHz clocks.

SE 1 = Enable, 0 = Disable

1

10

VTT_PWRGD#/PD I, PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,

FS_C, FS_D, and FSE inputs. After VTT_PWRGD# (active LOW) assertion, this pin

becomes a real-time input for asserting power-down (active HIGH).

11

12

VDD_48

PWR 3.3V power supply for outputs.

FS_A/USB48_0

I/O,PD, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

SE

13

VSS_48

GND Ground for outputs.

14,15

16

DOT96T, DOT96C O, DIF Fixed 96-MHz clock output.

FS_B/USB48_1 I/O,PU, 3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.

SE Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

17,18,19,20, SRCT/C

22,23,24,25,

31,30,33,32,

35,36

O, DIF Differential serial reference clocks. Outputs have overclocking capability.

21,28,34

26,27

VDD_SRC

PWR 3.3V power supply for outputs.

SRC4_SATAT,

SRC4_SATAC

O, DIF Differential serial reference clock. Recommended output for SATA.

29

37

38

39

VSS_SRC

VDDA

GND Ground for outputs.

PWR 3.3V power supply for PLL.

GND Ground for PLL.

VSSA

IREF

I

A precision resistor is attached to this pin, which is connected to the internal

current reference.

42

VDD_CPU

PWR 3.3V power supply for outputs.

O, DIF Differential CPU clock outputs.

GND Ground for outputs.

44,43,41,40 CPUT/C

45

46

47

48

49

50

51

52

VSS_CPU

SCLK

I

SMBus-compatible SCLOCK.

SMBus-compatible SDATA.

SDATA

I/O

VDD_REF

XOUT

PWR 3.3V power supply for outputs.

O, SE 14.318 MHz crystal output.

XIN

I

14.318 MHz crystal input.

VSS_REF

FS_D/REF0

GND Ground for outputs.

I/O,SE, 3.3V-tolerant input for CPU frequency selection/Reference clock.

PD Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

53

FS_C/REF1

PCI0/SRESET#

DF/PCI

I/O,SE, 3.3V-tolerant input for CPU frequency selection/Reference clock.

PD Selects test mode if pulled to V_{IHFS_C}when VTT_PWRGD# is asserted LOW.

Refer to DC Electrical Specifications table for V_{ILFS_C},V_{IMFS_C},V_{IHFS_C}specifications.

54

O

33 MHz clocks/3.3V LVTTL output for Watchdog reset.

PU When configured as SRESET# output this output becomes open drain type with a

high (>100k:) internal pull-up resistor.

I/O, SE 3.3V LVTTL input for Dynamic Frequency/33-MHz clocks output.

3,55,56

Rev 1.0,November 20, 2006

Page 2 of 22

CY28437

FS_C is a three-level input, when sampled at a voltage greater

than 2.1V by VTTPWRGD#, the device will enter test mode as

selected by the voltage level on the FS_B input.

Frequency Select Pins (FS_[A:E])

Host clock frequency selection is achieved by applying the

appropriate logic levels to FS_A, FS_B, FS_C, FS_D, and

FS_E inputs prior to VTT_PWRGD# assertion (as seen by the

clock synthesizer). Upon VTT_PWRGD# being sampled LOW

by the clock chip (indicating processor VTT voltage is stable),

the clock chip samples the FS_A, FS_B, FS_C, FS_D, and

FS_E input values. For all logic levels of FS_A, FS_B, FS_C,

FS_D, and FS_E, VTT_PWRGD# employs a one-shot

functionality in that once a valid LOW on VTT_PWRGD# has

been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C,

FS_D, and FS_E transitions will be ignored, except in test

mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

clock output buffers, can be individually enabled or disabled.

The registers associated with the Serial Data Interface

initialize to their default setting upon power-up, and therefore

use of this interface is optional. Clock device register changes

are normally made upon system initialization, if any are

required. The interface cannot be used during system

operation for power management functions.

Input Conditions

FS_C FS_B

Output Frequency

FS_D

FS_A

CPU

SRC

CPU PLL CPU M CPU N CPU N SRC PLL

SRC M

SRC N

Gear

divider DEFAULT allowable

Gear

divider (not DEFAULT allowable

Constants

range for Constants changeable

range for

DAF

byuser)

FSEL_3 FSEL_2 FSEL_1 FSEL_0

(MHz)

(G)

60

200 200 - 266

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

100

30

40

60

63

60

63

60

63

60

63

60

62

200

175

200

175

200

212

211

167

211

200

167

207

200 - 250

175 - 262

200 - 250

175 - 262

200 - 250

212 - 262

211 - 262

167 - 250

211 - 262

200 - 250

167 - 250

207 - 258

30

60

200 200 - 266

200 167 - 266

133.3333333

166.6666667

200

60

266.6666667

333.3333333

400

80

120

30

100.952381

133.968254

167

40

60

200.952381

266.6666667

334

60

80

120

400.6451613

X

HIGH

LOW

HIGH

X

Tristate

REF/N

Tristate

REF/N

Tristate Tristate Tristate Tristate

REF/N REF/N REF/N REF/N

Figure 1. CPU and SRC Frequency Select Tables

Rev 1.0,November 20, 2006

Page 3 of 22

CY28437

system controller can access individually indexed bytes. The

offset of the indexed byte is encoded in the command code,

as described in Table 1.

Data Protocol

The clock driver serial protocol accepts byte write, byte read,

block write, and block read operations from the controller. For

block write/read operation, the bytes must be accessed in

sequential order from lowest to highest byte (most significant

bit first) with the ability to stop after any complete byte has

been transferred. For byte write and byte read operations, the

The block write and block read protocol is outlined in Table 2

while Table 3 outlines the corresponding byte write and byte

read protocol. The slave receiver address is 11010010 (D2h).

Table 1. Command Code Definition

Bit

Description

7

0 = Block read or block write operation, 1 = Byte read or byte write operation

(6:0)

Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be

'0000000'

Table 2. Block Read and Block Write Protocol

Block Write Protocol

Block Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeat start

18:11

19

18:11

19

27:20

Byte Count – 8 bits

(Skip this step if I²C_EN bit set)

20

28

36:29

37

Acknowledge from slave

Data byte 1 – 8 bits

27:21

28

Slave address – 7 bits

Read = 1

Acknowledge from slave

Data byte 2 – 8 bits

29

Acknowledge from slave

Byte Count from slave – 8 bits

Acknowledge

45:38

46

37:30

38

Acknowledge from slave

Data Byte /Slave Acknowledges

Data Byte N – 8 bits

Acknowledge from slave

Stop

....

46:39

47

Data byte 1 from slave – 8 bits

Acknowledge

....

55:48

56

Data byte 2 from slave – 8 bits

Acknowledge

....

Data bytes from slave / Acknowledge

Data Byte N from slave – 8 bits

NOT Acknowledge

....

Stop

Table 3. Byte Read and Byte Write Protocol

Byte Write Protocol

Byte Read Protocol

Description

Bit

1

Description

Bit

1

Start

8:2

9

Slave address – 7 bits

Write

8:2

9

Slave address – 7 bits

Write

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Data byte – 8 bits

10

Acknowledge from slave

Command Code – 8 bits

Acknowledge from slave

Repeated start

18:11

19

18:11

19

27:20

20

Rev 1.0,November 20, 2006

Page 4 of 22

CY28437

Table 3. Byte Read and Byte Write Protocol (continued)

Byte Write Protocol

Byte Read Protocol

Description

Bit

28

29

Description

Acknowledge from slave

Stop

Bit

27:21

28

Slave address – 7 bits

Read

29

Acknowledge from slave

Data from slave – 8 bits

NOT Acknowledge

Stop

37:30

38

39

Control Registers

Byte 0: Control Register 0

Bit

@Pup

Name

Description

7

1

SRC[T/C]7

SRC[T/C]7 Output Enable

0 = Disable (Tri-state), 1 = Enable

6

5

4

3

2

1

0

1

SRC[T/C]6

SRC[T/C]5

SRC[T/C]6 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]5 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]4_SATA

SRC[T/C]3

SRC[T/C]4_SATA Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]3 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]2

SRC[T/C]2 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]1

SRC[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enable

SRC[T/C]0

SRC[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enable

Byte 1: Control Register 1

Bit

@Pup

Name

Description

7

1

PCIF0

PCIF0 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

1

DOT96[T/C]

USB_0

DOT96[T/C]MHz Output Enable

0 = Disable (Tri-state), 1 = Enabled

USB_0 MHz Output Enable

0 = Disabled, 1 = Enabled

REF

REF Output Enable

0 = Disabled, 1 = Enabled

3

2

0

1

RESERVED

CPU[T/C]1

RESERVED, Set = 0

CPU[T/C]1 Output Enable

0 = Disable (Tri-state), 1 = Enabled

1

0

1

0

CPU[T/C]0

CPU

CPU[T/C]0 Output Enable

0 = Disable (Tri-state), 1 = Enabled

PLL1 (CPU PLL) Spread Spectrum Enable

0 = Spread off, 1 = Spread on

Rev 1.0,November 20, 2006

Page 5 of 22

CY28437

Byte 2: Control Register 2

Bit

@Pup

Name

Description

7

1

PCI5

PCI5 Output Enable

0 = Disabled, 1 = Enabled

6

5

4

3

2

1

PCI4

PCI3

PCI2

PCI1

PCI0

PCI4 Output Enable

0 = Disabled, 1 = Enabled

PCI3 Output Enable

0 = Disabled, 1 = Enabled

PCI2 Output Enable

0 = Disabled, 1 = Enabled

PCI1 Output Enable

0 = Disabled, 1 = Enabled

PCI0 Output Enable

0 = Disabled, 1 = Enabled

1

0

1

RESERVED

PCIF1

RESERVED, Set = 1

PCIF1 Output Enable

0 = Disabled, 1 = Enabled

Byte 3: Control Register 3

Bit

@Pup

Name

Description

7

0

SRC[T/C]7

Allow control of SRC[T/C]7 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

6

5

4

3

2

1

0

SRC[T/C]6

SRC[T/C]5

Allow control of SRC[T/C]6 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]5 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC[T/C]4_SATA

SRC[T/C]3

Allow control of SRC[T/C]4_SATA with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Allow control of SRC[T/C]3 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC[T/C]2

Allow control of SRC[T/C]2 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC[T/C]1

Allow control of SRC[T/C]1 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

SRC[T/C]0

Allow control of SRC[T/C]0 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

Byte 4: Control Register 4

Bit

@Pup

Name

Description

7

HW

FS_E

FS_E Reflects the value of the FS_E pin sampled on power-up. 0 = FS_E

was LOW during VTT_PWRGD# assertion.

6

0

DOT96

DOT_PWRDWN Drive Mode

0 = Driven in PWRDWN, 1 = Tri-state

5

4

0

RESERVED

PCIF1

RESERVED, Set = 0

Allow control of PCIF1 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

3

0

PCIF0

Allow control of PCIF0 with assertion of SW PCI_STP#

0 = Free running, 1 = Stopped with PCI_STP#

2

1

0

1

RESERVED

RESERVED, Set = 1

Rev 1.0,November 20, 2006

Page 6 of 22

CY28437

Byte 5: Control Register 5

Bit

@Pup

Name

Description

7

0

SRC

SRC Stop Drive Mode

0 = Driven when PCI_STP# asserted,1 = Tri-state when PCI_STP#

asserted

6

5

4

3

0

RESERVED

SRC[7:0]

RESERVED, Set = 0

SRC PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

2

1

0

RESERVED

CPU[T/C]1

RESERVED, Set = 0

CPU[T/C]1 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

0

CPU[T/C]0

CPU[T/C]0 PWRDWN Drive Mode

0 = Driven when PD asserted,1 = Tri-state when PD asserted

Byte 6: Control Register 6

Bit

@Pup

Name

Description

7

0

TEST_SEL

REF/N or Tri-state Select

0 = Tri-state, 1 = REF/N Clock

6

5

4

3

0

HW

1

TEST_MODE

FS_D

Test Clock Mode Entry Control

0 = Normal operation, 1 = REF/N or Tri-state mode,

FS_D reflects the value of the FS_D pin sampled on power-up.

0 = FS_D was LOW during VTT_PWRGD# assertion

REF0

REF Output Drive Strength

0 = High, 1 = Low

1

PCI, PCIF and SRC clock SW PCI_STP# Function

outputs except those set 0=SW PCI_STP assert, 1= SW PCI_STP deassert

to free running

When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will

be stopped in a synchronous manner with no short pulses.

When this bit is set to 1, all STOPPED PCI, PCIF and SRC outputs will

resume in a synchronous manner with no short pulses.

2

1

0

HW

FS_C

FS_B

FS_A

FS_C Reflects the value of the FS_C pin sampled on power-up

0 = FS_C was low during VTT_PWRGD# assertion

FS_B Reflects the value of the FS_B pin sampled on power-up

0 = FS_B was low during VTT_PWRGD# assertion

FS_A Reflects the value of the FS_A pin sampled on power-up

0 = FS_A was low during VTT_PWRGD# assertion

Byte 7: Vendor ID

Bit

7

@Pup

Name

Description

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

0

1

0

Revision Code Bit 3

Revision Code Bit 2

Revision Code Bit 1

Revision Code Bit 0

Vendor ID Bit 3

6

5

4

3

2

Vendor ID Bit 2

1

Vendor ID Bit 1

0

Vendor ID Bit 0

Rev 1.0,November 20, 2006

Page 7 of 22

CY28437

Byte 8: Control Register 8

Bit

@Pup

Name

Description

7

0

CPU_SS

Spread Selection for CPU PLL

0: –0.5% (peak to peak)

1: –1.0% (peak to peak)

6

0

CPU_DWN_SS

Spread Selection for CPU PLL

0: Down spread

1: Center spread

5

4

0

SRC_SS_OFF

SRC_SS

SRC Spread Spectrum Enable

0 = Spread off, 1 = Spread on

Spread Selection for SRC PLL

0: –0.5% (peak to peak)

1: –1.0% (peak to peak)

3

2

0

1

RESERVED

USB

RESERVED, Set = 0

48-MHz Output Drive Strength

0 = 2x, 1 = 1x

1

0

1

0

PCI

33-MHz Output Drive Strength

0 = 2x, 1 = 1x

RESERVED

RESERVED, Set = 0

Byte 9: Control Register 9

Bit

7

@Pup

Name

Description

0

DF_Limit2

DF_Limit1

DF_Limit0

DF_EN

Dynamic Frequency Max threshold. These three bits will set the max

allowed CPU frequency for Dynamic Frequency

6

5

4

Dynamic Frequency Enable

0 = Disable, 1 = Enable

3

2

1

0

FSEL_D

FSEL_C

FSEL_B

FSEL_A

SW Frequency selection bits. See Table 1.

Byte 10: Control Register 10

Bit

@Pup

Name

Description

7

0

Recovery_Frequency This bit allows selection of the frequency setting that the clock will be

restored to once the system is rebooted

0: Use HW settings, 1: Recovery N[8:0]

6

0

Timer_SEL

Timer_SEL selects the WD reset function at SRESET pin when WD time

out.

0 = Reset and Reload Recovery_Frequency

1 = Only Reset

5

4

1

0

Time_Scale

WD_Alarm

Time_Scale allows selection of WD time scale

0 = 294 ms 1 = 2.34 s

WD_Alarm is set to “1” when the watchdog times out. It is reset to “0” when

the system clears the WD_TIMER time stamp.

3

2

1

0

WD_TIMER2

WD_TIMER1

WD_TIMER0

Watchdog timer time stamp selection

000: Reserved (test mode)

001: 1 * Time_Scale

010: 2 * Time_Scale

011: 3 * Time_Scale

100: 4 * Time_Scale

101: 5 * Time_Scale

110: 6 * Time_Scale

111: 7 * Time_Scale

Rev 1.0,November 20, 2006

Page 8 of 22

CY28437

Byte 10: Control Register 10 (continued)

Bit

@Pup

Name

Description

0

WD_EN

Watchdog timer enable, when the bit is asserted, Watchdog timer is

triggered and time stamp of WD_Timer is loaded

0 = Disable, 1 = Enable

Byte 11: Control Register 11

Bit

@Pup

Name

Description

7

0

CPU_DAF_N7

If Prog_CPU_EN is set, the values programmed in CPU_DAF_N[8:0] and

CPU_DAF_M[6:0] will be used to determine the CPU output frequency.

The setting of the FS_Override bit determines the frequency ratio for CPU

and other output clocks. When it is cleared, the same frequency ratio

stated in the Latched FS[E:A] register will be used. When it is set, the

frequency ratio stated in the FSEL[3:0] register will be used.

6

5

4

3

2

1

0

CPU_DAF_N6

CPU_DAF_N5

CPU_DAF_N4

CPU_DAF_N3

CPU_DAF_N2

CPU_DAF_N1

CPU_DAF_N0

Byte 12: Control Register 12

Bit

@Pup

Name

Description

7

0

CPU_DAF_N8

If Prog_CPU_EN is set, the values programmed is in CPU_FSEL_N[8:0]

and CPU_FSEL_M[6:0] will be used to determine the CPU output

frequency.

The setting of the FS_Override bit determines the frequency ratio for CPU

and other output clocks. When it is cleared, the same frequency ratio

stated in the Latched FS[E:A] register will be used. When it is set, the

frequency ratio stated in the FSEL[3:0] register will be used.

6

5

4

3

2

1

0

CPU_DAF_M6

CPU_DAF_M5

CPU_DAF_M4

CPU_DAF_M3

CPU_DAF_M2

CPU_DAF_M1

CPU_DAF_M0

Byte 13: Control Register 13

Bit

7

@Pup

Name

Description

SRC Dial-A-Frequency Bit N7

SRC Dial-A-Frequency Bit N6

SRC Dial-A-Frequency Bit N5

SRC Dial-A-Frequency Bit N4

SRC Dial-A-Frequency Bit N3

SRC Dial-A-Frequency Bit N2

SRC Dial-A-Frequency Bit N1

SRC Dial-A-Frequency Bit N0

0

SRC_N7

SRC_N6

SRC_N5

SRC_N4

SRC_N3

SRC_N2

SRC_N1

SRC_N0

6

5

4

3

2

1

0

Rev 1.0,November 20, 2006

Page 9 of 22

CY28437

Byte 14: Control Register 14

Bit

7

@Pup

Name

SRC_N8

Description

0

SRC Dial-A-Frequency Bit N8

Software Reset.

6

SW_RESET

When set the device will assert a reset signal on SRESET# upon

completion of the block/word/byte write that set it. After asserting and

deasserting the SRESET# this bit will self clear (set to 0).

The SRESET# pin must be enabled by latching SRESET#_EN on

VTT_PRWGD# to utilize this feature.

5

4

0

FS_[E:A]

FS_Override

0 = Select operating frequency by FS(D:A) input pins

1 = Select operating frequency by FSEL_(3:0) settings

SMSW_SEL

Smooth switch select

0: Select CPU_PLL

1: Select SRC_PLL

3

2

1

0

1

RESERVED

PCIF

RESERVED, Set = 0

Free running 33-MHz Output Drive Strength

0 = 2x, 1 = 1x

0

Recovery_N8

Watchdog Recovery Bit

Byte 15: Control Register 15

Bit

7

@Pup

Name

Description

Watchdog Recovery Bit

0

Recovery N7

Recovery N6

Recovery N5

Recovery N4

Recovery N3

Recovery N2

Recovery N1

Recovery N0

6

5

4

3

2

1

0

Byte 16: Control Register 16

Bit

@Pup

Name

Description

7

1

REF1

REF1 Output Enable

0 = Disable, 1 = Enable

6

5

1

0

USB48_1

USB48_1 Output Enable

0 = Disable, 1 = Enable

SRC_FREQ_SEL

SRC Frequency selection

0: SRC frequency is selected via the FSE pin

1: SRC frequency is initially set to 167 MHz.

4

3

0

RESERVED

SRC_SATA

RESERVED, Set = 0

SATA PLL Spread Spectrum Enable

0 = Spread off, 1 = Spread on

2

1

0

1

Prog_SRC_EN

Prog_CPU_EN

Programmable SRC frequency enable

0 = Disabled, 1 = Enabled.

Programmable CPU frequency enable

0 = Disabled, 1 = Enabled.

Watchdog Autorecovery Watchdog Autorecovery Mode

0 = Disable (Manual), 1= Enable (Auto)

Rev 1.0,November 20, 2006

Page 10 of 22

CY28437

Table 4. Crystal Recommendations

Frequency

(Fund)

Drive

(max.)

Shunt Cap Motional

(max.)

Tolerance

(max.)

Stability

(max.)

Aging

(max.)

Cut

Loading Load Cap

(max.)

14.31818 MHz

AT

Parallel 20 pF

0.1 mW

5 pF

0.016 pF

35 ppm

30 ppm

5 ppm

The CY28437 requires a parallel resonance crystal. Substi-

tuting a series resonance crystal will cause the CY28437 to

operate at the wrong frequency and violate the ppm specifi-

cation. For most applications there is a 300-ppm frequency

shift between series and parallel crystals due to incorrect

loading.

Clock Chip

Ci2

Ci1

3 to 6p

Crystal Loading

Crystal loading plays a critical role in achieving low ppm perfor-

mance. To realize low ppm performance, the total capacitance

the crystal will see must be considered to calculate the appro-

priate capacitive loading (CL).

X2

X1

Cs2

Cs1

Trace

2.8pF

Figure 2 shows a typical crystal configuration using the two

trim capacitors. An important clarification for the following

discussion is that the trim capacitors are in series with the

crystal not parallel. It’s a common misconception that load

capacitors are in parallel with the crystal and should be

approximately equal to the load capacitance of the crystal.

This is not true.

XTAL

Ce1

Ce2

Trim

33pF

Figure 3. Crystal Loading Example

As mentioned previously, the capacitance on each side of the

crystal is in series with the crystal. This mean the total capac-

itance on each side of the crystal must be twice the specified

load capacitance (CL). While the capacitance on each side of

the crystal is in series with the crystal, trim capacitors

(Ce1,Ce2) should be calculated to provide equal capacitance

loading on both sides.

Use the following formulas to calculate the trim capacitor

values for Ce1 and Ce2.

Figure 2. Crystal Capacitive Clarification

Load Capacitance (each side)

Ce = 2 * CL – (Cs + Ci)

Calculating Load Capacitors

In addition to the standard external trim capacitors, trace

capacitance and pin capacitance must also be considered to

correctly calculate crystal loading. As mentioned previously,

the capacitance on each side of the crystal is in series with the

crystal. This means the total capacitance on each side of the

crystal must be twice the specified crystal load capacitance

(CL). While the capacitance on each side of the crystal is in

series with the crystal, trim capacitors (Ce1,Ce2) should be

calculated to provide equal capacitive loading on both sides.

Total Capacitance (as seen by the crystal)

1

CLe

=

1

Ce2 + Cs2 + Ci2

1

Ce1 + Cs1 + Ci1

(

)

+

CL....................................................Crystal load capacitance

CLe......................................... Actual loading seen by crystal

using standard value trim capacitors

Ce..................................................... External trim capacitors

Cs..............................................Stray capacitance (terraced)

Ci ...........................................................Internal capacitance

(lead frame, bond wires etc.)

Rev 1.0,November 20, 2006

Page 11 of 22

CY28437

0 (0000) The allowable values for N are detailed in the

frequency select table in Figure 1.

Dynamic Frequency

Dynamic Frequency – Dynamic Frequency (DF) is a technique

to increase the CPU frequency dynamically from any starting

value. The user selects the starting point, either by HW, FSEL,

or DAF, then enables DF. After that, DF will dynamically

change as determined by the value on the DF[2:0] pins.

CPU_DAF_M – There are 7 bits (for 128 values) to linearly

change the CPU frequency (limited by VCO range). Default =

0. The allowable values for M are detailed in the frequency

select table in Figure 1.

SRC_DAF Enable – This bit enables SRC DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the SRC_DAF_N

register. Note: the SRC_DAF_N register must contain valid

values before SRC_DAF is set. Default = 0 (No DAF)

DF/PCI Pin – These PCI pins incorporate dual functions, either

DF or PCI. The function is selected by the DF_EN pin. When

used as DF, these three pins will map to eight entries that

correspond to different “N” values for Dynamic Frequency.

Below is a table that list the combinations along with the

increase in “N”.

SRC_DAF_N – There are 9 bits (for 512 values) to linearly

change the CPU frequency (limited by VCO range). Default =

0 (0000) The allowable values for N are detailed in the

frequency select table in Figure 1.

DOC[2:0]

000

DOC N value

Original Frequency

Recovery – The recovery mechanism during CPU DAF when

the system locks up and the Watchdog timer is enabled is

determined by the “Watchdog Recovery Mode” and

“Watchdog Auto recovery Enable” bits. The possible recovery

methods are: (A) Auto, (B) Manual (by Recovery N), (C) HW,

and (D) No recovery—just send reset signal.

001

+2

010

+6

011

+10

+14

+18

+30

+40

100

101

There is no recovery mode for SRC Dial-a-frequency.

110

Software Frequency Select

111

This mode allows the user to select the CPU output

frequencies using the Software Frequency select bits in the

SMBUS register.

DF_EN bit – This bit enables the DF mode. By default, it is not

set. When set, the operating frequency is determined by

DF[2:0] pins. Default = 0, (No DF)

FSEL – There are 4 bits (for 16 combinations) to select prede-

termined CPU frequencies from a table. The table selections

are detailed in Figure 1.

DF_Limit bit – There are three bits that allow the user to set an

upper limit to prevent CPU runaway. In the event that the user

uses DAF with DF, this feature will provide some safeguard so

the CPU won’t burn up.

FS_Override – This bit allows the CPU frequency to be

selected from HW or FSEL settings. By default, this bit is not

set and the CPU frequency is selected by HW. When this bit

is set, the CPU frequency is selected by the FSEL bits. Default

= 0

Dial-A-Frequency (CPU and SRC)

This feature allows the user to overclock their system by slowly

stepping up the CPU or SRC frequency. When the program-

mable output frequency feature is enabled, the CPU and SRC

frequencies are determined by the following equation

Recovery – The recovery mechanism during FSEL when the

system locks up is determined by the “Watchdog Recovery

Mode” and “Watchdog Auto recovery Enable” bits. The only

possible recovery method is from the Hardware Settings. Auto

recovery or manual recovery can cause a wrong output

frequency because the output divider may have changed with

the selected CPU frequency and these recovery methods will

not recover the original output divider setting.

Fcpu = G * N/M or Fcpu=G2 * N, where G2 = G / M

“N” and “M” are the values programmed in Programmable

Frequency Select N-Value Register and M-Value Register,

respectively. “G” stands for the PLL Gear Constant, which is

determined by the programmed value of FS[E:A]. See

Figure 1 for the Gear Constant for each Frequency selection.

The PCI Express only allows user control of the N register, the

M value is fixed and documented in Figure 1.

Smooth Switching

The device contains one smooth switch circuit that is shared

by the CPU PLL and SRC PLL. The smooth switch circuit

ensures that when the output frequency changes by

overclocking, the transition from the old frequency to the new

frequency is a slow, smooth transition containing no glitches.

The rate of change of output frequency when using the smooth

switch circuit is less than 1 MHz/0.667 Ps. The frequency

overshoot and undershoot will be less than 2%.

In this mode, the user writes the desired N and M value into

the DAF I2C registers. The user cannot change only the M

value and must change both the M and the N values at the

same time, if they require a change to the M value. The user

may change only the N value if required.

Associated Register bits

CPU_DAF Enable – This bit enables CPU DAF mode. By

default, it is not set. When set, the operating frequency is

determined by the values entered into the CPU_DAF_N

register. Note: the CPU_DAF_N and M register must contain

valid values before CPU_DAF is set. Default = 0 (No DAF)

The Smooth Switch circuit can be assigned to either PLL via

register byte 14 bit 4. By default the smooth switch circuit is

assigned to the CPU PLL. Either PLL can still be overclocked

when it does not have control of the smooth switch circuit but

it is not guaranteed to transition to the new frequency without

large frequency glitches.

CPU_DAF_N – There are 9 bits (for 512 values) to linearly

change the CPU frequency (limited by VCO range). Default =

Rev 1.0,November 20, 2006

Page 12 of 22

CY28437

It is not recommended to enable overclocking and change the

N values of both PLLs in the same SMBUS block write.

Watchdog Autorecovery Enable – This bit is set by default and

the recovered values are automatically written into the

“Watchdog Recovery Register” and reloaded by the watchdog

function. When this bit is not set, the user is allowed to write to

the “Watchdog Recovery Register”. The value stored in the

“Watchdog Recovery Register” will be used for recovery.

Default = 1, Autorecovery.

Watchdog Timer

The Watchdog timer is used in the system in conjunction with

overclocking. It is used to provide a reset to a system that has

hung up due to overclocking the CPU and the Front side bus.

The Watchdog is enabled by the user and if the system

completes its checkpoints, the system will clear the timer.

However, when the timer runs out, there will be a reset pulse

generated on the SRESET# pin for 20 ms that is used to reset

the system.

Watchdog Recovery Register – This is a nine-bit register to

store the Watchdog N recovery value. This value can be

written by the Auto recovery or User depending on the state of

the “Watchdog Auto recovery Enable bit”.

Watchdog Recovery Modes

When the Watchdog is enabled (WD_EN = 1) the Watchdog

timer will start counting down from a value of Watchdog_timer

* time scale. If the Watchdog timer reaches 0 before the

WD_EN bit is cleared then it will assert the SRESET# signal

and set the Watchdog Alarm bit to 1.

There are three operating modes that require Watchdog

recovery. The modes are Dial-A-Frequency (DAF), Dynamic

Clocking (DF), or Frequency Select. There are 4 different

recovery modes: The following section lists the operating

mode and the recovery mode associated with it.

To use the Watchdog the SRESET# pin must be enabled by

SRESET_EN pin being sampled LOW by VTTPWRGD#

assertion during system boot-up.

Recover to Hardware M,N, O

When this recovery mode is selected, in the event of a

watchdog timeout, the original M, N, and O values that were

latched by the HW FSEL pins at chip boot-up should be

reloaded.

At any point during the Watchdog timer countdown, if the time

stamp or Watchdog timer bits are changed, the timer will reset

and start counting down from the new value.

After the Reset pulse, the Watchdog will stay inactive until

either:

Autorecovery

When this recovery mode is selected, in the event of a

Watchdog timeout, the M and N values stored in the Recovery

M and N registers should be reloaded. The current values of

M and N will be latched into the internal recovery M and N

registers by the WD_EN bit being set.

1. A new time stamp or Watchdog timer value is loaded.

2. The WD_EN bit is cleared and then set again.

Watchdog Register Bits

The following register bits are associated with the Watchdog

timer:

Manual Recovery

Watchdog Enable – This bit (by default) is not set, which

disables the Watchdog. When set, the Watchdog is enabled.

Also, when there is a transition from LOW to HIGH, the timer

reloads. Default = 0, disable

When this recovery mode is selected, in the event of a

Watchdog timeout, the N value as programmed by the user in

the N recovery register, and the M value that is stored in the

Recovery M register (not accessible by the user) should be

restored. The current M value should be latched M recovery

register by the WD_EN bit being set.

Watchdog Timer – There are three bits (for seven combina-

tions) to select the timer value. Default = 000. The Value '000'

is a reserved test mode.

No Recovery

Watchdog Alarm – This bit is a flag and when it is set, it

indicates that the timer has expired. This bit is not set by

default. When the bit is set, the user is allowed to clear. Default

= 0.

If no recovery mode is selected, in the event of a watchdog

time out, the device should just assert the SRESET# and keep

the current values of M and N

Software Reset

Watchdog Time Scale – This bit selects the multiplier. When

this bit is not set, the multiplier will be 250 ms. When set (by

default), the multiplier will be 3s. Default = 1.

Software reset is a reset function which is used to send out a

pulse from the SRESET# pin. It is controlled by the

SW_RESET enable register bit. Upon completion of the

byte/word/block write in which the SW_RESET bit was set, the

device will send a RESET pulse on the SRESET# pin. The

duration of the SRESET# pulse should be the same as the

duration of the SRESET# pulse after a Watchdog timer time

out.

Watchdog Reset Mode – This selects the Watchdog reset

mode. When this bit is not set (by default), the Watchdog will

send a reset pulse and reload the recovery frequency depends

on Watchdog Recovery Mode setting. When set, it just send a

reset pulse. Default = 0, Reset & Recover Frequency.

Watchdog Recovery Mode – This bit selects the location to

recover from. One option is to recover from the HW settings

(already stored in SMBUS registers for readback capability)

and the second is to recover from a register called “Recovery

N”. Default = 0 (Recover from the HW setting).

After the SRESET# pulse is asserted the SW_RESET bit

should be automatically cleared by the device.

Rev 1.0,November 20, 2006

Page 13 of 22

CY28437

PD (Power-down) Clarification

output are held with “Diff clock” pin driven high at 2 x Iref, and

“Diff clock#” tri-state. If the control register PD drive mode bit

corresponding to the output of interest is programmed to “1”,

then both the “Diff clock” and the “Diff clock#” are tri-state. Note

the example below shows CPUT = 133 MHz and PD drive

mode = ‘1’ for all differential outputs. This diagram and

description is applicable to valid CPU frequencies 100, 133,

166, 200, 266, 333, and 400 MHz. In the event that PD mode

is desired as the initial power-on state, PD must be asserted

high in less than 10 Ps after asserting Vtt_PwrGd#.

The VTT_PWRGD#/PD pin is a dual-function pin. During initial

power-up, the pin functions as VTT_PWRGD#. Once

VTT_PWRGD# has been sampled LOW by the clock chip, the

pin assumes PD functionality. The PD pin is an asynchronous

active HIGH input used to shut off all clocks cleanly prior to

shutting off power to the device. This signal is synchronized

internal to the device prior to powering down the clock synthe-

sizer. PD is also an asynchronous input for powering up the

system. When PD is asserted HIGH, all clocks need to be

driven to a low value and held prior to turning off the VCOs and

the crystal oscillator.

PD Deassertion

The power-up latency is less than 1.8 ms. This is the time from

the deassertion of the PD pin or the ramping of the power

supply until the time that stable clocks are output from the

clock chip. All differential outputs stopped in a three-state

condition resulting from power down will be driven high in less

than 300 Ps of PD deassertion to a voltage greater than

200 mV. After the clock chip’s internal PLL is powered up and

locked, all outputs will be enabled within a few clock cycles of

each other. Figure 5 is an example showing the relationship of

clocks coming up.

PD (Power-down) Assertion

When PD is sampled HIGH by two consecutive rising edges

of CPUC, all single-ended outputs will be held LOW on their

next HIGH-to-LOW transition and differential clocks must be

held HIGH or tri-stated (depending on the state of the control

register drive mode bit) on the next diff clock# HIGH-to-LOW

transition within four clock periods. When the SMBus PD drive

mode bit corresponding to the differential (CPU, SRC, and

DOT) clock output of interest is programmed to ‘0’, the clock

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33 MHz

REF

Figure 4. Power-down Assertion Timing Waveform

Tstable

<1.8ms

PD

CPUT, 133MHz

CPUC, 133MHz

SRCT 100MHz

SRCC 100MHz

USB, 48MHz

DOT96T

DOT96C

PCI, 33MHz

REF

Tdrive_PWRDN#

<300PS, >200mV

Figure 5. Power-down Deassertion Timing Waveform

Rev 1.0,November 20, 2006

Page 14 of 22

CY28437

S2

S1

VTT_PWRGD# = Low

Delay

>0.25mS

Sample

Inputs straps

VDD_A = 2.0V

Wait for <1.8ms

S0

S3

VDD_A = off

Normal

Operation

Enable Outputs

Power Off

VTT_PWRGD# = toggle

Figure 6. Clock Generator Power-up/Run State Diagram

Rev 1.0,November 20, 2006

Page 15 of 22

CY28437

Absolute Maximum Conditions

Parameter

V_DD

Description

Core Supply Voltage

Condition

Min.

–0.5

Max.

4.6

Unit

V

V_{DD_A}

V_IN

Analog Supply Voltage

4.6

V

Input Voltage

Relative to V_SS

–0.5 V_DD+ 0.5 VDC

T_S

Temperature, Storage

Non-functional

–65

150

70

150

20

60

–

°C

T_A

Temperature, Operating Ambient

Temperature, Junction

Functional

0

–

T_J

Functional

°C

Ø_JC

Dissipation, Junction to Case

Dissipation, Junction to Ambient

ESD Protection (Human Body Model)

Flammability Rating

Mil-STD-883E Method 1012.1

JEDEC (JESD 51)

MIL-STD-883, Method 3015

At 1/8 in.

–

°C/W

V

Ø_JA

–

ESD_HBM

UL-94

MSL

2000

V–0

1

Moisture Sensitivity Level

Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

DC Electrical Specifications

Parameter

All V_DDs

V_ILI2C

V_IHI2C

V_{IL_FS}

V_{IH_FS}

V_{ILFS_C}

V_{IMFS_C}

V_{IH FS_C}

V_IL

Description

3.3V Operating Voltage

Input Low Voltage

Condition

Min.

Max.

Unit

V

3.3 5%

3.135

3.465

SDATA, SCLK

–

1.0

V

Input High Voltage

2.2

–

V

FS_[A:B,D:E] Input Low Voltage

FS_[A:B,D:E] Input High Voltage

FS_C Low Range

V_SS– 0.3

0.35

V

0.7

V_DD+ 0.5

V

0

0.35

V

FS_C Mid Range

0.7

1.7

V

FS_C High Range

2.1

V_DD

V

3.3V Input Low Voltage

3.3V Input High Voltage

Input Low Leakage Current

Input High Leakage Current

3.3V Output Low Voltage

3.3V Output High Voltage

High-impedance Output Current

Input Pin Capacitance

Output Pin Capacitance

Pin Inductance

V_SS– 0.3

0.8

V

V_IH

2.0

V_DD+ 0.3

V

I_IL

Except internal pull-up resistors, 0 < V_IN< V_DD

Except internal pull-down resistors, 0 < V_IN< V_DD

I_OL= 1 mA

–5

–

5

PA

V

I_IH

–

V_OL

–

0.4

–

V_OH

I_OH= –1 mA

2.4

V

I_OZ

–10

10

5

PA

pF

nH

V

C_IN

3

C_OUT

L_IN

3

5

–

7

V_XIH

Xin High Voltage

0.7V_DD

V_DD

0.3V_DD

500

70

2

V_XIL

Xin Low Voltage

0

–

V

I_DD3.3V

I_PD3.3V

I_PT3.3V

Dynamic Supply Current

Power-down Supply Current

At max. load and freq. per Figure 9

PD asserted, Outputs Driven

PD asserted, Outputs Tri-state

mA

Rev 1.0,November 20, 2006

Page 16 of 22

CY28437

AC Electrical Specifications

Parameter

Description

Condition

Min.

Max.

Unit

Crystal

T_DC

XIN Duty Cycle

XIN Period

Thedevice willoperatereliably withinput

dutycyclesupto30/70buttheREFclock

duty cycle will not be within specification

47.5

52.5

%

T_PERIOD

When XIN is driven from an external

clock source

69.841

71.0

ns

T_R/ T_F

T_CCJ

XIN Rise and Fall Times

XIN Cycle to Cycle Jitter

Long-term Accuracy

Measured between 0.3V_DDand 0.7V_DD

As an average over 1-Ps duration

Over 150 ms

–

10.0

500

300

ns

ps

L_ACC

ppm

CPU at 0.7V (SSC refers to –0.5% spread spectrum)

T_DC

CPUT and CPUC Duty Cycle

Measured at crossing point V_OX

45

55

%

T_PERIOD

100-MHz CPUT and CPUC Period

133-MHz CPUT and CPUC Period

166-MHz CPUT and CPUC Period

200-MHz CPUT and CPUC Period

266-MHz CPUT and CPUC Period

333-MHz CPUT and CPUC Period

400-MHz CPUT and CPUC Period

9.997001 10.00300 ns

7.497751 7.502251 ns

5.998201 6.001801 ns

4.998500 5.001500 ns

3.748875 3.751125 ns

2.999100 3.000900 ns

2.499250 2.500750 ns

9.997001 10.05327 ns

7.497751 7.539950 ns

5.998201 6.031960 ns

4.998500 5.026634 ns

3.748875 3.769975 ns

2.999100 3.015980 ns

2.499250 2.513317 ns

9.912001 10.08800 ns

7.412751 7.587251 ns

5.913201 6.086801 ns

4.913500 5.086500 ns

3.663875 3.836125 ns

2.914100 3.085900 ns

2.414250 2.585750 ns

9.912001 10.13827 ns

T_PERIOD

T_PERIODSS

T_PERIODAbs

100-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

133-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

166-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

200-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

266-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

333-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

400-MHz CPUT and CPUC Period, SSC Measured at crossing point V_OX

100-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

133-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

166-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

200-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

266-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

333-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

400-MHz CPUT and CPUC Absolute period Measured at crossing point V_OX

T_PERIODSSAbs100-MHz CPUT and CPUC Absolute

period, SSC

Measured at crossing point V_OX

T_PERIODSSAbs133-MHz CPUT and CPUC Absolute

period, SSC

7.412751 7.624950 ns

5.913201 6.116960 ns

4.913500 5.111634 ns

3.663875 3.854975 ns

2.914100 3.100980 ns

2.414250 2.598317 ns

T_PERIODSSAbs166-MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs200-MHz CPUT and CPUC Absolute

period, SSC

T_PERIODSSAbs266-MHz CPUT and CPU C Absolute Measured at crossing point V_OX

period, SSC

T_PERIODSSAbs333-MHz CPUT and CPUC Absolute

period, SSC

Measured at crossing point V_OX

T_PERIODSSAbs400-MHz CPUT and CPUC Absolute

period, SSC

T_SKEW

CPU0 to CPU1

–

100

ps

Rev 1.0,November 20, 2006

Page 17 of 22

CY28437

AC Electrical Specifications (continued)

Parameter

T_CCJ

Description

CPUT/C Cycle to Cycle Jitter

Long Term accuracy

Condition

Min.

Max.

65

Unit

ps

Measured at crossing point V_OX

–

L_ACC

Measured using frequency counter over

0.15 seconds.

300

ppm

T_R/ T_F

T_RFM

CPUT and CPUC Rise and Fall Times Measured from V_OL= 0.175 to

V_OH= 0.525V

130

–

700

29

ps

%

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/(T_R+ T_F)

'T_R

Rise Time Variation

–

125

ps

mV

V

'T_F

Fall Time Variation

125

V_HIGH

V_LOW

V_OX

Voltage High

Math averages Figure 9

660

–150

250

–

850

Voltage Low

–

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

550

V_OVS

V_UDS

V_RB

V_HIGH+ 0.3

–0.3

–

V

See Figure 9. Measure SE

0.2

V

SRC

T_DC

SRCT and SRCC Duty Cycle

Measured at crossing point V_OX

45

55

%

T_PERIOD

100-MHz SRCT and SRCC Period

9.997001 10.00300 ns

9.997001 10.05327 ns

9.872001 10.12800 ns

T_PERIODSS

T_PERIODAbs

100-MHz SRCT and SRCC Period, SSC Measured at crossing point V_OX

100-MHz SRCT and SRCC Absolute

Period

Measured at crossing point V_OX

T_PERIODSSAbs100-MHz SRCT and SRCC Absolute

Period, SSC

Measured at crossing point V_OX

9.872001 10.17827 ns

T_SKEW

T_CCJ

Any SRCT/C to SRCT/C Clock Skew

SRCT/C Cycle to Cycle Jitter

SRCT/C Long Term Accuracy

Measured at crossing point V_OX

–

250

125

300

700

ps

L_ACC

–

ppm

ps

T_R/ T_F

SRCT and SRCC Rise and Fall Times Measured from V_OL= 0.175 to

V_OH= 0.525V

130

T_RFM

Rise/Fall Matching

Determined as a fraction of

2*(T_R– T_F)/(T_R+ T_F)

–

20

%

'T_R

Rise TimeVariation

–

125

ps

mV

V

'T_F

Fall Time Variation

125

V_HIGH

V_LOW

Voltage High

Math averages Figure 9

660

–150

250

–

850

Voltage Low

–

V_OX

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

Minimum Undershoot Voltage

Ring Back Voltage

550

V_OVS

V_HIGH+ 0.3

V_UDS

–0.3

–

V

V_RB

See Figure 9. Measure SE

0.2

V

PCI/PCIF

T_DC

PCI Duty Cycle

Measurement at 1.5V

45

55

%

T_PERIOD

T_PERIODSS

T_PERIODAbs

Spread Disabled PCIF/PCI Period

29.99100 30.00900 ns

29.9910 30.15980 ns

29.49100 30.50900 ns

29.49100 30.65980 ns

Spread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

Spread Disabled PCIF/PCI Period Measurement at 1.5V

T_PERIODSSAbsSpread Enabled PCIF/PCI Period, SSC Measurement at 1.5V

T_HIGH

T_LOW

PCIF and PCI high time

PCIF and PCI low time

Measurement at 2.4V

Measurement at 0.4V

12.0

–

ns

Rev 1.0,November 20, 2006

Page 18 of 22

CY28437

AC Electrical Specifications (continued)

Parameter

Edge Rate

T_SKEW

Description

Rising edge rate

Falling edge rate

Condition

Min.

0.85

–

Max.

6.0

Unit

V/ns

ps

Measured between 0.8V and 2.0V

6.0

Any PCI clock to Any PCI clock Skew Measurement at 1.5V

500

550

T_CCJ

PCIF and PCI Cycle to Cycle Jitter

Measurement at 1.5V

–

ps

DOT

T_DC

DOT96T and DOT96C Duty Cycle

DOT96T and DOT96C Period

Measured at crossing point V_OX

45

55

%

T_PERIOD

T_PERIODAbs

T_CCJ

10.41354 10.41979 ns

10.16354 10.66979 ns

DOT96T and DOT96C Absolute Period Measured at crossing point V_OX

DOT96T/C Cycle to Cycle Jitter

DOT96T/C Long Term Accuracy

Long Term jitter

Measured at crossing point V_OX

Measurement taken from cross point

–

250

100

700

ps

ppm

ps

L_ACC

T_LTJ

V_OX@1 Ps

Measurement taken from cross point

V_OX@10ꢀPs

–

130

–

700

20

ps

%

T_R/ T_F

T_RFM

DOT96T and DOT96C Rise and Fall Times Measured from V_OL= 0.175 to V_OH

0.525V

=

Rise/Fall Matching

Determined as a fraction of

*(T_R– T_F)/(T_R+ T_F)

'T_R

Rise Time Variation

–

125

850

–

ps

'T_F

Fall Time Variation

V_HIGH

V_LOW

V_OX

Voltage High

Math averages Figure 9

660

–150

250

–

mV

V

Voltage Low

Crossing Point Voltage at 0.7V Swing

Maximum Overshoot Voltage

550

V_OVS

V_HIGH

0.3

+

V_UDS

V_RB

Minimum Undershoot Voltage

Ring Back Voltage

–0.3

–

V

See Figure 9. Measure SE

0.2

USB

T_DC

Duty Cycle

Measurement at 1.5V In High Drive

mode

45

55

%

T_PERIOD

T_PERIODAbs

T_HIGH

Period

Measurement at 1.5V

20.83125 20.83542 ns

20.48125 21.18542 ns

Absolute Period

USB high time

USB low time

Measurement at 1.5V

Measurement at 2.4V

8.094

7.694

0.52

–

10.5

2.4

ns

T_LOW

Measurement at 0.4V

Edge Rate

T_CCJ

Rising edge rate

Falling edge rate

Cycle to Cycle Jitter

Long Term jitter

Measured between 0.8V and 2.0V

Measurement at 1.5V

V/ns

ps

2.4

200

700

T_LTJ

Measurement taken from cross point

–

ps

V_OX@1 Ps

Measurement taken from cross point

V_OX@10 Ps

–

700

ps

Measurement taken from cross point

V_OX@125 Ps

REF

T_DC

REF Duty Cycle

REF Period

Measurement at 1.5V

45

55

%

T_PERIOD

69.8203

69.8622

ns

T_PERIODAbs

REF Absolute Period

68.82033 70.86224 ns

Rev 1.0,November 20, 2006

Page 19 of 22

CY28437

AC Electrical Specifications (continued)

Parameter

T_R/ T_F

Description

REF Rise and Fall Times

Rising edge rate

Condition

Min.

0.5

1.0

–

Max.

2.0

Unit

V/ns

ps

Measured between 0.8V and 2.0V

Measurement at 1.5V

Edge Rate

T_CCJ

4.0

Falling edge rate

4.0

REF Cycle to Cycle Jitter

1000

ENABLE/DISABLE and SET-UP

T_STABLE

Clock Stabilization from Power-up

–

1.8

ms

Test and Measurement Set-up

For PCI Single-ended Signals and Reference

The following diagram shows the test load configurations for

the single-ended PCI, USB, and REF output signals.

Measurement

Point

ꢁꢁ:

PCI/

USB

ꢂꢃ:

5pF

Measurement

Point

ꢄꢅ:

ꢂꢃ:

5pF

REF

Measurement

Point

5pF

Figure 7. Single-ended Load Configuration

Measurement

Point

ꢄꢅ:

ꢂꢃ:

5pF

Measurement

Point

ꢄꢅ:

PCI/

USB

5pF

Measurement

Point

ꢄꢅ:

ꢂꢃ:

5pF

Measurement

Point

ꢄꢅ:

REF

ꢂꢃ:

5pF

Measurement

Point

5pF

Figure 8. Single-ended Load Configuration HIGH DRIVE OPTION

Rev 1.0,November 20, 2006

Page 20 of 22

CY28437

For Differential CPU, SRC and DOT96 Output Signals

The following diagram shows the test load configuration for the

differential CPU and SRC outputs.

M e a s u re m e n t

P o in t

ꢁ ꢁ :

C P U T

S R C T

2 p F

ꢆ ꢇ ꢈꢇ :

D O T 9 6 T

ꢄ ꢃ ꢃ : ꢀD iffe re n tia l

M e a s u re m e n t

P o in t

2 p F

C P U C

ꢁ ꢁ :

S R C C

D O T 9 6 C

ꢆ ꢇ ꢈꢇ :

IR E F

ꢆ ꢉ ꢊ :

Figure 9. 0.7V Single-ended Load Configuration

3 .3 V s ig n a ls

T _{D C}

-

3 .3 V

2 .4 V

1 .5 V

0 .4 V

0 V

T _R

T _F

Figure 10. Single-ended Output Signals (for AC Parameters Measurement)

Ordering Information

Part Number

Lead-free

Package Type

Product Flow

CY28437OXC

CY28437OXCT

CY28437ZXC

CY28437ZXCT

56-pin SSOP

Commercial, 0q to 85qC

56-pin SSOP – Tape and Reel

56-pin TSSOP

56-pin TSSOP – Tape and Reel

Rev 1.0,November 20, 2006

Page 21 of 22

CY28437

Package Diagrams

56-Lead Shrunk Small Outline Package O56

.020

28

1

0.395

0.420

0.292

0.299

DIMENSIONS IN INCHES MIN.

MAX.

29

56

0.720

0.730

SEATING PLANE

0.005

0.010

0.088

0.092

0.095

0.110

.010

GAUGE PLANE

0.110

0.024

0.040

0.025

BSC

0.008

0.016

0°-8°

0.008

0.0135

56-Lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56

0.249[0.009]

28

1

DIMENSIONS IN MM[INCHES] MIN.

MAX.

7.950[0.313]

8.255[0.325]

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.42gms

5.994[0.236]

6.198[0.244]

PART #

Z5624 STANDARD PKG.

ZZ5624 LEAD FREE PKG.

29

56

13.894[0.547]

14.097[0.555]

1.100[0.043]

MAX.

GAUGE PLANE

0.25[0.010]

0.20[0.008]

0.508[0.020]

0.762[0.030]

0°-8°

0.051[0.002]

0.152[0.006]

0.851[0.033]

0.950[0.037]

0.500[0.020]

BSC

0.100[0.003]

0.200[0.008]

0.170[0.006]

0.279[0.011]

SEATING

PLANE

While SLI has reviewed all information herein for accuracy and reliability, Spectra Linear Inc. assumes no responsibility for the use of any cir-

cuitry or for the infringement of any patents or other rights of third parties which would result from each use. This product is intended for use in

normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, or any other applica-

tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursuant to additional

processing by Spectra Linear Inc., and expressed written agreement by Spectra Linear Inc. Spectra Linear Inc. reserves the right to change any

circuitry or specification without notice.

Rev 1.0, November 20, 2006

Page 22 of 22


型号：	CY28437OXC
厂家：	SPECTRALINEAR INC
描述：	Clock Generator for Intel Grantsdale Chipset 时钟发生器为英特尔的Grantsdale芯片组时钟发生器
文件：	总22页 (文件大小：195K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CY28437OXC [SPECTRALINEAR]

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