AOD609 [FREESCALE]
Complementary Enhancement; 加强互补
| 型号： | AOD609 |
| 厂家： | 
Freescale |
| 描述： | Complementary Enhancement |
| 文件： | 总9页 (文件大小：728K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AOD609
Complementary Enhancement
Mode Field Effect Transistor
General Description
The AOD609 uses advanced trench technology MOSFETs to provide excellent RDS(ON) and low gate
charge. The complementary MOSFETs may be used in H-bridge, Inverters and other applications.
Features
n-channel
V
DS (V) = 40V, ID = 12A (VGS=10V)
RDS(ON)< 30mΩ (VGS=10V)
DS(ON)< 40mΩ (VGS=4.5V)
R
p-channel
VDS (V) = -40V, ID = -12A (VGS=-10V)
RDS(ON)< 45mΩ (VGS= -10V)
R
DS(ON)< 66mΩ (VGS= -4.5V)
Top View
D1/D2
Drain Connected to
Tab
G1
G2
S1
S2
n-channel
p-channel
Absolute Maximum Ratings TA=25°C unless otherwise noted
Parameter
Max n-channel
Symbol
Max p-channel
Units
VDS
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain
Current B,H
Pulsed Drain Current B
Avalanche Current C
40
±20
12
-40
V
VGS
±20
-12
V
TC=25°C
TC=100°C
ID
12
-12
A
IDM
IAR
EAR
30
-30
14
-20
Repetitive avalanche energy L=0.1mHC
9.8
20
mJ
W
TC=25°C
Power Dissipation
27
30
PD
TC=100°C
14
15
TA=25°C
Power Dissipation
TA=70°C
2
2
PDSM
W
1.3
1.3
TJ, TSTG
Junction and Storage Temperature Range
-55 to 175
-55 to 175
°C
Thermal Characteristics: n-channel and p-channel
Parameter
Symbol
Device
Typ
17.4
50
Max
Units
°C/W
°C/W
°C/W
Maximum Junction-to-Ambient A,D
n-ch
n-ch
n-ch
25
60
5.5
t ≤ 10s
RθJA
Maximum Junction-to-Ambient A,D
Steady-State
Maximum Junction-to-Lead C
Steady-State
RθJC
RθJA
RθJC
4
Maximum Junction-to-Ambient A,D
Maximum Junction-to-Ambient A,D
p-ch
p-ch
p-ch
16.7
50
3.5
25
60
5
°C/W
°C/W
°C/W
t ≤ 10s
Steady-State
Maximum Junction-to-Lead C
Steady-State
1/9
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AOD609
Complementary Enhancement
Mode Field Effect Transistor
N Channel Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
BVDSS
Drain-Source Breakdown Voltage
ID=250µA, VGS=0V
40
V
VDS=40V, VGS=0V
1
5
IDSS
Zero Gate Voltage Drain Current
µA
TJ=55°C
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
V
V
DS=0V, VGS= ±20V
±100
3
nA
V
VGS(th)
ID(ON)
DS=VGS ID=250µA
1.7
30
2.5
VGS=10V, VDS=5V
VGS=10V, ID=12A
A
24
37
30
46
40
RDS(ON)
TJ=125°C
Static Drain-Source On-Resistance
mΩ
VGS=4.5V, ID=8A
31
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
V
DS=5V, ID=12A
25
S
V
A
IS=1A,VGS=0V
0.76
1
2
Maximum Body-Diode Continuous Current
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
516
82
650
pF
pF
pF
Ω
VGS=0V, VDS=20V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
43
VGS=0V, VDS=0V, f=1MHz
4.6
6.9
SWITCHING PARAMETERS
Qg (10V)
Total Gate Charge
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
8.3
2.3
1.6
6.4
3.6
16.2
6.6
18
10.8
nC
nC
nC
ns
ns
ns
ns
V
GS=10V, VDS=20V,
Qgs
Qgd
tD(on)
tr
ID=12A
VGS=10V, VDS=20V, RL=1.4Ω,
R
GEN=3Ω
tD(off)
tf
trr
IF=12A, dI/dt=100A/µs
IF=12A, dI/dt=100A/µs
24
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
ns
nC
Qrr
10
A: The value of R
is measured with the device in a still air environment with TA =25°C. The power dissipation P
and current rating IDSM are based
θJA
DSM
on TJ(MAX)=150°C, using the steady state junction-to-ambient thermal resistance.
B. The power dissipation P is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper dissipation lim
D
for cases where additional heatsinking is used.
C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming a
maximum junction temperature of TJ(MAX)=175°C. The SOA curve provides a single pulse rating.
2
G. These tests are performed with the device mounted on 1 in FR-4 board with 2oz. Copper, in a still air environment with T=25°C.
A
H. The maximum current rating is limited by bond-wires.
*This device is guaranteed green after data code 8X11 (Sep S1T 2008).
Rev4: Aug 2009
2/9
www.freescale.net.cn
AOD609
Complementary Enhancement
Mode Field Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS: N-CHANNEL
30
25
20
15
10
5
30
25
20
15
10
5
10V
5V
4.5V
VDS=5V
4V
125°C
VGS=3.5V
25°C
0
0
0
1
2
3
4
5
2
2.5
3
3.5
GS(Volts)
4
4.5
VDS (Volts)
V
Fig 1: On-Region Characteristics
Figure 2: Transfer Characteristics
36
34
32
30
28
26
24
22
20
1.8
1.6
1.4
1.2
1
VGS=4.5V
VGS=10V
ID=12A
VGS=10V
VGS=4.5V
ID=8A
0.8
0.6
0
5
10
15
20
-50
-25
0
25
50
75
100 125 150
ID (A)
Temperature (°C)
Figure 3: On-Resistance vs. Drain Current and
Gate Voltage
Figure 4: On-Resistance vs. Junction
Temperature
90
100
10
ID=12A
70
50
30
10
1
125°C
25°C
0.1
125°C
25°C
0.01
0.001
0.0001
0.0
0.2
0.4
0.6
0.8
1.0
1.2
VSD (Volts)
3
4
5
6
7
8
9
10
VGS (Volts)
Figure 6: Body-Diode Characteristics
Figure 5: On-Resistance vs. Gate-Source Voltage
3/9
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AOD609
Complementary Enhancement
Mode Field Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS: N-CHANNEL
800
600
400
200
0
10
VDS=20V
ID= 12A
8
Ciss
6
4
Crss
Coss
2
0
0
10
20
VDS (Volts)
30
40
0
2
4
6
8
10
Qg (nC)
Figure 7: Gate-Charge Characteristics
Figure 8: Capacitance Characteristics
1000
100
10
100
10
TJ(Max)=150°C
TA=25°C
10µs
100µs
1
RDS(ON)
1ms
10ms
limited
0.1s
0.1
0.01
1s
10s
TJ(Max)=150°C
TA=25°C
DC
1
0.1
1
10
100
0.00001
0.001
0.1
10
1000
VDS (Volts)
Pulse Width (s)
Figure 10: Single Pulse Power Rating Junction-to-
Ambient (Note E)
Figure 9: Maximum Forward Biased Safe
Operating Area (Note E)
10
D=Ton/T
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
TJ,PK=TA+PDM.ZθJA.RθJA
RθJA=50°C/W
1
PD
0.1
Ton
T
Single Pulse
0.001 0.01
0.01
0.00001
0.0001
0.1
1
10
100
1000
Pulse Width (s)
Figure 11: Normalized Maximum Transient Thermal Impedance
4/9
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AOD609
Complementary Enhancement
Mode Field Effect Transistor
Gate Charge Test Circuit & Waveform
Vgs
Qg
10V
+
VDC
+
Qgd
Qgs
Vds
VDC
-
-
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
Vds
90%
10%
+
DUT
Vdd
Vgs
VDC
Rg
-
Vgs
Vgs
td(on)
t
r
td(off)
t
f
ton
toff
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
L
EAR= 1/2 LIA2R
BVDSS
Vds
Id
Vgs
Vds
+
Vgs
Vdd
I AR
VDC
Id
Rg
-
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Q rr = - Idt
Vds +
Vds -
Ig
DUT
Vgs
trr
L
Isd
I F
Isd
Vgs
dI/dt
I RM
+
Vdd
VDC
Vdd
-
Vds
5/9
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AOD609
Complementary Enhancement
Mode Field Effect Transistor
P-Channel Electrical Characteristics (TJ=25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
STATIC PARAMETERS
BVDSS
Drain-Source Breakdown Voltage
ID= -250µA, VGS=0V
-40
V
VDS= -40V, VGS=0V
-1
-5
IDSS
Zero Gate Voltage Drain Current
µA
TJ=55°C
IGSS
Gate-Body leakage current
Gate Threshold Voltage
On state drain current
VDS=0V, VGS= ±20V
±100
-3
nA
V
VGS(th)
ID(ON)
VDS=VGS ID= -250µA
-1.7
-30
-2
VGS= -10V, VDS= -5V
VGS= -10V, ID= -12A
A
36
52
45
65
66
RDS(ON)
TJ=125°C
Static Drain-Source On-Resistance
mΩ
VGS= -4.5V, ID= -8A
VDS= -5V, ID= -12A
IS= -1A,VGS=0V
51
gFS
VSD
IS
Forward Transconductance
Diode Forward Voltage
22
S
V
A
-0.76
-1
-2
Maximum Body-Diode Continuous Current
DYNAMIC PARAMETERS
Ciss
Coss
Crss
Rg
Input Capacitance
900
97
1125
pF
pF
pF
Ω
VGS=0V, VDS= -20V, f=1MHz
Output Capacitance
Reverse Transfer Capacitance
Gate resistance
68
VGS=0V, VDS=0V, f=1MHz
14
SWITCHING PARAMETERS
Qg (-10V)
Total Gate Charge
Total Gate Charge
Gate Source Charge
Gate Drain Charge
Turn-On DelayTime
Turn-On Rise Time
Turn-Off DelayTime
Turn-Off Fall Time
16.2
7.2
3.8
3.5
6.2
8.4
44.8
41.2
21
21
nC
nC
nC
nC
ns
Q (-4.5V)
g
9.4
V
GS= -10V, VDS= -20V,
ID= -12A
Qgs
Qgd
tD(on)
tr
ns
VGS= -10V, VDS= -20V, RL=1.4Ω,
RGEN=3Ω
tD(off)
tf
ns
ns
trr
IF= -12A, dI/dt=100A/µs
IF= -12A, dI/dt=100A/µs
27
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
ns
Qrr
14
nC
A: The value of R
is measured with the device in a still air environment with TA =25°C. The power dissipation P
and current rating IDSM are
θJA
DSM
based on TJ(MAX)=150°C, using t ≤ 10s junction-to-ambient thermal resistance.
B. The power dissipation P is based on TJ(MAX)=175°C, using junction-to-case thermal resistance, and is more useful in setting the upper
D
dissipation limit for cases where additional heatsinking is used.
C: Repetitive rating, pulse width limited by junction temperature TJ(MAX)=175°C.
D. The RθJA is the sum of the thermal impedence from junction to case RθJC and case to ambient.
E. The static characteristics in Figures 1 to 6 are obtained using <300µs pulses, duty cycle 0.5% max.
F. These curves are based on the junction-to-case thermal impedence which is measured with the device mounted to a large heatsink, assuming
a maximum junction temperature of TJ(MAX)=175°C. The SOA curve provides a single pulse rating.
2
G. These tests are performed with the device mounted on 1 in FR-4 board with 2oz. Copper, in a still air environment with T=25°C.
A
H. The maximum current rating is limited by bond-wires.
*This device is guaranteed green after data code 8X11 (Sep S1T 2008).
Rev4: Aug 2009
6/9
www.freescale.net.cn
AOD609
Complementary Enhancement
Mode Field Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS: P-CHANNEL
30
25
20
15
10
5
30
25
20
15
10
5
VDS=-5V
-10V
-5V
-4V
-4.5V
VGS=-3.5V
125°C
25°C
0
0
0
1
2
3
4
5
1.5
2
2.5
3
3.5
4
4.5
-VDS (Volts)
-VGS(Volts)
Fig 12: On-Region Characteristics
Figure 13: Transfer Characteristics
65
60
55
50
45
40
35
30
1.7
1.5
1.3
1.1
0.9
0.7
VGS=-10V
ID=-12A
VGS=-4.5V
VGS=-4.5V
ID=-8A
VGS=-10V
-50
-25
0
25
50
75
100 125 150
0
5
10
15
20
-ID (A)
Temperature (°C)
Figure 14: On-Resistance vs. Drain Current and
Gate Voltage
Figure 15: On-Resistance vs. Junction
Temperature
130
110
90
100
10
ID=-12A
1
125°C
0.1
125°C
70
25°C
0.01
0.001
0.0001
25°C
50
30
0.0
0.2
0.4
0.6
0.8
1.0
1.2
3
4
5
6
7
8
9
10
-VSD (Volts)
-VGS (Volts)
Figure 16: On-Resistance vs. Gate-Source Voltage
Figure 17: Body-Diode Characteristics
7/9
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AOD609
Complementary Enhancement
Mode Field Effect Transistor
TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS: P-CHANNEL
10
1400
1200
1000
800
600
400
200
0
VDS=-20V
ID= -12A
8
Ciss
6
4
Crss
Coss
2
0
0
10
20
-VDS (Volts)
30
40
0
3
6
9
12
15
18
Qg (nC)
Figure 18: Gate-Charge Characteristics
Figure 19: Capacitance Characteristics
1000
100
10
100
10
TJ(Max)=150°C
TA=25°C
10µs
100µs
1
RDS(ON)
1ms
10ms
limited
0.1s
0.1
0.01
1s
10s
TJ(Max)=150°C
TA=25°C
DC
1
0.1
1
10
100
0.00001
0.001
0.1
10
1000
-VDS (Volts)
Pulse Width (s)
Figure 21: Single Pulse Power Rating Junction-to-
Ambient (Note E)
Figure 20: Maximum Forward Biased Safe
Operating Area (Note E)
10
D=Ton/T
In descending order
D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse
TJ,PK=TA+PDM.ZθJA.RθJA
RθJA=50°C/W
1
PD
0.1
Ton
T
Single Pulse
0.001
0.01
0.00001
0.0001
0.01
0.1
1
10
100
1000
Pulse Width (s)
Figure 22: Normalized Maximum Transient Thermal Impedance
8/9
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AOD609
Complementary Enhancement
Mode Field Effect Transistor
Gate Charge Test Circuit & Waveform
Vgs
Qg
-
-10V
-
VDC
Qgs
Qgd
+
Vds
VDC
+
DUT
Vgs
Ig
Charge
Resistive Switching Test Circuit & Waveforms
RL
Vds
toff
ton
t
td(off)
td(on)
t
r
f
Vgs
-
90%
10%
DUT
Vdd
Vgs
VDC
+
Rg
Vgs
Vds
Unclamped Inductive Switching (UIS) Test Circuit & Waveforms
EAR= 1/2 LIA2R
L
Vds
Id
Vgs
Vds
-
BVDSS
Vgs
Vdd
VDC
+
Id
Rg
I AR
DUT
Vgs
Vgs
Diode Recovery Test Circuit & Waveforms
Qrr = - Idt
Vds +
DUT
Vgs
trr
Vds -
L
-Isd
-IF
Isd
Vgs
dI/dt
-IRM
+
Vdd
VDC
Vdd
-
-Vds
Ig
9/9
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